Display panel and display device

Abstract

The invention discloses a display panel and a display device.The display panel comprises a first area and a second area, the first area comprises a wiring arrangement area and a circuit arrangement area, the wiring arrangement area and the circuit arrangement area are arranged in the first direction, and at least the second area comprises pixels; the circuit arrangement area comprises a first circuit and a second circuit, the first circuit and the second circuit are arranged in a second direction, the second direction intersects with the first direction, and the width of the first circuit in the first direction is larger than that of the second circuit in the first direction; wherein the wiring arrangement area comprises a first wiring arrangement area and a second wiring arrangement area, in the first direction, the first circuit is overlapped with the first wiring arrangement area, the second circuit is overlapped with the second wiring arrangement area, and the width of the first wiring arrangement area in the first direction is smaller than that of the second wiring arrangement area in the first direction. At least a narrow frame can be realized.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The border area of ​​the display panel is usually arranged with circuits and wiring, and the layout of the two affects the width of the border. How to adjust the layout of circuits and wiring to achieve a narrow border is one of the research hotspots in the industry. Summary of the invention

[0003] The present invention provides a display panel and a display device to at least achieve a narrow frame.

[0004] According to one aspect of the present invention, a display panel is provided, comprising a first area and a second area, the first area comprising a wiring arrangement area and a circuit arrangement area, the wiring arrangement area and the circuit arrangement area are arranged along a first direction, and at least the second area comprises pixels;

[0005] The circuit arrangement area includes a first circuit and a second circuit, the first circuit and the second circuit are arranged along a second direction, the second direction intersects the first direction, and the width of the first circuit in the first direction is greater than the width of the second circuit in the first direction; wherein,

[0006] The wiring arrangement area includes a first wiring arrangement area and a second wiring arrangement area. Along the first direction, the first circuit overlaps with the first wiring arrangement area, and the second circuit overlaps with the second wiring arrangement area. The width of the first wiring arrangement area in the first direction is smaller than the width of the second wiring arrangement area in the first direction.

[0007] According to another aspect of the present invention, a display device is provided, comprising the display panel provided by any embodiment of the present invention.

[0008] The technical solution of the embodiment of the present invention adjusts the width of the circuit in the circuit layout area in the first direction so that the width of the first circuit in the first direction is greater than the width of the second circuit in the first direction. Since the first circuit overlaps with the first wiring layout area along the first direction, and the second circuit overlaps with the second wiring layout area along the first direction, and the width of the first wiring layout area in the first direction is less than the width of the second wiring layout area in the first direction, the wiring layout area and the width of the corresponding circuit in the first direction can be complementary, which is not only conducive to achieving a narrow frame, but also can reduce the width of the second circuit in the first direction to leave enough space for the second wiring layout area to set the wiring, thereby improving the product yield.

[0009] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0012] Figure 2 yes Figure 1 A schematic diagram of an enlarged structure of the Q1 region;

[0013] Figure 3 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0014] Figure 4 yes Figure 3 A schematic structural diagram of a pixel in the display panel shown;

[0015] Figure 5 is with Figure 4 The corresponding driving timing diagram of the pixel circuit;

[0016] Figure 6 is a circuit structure diagram of a first circuit and a second circuit provided by an embodiment of the present invention;

[0017] Figure 7 is with Figure 6 A corresponding schematic diagram of the layout structure of a first circuit;

[0018] Figure 8 is with Figure 6 A corresponding schematic diagram of the layout structure of a second circuit;

[0019] Fig. 9 is a circuit structure diagram of another first circuit and a second circuit provided by an embodiment of the present invention;

[0020] Fig.10 is with Fig. 9 A corresponding schematic diagram of the layout structure of a first circuit;

[0021] Fig.11 is with Fig. 9 A corresponding schematic diagram of the layout structure of a second circuit;

[0022] Fig.12 yes Figure 1 Another enlarged structural diagram of the middle Q1 region;

[0023] Fig.13 yes Figure 1 Another enlarged structural diagram of the middle Q1 region;

[0024] Fig.14 is with Fig.13 A corresponding schematic diagram of the layout structure of a first circuit;

[0025] Fig.15 is with Fig.13 A corresponding schematic diagram of the layout structure of a second circuit;

[0026] Fig.16 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0027] Fig.17 yes Fig.16 A schematic diagram of an enlarged structure of the middle Q2 region;

[0028] Fig.18 It is a circuit structure diagram of another first circuit and a second circuit provided by an embodiment of the present invention;

[0029] Fig.19 is with Fig.18 A corresponding schematic diagram of the layout structure of a first circuit;

[0030] Fig. 20 is with Fig.18 A corresponding schematic diagram of the layout structure of a second circuit;

[0031] Fig.21 is with Fig.18 A corresponding schematic diagram of another layout structure of the first circuit;

[0032] Fig. 22 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0033] Fig.23 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0034] Fig.24 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0035] Fig.25 is along Fig.24 A schematic cross-sectional structural diagram of the display panel taken along line VV';

[0036] Fig.26 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0037] Fig. 27It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0039] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0040] First of all, it should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left" and "right" and similar words are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In addition, the shapes and sizes of the components in the accompanying drawings do not reflect the true proportions, and the purpose is only to illustrate the content of the present invention.

[0041] In the related art, in the border area of ​​the display panel, the area where the circuit is arranged (hereinafter referred to as the circuit arrangement area) and the area where the wiring is arranged (hereinafter referred to as the wiring arrangement area) are usually arranged side by side in the direction from the non-display area to the display area. For special-shaped display screens, in the special-shaped border area, the wiring arrangement areas at different positions occupy different widths due to the different number of wirings. For example, for circular, annular or rounded display screens, the closer to the lower border, the more fan-out wirings corresponding to the data lines, that is, the closer to the lower border, the larger the width of the arrangement area of ​​the fan-out wiring, and the circuits arranged side by side will also occupy a certain width, making it more difficult to achieve a narrow border.

[0042] In view of this, an embodiment of the present invention provides a display panel, which includes a first area and a second area, the first area includes a wiring layout area and a circuit layout area, the wiring layout area and the circuit layout area are arranged along a first direction, and at least the second area includes pixels; the circuit layout area includes a first circuit and a second circuit, the first circuit and the second circuit are arranged along a second direction, the second direction intersects with the first direction, and the width of the first circuit in the first direction is greater than the width of the second circuit in the first direction; wherein the wiring layout area includes a first wiring layout area and a second wiring layout area, along the first direction, the first circuit overlaps with the first wiring layout area, the second circuit overlaps with the second wiring layout area, and the width of the first wiring layout area in the first direction is less than the width of the second wiring layout area in the first direction.

[0043] By adopting the above scheme, since the first circuit overlaps with the first wiring layout area along the first direction, the second circuit overlaps with the second wiring layout area along the first direction, and the width of the first wiring layout area in the first direction is smaller than the width of the second wiring layout area, by adjusting the width of the circuit in the circuit layout area in the first direction, the width of the first circuit corresponding to the first wiring layout area in the first direction is made larger than the width of the second circuit corresponding to the second wiring layout area in the first direction, so that the width of the wiring layout area and the corresponding circuit in the first direction can be complementary, which is not only conducive to achieving a narrow frame, but also can reduce the width of the second circuit in the first direction, so that sufficient space for arranging wiring in the second wiring layout area is reserved, thereby improving product yield.

[0044] The above is the core idea of ​​the present invention. The technical scheme of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0045] Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention, such as Figure 1As shown, the display panel 100 includes a first area A1 and a second area A2, the first area A1 includes a wiring layout area 1 and a circuit layout area 2, the wiring layout area 1 and the circuit layout area 2 are arranged along a first direction D1, and at least the second area A2 includes a pixel PX; the circuit layout area 2 includes a first circuit 21 and a second circuit 22, the first circuit 21 and the second circuit 22 are arranged along a second direction D2, the second direction D2 intersects with the first direction D1, and a width C1 of the first circuit 21 in the first direction D1 is greater than a width E1 of the second circuit 22 in the first direction D1; wherein, the wiring layout area 1 includes a first wiring layout area 11 and a second wiring layout area 12, along the first direction D1, the first circuit 21 overlaps with the first wiring layout area 11, the second circuit 22 overlaps with the second wiring layout area 12, and a width B1 of the first wiring layout area 11 in the first direction D1 is less than a width B2 of the second wiring layout area 12 in the first direction D1.

[0046] Reference Figure 1 Optionally, in this embodiment, the first area A1 does not include pixels, and only the second area A2 includes pixels PX. In other words, the first area A1 is a non-display area (frame area), and the second area A2 is a display area.

[0047] Optionally, the display panel provided in the embodiment of the present invention is a special-shaped display screen, at least part of the edge of the display panel is arc-shaped, and the wiring layout area 1 and the circuit layout area 2 overlap with the arc-shaped area in the first area A1. Figure 1 The shape of the display panel is circular as an example for illustration.

[0048] Further, refer to Figure 1 The first area A1 includes a wiring layout area 1 and a circuit layout area 2, the wiring layout area 1 and the circuit layout area 2 are arranged along a first direction D1, the circuit layout area 2 includes a first circuit 21 and a second circuit 22, along the first direction D1, the first circuit 21 overlaps with the first wiring layout area 11, the second circuit 22 overlaps with the second wiring layout area 12, and the first circuit 21 and the second circuit 22 are arranged along the second direction D2. Specifically, a plurality of first circuits 21 and the first wiring layout area 11 are arranged side by side along the first direction D1, a plurality of second circuits 22 and the second wiring layout area 12 are arranged side by side along the first direction D1, and a plurality of first circuits 21 and a plurality of second circuits 22 are arranged along the second direction D2.

[0049] The first direction D1 can be understood as the direction from the first area A1 to the second area A2. It can be understood that for a special-shaped display screen, the first direction D1 will change as the position of the reference point changes. For example Figure 1In the circular display screen shown, the first direction D1 is a radial direction, and the first direction D1 at different positions is different, but all point to the center direction of the circle. The second direction D2 intersects with the first direction D1, so the second direction D2 will also change with the change of the first direction D1.

[0050] Reference Figure 1 Due to the different number of routing lines, the width of the first routing layout area 11 in the first direction D1 is smaller than the width of the second routing layout area 12 in the first direction D1. In this embodiment, by adjusting the width of the circuit in the circuit layout area in the first direction D1, the width of the first circuit 21 corresponding to the first routing layout area 11 in the first direction D1 is set to be larger than the width of the second circuit 22 corresponding to the second routing layout area 12 in the first direction D1, so that the widths of the routing layout area and the corresponding circuit in the first direction D1 can be complementary, which is not only conducive to achieving a narrow frame, but also can reduce the width E1 of the second circuit 22 in the first direction D1, so as to leave enough space for the second routing layout area 12 to set the routing, thereby improving the product yield.

[0051] For example, referring to the above description, the routing area 1 can be used to arrange fan-out routing. Figure 1 The closer to the bottom frame, the greater the number of fan-out wirings, so that the width of the first wiring arrangement area 11 located at the top in the first direction D1 is smaller than the width of the second wiring arrangement area 12 located at the bottom in the first direction D1.

[0052] Accordingly, the circuit layout area 2 can be used to arrange the gate drive circuit, and the gate drive circuit and the fan-out wiring arrangement area are arranged along the first direction D1. The width adjustment method of the gate drive circuit in the first direction D1 will be described in detail later, and will not be repeated here.

[0053] It should be noted that the routing lines arranged in the routing layout area 1 may include but are not limited to fan-out routing lines, and the circuits arranged in the circuit layout area 2 may include but are not limited to gate drive circuits, which are not limited in the embodiment of the present invention. Different routing lines and different circuits may be arranged in different area ranges within the first area 1, which are not limited in the embodiment of the present invention.

[0054] It should also be noted that Figure 1 Only the example of dividing the wiring layout area 1 into two areas with different widths in the first direction D1 (i.e., the first wiring layout area 11 and the second wiring layout area 12) is used for illustration. In other embodiments, the wiring layout area 1 can also be divided into more areas, and the widths of the areas in the first direction D1 are different. The embodiment of the present invention is not limited to this. Accordingly, the circuit layout area 2 can include more circuits with different widths in the first direction to match the widths of each wiring layout area.

[0055] In summary, the embodiment of the present invention adjusts the width of the circuit in the circuit layout area in the first direction so that the width of the first circuit in the first direction is greater than the width of the second circuit in the first direction. Since the first circuit overlaps with the first wiring layout area along the first direction, and the second circuit overlaps with the second wiring layout area along the first direction, and the width of the first wiring layout area in the first direction is less than the width of the second wiring layout area, the wiring layout area and the width of the corresponding circuit in the first direction can be complementary, which is not only conducive to achieving a narrow frame, but also can reduce the width of the second circuit in the first direction to leave enough space for the second wiring layout area to set the wiring, thereby improving the product yield.

[0056] Based on the above embodiments, Figure 1 Optionally, the first circuit 21 and the second circuit 22 have the same circuit structure, and a width C2 of the first circuit 21 in the second direction D2 is smaller than a width E2 of the second circuit 22 in the second direction D2.

[0057] The first circuit 21 and the second circuit 22 have the same circuit structure. Specifically, it can be understood that the components in the first circuit 21 and the second circuit 22 are the same, and the connection relationship between the components is the same.

[0058] Specifically, in this embodiment, the circuit structures of the first circuit 21 and the second circuit 22 are the same, but the layouts of the first circuit 21 and the second circuit 22 are different, or in other words, the layouts of the components in the first circuit 21 and the second circuit 22 are different. For the first circuit 21, by compressing the width C2 of the first circuit 21 along the second direction D2, the width C1 of the first circuit 21 along the first direction D1 is larger, and for the second circuit 22, by increasing the width E2 of the second circuit 22 along the second direction D2, the width E1 of the second circuit 22 along the first direction D1 is smaller. Specifically, by designing the width C2 of the first circuit 21 along the second direction D2 to be smaller than the width E2 of the second circuit 22 along the second direction D2, the width C1 of the first circuit 21 along the first direction D1 is larger than the width E1 of the second circuit 22 along the first direction D1, thereby achieving the design purpose of a narrow frame, and at the same time leaving enough space for the second wiring arrangement area 12 to set wiring.

[0059] Figure 2 yes Figure 1 A schematic diagram of an enlarged structure of the Q1 region in the figure, Figure 2 As shown, optionally, the first circuit 21 and the second circuit 22 include the same first subdivision 201 and the same second subdivision 202; in the first circuit 21, the first subdivision 201 and the second subdivision 202 are arranged side by side along the first direction D1; in the second circuit 22, the first subdivision 201 and the second subdivision 202 are arranged side by side along the second direction D2.

[0060] Specifically, in this embodiment, the first circuit 21 and the second circuit 22 have the same circuit structure, and the components in the circuit structure can be divided into two groups, one group of components constitutes the first subdivision 201, and the other group of components constitutes the second subdivision 202, so that the first circuit 21 and the second circuit 202 have the same first subdivision 201 and second subdivision 202. Further, for the first circuit 21, the first subdivision 201 and the second subdivision 202 are arranged side by side along the first direction D1, and for the second circuit 22, the first subdivision 201 and the second subdivision 202 are arranged side by side along the second direction D2, so that the width C1 of the first circuit 21 in the first direction D1 is greater than the width E1 of the second circuit 22 in the first direction D1, and the width C2 of the first circuit 21 in the second direction D2 is less than the width E2 of the second circuit 22 in the second direction D2, thereby achieving the design purpose of a narrow frame, and at the same time leaving enough space for arranging the wiring in the second wiring arrangement area 12.

[0061] The configuration of the first circuit and the second circuit is described in detail below in conjunction with a specific circuit structure.

[0062] Reference Figure 1 In a specific embodiment, optionally, both the first circuit 21 and the second circuit 22 include a shift register unit VSR, and accordingly, the first wiring layout area 11 and the second wiring layout area 12 are arranged with fan-out wiring.

[0063] Specifically, a plurality of shift register units VSR are cascaded in sequence to form a gate driving circuit, which is used to transmit a gate control signal to a pixel through a scan line to control the light emission of the pixel. Figure 1 As shown, along the first direction, the first wiring layout area 11 and the second wiring layout area 12 overlap with multiple shift register units VSR, wherein the width of the shift register unit VSR corresponding to the first wiring layout area 11 in the first direction D1 is smaller than the width of the shift register unit VSR corresponding to the second wiring layout area 12 in the first direction D1, and the width of the shift register unit VSR corresponding to the first wiring layout area 11 in the second direction D2 is larger than the width of the shift register unit VSR corresponding to the second wiring layout area 12 in the second direction D2, which is conducive to achieving a narrow frame, while leaving enough space for the second wiring layout area 12 to set a larger number of fan-out wiring.

[0064] The display panel generally includes a scanning shift register unit and a light emitting shift register unit. Optionally, the first circuit 21 and the second circuit 22 each include at least one scanning shift register unit and / or at least one light emitting shift register unit.

[0065] Among them, the scanning shift register unit and the light-emitting shift register unit are electrically connected to the pixel through different scanning lines respectively. The pixel driving process includes a pre-stage and a light-emitting stage. The scanning shift register unit is specifically used to provide a gate control signal to the pixel through the scanning line in the pre-stage, and the light-emitting shift register unit is specifically used to provide a gate control signal to the pixel through the scanning line in the light-emitting stage. The two cooperate to realize the light-emitting drive of the pixel.

[0066] For example, Figure 3 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Figure 3 As shown, the display panel 100 includes a scanning shift register unit VSR1 and a light emitting shift register unit VSR2. Figure 4 yes Figure 3 A schematic diagram of the structure of a pixel in a display panel is shown. Figure 5 is with Figure 4 The corresponding pixel circuit driving timing diagram, combined with Figure 3-Figure 5As shown, the pixel PX includes a light emitting element (LED) and a pixel circuit electrically connected to the light emitting element, the display panel 100 includes a first scan line G1, a second scan line G2 and a third scan line G3, the pixel circuit is electrically connected to the first scan line G1, the second scan line G2 and the third scan line G3 respectively, the first scan line G1 and the second scan line G2 are electrically connected to the scan shift register unit VSR1, and the third scan line G3 is electrically connected to the light emitting shift register unit VSR2. The working process of the pixel circuit includes an initialization phase t1, a data writing phase t2 and a light emitting phase t3, wherein the initialization phase t1 and the data writing phase t2 are pre-phases. In the initialization phase t1, the scan shift register unit VSR1 is used to provide an initialization control signal S1 to the pixel circuit through the first scan line G1, so that the initialization transistor T2 is turned on under the control of the initialization control signal S1, so that the initialization signal Vref is written into the gate of the driving transistor T1, and the gate of the driving transistor T1 is initialized. In the data writing stage t2, the scanning shift register unit VSR1 is used to provide the pixel circuit with a data writing control signal S2 through the second scanning line G2, so that the data writing transistor T3 and the threshold compensation transistor T4 are turned on under the control of the data writing control signal S2, so that the data writing transistor T3 writes the data signal Vdata into the gate of the driving transistor T1, and at the same time, the threshold compensation transistor T4 drives the gate of the transistor T1 with the threshold voltage compensation value of the driving transistor T1. In addition, in the data writing stage t2, the reset transistor T7 can be turned on under the control of the data writing control signal S2, and the initialization signal Vref is written into the anode of the light emitting diode LED to reset the anode voltage of the light emitting diode LED. In the light emitting stage t3, the light emitting shift register unit VSR2 is used to provide the pixel circuit with a light emitting control signal EMIT through the third scanning line G3, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on under the control of the light emitting control signal EMIT. Since the storage capacitor Cst stores the gate potential of the driving transistor T1, the driving transistor T1 generates a driving current based on the gate potential and the potential of the first power signal terminal PVDD to drive the LED to emit light. Figure 8 In the embodiment, PVEE is a second power signal terminal, and a potential of the second power signal terminal PVEE is less than a potential of the first power signal terminal PVDD.

[0067] It should be noted that Figure 3Only the case where the first scan line G1 and the second scan line G2 are electrically connected to the same group of shift register units VSR1 is used as an example for illustration. At this time, the gate drive circuit formed by the cascade connection of the group of shift register units VSR1 provides both the initialization control signal S1 and the data writing control signal S2 for the pixel circuit. In other embodiments, the first scan line G1 and the second scan line G2 may also be electrically connected to different groups of shift register units VSR1, and the initialization control signal S1 and the data writing control signal S2 are provided to the pixel circuit respectively through different gate drive circuits.

[0068] Specifically, refer to Figure 3 When the scanning shift register unit VSR1 and the light-emitting shift register unit VSR2 are set in a single-sided driving manner, the optional first circuit 21 and the second circuit 22 both include at least one scanning shift register unit VSR1 or at least one light-emitting shift register unit VSR2. For example, the first circuit and the second circuit located at the left frame of the screen both include at least one scanning shift register unit VSR1, and the first circuit and the second circuit located at the right frame of the screen both include at least one light-emitting shift register unit VSR2. When the scanning shift register unit VSR1 and the light-emitting shift register unit VSR2 are set in a double-sided driving manner, the optional first circuit 21 and the second circuit 22 both include at least one scanning shift register unit VSR1 and at least one light-emitting shift register unit VSR2.

[0069] Figure 6 is a circuit structure diagram of a first circuit and a second circuit provided by an embodiment of the present invention, Figure 7 is with Figure 6 A corresponding schematic diagram of the layout structure of a first circuit, Figure 8 is with Figure 6 A corresponding schematic diagram of the layout structure of the second circuit is shown in FIG. Figure 6-Figure 8 As shown, optionally, the first circuit 21 and the second circuit both include a shift register unit (such as a scan shift register unit VSR1), the shift register unit includes a first type transistor MA and a second type transistor MB, the width-to-length ratio of the first type transistor MA is greater than the width-to-length ratio of the second type transistor MB; the first subsection 201 is at least composed of the first type transistor MA, and the second subsection 202 is at least composed of the second type transistor MB; in the first circuit 21 (such as Figure 7 ), the first subsection 201 and the second subsection 202 are arranged side by side along the first direction D1; in the second circuit 22 (such as Figure 8 ), the first section 201 and the second section 202 are arranged side by side along the second direction D2.

[0070] For example, Figure 6-Figure 8Taking the example that both the first circuit 21 and the second circuit 22 include a scan shift register unit VSR1 , the layout design of the first circuit 21 and the second circuit 22 is illustrated.

[0071] like Figure 6 As shown, the scan shift register unit VSR1 includes eight transistors, such as M1, M2, M3, M4, M5, M6, M7 and M8, wherein the transistors M1, M2, M3, M4, M5 and M6 act as switches and are switch transistors, and their width-to-length ratio is usually small, while the transistor M7 is electrically connected to the output terminal OUT of the scan shift register unit VSR1, and the transistor M8 is electrically connected to the output terminal OUT of the scan shift register unit VSR1, both of which affect the stability of the output signal, therefore, the width-to-length ratio of the transistors M7 and M8 is usually designed to be large. In view of this, the transistors M7 and M8 can be used as the first type of transistors MA, and the transistors M1, M2, M3, M4, M5 and M6 can be used as the second type of transistors MB, the first type of transistors MA constitute the first subdivision 201, and the second type of transistors MB constitute the second subdivision 202, in the first circuit 21 (such as Figure 7 ), the first subsection 201 and the second subsection 202 are arranged side by side along the first direction D1; in the second circuit 22 (such as Figure 8 ), the first division 201 and the second division 202 are arranged side by side along the second direction D2, so that the width of the first circuit 21 in the first direction D1 is greater than the width of the second circuit 22 in the first direction D1, and the width of the first circuit 21 in the second direction D2 is less than the width of the second circuit 22 in the second direction D2, thereby achieving the design purpose of a narrow frame, and at the same time leaving enough space for the second wiring arrangement area 12 to arrange a larger number of fan-out wirings.

[0072] For example, Fig. 9 is a circuit structure diagram of another first circuit and a second circuit provided by an embodiment of the present invention, Fig. 9 Take the example that both the first circuit 21 and the second circuit 22 include a light emitting shift register unit VSR2 for illustration. Fig. 9 As shown, optionally, the transistors M9 and M10 electrically connected to the output terminal OUT of the light emitting shift register unit VSR2 can be used as the first type of transistors MA to form the first subdivision 201, and the remaining transistors (M1, M2, M3, M4, M5, M6, M7, M8 and M11) are electrically connected to the first type of transistors MA, are switch tubes, and can be used as the second type of transistors MB to form the second subdivision 202. The layout of the light emitting shift register unit VSR2 corresponding to the first circuit 21 and the second circuit 22 can be referred to Figure 7 and Figure 8 The layout of the scan shift register unit VSR1 is designed, and will not be illustrated one by one here.

[0073] It should be noted that Figure 6 and Fig. 9 The circuit structure of the shift register unit shown is for illustration only and is not intended to be limiting. Currently, the scanning shift register unit and the light emitting shift register unit can adopt a variety of different circuit structures. Each circuit structure can refer to the following rules to classify the transistors in the shift register unit, and then determine the first division and the second division according to the division result. In the layout design of the first circuit, the first division and the second division are arranged side by side along the first direction. In the layout design of the second circuit, the first division and the second division are arranged side by side along the second direction to achieve the purpose of the invention of this application. Specifically, refer to Figure 6 and Fig. 9 As an example, optionally, a rule for determining whether each transistor in the shift register unit belongs to the first type transistor MA or the second type transistor MB is as follows: the first type transistor MA is electrically connected to the output terminal OUT of the shift register unit; the second type transistor MB is electrically connected to the first type transistor MA.

[0074] Reference Figure 6 or Fig. 9 , the shift register unit also includes capacitors, such as Figure 6 The two capacitors (C1 and C2) in the scan shift register unit VSR1 are shown. Fig. 9 The four capacitors (C1, C2, C3 and C4) in the light emitting shift register unit VSR2 are shown. The capacitors in the shift register unit can be divided into the first subsection or the second subsection according to the principle of proximity, which is not limited in the embodiment of the present invention.

[0075] For example, refer to Figure 6-Figure 8 In the scan shift register circuit VSR1, the capacitor C1 is electrically connected to the gate of the transistor M7, and the capacitor C2 is electrically connected to the gate of the transistor M8. Therefore, in the layout design, the capacitor C1 is adjacent to the transistor M7, and one of the capacitor plates of the capacitor C1 can be formed by the gate of the transistor M7. Similarly, the capacitor C2 is adjacent to the transistor M8, and one of the capacitor plates of the capacitor C2 can be formed by the gate of the transistor M8. Therefore, Figure 6 In the scan shift register unit shown, the capacitor C1 and the capacitor C2 can be divided into a first subsection 201 .

[0076] Fig.10 is with Fig. 9 A corresponding schematic diagram of the layout structure of a first circuit, Fig.11 is with Fig. 9 A corresponding schematic diagram of the layout structure of the second circuit, refer to Figure 9-11Optionally, both the first circuit 21 and the second circuit 22 include a shift register unit (such as a light emitting shift register unit VSR2); the shift register unit includes a first type transistor MA, which is electrically connected to the output terminal OUT of the shift register unit; the first type transistor MA includes a plurality of first sub-transistors MU arranged in parallel; the first circuit 21 includes a first shift register unit 211, in which all the first sub-transistors MU in the first type transistor MA are arranged in an a*b array in the first direction D1 and the second direction D2; the second circuit 22 includes a second shift register unit 221, in which all the first sub-transistors MU in the first type transistor MA are arranged in a c*d array in the first direction D1 and the second direction D2; wherein a and c represent the number of the first sub-transistors MU in the first direction D1, and b and d represent the number of the first sub-transistors MU in the second direction D2; a×b=c×d; in the first direction, a>c; in the second direction, b<d.

[0077] Referring to the above description, the first type of transistor MA has a large width-to-length ratio, and the layout design of such transistors is usually implemented by connecting multiple transistors with small width-to-length ratios in parallel. In this embodiment, the first type of transistor MA is obtained by connecting N first sub-transistors MU in parallel (N=a×b=c×d).

[0078] Specifically, this embodiment adjusts the arrangement of the N first sub-transistors MU in the first type of transistors MA in the first direction D1 and the second direction D2. For any first type of transistors MA, the number a of the first sub-transistors MU in the first direction D1 in the layout design of the first circuit 21 is greater than the number c of the first sub-transistors MU in the first direction D1 in the layout design of the second circuit 22, and the number b of the first sub-transistors MU in the second direction D2 in the layout design of the first circuit 21 is less than the number d of the first sub-transistors MU in the second direction D2 in the layout design of the second circuit 22, so as to achieve that the width of the first circuit 21 in the first direction D1 is greater than the width of the second circuit 22 in the first direction D1, and the width of the first circuit 21 in the second direction D2 is less than the width of the second circuit 22 in the second direction D2, thereby achieving the design purpose of a narrow frame, and at the same time leaving enough space for the second wiring layout area 12 to set a large number of fan-out wirings.

[0079] For example, refer to Figure 9-11 In the light emitting shift register unit VSR2 shown in FIG. 1 , transistors M9 and M10 are first-type transistors MA. Fig.10 and Fig.11In the first circuit 21 and the second circuit 22, the transistor M9 is composed of 10 first sub-transistors MU connected in parallel. The difference is that in the first circuit 21, the 10 first sub-transistors MU in the transistor M9 are arranged in a 2*5 array in the first direction D1 and the second direction D2 (i.e., a=2, b=5), while in the second circuit 22, the 10 first sub-transistors MU in the transistor M9 are arranged in a 1*10 array in the first direction D1 and the second direction D2 (i.e., c=1, d=10). In the first circuit 21 and the second circuit 22, the transistor M10 is also composed of 10 first sub-transistors MU connected in parallel, and the layout design is the same as that of the transistor M9, which will not be repeated here. Comparison Fig.10 and Fig.11 It can be seen that by performing the above-mentioned differentiated arrangement of the first type of transistors in the layout of the first circuit and the second circuit, the width of the first type of transistor MA in the first circuit 21 in the first direction D1 can be greater than the width of the first type of transistor MA in the second circuit 22 in the first direction D1, and the width of the first type of transistor MA in the first circuit 21 in the second direction D2 can be less than the width of the first type of transistor MA in the second circuit 22 in the second direction D2. Since the first type of transistor MA is larger in size, it occupies a larger area in the layout of the shift register unit, which is conducive to achieving that the width of the first circuit 21 in the first direction D1 is greater than the width of the second circuit 22 in the first direction D1, and the width of the first circuit 21 in the second direction D2 is less than the width of the second circuit 22 in the second direction, thereby achieving the design purpose of a narrow frame, and at the same time leaving enough space for the second wiring layout area 12 to set a larger number of fan-out wiring.

[0080] According to the above description, the shift register unit can be divided into a first section consisting of a first type of transistor MA and a second section consisting of a second type of transistor MB. It should be noted that: Fig.10 and Fig.11 Only the arrangement of the first sub-transistor MU in the first type of transistor MA in the first circuit 21 and the second circuit 22 is different, and the first division 201 and the second division 202 are both arranged side by side along the second direction D2. In other embodiments, the first division 201 and the second division 202 are both arranged side by side along the second direction D2 or are both arranged side by side along the first direction; or, when the arrangement of the first sub-transistor MU in the first type of transistor MA in the first circuit 21 and the second circuit 22 is different, the arrangement of the first division 201 and the second division 202 in the first circuit 21 and the second circuit 22 may also be different. For example, the first division 201 and the second division 202 in the first circuit 21 may be arranged side by side along the first direction D1, and the first division 201 and the second division 202 in the second circuit 22 may be arranged side by side along the second direction D2, with reference to the above embodiment.

[0081] Similarly, refer to Figure 7 and Figure 8 , Figure 7 and Figure 8 Only the arrangement of the first sub-section 201 and the second sub-section 202 in the first circuit 21 and the second circuit 22 is different, while the arrangement of the first sub-transistors in the first type of transistors MA (such as M7 and M8) is the same is used as an example for illustration. In other embodiments, Figure 7 and Figure 8 When only the arrangement of the first sub-sections 201 and the second sub-sections 202 in the first circuit 21 and the second circuit 22 is different, the first sub-transistors MU in the first type of transistors MA may also be arranged differently in the first circuit 21 and the second circuit 22 .

[0082] In summary, when the first circuit and the second circuit include shift register units (scanning shift register units and / or light-emitting shift register units), the layouts of the first circuit and the second circuit can be adjusted by adjusting the arrangement of the first division and the second division, and / or adjusting the arrangement of the first sub-transistor in the first type of transistor, so as to meet the design requirements for the relative sizes of the first circuit and the second circuit in the first direction and the second direction.

[0083] The above embodiments illustrate the layout design of the first circuit and the second circuit by taking the first circuit and the second circuit including a scanning shift register unit or including a light emitting shift register unit as an example. Fig.12 yes Figure 1 Another enlarged structural diagram of the Q1 region is shown in Figure 2. Fig.12 As shown, optionally, the first circuit 21 and the second circuit 22 each include at least one scanning shift register unit VSR1 and at least one light emitting shift register unit VSR2, and the scanning shift register unit VSR1 and the light emitting shift register unit VSR2 are arranged side by side along the first direction D1. In this way, the scanning shift register unit VSR1 and the light emitting shift register unit VSR2 can be arranged on both the left and right sides of the second area A2 to achieve bilateral driving and ensure display effect.

[0084] Specifically, when the first circuit 21 and the second circuit 22 include both the scanning shift register unit VSR1 and the light emitting shift register unit VSR2, the layout of at least one of the scanning shift register unit VSR1 and the light emitting shift register unit VSR2 can be optionally adjusted, and the adjustment method can refer to the above description, which will not be repeated here. In addition, when the layouts of the scanning shift register unit VSR1 and the light emitting shift register unit VSR2 in the first circuit and the second circuit are different, the layout adjustment method of the scanning shift register unit VSR1 and the layout adjustment method of the light emitting shift register unit VSR2 can be the same or different, and the embodiment of the present invention does not limit this.

[0085] Fig.13 yes Figure 1 Another enlarged structural diagram of the Q1 region is shown in Figure 2. Fig.13 As shown, optionally, the first circuit 21 and the second circuit 22 each include at least two scanning shift register units VSR1 and at least one light emitting shift register unit VSR2; at least two scanning shift register units VSR1 are arranged side by side along the second direction D2, and along the first direction D1, the light emitting shift register unit VSR2 overlaps with at least two scanning shift register units VSR1.

[0086] Specifically, in this embodiment, the light-emitting shift register unit VSR2 overlaps with at least two scanning shift register units VSR1 along the first direction D1. At this time, the light-emitting shift register unit VSR2 can simultaneously provide light-emitting control signals for at least two rows of pixel circuits, and simultaneously control the light emission of at least two rows of pixels, thereby reducing the number of settings of the light-emitting shift register unit VSR2 and reducing the difficulty of layout design.

[0087] For example, Fig.13 Take an example where one light-emitting shift register unit VSR2 and two scanning shift register units VSR1 overlap along the first direction D1. Fig.14 is with Fig.13 A corresponding schematic diagram of the layout structure of a first circuit, Fig.15 is with Fig.13 A corresponding schematic diagram of the layout structure of the second circuit is shown in FIG. Fig.14As shown, in the first circuit 21, the first division 201 and the second division 202 in the optional scanning shift register unit VSR1 are arranged side by side along the first direction D1, the two scanning shift register units VSR1 are arranged side by side along the second direction D2, the first division 201 and the second division 202 in the light emitting shift register unit VSR2 are arranged side by side along the second direction D2, and all first sub-transistors MU of the first type transistor MA in the first division 201 are arranged in an a*b array along the first direction D1 and the second direction D2 (for transistor M9, a=2, b=5; for transistor M10, a=2, b=5). In the second circuit, the first division 201 and the second division 202 in the optional scanning shift register unit VSR1 are arranged side by side along the second direction D2, the two scanning shift register units VSR1 are arranged side by side along the second direction D2, the first division 201 and the second division 202 in the light-emitting shift register unit VSR2 are arranged side by side along the second direction D2, and all first sub-transistors MU of the first type transistor MA in the first division 201 are arranged in a c*d array along the first direction D1 and the second direction D2 (for transistor M9, c=1, d=10; for transistor M10, c=1, d=10). By such arrangement, the width of the scanning shift register unit VSR1 in the first circuit 21 along the first direction D1 is greater than the width of the scanning shift register unit VSR1 in the second circuit 22 along the first direction D1, the width of the scanning shift register unit VSR1 along the second direction D2 is less than the width of the scanning shift register unit VSR1 in the second circuit 22 along the second direction D2, the width of the light-emitting shift register unit VSR2 along the first direction D1 is greater than the width of the light-emitting shift register unit VSR2 in the second circuit 22 along the first direction D1, and the width of the light-emitting shift register unit VSR2 along the second direction D2 is less than the width of the light-emitting shift register unit VSR2 in the second circuit 22 along the second direction D2, so that the width of the first circuit 21 in the first direction D1 is greater than the width of the second circuit 22 in the first direction D1, and the width of the first circuit 21 in the second direction D2 is less than the width of the second circuit 22 in the second direction D2, thereby achieving the design purpose of a narrow frame, and at the same time leaving enough space for the second wiring arrangement area 12 to arrange a large number of fan-out wirings. In addition, since the light-emitting shift register unit VSR2 overlaps with the two scanning shift register units VSR1 along the first direction D1 at the same time, by arranging the first division 201 and the second division 202 in the light-emitting shift register unit VSR2 to be arranged side by side along the second direction D2 in the first circuit 21 and the second circuit 22, it is beneficial for the size of the light-emitting shift register unit VSR2 along the second direction D2 to be consistent with the size of the two scanning shift register units VSR1 along the second direction D2, thereby reducing space waste.

[0088] Reference Figure 1When the first wiring layout area 11 and the second wiring layout area 12 are used to arrange fan-out wiring, and the circuit layout area 2 is used to arrange the shift register unit VSR, optionally, the first circuit 21 is located on the side of the first wiring layout area 11 close to the second area A2; the second circuit 22 is located on the side of the second wiring layout area 12 close to the second area A2. In this way, the shift register unit VSR can be located on the side of the fan-out wiring close to the display area, which is beneficial for both the electrical connection of the shift register unit VSR with the scan line and the electrical connection of the fan-out wiring with the pad in the binding area A11. Among them, the binding area A11 is used to bind the driver chip, or to bind the circuit board, so as to be electrically connected to the driver chip through the circuit board. The driver chip is used to realize the transmission of data signals by electrically connecting the fan-out wiring to the data line, and is also used to transmit control signals to the shift register unit (for example Figure 6 and Fig. 9 The start signals STV and IN, clock signals CK and XCK, power signals VGH and VGL, etc. shown in FIG. 1 are used to control the working state of the shift register unit VSR.

[0089] In summary, the above embodiments take the case where the first circuit and the second circuit have the same structure and both include a shift register unit as an example, and explain in detail how to achieve the effect of reducing the border width by making the width of the first circuit in the first direction greater than the width of the second circuit in the first direction, and the width of the first circuit in the second direction less than the width of the second circuit in the second direction.

[0090] In other embodiments, Fig.16 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Fig.17 yes Fig.16 A schematic diagram of an enlarged structure of the Q2 region, such as Fig.16 and Fig.17 As shown, optionally, both the first circuit 11 and the second circuit 12 include an electrostatic protection circuit ESD, and accordingly, the first wiring arrangement area 11 and the second wiring arrangement area 12 are arranged with data compensation wiring 3 .

[0091] Reference Fig.16 and Fig.17 For a special-shaped screen, the length of the data line S at different positions of the special-shaped area of ​​the display panel is different (the length specifically refers to the length of the data line in the display area), for example Fig.16 In the circular display panel shown, the closer to the edge of the panel, the shorter the length of the data line S is, and the closer to the center of the panel, the longer the length of the data line S is. Fig.16 The length of the data line Si is smaller than that of the data line Sj, and the length of the data line Sj is smaller than that of the data line Sk. This results in different loads on different data lines, and load compensation is required to ensure that the loads of different data lines are the same, thereby ensuring display uniformity.

[0092] The data compensation line 3 is used to perform load compensation on the data line. Fig.17 The data compensation line 3 overlaps with the data line S extending to the first area A1, and the two form a capacitor. The load compensation of the data line is performed by means of the compensation capacitor, which is referred to as RC compensation. The size of the compensation capacitor is determined according to the length of the data line. Specifically, the smaller the length of the data line, the larger the compensation capacitor required, that is, the longer the length of the data compensation line 3 is. For example Fig.17 As shown, the length of the data compensation line 3i corresponding to the data line Si is greater than the length of the data compensation line 3j corresponding to the data line Sj, and the length of the data compensation line 3j corresponding to the data line Sj is greater than the length of the data compensation line 3k corresponding to the data line Sk.

[0093] The electrostatic protection circuit ESD is used to provide electrostatic protection for the data line S. Fig.17 The data line S is electrically connected to the electrostatic protection circuit ESD. When there is an abnormality in the signal transmitted on the data line S, the abnormal charge can be eliminated by the electrostatic protection circuit ESD to protect the data line.

[0094] Since the wiring layout area 1 for arranging the data compensation wiring 3 and the circuit layout area 2 for arranging the electrostatic protection circuit ESD are arranged along the first direction D1, and the lengths of the data compensation wiring 3 in different areas along the first direction D1 are different, that is, the occupied spaces are not equal, this embodiment differentiates the layout of the electrostatic protection circuit ESD, that is, the width of the electrostatic protection circuit ESD corresponding to the first circuit 21 along the first direction D1 is set to be greater than the width of the electrostatic protection circuit ESD corresponding to the second circuit 22 along the first direction D1, so that the width of the electrostatic protection circuit ESD and the data compensation wiring 3 in the first direction can be complementary, which is conducive to achieving a narrow frame, and can also leave enough space for the second wiring layout area 12 to set a longer data compensation wiring by reducing the width of the electrostatic protection circuit ESD corresponding to the second circuit 22 along the first direction D1, thereby ensuring the load consistency of the data line and improving the display effect.

[0095] Fig.18 is a circuit structure diagram of another first circuit and a second circuit provided by an embodiment of the present invention, Fig.19 is with Fig.18 A corresponding schematic diagram of the layout structure of a first circuit, Fig. 20 is with Fig.18 A corresponding schematic diagram of the layout structure of the second circuit is shown in FIG. Figure 18-Figure 20As shown, optionally, the electrostatic protection circuit ESD includes a first switch unit 41 and a second switch unit 42, the first end of the first switch unit 41 is electrically connected to the first level signal terminal VGH, the second end of the first switch unit 41, the first end of the second switch unit 42 and the data line S are connected to the first node N1, the second end of the second switch unit 42 is electrically connected to the second level signal terminal VGL, the voltage of the first level signal of the first level signal terminal VGH is greater than the voltage of the second level signal of the second level signal terminal VGL; the control end of the first switch unit 41 is electrically connected to the first level signal terminal VGH, and the control end of the second switch unit 42 is electrically connected to the first node N1; the first division 201 is composed of the first switch unit 41, and the second division 202 is composed of the second switch unit 42. In the electrostatic protection circuit ESD corresponding to the first circuit 21, the first division 201 (i.e., the first switch unit 41) and the second division 202 (i.e., the second switch unit 42) are arranged side by side along the first direction D1, and in the electrostatic protection circuit ESD corresponding to the second circuit 22, the first division 201 (i.e., the first switch unit 41) and the second division 202 (i.e., the second switch unit 42) are arranged side by side along the second direction D2, thereby achieving that the width of the first circuit 21 along the first direction D1 is greater than the width of the second circuit 22 along the first direction D1, and the width of the first circuit 21 along the second direction D2 is less than the width of the second circuit 22 along the second direction D2, which can achieve the design purpose of reducing the border width and providing sufficient space for the second wiring layout area to layout longer data compensation wiring.

[0096] Reference Fig.18 Optionally, the first switch unit 41 includes a first switch transistor K1 and a second switch transistor K2 connected in series, and the control ends of the first switch transistor K1 and the second switch transistor K2 are electrically connected to the first level signal end VGH; the second switch unit 42 includes a third switch transistor K3 and a fourth switch transistor K4 connected in series, and the control ends of the third switch transistor K3 and the fourth switch transistor K4 are electrically connected to the first node N1.

[0097] Specifically, the data signal data on the data line S serves as the input signal IN of the electrostatic protection circuit ESD. When the voltage of the data signal data is less than the second level signal (VGL), the signal is abnormal. At this time, the third switch transistor K3 and the fourth switch transistor K4 are turned on, and the abnormal charge can be conducted away through the path where the second switch unit 42 is located. When the voltage of the data signal data is greater than the first level signal (VGH), the signal is abnormal. At this time, the first switch transistor K1 and the second switch transistor K2 are turned on, and the abnormal charge can be conducted away through the path where the first switch unit 41 is located, thereby ensuring that the voltage on the data line is within a safe range and playing a role in electrostatic protection.

[0098] Furthermore, compared Fig.19 and Fig. 20 Optionally, the first circuit 21 includes a first electrostatic protection circuit SED1, in which the first switch transistor K1, the second switch transistor K2, the third switch transistor K3 and the fourth switch transistor K4 are arranged side by side along the first direction D1; the second circuit 22 includes a second electrostatic protection circuit ESD2, in which the first switch transistor K1, the second switch transistor K2, the third switch transistor K3 and the fourth switch transistor K4 are arranged side by side along the second direction D2. In this way, the width of the first electrostatic protection circuit ESD1 along the first direction D1 can be greater than the width of the second electrostatic protection circuit ESD2 along the first direction D1, and the width of the first electrostatic protection circuit ESD1 along the second direction D2 can be less than the width of the second electrostatic protection circuit ESD2 along the second direction D2, so as to achieve the design purpose of reducing the frame width and providing enough space for the second wiring layout area to arrange a longer data compensation wiring.

[0099] Fig.21 is with Fig.18 A corresponding schematic diagram of another layout structure of the first circuit is shown in FIG. Fig.21 As shown, in other embodiments, optionally in the first electrostatic protection circuit ESD1, the first switch transistor K1 and the second switch transistor K2 are arranged side by side along the second direction D2, the third switch transistor K3 and the fourth switch transistor K4 are arranged side by side along the second direction D2, and the first switch unit 41 composed of the first switch transistor K1 and the second switch transistor K2 and the second switch unit 42 composed of the third switch transistor K3 and the fourth switch transistor K4 are arranged side by side along the first direction. Fig.21 and Fig. 20 With such a configuration, it can also be achieved that the width of the first electrostatic protection circuit ESD1 along the first direction D1 is greater than the width of the second electrostatic protection circuit ESD2 along the first direction D1, and the width of the first electrostatic protection circuit ESD1 along the second direction D2 is less than the width of the second electrostatic protection circuit ESD2 along the second direction D2, which can achieve the design purpose of reducing the border width and providing sufficient space for the second wiring layout area to layout longer data compensation wiring.

[0100] Reference Fig.16 When the wiring layout area 1 is used to layout the data compensation wiring and the circuit layout area 2 is used to layout the electrostatic protection circuit ESD, optionally, the first circuit 21 is located on the side of the first wiring layout area 11 away from the second area A2; the second circuit 22 is located on the side of the second wiring layout area 12 away from the second area A2. In this way, the electrostatic protection circuit ESD can be electrically connected to the end of the data line S to ensure the electrostatic protection effect.

[0101] Fig. 22is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig. 22 As shown, when both the first circuit 21 and the second circuit 22 include an electrostatic protection circuit ESD, optionally, the display panel 100 further includes a third circuit 5 and a fourth circuit 6, wherein the third circuit 5 is located on a side of the first circuit 21 away from the first wiring layout area 11, and the fourth circuit 6 is located on a side of the second circuit 22 away from the second wiring layout area 12; the width of the third circuit 5 in the first direction D1 is smaller than the width of the fourth circuit 6 in the first direction D1; the width of the third circuit 5 in the second direction D2 is larger than the width of the fourth circuit 6 in the second direction D2. In this way, the widths of the third circuit 5 and the first circuit 21 in the first direction D1 can be complementary, and the widths of the fourth circuit 6 and the second circuit 22 in the first direction D1 can be complementary, which is conducive to further making full use of the space on the side of the circuit layout area corresponding to the electrostatic protection circuit away from the wiring layout area corresponding to the data compensation wiring, thereby improving space utilization.

[0102] It should be noted that, in other embodiments, when the widths of the circuit layout area corresponding to the electrostatic protection circuit and the wiring layout area corresponding to the data compensation wiring at different positions along the first direction are basically the same, the widths of the third circuit and the fourth circuit in the first direction may not be set differently, and technical personnel in this field may design it according to actual needs.

[0103] Reference Fig. 22 Optionally, the third circuit 5 and the fourth circuit 6 include a shift register unit VSR. The third circuit 5 and the fourth circuit 6 may include shift register units VSR with the same circuit structure, for example, both include at least one scanning shift register unit VSR1 and / or at least one light emitting shift register unit VSR2. The layout design of the third circuit 5 and the fourth circuit 6 may be performed with reference to the scheme of the above embodiment, so as to realize that the width of the third circuit 5 in the first direction D1 is smaller than the width of the fourth circuit 6 in the first direction D1; the width of the third circuit 5 in the second direction D2 is larger than the width of the fourth circuit 6 in the second direction D2, which will not be described in detail here.

[0104] In summary, the above embodiments take the example that the circuit structures of the first circuit and the second circuit are the same and both include an electrostatic protection circuit, and explain in detail how to achieve the effect of reducing the border width by making the width of the first circuit in the first direction greater than the width of the second circuit in the first direction, and the width of the first circuit in the second direction less than the width of the second circuit in the second direction.

[0105] In other embodiments, the first circuit and the second circuit may also have different circuit structures. Fig.23 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.23As shown, optionally, a width C1 of the first circuit 21 in the first direction D1 is greater than a width E1 of the second circuit 22 in the first direction D1, and a width C2 of the first circuit 21 in the second direction D2 is equal to a width E2 of the second circuit 22 in the second direction D2.

[0106] In this embodiment, the first circuit 21 and the second circuit 22 have different circuit structures, specifically, the first circuit 21 and the second circuit 22 may include different components, or the first circuit 21 and the second circuit 22 may include different numbers of circuits, which is not limited in this embodiment of the present invention. The width C1 of the first circuit 21 in the first direction D1 is greater than the width E1 of the second circuit 22 in the first direction D1, which is conducive to achieving a narrow frame and leaving enough space for the second wiring arrangement area 12 to arrange wiring.

[0107] In a specific embodiment, referring to Fig.23 Optionally, the first circuit 21 includes at least one scanning shift register unit VSR1 and at least one light emitting shift register unit VSR2; the second circuit 22 includes one scanning shift register unit VSR1 or one light emitting shift register unit VSR2.

[0108] In this embodiment, the width of the first circuit 21 along the first direction D1 can be understood as the sum of the widths of the scanning shift register unit VSR1 and the light-emitting shift register unit VSR2 along the first direction D1. Since the first circuit 21 includes both the scanning shift register circuit VSR1 and the light-emitting shift register unit VSR2, and the second circuit 22 includes one scanning shift register unit VSR1 or one light-emitting shift register unit VSR2, the width of the first circuit 21 along the first direction is greater than the width of the second circuit 22 along the first direction.

[0109] In this embodiment, the width of the first circuit 21 in the second direction D2 is equal to the width of the second circuit 22 in the second direction D2, which can be understood as the width of the second circuit 22 and the portion of the first circuit 21 having the same circuit structure along the second direction being equal. Exemplarily, when the second circuit 22 includes a scanning shift register unit VSR1, the width of the second circuit 22 along the second direction is equal to that of the scanning shift register unit VSR1 in the first circuit 21, and when the second circuit 22 includes a light emitting shift register unit VSR2, the width of the second circuit 22 along the second direction is equal to that of the light emitting shift register unit VSR2 in the first circuit 21.

[0110] As described above, when the wiring layout area 1 is used to arrange fan-out wiring, the closer to the lower frame, the more fan-out wiring there is, so that the width of the first wiring layout area 11 located at the upper position in the first direction D1 is smaller than the width of the second wiring layout area 12 located at the lower position in the first direction D1. By setting the width of the first circuit in the first direction D1 to be larger than the width of the second circuit 22 in the first direction D1, a narrow frame can be achieved, and at the same time, sufficient space is reserved for the second wiring layout area 12 to arrange a larger number of fan-out wiring. In the display panel, the shift register unit VSR can be set in a single-side drive mode or a double-side drive mode, refer to Fig.23 Since the closer to the lower frame, the fewer pixels are connected on the scan line, the fewer pixels are driven by the shift register unit. Therefore, in this embodiment, by setting the first circuit 21 to include both the scanning shift register unit VSR1 and the light emitting shift register unit VSR2, double-sided driving can be achieved, which can not only meet the driving requirements for a larger number of pixels, but also enable the first circuit 21 to have a larger width in the first direction D1. By setting the second circuit 22 to include the scanning shift register unit VSR1 or the light emitting shift register unit VSR2, the second circuit 22 can have a smaller width in the first direction while meeting the driving requirements for a smaller number of pixels, thereby achieving design purposes such as a narrow frame.

[0111] It should be noted that Fig.23 The first circuit 21 includes a scanning shift register unit VSR1 and a light emitting shift register unit VSR2 as an example for illustration. In other embodiments, the first circuit 21 may include a larger number of scanning shift register units VSR1 and / or a larger number of light emitting shift register units VSR2, which is not limited in the embodiment of the present invention. Fig.23 Only the example in which the second circuit 22 in the left frame of the panel includes the light-emitting shift register unit VSR2 and the second circuit in the right frame includes the scanning shift register unit VSR1 is used for illustration. In other embodiments, the second circuit 22 in the left frame may include the scanning shift register unit VSR1 and the second circuit in the right frame may include the light-emitting shift register unit VSR2, and the embodiment of the present invention does not limit this.

[0112] Fig.24 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.24As shown, in a specific embodiment, optionally, the first wiring layout area 11 includes a first sub-wiring layout area 11a and a second sub-wiring layout area 11b, and the second wiring layout area 12 includes a third sub-wiring layout area 12a and a fourth sub-wiring layout area 12b; the first sub-wiring layout area 11a and the third sub-wiring layout area 12a are connected to form a first circuit area F1, and the second sub-wiring layout area 11b and the fourth sub-wiring layout area 12b are connected to form a second circuit area F2; the first circuit 21 includes a first sub-circuit 21a and a second sub-circuit 21b, and the second circuit 22 includes a third sub-circuit 22a and a fourth sub-circuit 22b; along the first direction D1, the first sub-circuit 21a and the first sub-wiring layout area 12a are connected to each other to form a first circuit area F1, and the second sub-wiring layout area 11b and the fourth sub-wiring layout area 12b are connected to each other to form a second circuit area F2. The first sub-circuit 21a overlaps with the second sub-wiring layout area 11a, the second sub-circuit 21b overlaps with the second sub-wiring layout area 11b, the third sub-circuit 22a overlaps with the third sub-wiring layout area 12a, and the fourth sub-circuit 22b overlaps with the fourth sub-wiring layout area 12b; the first line area F1 is arranged with fan-out wiring, the first sub-circuit 21a and the third sub-circuit 22a include a shift register unit VSR; the second line area F2 is arranged with data compensation wiring, the second sub-circuit 21b and the fourth sub-circuit 22b include an electrostatic protection circuit ESD, and the electrostatic protection circuit ESD is electrically connected to the data line; the first area A1 includes a binding area A11, and the first line area F1 is located on the side of the second line area F2 close to the binding area A11.

[0113] Specifically, the fan-out routing needs to be electrically connected to the data line of the display area (such as the second area A2) and the pad in the binding area A11 respectively to realize the transmission of the data signal, and the data compensation routing needs to overlap with the data line to form a capacitor to compensate for the load of the data line. In view of this, in order to simultaneously meet the wiring requirements of the fan-out routing and the data compensation routing and reduce the wiring difficulty, in this embodiment, the first circuit area F1 for arranging the fan-out routing is set on the side of the second circuit area F2 for arranging the data compensation routing close to the binding area A11.

[0114] Further, referring to the above description, in the special-shaped display screen, different positions of the first circuit area F1 where the fan-out routing is located have different widths in the first direction. In order to achieve a narrow frame and meet the wiring requirements of the fan-out routing, the shift register unit overlapping with the first circuit area along the first direction can be adjusted in the layout. The specific adjustment method can be referred to the above description and will not be repeated here.

[0115] In addition, referring to the above description, in the special-shaped display screen, different positions of the second circuit area F2 where the data compensation line is located have different widths in the first direction. In order to achieve a narrow frame and meet the wiring requirements of the data compensation line, the electrostatic protection circuit overlapping with the second circuit area along the first direction can be adjusted in layout. The specific adjustment method can be referred to the above description and will not be repeated here.

[0116] Further, refer to Fig.24 For the shift register unit VSR overlapping with the second line region F2 and the electrostatic protection circuit ESD in the first direction D1, the widths thereof in the first direction may be equal or unequal, which is not limited in the embodiment of the present invention. Fig.24 , the third circuit 5 and the fourth circuit 6 can be shift register units, wherein the third circuit 5 is located on the side of the second sub-circuit 21b away from the first sub-wiring layout area 11b, and the fourth circuit 6 is located on the side of the fourth sub-circuit 22b away from the fourth sub-wiring layout area 12b; the width of the third circuit 5 in the first direction D1 is smaller than the width of the fourth circuit 6 in the first direction D1. In this way, the widths of the third circuit 5 and the second sub-circuit 21b in the first direction D1 can be complementary, and the widths of the fourth circuit 6 and the fourth sub-circuit 22b in the first direction D1 can be complementary, which is conducive to further making full use of the space on the side of the circuit layout area corresponding to the electrostatic protection circuit away from the wiring layout area corresponding to the data compensation wiring, thereby improving space utilization.

[0117] For example, Fig.25 is along Fig.24 A schematic diagram of the cross-sectional structure of the display panel taken at VV', as shown in FIG. Fig.24 and Fig.25 As shown, optionally, the wiring arrangement area 1 includes a first wiring 101 and a second wiring 102 , at least a portion of the first wiring 101 is located in the first metal layer Y1 , and at least a portion of the second wiring 102 is located in the second metal layer Y2 .

[0118] Specifically, by dividing the routing in the routing layout area 1 into a first routing 101 and a second routing 102, at least a portion of the first routing 101 is set on the first metal layer Y1, and at least a portion of the second routing 102 is set on the second metal layer Y2, the routing in the routing layout area is set by different metal layers, which is helpful to reduce the risk of short circuit between the routings.

[0119] For example, refer to Fig.25 In a specific embodiment, the first routing line 101 and the second routing line 102 may be alternately arranged along the first direction D1, the first routing line 101 is located in the first metal layer Y1, and the second routing line 102 is located in the second metal layer Y2.

[0120] Exemplarily, referring to the above description, the circuit arranged in the circuit arrangement area 2 generally includes components such as a transistor T and a capacitor C, the transistor T includes a gate GE, a source SE and a drain DE, the capacitor C includes a first electrode CE1 and a second electrode CE2, and the first metal layer Y1 and the second metal layer Y2 can be two of the gate GE, the source SE, the drain DE, the first electrode CE1 and the second electrode CE2 located in different film layers. Exemplarily, Fig.25Taking the gate GE and the first electrode CE1 as being located in the same metal film layer, the source SE and the drain DE as being located in the same metal film layer, the second electrode CE2 as being located between the two metal film layers, the first metal layer Y1 as the film layer where the gate GE is located, and the second metal layer Y2 as the film layer where the second electrode CE2 is located as an example for illustration. In other embodiments, the first metal layer where the first wiring 101 is located and the second metal layer where the second wiring 102 is located may also select other metal film layers, which is not limited in the embodiment of the present invention.

[0121] It should also be noted that Fig.25 The cross section of the first circuit area where the fan-out wiring is located is taken as an example for illustration. The data compensation wiring may also be arranged in different metal film layers, which is not limited in the embodiment of the present invention.

[0122] It should also be noted that the above embodiments are only illustrated by taking the shape of a circular display panel as an example. In other embodiments, the display panel may also be annular, or may also be a display panel with partially rounded corners, which is not limited in the embodiments of the present invention. Fig.26 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.26 As shown, optionally, the first area A1 includes a rounded corner area A12 , and at least a portion of the wiring arrangement area 1 and the circuit arrangement area 2 are located in the rounded corner area A12 .

[0123] For example, Fig.26 The rounded corner areas at the lower left and lower right may include a routing layout area and a circuit layout area. The routing layout area is used to layout fan-out routing, and the circuit layout area is used to layout shift register units. The corresponding setting method can refer to the above description and will not be repeated here.

[0124] For example, Fig.26 The rounded corner areas in the upper left and upper right of the middle may include a wiring layout area and a circuit layout area. The wiring layout area is used to layout data compensation wiring, and the circuit layout area is used to layout electrostatic protection circuits. The corresponding setting methods can refer to the above description and will not be repeated here.

[0125] Finally, it should be noted that the above embodiments are all illustrated by taking the first area of ​​the display panel as a non-display area (frame area), that is, the first area does not include pixels. In other embodiments, the first area may also include pixels. In this case, the pixel circuits can be concentrated in the middle area by compressing the layout of the pixel circuits, and the circuits and wiring originally arranged in the non-display area can be compressed into the display area to achieve a frameless display panel design. In this case, the technical solution of the embodiment of the present invention is conducive to reducing the total width occupied by the wiring layout area and the circuit layout area in the first direction, thereby reducing the design difficulty of the pixel circuits in the internal area.

[0126] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Fig. 27 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig. 27 As shown, the display device 200 includes the display panel 100 provided in any of the above embodiments, and thus has the same beneficial effects as the above display panel. The same points can be found in the description of the above embodiments, which will not be repeated here. The display device 200 can be any type of LED display. In addition, the display device 200 provided in the embodiment of the present invention can be Fig. 27 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0127] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: It includes a first area and a second area, the first area includes a wiring arrangement area and a circuit arrangement area, the wiring arrangement area and the circuit arrangement area are arranged along a first direction, and at least the second area includes pixels; The circuit arrangement area includes a first circuit and a second circuit, the first circuit and the second circuit are arranged along a second direction, the second direction intersects the first direction, and the width of the first circuit in the first direction is greater than the width of the second circuit in the first direction; wherein, The routing layout area includes a first routing layout area and a second routing layout area. Along the first direction, the first circuit overlaps with the first routing layout area, and the second circuit overlaps with the second routing layout area. The width of the first routing layout area in the first direction is smaller than the width of the second routing layout area in the first direction.

2. The display panel according to claim 1, characterized in that: The first circuit and the second circuit have the same circuit structure, and a width of the first circuit in the second direction is smaller than a width of the second circuit in the second direction.

3. The display panel according to claim 2, characterized in that: The first circuit and the second circuit include a same first subsection and a same second subsection; In the first circuit, the first subsection and the second subsection are arranged side by side along the first direction; In the second circuit, the first section and the second section are arranged side by side along the second direction.

4. The display panel according to claim 3, characterized in that: The first circuit and the second circuit both include an electrostatic protection circuit; The electrostatic protection circuit comprises a first switch unit and a second switch unit, wherein the first end of the first switch unit is electrically connected to the first level signal end, the second end of the first switch unit, the first end of the second switch unit and the data line are connected to a first node, the second end of the second switch unit is electrically connected to the second level signal end, the voltage of the first level signal at the first level signal end is greater than the voltage of the second level signal at the second level signal end; the control end of the first switch unit is electrically connected to the first level signal end, and the control end of the second switch unit is electrically connected to the first node; The first subsection is composed of the first switch unit, and the second subsection is composed of the second switch unit.

5. The display panel according to claim 4, characterized in that: The first switch unit includes a first switch transistor and a second switch transistor connected in series, and the control terminals of the first switch transistor and the second switch transistor are both electrically connected to the first level signal terminal; the second switch unit includes a third switch transistor and a fourth switch transistor connected in series, and the control terminals of the third switch transistor and the fourth switch transistor are both electrically connected to the first node; The first circuit includes a first electrostatic protection circuit, in which the first switch transistor, the second switch transistor, the third switch transistor and the fourth switch transistor are arranged side by side along the first direction; or the first switch transistor and the second switch transistor are arranged side by side along the second direction, and the third switch transistor and the fourth switch transistor are arranged side by side along the second direction; The second circuit includes a second electrostatic protection circuit, in which the first switch transistor, the second switch transistor, the third switch transistor and the fourth switch transistor are arranged side by side along the second direction.

6. The display panel according to claim 4, characterized in that: The first circuit is located on a side of the first wiring arrangement area away from the second area; the second circuit is located on a side of the second wiring arrangement area away from the second area.

7. The display panel according to claim 6, characterized in that: The display panel further includes a third circuit and a fourth circuit, wherein the third circuit is located on a side of the first circuit away from the first wiring arrangement area, and the fourth circuit is located on a side of the second circuit away from the second wiring arrangement area; The width of the third circuit in the first direction is smaller than the width of the fourth circuit in the first direction; the width of the third circuit in the second direction is larger than the width of the fourth circuit in the second direction.

8. The display panel according to claim 7, characterized in that: The third circuit and the fourth circuit include a shift register unit.

9. The display panel according to claim 4, characterized in that: Data compensation wiring is arranged in the first wiring arrangement area and the second wiring arrangement area.

10. The display panel according to claim 3, characterized in that: The first circuit and the second circuit both include a shift register unit; The shift register unit includes a first type of transistor and a second type of transistor, wherein the width-to-length ratio of the first type of transistor is greater than the width-to-length ratio of the second type of transistor; The first subsection is composed of at least the first type of transistors, and the second subsection is composed of at least the second type of transistors.

11. The display panel according to claim 10, characterized in that: The first type of transistor is electrically connected to the output end of the shift register unit; The second type of transistors are electrically connected to the first type of transistors.

12. The display panel according to claim 2, characterized in that: The first circuit and the second circuit both include a shift register unit; The shift register unit includes a first type of transistor, and the first type of transistor is electrically connected to the output end of the shift register unit; the first type of transistor includes a plurality of first sub-transistors arranged in parallel; The first circuit includes a first shift register unit, in which all the first sub-transistors in the first type of transistors are arranged in an a*b array in the first direction and the second direction; The second circuit includes a second shift register unit, in which all the first sub-transistors in the first type of transistors are arranged in a c*d array in the first direction and the second direction; Wherein, a and c represent the number of the first sub-transistors in the first direction, and b and d represent the number of the first sub-transistors in the second direction; a×b=c×d; In the first direction, a>c; In the second direction, b<d.

13. The display panel according to claim 10 or 12, characterized in that: The display panel includes a scanning shift register unit and a light emitting shift register unit; The first circuit and the second circuit each include at least one of the scanning shift register units and / or at least one of the light emitting shift register units.

14. The display panel according to claim 13, characterized in that: The first circuit and the second circuit each include at least one scanning shift register unit and at least one light emitting shift register unit, and the scanning shift register unit and the light emitting shift register unit are arranged side by side along the first direction.

15. The display panel according to claim 14, characterized in that: The first circuit and the second circuit each include at least two scanning shift register units and at least one light emitting shift register unit; The at least two scanning shift register units are arranged side by side along the second direction, and along the first direction, the light emitting shift register unit overlaps with the at least two scanning shift register units.

16. The display panel according to claim 10 or 12, characterized in that: The first circuit is located at a side of the first wiring arrangement area close to the second area; the second circuit is located at a side of the second wiring arrangement area close to the second area.

17. The display panel according to claim 10 or 12, characterized in that: The first wiring arrangement area and the second wiring arrangement area are arranged with fan-out wiring.

18. The display panel according to claim 1, characterized in that: A width of the first circuit in the second direction is equal to a width of the second circuit in the second direction.

19. The display panel according to claim 18, characterized in that: The first circuit includes at least one scanning shift register unit and at least one light emitting shift register unit; The second circuit includes a scanning shift register unit or a light emitting shift register unit.

20. The display panel according to claim 1, characterized in that: The first routing layout area includes a first sub-routing layout area and a second sub-routing layout area, and the second routing layout area includes a third sub-routing layout area and a fourth sub-routing layout area; the first sub-routing layout area and the third sub-routing layout area are connected to form a first wiring area, and the second sub-routing layout area and the fourth sub-routing layout area are connected to form a second wiring area; The first circuit includes a first subcircuit and a second subcircuit, and the second circuit includes a third subcircuit and a fourth subcircuit; along the first direction, the first subcircuit overlaps with the first sub-wiring arrangement area, the second subcircuit overlaps with the second sub-wiring arrangement area, the third subcircuit overlaps with the third sub-wiring arrangement area, and the fourth subcircuit overlaps with the fourth sub-wiring arrangement area; The first circuit area is arranged with fan-out routing, and the first sub-circuit and the third sub-circuit include shift register units; The second circuit area is arranged with a data compensation line, the second sub-circuit and the fourth sub-circuit include an electrostatic protection circuit, and the electrostatic protection circuit is electrically connected to the data line; The first region includes a binding area, and the first circuit area is located on a side of the second circuit area close to the binding area.

21. The display panel according to claim 1, characterized in that: The routing area includes a first routing line and a second routing line, at least a portion of the first routing line is located in a first metal layer, and at least a portion of the second routing line is located in a second metal layer.

22. The display panel according to claim 1, characterized in that: The first region includes a rounded corner area, and at least parts of the wiring arrangement area and the circuit arrangement area are located in the rounded corner area.

23. The display panel according to claim 1, characterized in that: The display panel has a circular shape.

24. A display device, characterized in that: A display panel comprising any one of claims 1-23.

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