Display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprises a first area and a second area, the first area comprises a wire arrangement area and a circuit arrangement area, the wire arrangement area and the circuit arrangement area are arranged along a first direction, and at least the second area comprises a pixel; the circuit arrangement area comprises a first circuit and a second circuit, the first circuit and the second circuit are arranged along a second direction, the second direction intersects the first direction, and the width of the first circuit in the first direction is greater than the width of the second circuit in the first direction; wherein the wire arrangement area comprises a first wire arrangement area and a second wire arrangement area, along the first direction, the first circuit overlaps the first wire arrangement area, the second circuit overlaps the second wire arrangement area, and the width of the first wire arrangement area in the first direction is less than the width of the second wire arrangement area in the first direction. The application can at least realize a narrow frame.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] The frame area of the display panel is usually arranged with circuits and wires, and the layout of the two affects the width of the frame. How to adjust the layout of the circuits and wires is beneficial to realize narrow frame and is one of the research hotspots in the industry. SUMMARY

[0003] The present application provides a display panel and a display device to realize at least narrow frame.

[0004] According to an aspect of the present application, a display panel is provided, comprising a first area and a second area, the first area comprising a wire arrangement area and a circuit arrangement area, the wire arrangement area and the circuit arrangement area being arranged along a first direction, and at least the second area comprising a pixel;

[0005] The circuit arrangement area comprises a first circuit and a second circuit, the first circuit and the second circuit being arranged along a second direction, the second direction intersecting the first direction, and the width of the first circuit in the first direction being greater than the width of the second circuit in the first direction; wherein,

[0006] The wire arrangement area comprises a first wire arrangement area and a second wire arrangement area, along the first direction, the first circuit overlapping the first wire arrangement area, the second circuit overlapping the second wire arrangement area, and the width of the first wire arrangement area in the first direction being less than the width of the second wire arrangement area in the first direction.

[0007] According to another aspect of the present application, a display device is provided, comprising the display panel provided by any one of the embodiments of the present application.

[0008] The technical solution of the embodiments of the present application adjusts the width of the circuit in the first direction in the circuit arrangement area, so that the width of the first circuit in the first direction is greater than the width of the second circuit in the first direction. Since the first circuit overlaps the first wire arrangement area along the first direction, and the second circuit overlaps the second wire arrangement area along the first direction, and the width of the first wire arrangement area in the first direction is less than the width of the second wire arrangement area in the first direction, the width of the wire arrangement area and the corresponding circuit in the first direction can be complementary. This is not only beneficial to realize narrow frame, but also can reduce the width of the second circuit in the first direction to leave enough space for the second wire arrangement area to set wires, thereby improving product yield.

[0009] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0011] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0012] Figure 2 is Figure 1 is an enlarged structural schematic diagram of a Q1 region in

[0013] Figure 3 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0014] Figure 4 is Figure 3 is a structural schematic diagram of a pixel in the display panel shown in

[0015] Figure 5 is a driving timing diagram of a pixel circuit corresponding to Figure 4

[0016] is a circuit structural schematic diagram of a first circuit and a second circuit provided by an embodiment of the present application; Figure 6

[0017] is a layout structural schematic diagram of a first circuit corresponding to Figure 7 Figure 6 is a layout structural schematic diagram of a second circuit corresponding to

[0018] Figure 8 Figure 6 is a layout structural schematic diagram of a second circuit corresponding to

[0019] Figure 9 is a circuit structural schematic diagram of another first circuit and another second circuit provided by an embodiment of the present application;

[0020] Figure 10 is a layout structural schematic diagram of a first circuit corresponding to Figure 9

[0021] Figure 11 is a layout structural schematic diagram of a second circuit corresponding to Figure 9

[0022] is Figure 12 is another enlarged structural schematic diagram of a Q1 region in Figure 1 ​​​​

[0023] Figure 13 is Figure 1 Another amplification structure schematic view of Q1 region in the middle;

[0024] Figure 14 is Figure 13 The layout structure schematic view of a first circuit corresponding to;

[0025] Figure 15 is Figure 13 The layout structure schematic view of a second circuit corresponding to;

[0026] Figure 16 is another display panel structure schematic view provided by the embodiment of the present application;

[0027] Figure 17 is Figure 16 An amplification structure schematic view of Q2 region in the middle;

[0028] Figure 18 is another first circuit and second circuit circuit structure schematic view provided by the embodiment of the present application;

[0029] Figure 19 is Figure 18 The layout structure schematic view of a first circuit corresponding to;

[0030] Figure 20 is Figure 18 The layout structure schematic view of a second circuit corresponding to;

[0031] Figure 21 is another first circuit layout structure schematic view corresponding to; Figure 18

[0032] Figure 22 is another display panel structure schematic view provided by the embodiment of the present application;

[0033] Figure 23 is another display panel structure schematic view provided by the embodiment of the present application;

[0034] Figure 24 is another display panel structure schematic view provided by the embodiment of the present application;

[0035] Figure 25 is a cross-sectional structure schematic view of the display panel along VV'; Figure 24

[0036] is another display panel structure schematic view provided by the embodiment of the present application; Figure 26

[0037] Figure 27 ​​is a structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order for those skilled in the technical field to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts should fall within the scope of the present application.

[0039] Various modifications and changes can be made to the present application in light of the above description, without departing from the spirit or scope of the present application. Accordingly, the present application is intended to embrace all modifications and alterations of this application that fall within the scope of the claims (technical solutions claimed), and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other without contradiction, if possible.

[0040] First of all, it should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present application should be understood as the usual meaning understood by those skilled in the art to which the present application belongs. The terms "first", "second", and similar terms used in the present application do not represent any order, number, or importance, but are only used to distinguish different components. "Include" and similar terms mean that the elements or objects before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and similar terms are only used to represent relative positional relationships, which may change accordingly when the absolute position of the described object changes. In addition, the shapes and sizes of the components in the drawings do not reflect the true proportions, but only serve to illustrate the content of the present application.

[0041] In the related art, in the frame area of the display panel, the area where the circuit is arranged (hereinafter referred to as the circuit arrangement area) and the area where the trace is arranged (hereinafter referred to as the trace arrangement area) are arranged side by side along the direction from the non-display area to the display area. For a special-shaped display screen, the trace arrangement area at different positions in the special-shaped frame area occupies different widths due to the different number of traces, for example, for a circular, ring-shaped or display screen with rounded corners, the closer to the lower frame, the more the number of fan-out traces corresponding to the data line, that is, the closer to the lower frame, the larger the width of the fan-out trace arrangement area, plus the circuit arranged side by side also occupies a certain width, making it difficult to realize a narrow frame.

[0042] Therefore, the display panel provided by the embodiments of the present application includes a first region and a second region, the first region includes a wire arrangement region and a circuit arrangement region, the wire arrangement region and the circuit arrangement region are arranged along a first direction, and at least the second region includes a pixel; the circuit arrangement region includes a first circuit and a second circuit, the first circuit and the second circuit are arranged along a second direction, the second direction intersects the first direction, and a width of the first circuit in the first direction is greater than a width of the second circuit in the first direction; wherein the wire arrangement region includes a first wire arrangement region and a second wire arrangement region, along the first direction, the first circuit overlaps the first wire arrangement region, the second circuit overlaps the second wire arrangement region, and a width of the first wire arrangement region in the first direction is less than a width of the second wire arrangement region in the first direction.

[0043] By adopting the above scheme, since the first circuit overlaps the first wire arrangement region along the first direction and the second circuit overlaps the second wire arrangement region along the first direction, and the width of the first wire arrangement region in the first direction is less than the width of the second wire arrangement region, by adjusting the width of the circuit in the circuit arrangement region in the first direction, the width of the first circuit corresponding to the first wire arrangement region in the first direction is greater than the width of the second circuit corresponding to the second wire arrangement region in the first direction, so that the width of the wire arrangement region and the corresponding circuit in the first direction are complementary, which is not only beneficial to realize a narrow frame, but also can leave enough space for the second wire arrangement region to set wires by reducing the width of the second circuit in the first direction, thereby improving product yield.

[0044] The above is the core idea of the present application, and the technical solutions of the embodiments of the present application will be described clearly and completely in combination with the accompanying drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0045] Figure 1 is a structural schematic diagram of a display panel provided by the embodiments of the present application, as Figure 1As shown, the display panel 100 includes a first area A1 and a second area A2, the first area A1 includes a wire arrangement area 1 and a circuit arrangement area 2, the wire arrangement area 1 and the circuit arrangement area 2 are arranged along a first direction D1, and at least the second area A2 includes a pixel PX; the circuit arrangement area 2 includes a first circuit 21 and a second circuit 22, the first circuit 21 and the second circuit 22 are arranged along a second direction D2, the second direction D2 intersects the first direction D1, and a width C1 of the first circuit 21 in the first direction D1 is greater than a width E1 of the second circuit 22 in the first direction D1; wherein the wire arrangement area 1 includes a first wire arrangement area 11 and a second wire arrangement area 12, along the first direction D1, the first circuit 21 overlaps the first wire arrangement area 11, the second circuit 22 overlaps the second wire arrangement area 12, and a width B1 of the first wire arrangement area 11 in the first direction D1 is less than a width B2 of the second wire arrangement area 12 in the first direction D1.

[0046] With reference to Figure 1 Optionally, in the embodiment, the first area A1 does not include the pixel, and only the second area A2 includes the pixel PX, in other words, the first area A1 is a non-display area (a frame area), and the second area A2 is a display area.

[0047] Optionally, the display panel provided by the embodiment of the present application is a special-shaped display screen, at least part of the edges of the display panel is arc-shaped, and the wire arrangement area 1 and the circuit arrangement area 2 overlap the arc-shaped area in the first area A1. For example, Figure 1 Taking the shape of the display panel as a circular shape as an example.

[0048] Further, with reference to Figure 1 , the first area A1 includes the wire arrangement area 1 and the circuit arrangement area 2, the wire arrangement area 1 and the circuit arrangement area 2 are arranged along the first direction D1, the circuit arrangement area 2 includes the first circuit 21 and the second circuit 22, along the first direction D1, the first circuit 21 overlaps the first wire arrangement area 11, the second circuit 22 overlaps the second wire arrangement area 12, and the first circuit 21 and the second circuit 22 are arranged along the second direction D2. Specifically, a plurality of first circuits 21 and the first wire arrangement area 11 are side by side along the first direction D1, a plurality of second circuits 22 and the second wire arrangement area 12 are side by side along the first direction D1, and the plurality of first circuits 21 and the plurality of second circuits 22 are arranged along the second direction D2.

[0049] Wherein, the first direction D1 can be understood as a direction in which the first area A1 points to the second area A2. It can be understood that for the special-shaped display screen, the first direction D1 will change with the change of the position of the reference point. For example Figure 1The first direction D1 is a radial direction, and the first direction D1 at different positions is different, but all points to the center direction. The second direction D2 intersects with the first direction D1, and thus the second direction D2 also changes with the change of the first direction D1.

[0050] Referring to Figure 1 Due to the different number of wires, the width of the first wire arrangement area 11 in the first direction D1 is smaller than the width of the second wire arrangement area 12 in the first direction D1. In this embodiment, the width of the first circuit 21 corresponding to the first wire arrangement area 11 in the first direction D1 is greater than the width of the second circuit 22 corresponding to the second wire arrangement area 12 in the first direction D1, so that the width of the wire arrangement area and the corresponding circuit in the first direction D1 is complementary, which is not only beneficial to realize narrow frame, but also can reduce the width E1 of the second circuit 22 in the first direction D1 to provide sufficient space for the second wire arrangement area 12 to arrange wires and improve product yield.

[0051] For example, referring to the above description, the wire arrangement area 1 can be used to arrange fan-out wires. Referring to Figure 1 , the closer to the lower frame, the more the number of fan-out wires, so that the width of the first wire arrangement area 11 in the first direction D1 is smaller than the width of the second wire arrangement area 12 in the first direction D1.

[0052] Correspondingly, the circuit arrangement area 2 can be used to arrange a gate drive circuit, and the gate drive circuit is arranged along the first direction D1 with the setting area of the fan-out wire. The adjustment mode of the width of the gate drive circuit in the first direction D1 is described in detail later, which is not described here.

[0053] It should be noted that the wires arranged in the wire arrangement area 1 can include but are not limited to fan-out wires, and the circuits arranged in the circuit arrangement area 2 can include but are not limited to gate drive circuits, which are not limited by the embodiments of the present application. For different wires and different circuits, different regions can be set in the first region 1, and the embodiments of the present application are not limited.

[0054] It should also be noted that Figure 1 Only the wire arrangement area 1 is divided into two regions with different widths in the first direction D1 (i.e. the first wire arrangement area 11 and the second wire arrangement area 12) as an example, in other embodiments, the wire arrangement area 1 can be divided into more regions with different widths in the first direction D1, and the embodiments of the present application are not limited. Correspondingly, the circuit arrangement area 2 can include more circuits with different widths in the first direction to match the width of each wire arrangement area.

[0055] In summary, the embodiment of the present application adjusts the width of the circuit in the first direction in the circuit arrangement area, so that the width of the first circuit in the first direction is greater than the width of the second circuit in the first direction. Since the first circuit and the first trace arrangement area overlap in the first direction, and the second circuit and the second trace arrangement area overlap in the first direction, and the width of the first trace arrangement area in the first direction is less than the width of the second trace arrangement area, the width of the trace arrangement area and the corresponding circuit in the first direction is complementary, which is not only conducive to realizing narrow frame, but also can reduce the width of the second circuit in the first direction to leave enough space for the second trace arrangement area to set the trace, thereby improving product yield.

[0056] On the basis of the above embodiment, referring to Figure 1 Optionally, the first circuit 21 and the second circuit 22 have the same circuit structure, and the width C2 of the first circuit 21 in the second direction D2 is less than the width E2 of the second circuit 22 in the second direction D2.

[0057] Optionally, the first circuit 21 and the second circuit 22 have the same circuit structure, and the width C2 of the first circuit 21 in the second direction D2 is less than the width E2 of the second circuit 22 in the second direction D2.

[0058] Specifically, in the embodiment, the first circuit 21 and the second circuit 22 have the same circuit structure, but the layout of the first circuit 21 and the second circuit 22 is different, that is, the layout of the components in the first circuit 21 and the second circuit 22 is different. For the first circuit 21, by compressing the width C2 of the first circuit 21 in the second direction D2, the width C1 of the first circuit 21 in the first direction D1 is larger. For the second circuit 22, by increasing the width E2 of the second circuit 22 in the second direction D2, the width E1 of the second circuit 22 in the first direction D1 is smaller. Specifically, by designing the width C2 of the first circuit 21 in the second direction D2 to be less than the width E2 of the second circuit 22 in the second direction D2, the width C1 of the first circuit 21 in the first direction D1 is greater than the width E1 of the second circuit 22 in the first direction D1, thereby achieving the design purpose of narrow frame, and leaving enough space for the second trace arrangement area 12 to set the trace.

[0059] Figure 2 is Figure 1 an enlarged structure diagram of the Q1 area, as Figure 2 Optionally, the first circuit 21 and the second circuit 22 include the same first part 201 and the same second part 202; in the first circuit 21, the first part 201 and the second part 202 are arranged side by side in the first direction D1; in the second circuit 22, the first part 201 and the second part 202 are arranged side by side in the second direction D2.

[0060] Specifically, in the embodiment, the first circuit 21 and the second circuit 22 have the same circuit structure, and the components in the circuit structure can be divided into two groups, one group of components constitutes the first part 201, and the other group of components constitutes the second part 202, so that the first circuit 21 and the second circuit 202 have the same first part 201 and second part 202. Further, for the first circuit 21, the first part 201 and the second part 202 are arranged side by side along the first direction D1, and for the second circuit 22, the first part 201 and the second part 202 are arranged side by side along the second direction D2, so as to realize that the width C1 of the first circuit 21 in the first direction D1 is greater than the width E1 of the second circuit 22 in the first direction D1, and the width C2 of the first circuit 21 in the second direction D2 is less than the width E2 of the second circuit 22 in the second direction D2, thereby achieving the design purpose of narrow frame, and at the same time leaving enough space for the second wiring arrangement area 12 to arrange the wiring.

[0061] The arrangement mode of the first circuit and the second circuit will be described in detail below in combination with a specific circuit structure.

[0062] Referring to Figure 1 In a specific embodiment, optionally, the first circuit 21 and the second circuit 22 each include a shift register unit VSR, and correspondingly, the first wiring arrangement area 11 and the second wiring arrangement area 12 are arranged with fan-out wirings.

[0063] Specifically, a plurality of shift register units VSR are sequentially cascaded to form a gate drive circuit, which is used to transmit a gate control signal to a pixel through a scan line to control the light emission of the pixel. As shown in Figure 1 In the first direction, the first wiring arrangement area 11 and the second wiring arrangement area 12 each overlap with the plurality of shift register units VSR, wherein the width of the shift register unit VSR corresponding to the first wiring arrangement area 11 in the first direction D1 is less than the width of the shift register unit VSR corresponding to the second wiring arrangement area 12 in the first direction D1, and the width of the shift register unit VSR corresponding to the first wiring arrangement area 11 in the second direction D2 is greater than the width of the shift register unit VSR corresponding to the second wiring arrangement area 12 in the second direction D2, which is conducive to realizing a narrow frame, and at the same time leaving enough space for the second wiring arrangement area 12 to arrange a larger number of fan-out wirings.

[0064] The display panel usually includes a scan shift register unit and a light-emitting shift register unit, and optionally, the first circuit 21 and the second circuit 22 each include at least one scan shift register unit and / or at least one light-emitting shift register unit.

[0065] The scan shift register unit and the light emission shift register unit are electrically connected to the pixel through different scan lines. The pixel driving process includes a pre-processing stage and a light emission stage. The scan shift register unit is specifically used to provide the pixel with a gate control signal through the scan line in the pre-processing stage, and the light emission shift register unit is specifically used to provide the pixel with a gate control signal through the scan line in the light emission stage. The two work together to realize the light emission driving of the pixel.

[0066] For example, Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, such as... Figure 3 As shown, the display panel 100 includes a scan shift register unit VSR1 and a light emission shift register unit VSR2. Figure 4 yes Figure 3 The diagram shows the structure of one type of pixel in the display panel. Figure 5 Is with Figure 4 The corresponding pixel circuit driving timing diagram, combined with Figures 3-5As shown, the pixel PX includes a light emitting element (LED) and a pixel circuit electrically connected with the light emitting element, the display panel 100 includes a first scan line G1, a second scan line G2 and a third scan line G3, the pixel circuit is electrically connected with the first scan line G1, the second scan line G2 and the third scan line G3 respectively, the first scan line G1 and the second scan line G2 are electrically connected with a scan shift register unit VSR1, and the third scan line G3 is electrically connected with a light emitting shift register unit VSR2. The working process of the pixel circuit includes an initialization stage t1, a data writing stage t2 and a light emitting stage t3, wherein the initialization stage t1 and the data writing stage t2 are pre-stages. In the initialization stage t1, the scan shift register unit VSR1 is used to provide an initialization control signal S1 to the pixel circuit through the first scan line G1, so that the initialization transistor T2 is turned on under the control of the initialization control signal S1, and the initialization signal Vref is written to the gate of the driving transistor T1, so as to initialize the gate of the driving transistor T1. In the data writing stage t2, the scan shift register unit VSR1 is used to provide a data writing control signal S2 to the pixel circuit through the second scan line G2, so that the data writing transistor T3 and the threshold compensation transistor T4 are turned on under the control of the data writing control signal S2, and the data writing transistor T3 writes the data signal Vdata to the gate of the driving transistor T1, and at the same time, the threshold compensation transistor T4 writes the threshold voltage compensation value of the driving transistor T1 to the gate of the driving transistor T1. In addition, in the data writing stage t2, the reset transistor T7 can be turned on under the control of the data writing control signal S2, and the initialization signal Vref is written to the anode of the light emitting diode LED, so as to reset the voltage of the anode of the light emitting diode LED. In the light emitting stage t3, the light emitting shift register unit VSR2 is used to provide a light emitting control signal EMIT to the pixel circuit through the third scan line G3, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on under the control of the light emitting control signal EMIT. Since the storage capacitor Cst stores the gate potential of the driving transistor T1, the driving transistor T1 generates a driving current based on the gate potential and the potential of the first power signal terminal PVDD, and drives the LED to emit light. Figure 8 In the embodiment, the PVEE is a second power signal terminal, and the potential of the second power signal terminal PVEE is less than the potential of the first power signal terminal PVDD.

[0067] It should be noted that, Figure 3The illustration only takes the example of the first scan line G1 and the second scan line G2 being electrically connected to the same group of shift register units VSR1. In this case, the gate driving circuit formed by the cascaded shift register units VSR1 provides both the initialization control signal S1 and the data write control signal S2 to the pixel circuit. In other embodiments, the first scan line G1 and the second scan line G2 can also be electrically connected to different groups of shift register units VSR1, and different gate driving circuits can provide the initialization control signal S1 and the data write control signal S2 to the pixel circuit respectively.

[0068] Specifically, refer to Figure 3 When the scan shift register unit VSR1 and the light emission shift register unit VSR2 are configured in a single-sided driving manner, the first circuit 21 and the second circuit 22 may each include at least one scan shift register unit VSR1 or at least one light emission shift register unit VSR2. For example, the first circuit and the second circuit located on the left edge of the screen may each include at least one scan shift register unit VSR1, and the first circuit and the second circuit located on the right edge of the screen may each include at least one light emission shift register unit VSR2. When the scan shift register unit VSR1 and the light emission shift register unit VSR2 are configured in a dual-sided driving manner, the first circuit 21 and the second circuit 22 may each include at least one scan shift register unit VSR1 and at least one light emission shift register unit VSR2.

[0069] Figure 6 This is a schematic diagram of the circuit structure of a first circuit and a second circuit provided in an embodiment of the present invention. Figure 7 Is with Figure 6 A schematic diagram of the layout structure of a corresponding first circuit. Figure 8 Is with Figure 6 A corresponding layout structure diagram of a second circuit, such as... Figures 6-8 As shown, optionally, both the first circuit 21 and the second circuit include a shift register unit (such as a scan shift register unit VSR1). The shift register unit includes a first-type transistor MA and a second-type transistor MB. The aspect ratio of the first-type transistor MA is greater than that of the second-type transistor MB. The first portion 201 is composed of at least the first-type transistor MA, and the second portion 202 is composed of at least the second-type transistor MB. In the first circuit 21 (such as...) Figure 7 The first part 201 and the second part 202 are arranged side by side along the first direction D1; in the second circuit 22 (e.g. Figure 8 The first part 201 and the second part 202 are arranged side by side along the second direction D2.

[0070] For example, Figures 6-8Taking an example of the first circuit 21 and the second circuit 22 each comprising a scan shift register unit VSR1, the layout design of the first circuit 21 and the second circuit 22 is illustrated.

[0071] As shown in Figure 6 , the scan shift register unit VSR1 comprises eight transistors, such as M1, M2, M3, M4, M5, M6, M7 and M8, wherein the transistors M1, M2, M3, M4, M5 and M6 serve as switches, are switch transistors, and usually have a small width-length ratio, while the transistors M7 and M8 are electrically connected with the output terminal OUT of the scan shift register unit VSR1, and both of them affect the stability of the output signal, so the width-length ratio of the transistors M7 and M8 is usually large. In view of this, the transistors M7 and M8 can be taken as the first type of transistors MA, and the transistors M1, M2, M3, M4, M5 and M6 can be taken as the second type of transistors MB, the first part 201 is formed by the first type of transistors MA, and the second part 202 is formed by the second type of transistors MB. In the first circuit 21 (as shown in Figure 7 ), the first part 201 and the second part 202 are arranged side by side along the first direction D1; in the second circuit 22 (as shown in Figure 8 ), the first part 201 and the second part 202 are arranged side by side along the second direction D2, so as to realize that the width of the first circuit 21 in the first direction D1 is greater than the width of the second circuit 22 in the first direction D1, and the width of the first circuit 21 in the second direction D2 is less than the width of the second circuit 22 in the second direction D2, thereby achieving the design purpose of narrow frame, and leaving enough space for the second wiring layout area 12 to arrange a large number of fan-out wirings.

[0072] Exemplarily, Figure 9 is another circuit structure schematic diagram of the first circuit and the second circuit provided by the embodiment of the present application, Figure 9 taking an example of the first circuit 21 and the second circuit 22 each comprising a light-emitting shift register unit VSR2. As shown in Figure 9 , alternatively, the transistors M9 and M10 electrically connected with the output terminal OUT of the light-emitting shift register unit VSR2 can be taken as the first type of transistors MA, and form the first part 201, and the remaining transistors (M1, M2, M3, M4, M5, M6, M7, M8 and M11) are electrically connected with the first type of transistors MA, are switch transistors, and can be taken as the second type of transistors MB, and form the second part 202. The layout of the light-emitting shift register unit VSR2 corresponding to the first circuit 21 and the second circuit 22 can be designed with reference to the layout of the scan shift register unit VSR1 shown in Figure 7 and Figure 8 , and here is not exemplified one by one.

[0073] It should be noted that, Figure 6 and Figure 9 The circuit structure of the shift register unit shown in the drawings is only illustrative and not limiting. At present, the scan shift register unit and the light-emitting shift register unit can adopt a plurality of different circuit structures. Each circuit structure can be classified according to the following rules: the transistors in the shift register unit are classified into the first type of transistor MA and the second type of transistor MB, and then the first part and the second part are determined according to the classification result. In the layout design of the first circuit, the first part and the second part are arranged side by side along the first direction. In the layout design of the second circuit, the first part and the second part are arranged side by side along the second direction, so as to achieve the purpose of the application. Specifically, referring to the examples of Figure 6 and Figure 9 The determination rule of whether each transistor in the shift register unit belongs to the first type of transistor MA or the second type of transistor MB is as follows: the first type of transistor MA is electrically connected to the output terminal OUT of the shift register unit; and the second type of transistor MB is electrically connected to the first type of transistor MA.

[0074] Referring to Figure 6 or Figure 9 The shift register unit further includes a capacitor, such as Figure 6 Two capacitors (C1 and C2) in the scan shift register unit VSR1 shown in Figure 9 Four capacitors (C1, C2, C3 and C4) in the light-emitting shift register unit VSR2 shown in. For the capacitors in the shift register unit, they can be classified into the first part or the second part according to the principle of proximity, which is not limited by the embodiments of the application.

[0075] For example, referring to Figures 6-8 In the scan shift register circuit VSR1, the capacitor C1 is electrically connected to the gate of the transistor M7, and the capacitor C2 is electrically connected to the gate of the transistor M8. Therefore, in the layout design, the capacitor C1 is adjacent to the transistor M7, and one of the capacitor plates of the capacitor C1 can be formed by the gate of the transistor M7. Similarly, the capacitor C2 is adjacent to the transistor M8, and one of the capacitor plates of the capacitor C2 can be formed by the gate of the transistor M8. Therefore, Figure 6 In the scan shift register unit shown in

[0076] Figure 10 is a layout structure schematic diagram of a first circuit corresponding to Figure 9 is a layout structure schematic diagram of a second circuit corresponding to Figure 11 is a layout structure schematic diagram of a second circuit corresponding to Figure 9 Referring to Figures 9-11Optionally, the first circuit 21 and the second circuit 22 each comprise a shift register unit (e.g., a light-emitting shift register unit VSR2); the shift register unit comprises a first transistor MA, which is electrically connected with an output terminal OUT of the shift register unit; the first transistor MA comprises a plurality of first sub-transistors MU arranged in parallel; the first circuit 21 comprises a first shift register unit 211, in which all the first sub-transistors MU in the first transistor MA are arranged in an a*b array in a first direction D1 and a second direction D2; the second circuit 22 comprises a second shift register unit 221, in which all the first sub-transistors MU in the first transistor MA are arranged in a c*d array in the first direction D1 and the second direction D2; wherein a and c represent the number of the first sub-transistors MU in the first direction D1, b and d represent the number of the first sub-transistors MU in the second direction D2; a×b=c×d; in the first direction, a>c; in the second direction, b

[0077] As described above, the first transistor MA has a large width-to-length ratio, and for the layout design of such a transistor, a plurality of transistors with a small width-to-length ratio are usually connected in parallel. In this embodiment, the first transistor MA is obtained by connecting N first sub-transistors MU in parallel (N=a×b=c×d).

[0078] Specifically, in this embodiment, by adjusting the arrangement of the N first sub-transistors MU in the first transistor MA in the first direction D1 and the second direction D2, for any first transistor MA, the number a of the first sub-transistors MU in the first direction D1 in the layout design of the first circuit 21 is greater than the number c of the first sub-transistors MU in the first direction D1 in the layout design of the second circuit 22, and the number b of the first sub-transistors MU in the second direction D2 in the layout design of the first circuit 21 is less than the number d of the first sub-transistors MU in the second direction D2 in the layout design of the second circuit 22, so as to realize that the width of the first circuit 21 in the first direction D1 is greater than the width of the second circuit 22 in the first direction D1, and the width of the first circuit 21 in the second direction D2 is less than the width of the second circuit 22 in the second direction D2, thereby achieving the design purpose of narrow frame, and leaving enough space for the second wiring arrangement area 12 to arrange a large number of fan-out wirings.

[0079] For example, referring to the light-emitting shift register unit VSR2 shown in Figures 9-11 , wherein the transistors M9 and M10 are the first transistors MA. In comparison with Figure 10 and Figure 11In the first circuit 21 and the second circuit 22, the transistor M9 is composed of 10 first sub-transistors MU in parallel, and the difference is that, in the first circuit 21, the 10 first sub-transistors MU in the transistor M9 are arranged in a 2*5 array in the first direction D1 and the second direction D2 (i.e. a=2, b=5), while in the second circuit 22, the 10 first sub-transistors MU in the transistor M9 are arranged in a 1*10 array in the first direction D1 and the second direction D2 (i.e. c=1, d=10). In the first circuit 21 and the second circuit 22, the transistor M10 is also composed of 10 first sub-transistors MU in parallel, and the layout design is the same as that of the transistor M9, which will not be described here again. By comparison Figure 10 and Figure 11 It can be seen that, by making the above difference in the layout of the first type of transistor in the first circuit and the second circuit, the width of the first type of transistor MA in the first direction D1 in the first circuit 21 is greater than that in the second circuit 22, and the width of the first type of transistor MA in the second direction D2 in the first circuit 21 is smaller than that in the second circuit 22. Since the size of the first type of transistor MA is large, it occupies a large area in the layout of the shift register unit, thereby facilitating the realization of the width of the first circuit 21 in the first direction D1 being greater than that of the second circuit 22 in the first direction D1, and the width of the first circuit 21 in the second direction D2 being smaller than that of the second circuit 22 in the second direction D2, thereby achieving the design purpose of narrow frame, and leaving enough space for the second wiring layout area 12 to set a large number of fan-out wirings.

[0080] According to the above description, the shift register unit can be divided into a first part composed of the first type of transistor MA and a second part composed of the second type of transistor MB. It should be noted that, Figure 10 and Figure 11 For example, only the arrangement of the first sub-transistors MU in the first type of transistor MA in the first circuit 21 and the second circuit 22 is different, and the first part 201 and the second part 202 are arranged side by side along the second direction D2. In other embodiments, the first part 201 and the second part 202 can also be arranged side by side along the first direction, or when the arrangement of the first sub-transistors MU in the first type of transistor MA in the first circuit 21 and the second circuit 22 is different, the arrangement of the first part 201 and the second part 202 in the first circuit 21 and the second circuit 22 can also be different, for example, the first part 201 and the second part 202 in the first circuit 21 can be arranged side by side along the first direction D1, and the first part 201 and the second part 202 in the second circuit 22 can be arranged side by side along the second direction D2, according to the above embodiments.

[0081] Similarly, refer to Figure 7 and Figure 8 , Figure 7 and Figure 8 The illustration only takes the example where the arrangement of the first portion 201 and the second portion 202 in the first circuit 21 and the second circuit 22 is different, but the arrangement of the first sub-transistors in the first type of transistor MA (such as M7 and M8) is the same. In other embodiments, Figure 7 and Figure 8 The first sub-transistor MU in the first type of transistor MA can also be arranged differently in the first circuit 21 and the second circuit 22, depending only on the arrangement of the first part 201 and the second part 202 in the first circuit 21 and the second circuit 22.

[0082] In summary, when the first circuit and the second circuit include shift register units (scanning shift register units and / or light-emitting shift register units), the layout of the first circuit and the second circuit can be adjusted by adjusting the arrangement of the first and second portions, and / or adjusting the arrangement of the first sub-transistors in the first type of transistors, so as to achieve the design requirements for the relative size of the first circuit and the second circuit in the first and second directions.

[0083] The above embodiments illustrate the layout design of the first and second circuits by taking an example where the first and second circuits include a scan shift register unit or an emissive shift register unit. For example, Figure 12 yes Figure 1 Another enlarged structural diagram of the Q1 region is shown below. Figure 12 As shown, optionally, both the first circuit 21 and the second circuit 22 include at least one scan shift register unit VSR1 and at least one light emission shift register unit VSR2, which are arranged side by side along the first direction D1. This arrangement allows for the placement of scan shift register units VSR1 and light emission shift register units VSR2 on both the left and right sides of the second region A2, achieving dual-sided driving and ensuring optimal display performance.

[0084] Specifically, when both the first circuit 21 and the second circuit 22 include a scan shift register unit VSR1 and a light emission shift register unit VSR2, layout adjustment can be performed on at least one of the scan shift register unit VSR1 and the light emission shift register unit VSR2. The adjustment method can be referred to the description above and will not be repeated here. In addition, when the layouts of the scan shift register unit VSR1 and the light emission shift register unit VSR2 are different in both the first circuit and the second circuit, the layout adjustment method of the scan shift register unit VSR1 and the layout adjustment method of the light emission shift register unit VSR2 can be the same or different, and the embodiments of the present invention do not limit this.

[0085] Figure 13 yes Figure 1 Another enlarged structural diagram of the Q1 region is shown below. Figure 13 As shown, optionally, both the first circuit 21 and the second circuit 22 include at least two scan shift registers VSR1 and at least one light emission shift register VSR2; the at least two scan shift registers VSR1 are arranged side by side along the second direction D2, and along the first direction D1, the light emission shift register VSR2 overlaps with the at least two scan shift registers VSR1.

[0086] Specifically, in this embodiment, the light emission shift register unit VSR2 overlaps with at least two scan shift register units VSR1 along the first direction D1. At this time, the light emission shift register unit VSR2 can simultaneously provide light emission control signals to at least two rows of pixel circuits, and simultaneously control the light emission of at least two rows of pixels, thereby reducing the number of light emission shift register units VSR2 and reducing the difficulty of layout design.

[0087] For example, Figure 13 The illustration is given by taking an example where one light-emitting shift register VSR2 and two scan shift registers VSR1 overlap along the first direction D1. Correspondingly, Figure 14 Is with Figure 13 A schematic diagram of the layout structure of a corresponding first circuit. Figure 15 Is with Figure 13 A corresponding layout structure diagram of a second circuit, such as... Figure 14As shown, in the first circuit 21, the first part 201 and the second part 202 in the optional scan shift register unit VSR1 are arranged side by side along the first direction D1, the two scan shift register units VSR1 are arranged side by side along the second direction D2, the first part 201 and the second part 202 in the light-emitting shift register unit VSR2 are arranged side by side along the second direction D2, and all the first sub-transistors MU of the first type of transistors MA in the first part 201 are arranged in an a*b array along the first direction D1 and the second direction D2 (for the transistor M9, a=2, b=5; for the transistor M10, a=2, b=5). In the second circuit, the first part 201 and the second part 202 in the optional scan shift register unit VSR1 are arranged side by side along the second direction D2, the two scan shift register units VSR1 are arranged side by side along the second direction D2, the first part 201 and the second part 202 in the light-emitting shift register unit VSR2 are arranged side by side along the second direction D2, and all the first sub-transistors MU of the first type of transistors MA in the first part 201 are arranged in a c*d array along the first direction D1 and the second direction D2 (for the transistor M9, c=1, d=10; for the transistor M10, c=1, d=10). In this way, the width of the scan shift register unit VSR1 along the first direction D1 in the first circuit 21 is greater than the width of the scan shift register unit VSR1 along the first direction D1 in the second circuit 22, the width of the scan shift register unit VSR1 along the second direction D2 is less than the width of the scan shift register unit VSR1 along the second direction D2 in the second circuit 22, the width of the light-emitting shift register unit VSR2 along the first direction D1 is greater than the width of the light-emitting shift register unit VSR2 along the first direction D1 in the second circuit 22, and the width of the light-emitting shift register unit VSR2 along the second direction D2 is less than the width of the light-emitting shift register unit VSR2 along the second direction D2 in the second circuit 22, so that the width of the first circuit 21 along the first direction D1 can be greater than the width of the second circuit 22 along the first direction D1, and the width of the first circuit 21 along the second direction D2 can be less than the width of the second circuit 22 along the second direction D2, thereby achieving the design purpose of narrow frame, and at the same time, leaving enough space for the second wiring layout area 12 to arrange a larger number of fan-out wirings. In addition, since the light-emitting shift register unit VSR2 overlaps with the two scan shift register units VSR1 along the first direction D1, by arranging the first part 201 and the second part 202 in the light-emitting shift register unit VSR2 to be arranged side by side along the second direction D2 in the first circuit 21 and the second circuit 22, it is beneficial to make the size of the light-emitting shift register unit VSR2 along the second direction D2 consistent with the size of the two scan shift register units VSR1 along the second direction D2, thereby reducing space waste.

[0088] Reference Figure 1When the first wiring arrangement area 11 and the second wiring arrangement area 12 are used to arrange fan-out wirings, and the circuit arrangement area 2 is used to arrange shift register units (VSRs), optionally, the first circuit 21 is located on the side of the first wiring arrangement area 11 near the second area A2; the second circuit 22 is located on the side of the second wiring arrangement area 12 near the second area A2. This allows the shift register unit (VSR) to be located on the side of the fan-out wirings near the display area, which is beneficial for both the electrical connection between the shift register unit (VSR) and the scan lines, and the electrical connection between the fan-out wirings and the pads in the bonding area A11. The bonding area A11 is used to bond the driver chip, or to bond the circuit board, so that the circuit board can be electrically connected to the driver chip. The driver chip is used to transmit data signals through the fan-out wirings and data lines, and is also used to transmit control signals (e.g., to the shift register unit) to the shift register unit. Figure 6 and Figure 9 The start signals STV and IN, clock signals CK and XCK, power signals VGH and VGL, etc. shown are used to control the working state of the shift register unit VSR.

[0089] In summary, the above embodiments, taking the first circuit and the second circuit as having the same structure and both including a shift register unit, provide a detailed explanation of how to achieve the effect of reducing the border width, where the width of the first circuit in the first direction is greater than the width of the second circuit in the first direction, and the width of the first circuit in the second direction is less than the width of the second circuit in the second direction.

[0090] In other embodiments, Figure 16 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 17 yes Figure 16 A magnified structural diagram of the Q2 region, as shown below. Figure 16 and Figure 17 As shown, optionally, both the first circuit 11 and the second circuit 12 include electrostatic discharge (ESD) protection circuits, and correspondingly, the first routing area 11 and the second routing area 12 are provided with data compensation traces 3.

[0091] Reference Figure 16 and Figure 17 For irregularly shaped screens, the length of the data line S varies at different locations within the irregular area of ​​the display panel (this length specifically refers to the length of the data line within the display area), for example... Figure 16 As shown in the circular display panel, the closer to the edge of the panel, the shorter the length of the data line S; the closer to the center of the panel, the longer the length of the data line S. For example... Figure 16 The length of data line Si is less than the length of data line Sj, and the length of data line Sj is less than the length of data line Sk. This results in different loads on the different data lines, requiring load compensation to ensure that the loads on the different data lines are the same, thereby ensuring display uniformity.

[0092] The data compensation trace 3 is used for load compensation of the data line. Specifically, referring to Figure 17 , the data compensation trace 3 overlaps with the data line S extending to the first area A1, and the two form a capacitor. The load compensation of the data line is achieved by means of the compensation capacitor, which is referred to as RC compensation. The size of the compensation capacitor is determined according to the length of the data line. Specifically, the smaller the length of the data line, the larger the compensation capacitor required, that is, the greater the length of the data compensation trace 3. For example Figure 17 , as shown in the figure, the length of the data compensation trace 3i corresponding to the data line Si is greater than the length of the data compensation trace 3j corresponding to the data line Sj, and the length of the data compensation trace 3j corresponding to the data line Sj is greater than the length of the data compensation trace 3k corresponding to the data line Sk.

[0093] The electrostatic protection circuit ESD is used for electrostatic protection of the data line S. Specifically, referring to Figure 17 , the data line S is electrically connected with the electrostatic protection circuit ESD. When the signal transmitted on the data line S is abnormal, the abnormal charge can be eliminated by the electrostatic protection circuit ESD to protect the data line.

[0094] Since the trace arrangement area 1 where the data compensation trace 3 is arranged and the circuit arrangement area 2 where the electrostatic protection circuit ESD is arranged are arranged along the first direction D1, and the lengths of the data compensation traces 3 in different areas along the first direction D1 are different, that is, the spaces occupied are different. In this embodiment, the layout of the electrostatic protection circuit ESD is differentially set, that is, the width of the electrostatic protection circuit ESD corresponding to the first circuit 21 along the first direction D1 is greater than the width of the electrostatic protection circuit ESD corresponding to the second circuit 22 along the first direction D1. The width of the electrostatic protection circuit ESD and the data compensation trace 3 in the first direction can be complementary, which is conducive to realizing a narrow frame. In addition, by reducing the width of the electrostatic protection circuit ESD corresponding to the second circuit 22 along the first direction D1, sufficient space can be left for the second trace arrangement area 12 to set a longer data compensation trace, so as to ensure the load consistency of the data line, and further improve the display effect.

[0095] Figure 18 is another circuit structure schematic diagram of the first circuit and the second circuit provided by the embodiment of the present application, Figure 19 is a layout structure schematic diagram of a first circuit corresponding to Figure 18 , and Figure 20 is a layout structure schematic diagram of a second circuit corresponding to Figure 18 , such as Figures 18-20As shown, the electrostatic protection circuit ESD includes a first switch unit 41 and a second switch unit 42, a first end of the first switch unit 41 is electrically connected with the first level signal end VGH, a second end of the first switch unit 41, a first end of the second switch unit 42 and the data line S are connected to the first node N1, a second end of the second switch unit 42 is electrically connected with the second level signal end VGL, a voltage of the first level signal of the first level signal end VGH is greater than a voltage of the second level signal of the second level signal end VGL; a control end of the first switch unit 41 is electrically connected with the first level signal end VGH, a control end of the second switch unit 42 is electrically connected with the first node N1; the first part 201 is composed of the first switch unit 41, and the second part 202 is composed of the second switch unit 42. In the electrostatic protection circuit ESD corresponding to the first circuit 21, the first part 201 (i.e. the first switch unit 41) and the second part 202 (i.e. the second switch unit 42) are arranged side by side along the first direction D1, and in the electrostatic protection circuit ESD corresponding to the second circuit 22, the first part 201 (i.e. the first switch unit 41) and the second part 202 (i.e. the second switch unit 42) are arranged side by side along the second direction D2, so as to realize that the width of the first circuit 21 along the first direction D1 is greater than the width of the second circuit 22 along the first direction D1, and the width of the first circuit 21 along the second direction D2 is less than the width of the second circuit 22 along the second direction D2, which can achieve the design purposes of reducing the frame width and providing sufficient space for the second wiring layout area to arrange the longer data compensation wiring.

[0096] With reference to Figure 18 Optionally, the first switch unit 41 includes a first switch transistor K1 and a second switch transistor K2 connected in series, and control ends of the first switch transistor K1 and the second switch transistor K2 are electrically connected with the first level signal end VGH; the second switch unit 42 includes a third switch transistor K3 and a fourth switch transistor K4 connected in series, and control ends of the third switch transistor K3 and the fourth switch transistor K4 are electrically connected with the first node N1.

[0097] Specifically, the data signal data on the data line S is taken as the input signal IN of the electrostatic protection circuit ESD, when the voltage of the data signal data is less than the second level signal (VGL), the signal is abnormal, at this time, the third switch transistor K3 and the fourth switch transistor K4 are turned on, and the abnormal charge can be led away through the path where the second switch unit 42 is located, when the voltage of the data signal data is greater than the first level signal (VGH), the signal is abnormal, at this time, the first switch transistor K1 and the second switch transistor K2 are turned on, and the abnormal charge can be led away through the path where the first switch unit 41 is located, so as to ensure that the voltage on the data line is within a safe range, and the electrostatic protection effect is achieved.

[0098] Further,Figure 19 and Figure 20 Optionally, the first circuit 21 comprises a first electrostatic protection circuit ESD1, in which the first switch transistor K1, the second switch transistor K2, the third switch transistor K3 and the fourth switch transistor K4 are arranged side by side along the first direction D1; the second circuit 22 comprises a second electrostatic protection circuit ESD2, in which the first switch transistor K1, the second switch transistor K2, the third switch transistor K3 and the fourth switch transistor K4 are arranged side by side along the second direction D2. In this way, the width of the first electrostatic protection circuit ESD1 along the first direction D1 is greater than the width of the second electrostatic protection circuit ESD2 along the first direction D1, and the width of the first electrostatic protection circuit ESD1 along the second direction D2 is less than the width of the second electrostatic protection circuit ESD2 along the second direction D2, which can achieve the design purpose of reducing the frame width and providing sufficient space for the second wiring arrangement area to arrange longer data compensation wiring.

[0099] Figure 21 is the corresponding layout structure diagram of another first circuit, as Figure 18 shown in the figure, in other embodiments, in the first electrostatic protection circuit ESD1, the first switch transistor K1 and the second switch transistor K2 are arranged side by side along the second direction D2, the third switch transistor K3 and the fourth switch transistor K4 are arranged side by side along the second direction D2, and the first switch transistor K1 and the second switch transistor K2 constitute a first switch unit 41, and the third switch transistor K3 and the fourth switch transistor K4 constitute a second switch unit 42, which are arranged side by side along the first direction. Compared with Figure 21 and Figure 21 , in this way, the width of the first electrostatic protection circuit ESD1 along the first direction D1 is greater than the width of the second electrostatic protection circuit ESD2 along the first direction D1, and the width of the first electrostatic protection circuit ESD1 along the second direction D2 is less than the width of the second electrostatic protection circuit ESD2 along the second direction D2, which can achieve the design purpose of reducing the frame width and providing sufficient space for the second wiring arrangement area to arrange longer data compensation wiring. Figure 20 Referring to

[0100] , when the wiring arrangement area 1 is used to arrange data compensation wiring, and the circuit arrangement area 2 is used to arrange the electrostatic protection circuit ESD, optionally, the first circuit 21 is located on the side of the first wiring arrangement area 11 away from the second area A2; the second circuit 22 is located on the side of the second wiring arrangement area 12 away from the second area A2. In this way, the electrostatic protection circuit ESD can be electrically connected with the end of the data line S, and the electrostatic protection effect is ensured. Figure 16

[0101] Figure 22 ​is another structural schematic diagram of a display panel provided by an embodiment of the present application, as shown in Figure 22 As shown in the figure, when the first circuit 21 and the second circuit 22 both include the electrostatic protection circuit ESD, optionally, the display panel 100 further includes a third circuit 5 and a fourth circuit 6, the third circuit 5 is located on the side of the first circuit 21 away from the first wire arrangement area 11, and the fourth circuit 6 is located on the side of the second circuit 22 away from the second wire arrangement area 12; the width of the third circuit 5 in the first direction D1 is less than the width of the fourth circuit 6 in the first direction D1; the width of the third circuit 5 in the second direction D2 is greater than the width of the fourth circuit 6 in the second direction D2. In this way, the width of the third circuit 5 and the first circuit 21 in the first direction D1 is complementary, and the width of the fourth circuit 6 and the second circuit 22 in the first direction D1 is complementary, which is conducive to further making full use of the space on the side of the circuit arrangement area corresponding to the electrostatic protection circuit away from the wire arrangement area corresponding to the data compensation wire, and improving the space utilization.

[0102] It should be noted that in other embodiments, when the width of the circuit arrangement area corresponding to the electrostatic protection circuit and the wire arrangement area corresponding to the data compensation wire in the first direction is basically the same at different positions, the width of the third circuit and the fourth circuit in the first direction can also not be differentiated, and those skilled in the art can design according to actual needs.

[0103] Referring to Figure 22 Optionally, the third circuit 5 and the fourth circuit 6 include a shift register unit VSR. The third circuit 5 and the fourth circuit 6 can include shift register units VSR of the same circuit structure, for example, both of them include at least one scan shift register unit VSR1 and / or at least one light-emitting shift register unit VSR2, and the layout design of the third circuit 5 and the fourth circuit 6 can be performed according to the above-mentioned embodiments, so as to achieve that the width of the third circuit 5 in the first direction D1 is less than the width of the fourth circuit 6 in the first direction D1; the width of the third circuit 5 in the second direction D2 is greater than the width of the fourth circuit 6 in the second direction D2, and details are not repeated here.

[0104] In summary, the above-mentioned embodiments take the circuit structures of the first circuit and the second circuit being the same and both including the electrostatic protection circuit as an example, and details of how to achieve that the width of the first circuit in the first direction is greater than the width of the second circuit in the first direction, and the width of the first circuit in the second direction is less than the width of the second circuit in the second direction, so as to achieve the effect of reducing the frame width, etc.

[0105] In other embodiments, the first circuit and the second circuit can also have different circuit structures. For example, Figure 23 is another structural schematic diagram of a display panel provided by an embodiment of the present application, as shown in Figure 23As shown, optionally, the width C1 of the first circuit 21 in the first direction D1 is greater than the width E1 of the second circuit 22 in the first direction D1, and the width C2 of the first circuit 21 in the second direction D2 is equal to the width E2 of the second circuit 22 in the second direction D2.

[0106] In the embodiment, the first circuit 21 and the second circuit 22 have different circuit structures, which can be different components included in the first circuit 21 and the second circuit 22, or different number of circuits included in the first circuit 21 and the second circuit 22, and the embodiment of the present application does not limit this. The width C1 of the first circuit 21 in the first direction D1 is greater than the width E1 of the second circuit 22 in the first direction D1, which can be beneficial to realize narrow frame and leave enough space for the second wiring layout area 12 to arrange the wiring.

[0107] In a specific embodiment, referring to Figure 23 Optionally, the first circuit 21 includes at least one scan shift register unit VSR1 and at least one light-emitting shift register unit VSR2; and the second circuit 22 includes one scan shift register unit VSR1 or one light-emitting shift register unit VSR2.

[0108] In the embodiment, the width of the first circuit 21 in the first direction D1 can be understood as the sum of the widths of the scan shift register unit VSR1 and the light-emitting shift register unit VSR2 in the first direction D1. Since the first circuit 21 includes both the scan shift register unit VSR1 and the light-emitting shift register unit VSR2, and the second circuit 22 includes one scan shift register unit VSR1 or one light-emitting shift register unit VSR2, the width of the first circuit 21 in the first direction is greater than the width of the second circuit 22 in the first direction.

[0109] In the embodiment, the width of the first circuit 21 in the second direction D2 is equal to the width of the second circuit 22 in the second direction D2, which can be understood as that the part of the second circuit 22 with the same circuit structure as the first circuit 21 has the same width in the second direction. For example, when the second circuit 22 includes the scan shift register unit VSR1, the width of the scan shift register unit VSR1 of the second circuit 22 in the second direction is equal to the width of the scan shift register unit VSR1 of the first circuit 21 in the second direction; when the second circuit 22 includes the light-emitting shift register unit VSR2, the width of the light-emitting shift register unit VSR2 of the second circuit 22 in the second direction is equal to the width of the light-emitting shift register unit VSR2 of the first circuit 21 in the second direction.

[0110] As described above, when the wire arrangement area 1 is used to arrange the fan-out wires, the closer to the lower frame, the more the number of fan-out wires, so that the width of the first wire arrangement area 11 located on the upper position in the first direction D1 is smaller than the width of the second wire arrangement area 12 located on the lower position in the first direction D1. By setting the width of the first circuit in the first direction D1 to be larger than the width of the second circuit 22 in the first direction D1, a narrow frame can be achieved, and at the same time, enough space is left for the second wire arrangement area 12 to arrange a large number of fan-out wires. In the display panel, the shift register unit VSR can be arranged in a single-sided driving manner or in a double-sided driving manner. For details, refer to Figure 23 Since the closer to the lower frame, the fewer the number of pixels connected on the scanning line, and the fewer the number of pixels to be driven by the shift register unit, by setting the first circuit 21 to include the scanning shift register unit VSR1 and the light-emitting shift register unit VSR2, double-sided driving can be achieved, which can meet the driving requirement of a large number of pixels, and at the same time, the first circuit 21 has a large width in the first direction D1. By setting the second circuit 22 to include the scanning shift register unit VSR1 or the light-emitting shift register unit VSR2, the driving requirement of a small number of pixels can be met, and at the same time, the second circuit 22 has a small width in the first direction, so as to achieve the design purpose of a narrow frame.

[0111] It should be noted that, Figure 23 Only the first circuit 21 including one scanning shift register unit VSR1 and one light-emitting shift register unit VSR2 is taken as an example for illustration. In other embodiments, the first circuit 21 can include a larger number of scanning shift register units VSR1 and / or a larger number of light-emitting shift register units VSR2, which are not limited in the embodiments of the present application. In addition, Figure 23 Only the second circuit 22 in the left frame of the panel including the light-emitting shift register unit VSR2 and the second circuit in the right frame including the scanning shift register unit VSR1 is taken as an example for illustration. In other embodiments, the second circuit 22 in the left frame can include the scanning shift register unit VSR1, and the second circuit in the right frame can include the light-emitting shift register unit VSR2, which are not limited in the embodiments of the present application.

[0112] Figure 24 is another structure diagram of a display panel provided by the embodiments of the present application, as Figure 24As shown, in a specific embodiment, optionally, the first wiring arrangement area 11 includes a first sub-wiring arrangement area 11a and a second sub-wiring arrangement area 11b, and the second wiring arrangement area 12 includes a third sub-wiring arrangement area 12a and a fourth sub-wiring arrangement area 12b; the first sub-wiring arrangement area 11a and the third sub-wiring arrangement area 12a are connected to form a first circuit area F1, and the second sub-wiring arrangement area 11b and the fourth sub-wiring arrangement area 12b are connected to form a second circuit area F2; the first circuit 21 includes a first sub-circuit 21a and a second sub-circuit 21b, and the second circuit 22 includes a third sub-circuit 22a and a fourth sub-circuit 22b; along the first direction D1, the first sub-circuit 21a overlaps the first sub-wiring arrangement area 11a, the second sub-circuit 21b overlaps the second sub-wiring arrangement area 11b, the third sub-circuit 22a overlaps the third sub-wiring arrangement area 12a, and the fourth sub-circuit 22b overlaps the fourth sub-wiring arrangement area 12b; the first circuit area F1 is arranged with fan-out wires, the first sub-circuit 21a and the third sub-circuit 22a include a shift register unit VSR; the second circuit area F2 is arranged with data compensation wires, the second sub-circuit 21b and the fourth sub-circuit 22b include an electrostatic protection circuit ESD, and the electrostatic protection circuit ESD is electrically connected with the data line; the first area A1 includes a bonding area A11, and the first circuit area F1 is located on one side of the second circuit area F2 close to the bonding area A11.

[0113] Specifically, the fan-out wires need to be electrically connected with the data lines of the display area (such as the second area A2) and the pads in the bonding area A11 respectively to realize the transmission of data signals, and the data compensation wires need to overlap the data lines to form a capacitor to compensate the load of the data lines. In view of this, in order to simultaneously meet the wiring requirements of the fan-out wires and the data compensation wires and reduce the wiring difficulty, the first circuit area F1 for arranging the fan-out wires is arranged on one side of the second circuit area F2 for arranging the data compensation wires close to the bonding area A11 in the embodiment.

[0114] Further, as described above, in the special-shaped display screen, the widths of the first circuit area F1 where the fan-out wires are located in the first direction are different, in order to realize narrow frame and meet the wiring requirements of the fan-out wires, the layout of the shift register unit overlapping the first circuit area in the first direction can be adjusted, and the specific adjustment method can be referred to the description above, which will not be repeated here.

[0115] In addition, as described above, in the special-shaped display screen, the widths of the second circuit area F2 where the data compensation wires are located in the first direction are different, in order to realize narrow frame and meet the wiring requirements of the data compensation wires, the layout of the electrostatic protection circuit overlapping the second circuit area in the first direction can be adjusted, and the specific adjustment method can be referred to the description above, which will not be repeated here.

[0116] Further, as described above,Figure 24 For the shift register units VSR overlapping with the second circuit area F2 and the electrostatic protection circuit ESD in the first direction D1, the width in the first direction can be equal or not equal, and the embodiments of the present application do not limit this. For example, referring to Figure 24 The third circuit 5 and the fourth circuit 6 can be shift register units, wherein the third circuit 5 is located at the side of the second sub-circuit 21b away from the first sub-wire arrangement area 11b, and the fourth circuit 6 is located at the side of the fourth sub-circuit 22b away from the fourth sub-wire arrangement area 12b; the width of the third circuit 5 in the first direction D1 is smaller than the width of the fourth circuit 6 in the first direction D1. In this way, the width of the third circuit 5 and the second sub-circuit 21b in the first direction D1 is complementary, and the width of the fourth circuit 6 and the fourth sub-circuit 22b in the first direction D1 is complementary, which is beneficial to further make full use of the space of the electrostatic protection circuit corresponding to the circuit arrangement area away from the side of the data compensation wire corresponding to the wire arrangement area, and improve the space utilization.

[0117] For example, Figure 25 is a cross-sectional structure schematic diagram of the display panel taken along the line VV’ in Figure 24 As shown in Figure 24 and Figure 25 , optionally, the wire arrangement area 1 includes first wires 101 and second wires 102, and at least part of the first wires 101 are located in the first metal layer Y1, and at least part of the second wires 102 are located in the second metal layer Y2.

[0118] Specifically, by dividing the wires in the wire arrangement area 1 into the first wires 101 and the second wires 102, and setting at least part of the first wires 101 in the first metal layer Y1 and at least part of the second wires 102 in the second metal layer Y2, the wires in the wire arrangement area are set by different metal layers, which is beneficial to reduce the risk of short circuit between the wires.

[0119] For example, referring to Figure 25 In a specific embodiment, the first wires 101 and the second wires 102 can be alternately arranged in the first direction D1, the first wires 101 are located in the first metal layer Y1, and the second wires 102 are located in the second metal layer Y2.

[0120] For example, referring to the above description, the circuits arranged in the circuit arrangement area 2 generally include elements such as transistors T and capacitors C, the transistor T includes a gate GE, a source SE and a drain DE, the capacitor C includes a first plate CE1 and a second plate CE2, and the first metal layer Y1 and the second metal layer Y2 can be two of the gate GE, the source SE, the drain DE, the first plate CE1 and the second plate CE2 located in different film layers. For example, Figure 25The gate electrode GE and the first plate CE1 are located in the same metal film layer, the source electrode SE and the drain electrode DE are located in the same metal film layer, the second plate CE2 is located between the two metal film layers, the first metal layer Y1 is the film layer where the gate electrode GE is located, and the second metal layer Y2 is the film layer where the second plate CE2 is located. For example, the first metal layer where the first wire 101 is located and the second metal layer where the second wire 102 is located can also be selected as other metal film layers, and the embodiments of the present application are not limited thereto.

[0121] It should be further pointed out that, Figure 25 For example, only the cross section of the first line area where the fan-out wire is located is taken as an example, and for the data compensation wire, it can also be arranged in different metal film layers, and the embodiments of the present application are not limited thereto.

[0122] It should be further pointed out that, the above embodiments only take the shape of the display panel as a circle as an example, and in other embodiments, the display panel can also be annular, or can also be a display panel with a local rounded corner, and the embodiments of the present application are not limited thereto. For example, Figure 26 is another structure diagram of a display panel provided by the embodiments of the present application, as shown in Figure 26 Optionally, the first area A1 includes a rounded corner area A12, and at least part of the wire arrangement area 1 and the circuit arrangement area 2 are located in the rounded corner area A12.

[0123] For example, Figure 26 The rounded corner areas in the lower left and lower right of the display panel can include a wire arrangement area and a circuit arrangement area, the wire arrangement area is used to arrange fan-out wires, and the circuit arrangement area is used to arrange shift register units, and the corresponding setting mode can refer to the description above, and will not be repeated here.

[0124] For example, Figure 26 The rounded corner areas in the upper left and upper right of the display panel can include a wire arrangement area and a circuit arrangement area, the wire arrangement area is used to arrange data compensation wires, and the circuit arrangement area is used to arrange electrostatic protection circuits, and the corresponding setting mode can refer to the description above, and will not be repeated here.

[0125] Finally, it should be pointed out that, the above embodiments all take the first area of the display panel as a non-display area (a frame area), i.e., the first area does not include pixels as an example. In other embodiments, the first area can also include pixels, at this time, the layout of the pixel circuit can be compressed to concentrate the pixel circuit in the middle area, and the circuit and the wire originally arranged in the non-display area are compressed into the display area to realize the design of a borderless display panel. In this case, the technical solution of the embodiments of the present application is beneficial to reduce the total width of the wire arrangement area and the circuit arrangement area in the first direction, and is further beneficial to reduce the design difficulty of the pixel circuit in the internal area.

[0126] Based on the same inventive concept, embodiments of the present invention also provide a display device. For example, Figure 27 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 27 As shown, the display device 200 includes the display panel 100 provided in any of the above embodiments, and therefore has the same beneficial effects as the above display panel. The similarities can be found in the description of the above embodiments, and will not be repeated here. The display device 200 can be any type of LED display. Furthermore, the display device 200 provided in the embodiments of the present invention can be... Figure 27 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0127] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized by, The display panel comprises a first region and a second region, the first region comprises a trace arrangement region and a circuit arrangement region, the trace arrangement region and the circuit arrangement region are arranged along a first direction, and at least the second region comprises a pixel; The circuit arrangement region comprises a first circuit and a second circuit, the first circuit and the second circuit are arranged along a second direction, the second direction intersects the first direction, and a width of the first circuit in the first direction is greater than a width of the second circuit in the first direction; wherein, The trace arrangement region comprises a first trace arrangement region and a second trace arrangement region, along the first direction, the first circuit overlaps the first trace arrangement region, the second circuit overlaps the second trace arrangement region, and a width of the first trace arrangement region in the first direction is less than a width of the second trace arrangement region in the first direction; The first circuit and the second circuit have the same circuit structure, and a width of the first circuit in the second direction is less than a width of the second circuit in the second direction; The first circuit and the second circuit comprise the same first part and the same second part; In the first circuit, the first part and the second part are arranged side by side along the first direction; In the second circuit, the first part and the second part are arranged side by side along the second direction.

2. The display panel of claim 1, wherein, The first circuit and the second circuit each comprise an electrostatic protection circuit; The electrostatic protection circuit comprises a first switch unit and a second switch unit, a first end of the first switch unit is electrically connected to a first level signal end, a second end of the first switch unit, a first end of the second switch unit, and a data line are connected to a first node, a second end of the second switch unit is electrically connected to a second level signal end, a voltage of a first level signal of the first level signal end is greater than a voltage of a second level signal of the second level signal end; a control end of the first switch unit is electrically connected to the first level signal end, and a control end of the second switch unit is electrically connected to the first node; The first part is composed of the first switch unit, and the second part is composed of the second switch unit.

3. The display panel of claim 2, wherein, The first switch unit comprises a first switch transistor and a second switch transistor connected in series, and control ends of the first switch transistor and the second switch transistor are electrically connected to the first level signal end; the second switch unit comprises a third switch transistor and a fourth switch transistor connected in series, and control ends of the third switch transistor and the fourth switch transistor are electrically connected to the first node; The first circuit comprises a first electrostatic protection circuit, in the first electrostatic protection circuit, the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are arranged side by side along the first direction; or, the first switch transistor and the second switch transistor are arranged side by side along the second direction, and the third switch transistor and the fourth switch transistor are arranged side by side along the second direction; The second circuit comprises a second electrostatic protection circuit, in which the first switch transistor, the second switch transistor, the third switch transistor and the fourth switch transistor are arranged side by side in the second direction.

4. The display panel of claim 2, wherein, The first circuit is located on one side of the first wiring arrangement area away from the second area; and the second circuit is located on one side of the second wiring arrangement area away from the second area.

5. The display panel of claim 4, wherein, The display panel further comprises a third circuit and a fourth circuit, the third circuit is located on one side of the first circuit away from the first wiring arrangement area, and the fourth circuit is located on one side of the second circuit away from the second wiring arrangement area. The width of the third circuit in the first direction is less than the width of the fourth circuit in the first direction; and the width of the third circuit in the second direction is greater than the width of the fourth circuit in the second direction.

6. The display panel of claim 5, wherein, The third circuit and the fourth circuit comprise a shift register unit.

7. The display panel of claim 2, wherein, The first wiring arrangement area and the second wiring arrangement area are arranged with data compensation wires.

8. The display panel of claim 1, wherein, The first circuit and the second circuit each comprise a shift register unit. The shift register unit comprises a first type of transistor and a second type of transistor, the aspect ratio of the first type of transistor is greater than the aspect ratio of the second type of transistor. The first part is composed of at least the first type of transistor, and the second part is composed of at least the second type of transistor.

9. The display panel of claim 8, wherein, The first type of transistor is electrically connected to the output end of the shift register unit. The second type of transistor is electrically connected to the first type of transistor.

10. The display panel of claim 1, wherein, The first circuit and the second circuit each comprise a shift register unit. The shift register unit comprises a first type of transistor, the first type of transistor is electrically connected to the output end of the shift register unit, and the first type of transistor comprises a plurality of first sub-transistors arranged in parallel. The first circuit includes a first shift register unit, in which all the first sub-transistors in the first type of transistors are arranged in the first direction and the second direction Array arrangement; The second circuit includes a second shift register unit, in which all the first sub-transistors in the first type of transistors are arranged in the first direction and the second direction Array arrangement; Wherein, a and c represent the number of first sub-transistors in the first direction, and b and d represent the number of first sub-transistors in the second direction. a×b=c×d; In the first direction, a>c; In the second direction, b 11. The display panel of claim 8 or 10, wherein, The display panel comprises a scanning shift register unit and a light-emitting shift register unit. The first circuit and the second circuit each comprise at least one scanning shift register unit and / or at least one light-emitting shift register unit.

12. The display panel of claim 11, wherein, The first circuit and the second circuit each comprise at least one scanning shift register unit and at least one light-emitting shift register unit, and the scanning shift register unit and the light-emitting shift register unit are arranged side by side in the first direction.

13. The display panel of claim 12, wherein, The first circuit and the second circuit each comprise at least two scanning shift register units and at least one light-emitting shift register unit. The at least two scanning shift register units are arranged side by side in the second direction, and in the first direction, the light-emitting shift register unit overlaps both the at least two scanning shift register units.

14. The display panel of claim 8 or 10, wherein, The first circuit is located on one side of the first wiring arrangement area close to the second area; and the second circuit is located on one side of the second wiring arrangement area close to the second area.

15. The display panel of claim 8 or 10, wherein, The first trace arrangement area and the second trace arrangement area are arranged with fan-out traces.

16. The display panel of claim 1, wherein, The first trace arrangement area comprises a first sub-trace arrangement area and a second sub-trace arrangement area, and the second trace arrangement area comprises a third sub-trace arrangement area and a fourth sub-trace arrangement area; the first sub-trace arrangement area and the third sub-trace arrangement area are connected to form a first circuit area, and the second sub-trace arrangement area and the fourth sub-trace arrangement area are connected to form a second circuit area. The first circuit comprises a first sub-circuit and a second sub-circuit, and the second circuit comprises a third sub-circuit and a fourth sub-circuit; along the first direction, the first sub-circuit overlaps the first sub-trace arrangement area, the second sub-circuit overlaps the second sub-trace arrangement area, the third sub-circuit overlaps the third sub-trace arrangement area, and the fourth sub-circuit overlaps the fourth sub-trace arrangement area. The first circuit area is arranged with fan-out traces, and the first sub-circuit and the third sub-circuit comprise shift register units. The second circuit area is arranged with data compensation traces, the second sub-circuit and the fourth sub-circuit comprise electrostatic protection circuits, and the electrostatic protection circuits are electrically connected with data lines. The first area comprises a binding area, and the first circuit area is located on one side of the second circuit area close to the binding area.

17. The display panel of claim 1, wherein, The trace arrangement area comprises first traces and second traces, at least part of the first traces are located on a first metal layer, and at least part of the second traces are located on a second metal layer.

18. The display panel of claim 1, wherein, The first area comprises a rounded corner area, and at least part of the trace arrangement area and the circuit arrangement area are located in the rounded corner area.

19. The display panel of claim 1, wherein, The shape of the display panel comprises a circle.

20. A display device comprising: The display panel comprises any one of claims 1-19. The display panel comprises any one of claims 1-19.

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