Display circuit and repairing method thereof, display panel and display device

Abstract

The application discloses a display circuit and a repairing method thereof, a display panel and a display device, and relates to the technical field of display panels. In the circuit, a data line of a data driving module is electrically connected with a compensation trace of an in-plane compensation module, and an in-plane isolation module is arranged between the data line and the in-plane compensation module. The in-plane isolation module is used for determining a data display signal sent by the data driving module according to a breakpoint fault of the data line, and outputting the data display signal with an unchanged signal gain to the compensation trace. The in-plane compensation module is used for performing high-frequency gain compensation on the data display signal flowing through the compensation trace, and inputting the compensated data display signal to a repairing line, so that the display brightness of each pixel unit electrically connected with the repairing line is the same as the display brightness of each pixel unit electrically connected with a normal data line. The application significantly improves the display quality of the display panel after the line break is repaired.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to a display circuit and its repair method, a display panel, and a display device. Background Technology

[0002] In the manufacturing process of displays, vertically broken data cables are a common quality issue. Specifically, when a vertically broken data cable occurs, although the side of the data cable connected to the COF (Chip on Film) may still display, the other side will exhibit poor display quality.

[0003] Existing display repair methods typically involve pre-setting repair lines on the display panel. When a break in the data line is detected, the section disconnected from the data drive module at the break point is connected to the repair line. The repair line then replaces the broken section to transmit data signals, thus repairing the broken data line. However, the increased transmission path of the data signal after repair leads to a greater RC (resistor-capacitor) load. This increased RC load causes the high-frequency components of the data signal to attenuate much more than the low-frequency components. In the time domain, this manifests as a waveform rise delay, resulting in insufficient charging of the sub-pixel units on the repair line during the charging time. Consequently, the repaired section appears as an overall dark line when displayed, severely impacting the display quality of the repaired panel.

[0004] In summary, improving the display quality after repairing broken lines on a display panel is a pressing technical issue that needs to be addressed. Summary of the Invention

[0005] The main objective of this application is to provide a display circuit and its repair method, a display panel, and a display device, which aim to eliminate weak line problems in display repair and improve display quality.

[0006] To achieve the above objectives, this application provides a display circuit, which includes a data driving module, an in-plane isolation module and an in-plane compensation module disposed in the non-display area of ​​the display panel;

[0007] The data line of the data driving module is electrically connected to the compensation trace of the in-plane compensation module, and the in-plane isolation module is provided between the data line and the in-plane compensation module.

[0008] The in-plane isolation module is used to determine the data display signal sent by the data driving module based on the breakpoint fault that occurred in the data line, and to output a data display signal with unchanged signal gain to the compensation trace;

[0009] The in-plane compensation module is used to perform high-frequency gain compensation based on the data display signal after it flows through the compensation trace, and input the compensated data display signal to the repair line, so that the display brightness of each pixel unit electrically connected to the repair line is the same as the display brightness of each pixel unit electrically connected to the normal data line; wherein...

[0010] The repair line is the data line where the breakpoint fault corresponds to a data line that is not connected to the data driver module, and the normal data line is the data line where the breakpoint is electrically connected to the data driver module.

[0011] In one embodiment, the in-plane isolation module includes a first thin-film transistor, a first resistor, and a bias voltage terminal;

[0012] The gate terminal of the first thin-film transistor is electrically connected to the data line, the first path terminal of the first thin-film transistor is electrically connected to the bias voltage terminal, the second path terminal of the first thin-film transistor is electrically connected to the first terminal of the first resistor, and the second terminal of the first resistor is grounded.

[0013] The compensation trace is electrically connected between the second terminal of the first thin-film transistor and the first terminal of the first resistor.

[0014] In one embodiment, the in-plane compensation module includes a first capacitive-resistive unit, a second capacitive-resistive unit, and a second thin-film transistor;

[0015] The gate of the second thin-film transistor forms the input terminal of the in-plane compensation module and is electrically connected to the compensation trace. The first end of the first capacitive-resistive unit forms the communication terminal of the in-plane compensation module and is electrically connected to the first path terminal of the second thin-film transistor. The second end of the first capacitive-resistive unit is electrically connected to the power supply terminal.

[0016] The output terminal of the first capacitive resistor unit constitutes the output terminal of the in-plane compensation module, and is electrically connected to the side of the data driving module where the break point of the data line is not connected.

[0017] The second terminal of the second thin-film transistor is electrically connected to the input terminal of the second capacitive-resistive unit, and the output terminal of the second capacitive-resistive unit is grounded.

[0018] In one embodiment, the first capacitive-resistive unit includes a second resistor and a first capacitor;

[0019] The first end of the second resistor forms the first end of the first capacitive-resistive unit, and is electrically connected to the first pass terminal of the second thin-film transistor and the first end of the first capacitor, respectively.

[0020] The connection point where the first end of the second resistor is electrically connected to the first end of the first capacitor forms the output terminal of the first capacitive-resistive unit, and is electrically connected to the side of the data drive module where the break point of the data line is not connected.

[0021] The second end of the second resistor forms the second end of the first capacitive-resistive unit, and is electrically connected to the power supply terminal and the second end of the first capacitor, respectively.

[0022] In one embodiment, the second capacitive-resistive unit includes a third resistor and a second capacitor connected in parallel;

[0023] The first end of the third resistor connected in parallel with the second capacitor constitutes the input terminal of the second capacitive-resistive unit, and is electrically connected to the second path terminal of the second thin-film transistor.

[0024] The second end of the third resistor connected in parallel with the second capacitor forms the output terminal of the second capacitive-resistive unit, which is then grounded.

[0025] In one embodiment, the display circuit includes a cascaded component when the display panel is in high-frequency refresh mode, and the cascaded component is provided with a plurality of the in-plane compensation modules;

[0026] The output terminal of the in-plane compensation module is electrically connected to the input terminal of the adjacent in-plane compensation module, and a third capacitor is provided between the output terminal of the in-plane compensation module and the adjacent in-plane compensation module.

[0027] The first end of the third capacitor is electrically connected between the output end of the in-plane compensation module and the adjacent in-plane compensation module, and the second end of the third capacitor is electrically connected to the connection end of the adjacent in-plane compensation module.

[0028] Furthermore, to achieve the above objectives, this application also provides a method for repairing a display circuit. This method is applied to the display circuit described in any of the preceding claims, and includes the following steps:

[0029] Based on the breakpoint fault that occurred on the data line of the data driver module, the in-plane isolation module determines the data display signal sent by the data driver module, and outputs a data display signal with unchanged signal gain to the compensation trace of the in-plane compensation module.

[0030] After determining that the in-plane compensation module has access to the data display signal flowing through the compensation trace, high-frequency gain compensation is performed based on the data display signal, and the compensated data display signal is input to the repair line, enabling the display brightness of each pixel unit electrically connected to the repair line to be the same as the display brightness of each pixel unit electrically connected to the normal data line; wherein...

[0031] The repair line is the data line where the breakpoint fault corresponds to a data line that is not connected to the data driver module, and the normal data line is the data line where the breakpoint is electrically connected to the data driver module.

[0032] In one embodiment, the method for repairing the display circuit includes:

[0033] When the display panel is in high-frequency refresh mode, a cascaded component is constructed based on each of the in-plane compensation modules and the third capacitor set between each of the in-plane compensation modules and the adjacent in-plane compensation modules.

[0034] Based on the response of the high-frequency refresh mode, the ideal bandwidth corresponding to the high-frequency refresh mode is determined, and the bandwidth of the data display signal flowing through the compensation line is compensated by the cascaded component until the actual bandwidth of the data display signal is the same as the ideal bandwidth, and then the data display signal is output to the repair line.

[0035] In addition, to achieve the above objectives, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the display circuit described in any of the above claims.

[0036] Furthermore, to achieve the above objectives, this application also provides a display device, which includes at least:

[0037] The aforementioned display panel; or,

[0038] A processor, a memory, and a repair program for a display circuit stored in the memory that can be executed by the processor, wherein when the repair program for the display circuit is executed by the processor, it implements the steps of the repair method for the display circuit described in any of the preceding claims.

[0039] This application provides a display circuit and its repair method, a display panel, and a display device. By integrating an in-plane isolation module and an in-plane compensation module into the display circuit, the data lines of the interrupted data driving module are repaired, significantly improving the display quality of the display panel after the interruption is repaired. Specifically, the data lines of the data driving module are routed with the compensation traces of the in-plane compensation module, and an in-plane isolation module is provided between the data lines and the in-plane compensation module. When a breakpoint fault is detected in the data line of the data driver module, the in-plane isolation module provided in this application ensures that the data display signal sent by the data driver module is not interfered with. This allows the output of a data display signal with constant gain to the compensation trace, thus ensuring the integrity of the data display signal during its transmission from the data driver module to the compensation trace. Next, because the signal transmission path of the data display signal to the repair line becomes longer via the compensation trace, leading to an increased RC load, this application provides effective high-frequency gain compensation for the data display signal transmitted via the in-plane isolation module using an in-plane compensation module. This effectively suppresses the attenuation of high-frequency components in the data display signal, ensuring that the compensated data display signal can fully meet the charging requirements of each pixel unit on the repair line. Finally, the compensated data display signal is input to the repair line, ensuring that the pixel units connected to the repaired data line (i.e., the repair line) maintain the same display brightness as those connected to the normal data line, guaranteeing the uniformity of the entire display panel image and significantly improving the display quality after the broken line is repaired. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a wire break repair structure based on existing technology;

[0043] Figure 2 This is a schematic diagram comparing the ideal data input signal with the data input signal of the repaired trace;

[0044] Figure 3 This is a structural block diagram of the first embodiment of the display circuit of this application;

[0045] Figure 4This is a schematic diagram of the bilateral compensation structure involved in the embodiments of this application;

[0046] Figure 5 This is a schematic diagram of the in-plane isolation module structure involved in the embodiments of this application;

[0047] Figure 6 This is an equivalent signal model diagram of the in-plane isolation module involved in the embodiments of this application;

[0048] Figure 7 This is a schematic diagram of the in-plane compensation module structure involved in the embodiments of this application;

[0049] Figure 8 This is an equivalent signal model diagram of the in-plane compensation module involved in the embodiments of this application;

[0050] Figure 9 This is a schematic diagram of the amplitude-frequency response of the data display signal after compensation, according to an embodiment of this application.

[0051] Figure 10 This is a waveform diagram illustrating the signal state before and after entering the compensation stage in the embodiment of this application;

[0052] Figure 11 This is a schematic diagram of the two-level compensation in-plane structure involved in the embodiment of this application;

[0053] Figure 12 This is an equivalent signal model diagram corresponding to the two-level compensation in-plane structure involved in the embodiments of this application;

[0054] Figure 13 This is a schematic diagram of the terminal device involved in the embodiments of this application.

[0055] Explanation of icon numbers:

[0056] 10. Data driving module; 20. In-plane isolation module; 30. In-plane compensation module; 100. Display panel; L1. Compensation trace; T1. First thin-film transistor; R1. First resistor; VAA. Bias voltage terminal; RC1. First capacitive-resistive unit; RC2. Second capacitive-resistive unit; T2. Second thin-film transistor; R2. Second resistor; C1. First capacitor; R3. Third resistor; C2. Second capacitor; C3. Third capacitor.

[0057] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0059] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0060] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0061] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0062] An LCD (Liquid Crystal Display) panel consists of data lines, scan lines, TFTs (Thin Film Transistors), liquid crystal light valves, RGB (Red-Green-Blue) filters, and upper and lower polarizers. Its working principle is as follows: the scan lines first activate the first row of TFTs; then, the data lines send data voltage to each pixel in the first row to control the deflection angle of the liquid crystal, thus controlling the amount of light passing through the liquid crystal light valve, achieving different grayscale displays. Finally, the RGB filters achieve color displays.

[0063] An AMOLED (Active-matrix organic light-emitting diode) panel consists of data lines, scan lines, OLEDs (Organic Light-Emitting Diodes), and a power supply VDD. Its working principle is as follows: the scan lines first turn on the first row of TFTs, then the data lines send data voltage to each pixel in the first row. This data voltage controls the current flowing through the other TFTs, thus controlling the OLED brightness. Different RGB OLEDs are arranged into an OLED panel array to display images.

[0064] During the production of LCD and AMOLED display panels, some defective products may have broken data lines due to various reasons. These broken lines appear as a vertical dark line when the panel is lit, requiring scrapping. This indirectly increases costs and reduces production efficiency. To avoid this situation, refer to... Figure 1 , Figure 1 This is a schematic diagram of a broken wire repair structure based on existing technology. Figure 1 The data lines from A to C shown represent the normal output circuit of COF (Chip On Flex) before the breakpoint. Figure 1 The section from B to B' shown is the repair line. Figure 1 The B→B'→C segment shown is the repair output line after the breakpoint. Specifically, existing technology sets up such a circuit on LCD and OLED display panels. Figure 1 The repair line shown connects the section of the broken data line (with breakpoint C) that is disconnected from the data driver module to the repair line. By using the repair line to connect the section of the broken data line that is disconnected from the data driver module to the data driver module, a data signal is provided to the section of the broken data line that is disconnected from the data driver module, thereby enabling the section of the broken data line that is disconnected from the data driver module to light up.

[0065] Theoretically, the data signal transmitted from the repair line to the breakpoint should be consistent with the data signal output by the data driver module. However, in practical applications, the transmission path of the repaired data signal becomes longer, leading to a larger RC load. Its low-pass characteristic causes the attenuation of the high-frequency portion of the signal to be much greater than the attenuation of its low-frequency portion. This is reflected in the time domain by a delay in the waveform rise, resulting in insufficient charging of the sub-pixel units on the repair line during the charging time, leading to an overall dark line in the repaired segment. (Refer to...) Figure 2 , Figure 2 This is a schematic diagram comparing the ideal data input signal with the data input signal of the repaired trace. Figure 2 The LA shown is the ideal data input signal. Figure 2The LB shown represents the data input signal after the trace has been repaired. In other words, repairing a broken data line by setting a repair line results in poor image quality on the repaired display panel. Therefore, a voltage amplification or overshoot repair circuit, primarily composed of operational amplifiers, is installed on the PCBA (Printed Circuit Board Assembly) outside the display panel. However, the use of operational amplifiers and related components undoubtedly increases costs. Furthermore, since the use of operational amplifiers and related components involves traces on the PCBA, these traces actually contain parasitic capacitances. At high pixel frequencies and short charging times, their load effect significantly impacts the original COF output.

[0066] To address the aforementioned deficiencies, this application provides a display circuit and its repair method, a display panel, and a display device. By setting up a data line of the data driving module in the display circuit and electrically connecting it to the compensation trace of the in-plane compensation module through an in-plane isolation module, the data line with a breakpoint is effectively compensated in-plane, thereby significantly improving the display quality of the display panel after the breakpoint is repaired.

[0067] This application provides a display circuit, referring to... Figure 3 As shown, Figure 3 This is a structural block diagram of the first embodiment of the display circuit of this application. The display circuit includes a data driving module 10, and an in-plane isolation module 20 and an in-plane compensation module 30 disposed in the non-display area of ​​the display panel 100; the data line of the data driving module 10 is electrically connected to the compensation trace L1 of the in-plane compensation module 30, and the in-plane isolation module 20 is disposed between the data line and the in-plane compensation module 30.

[0068] In this embodiment, the data line of the data driving module 10 is electrically connected to the compensation trace L1 of the in-plane compensation module 30, and an in-plane isolation module 20 is electrically connected between the data line and the in-plane compensation module 30. This in-plane isolation module 20 not only avoids the load-draining effect of the subsequent compensation trace L1 circuit on the original COF output stage (i.e., the output terminal of the data driving module 10), but also ensures... Figure 1 The AC segment data line (i.e., the normal data line) shown ensures the normal display of each pixel unit connected to it; the in-plane isolation module 20 also ensures that the data display signal sent by the data driving module 10 is not interfered with, thus enabling the output of a data display signal with unchanged signal gain to the compensation trace L1; next, since the display circuit for repairing the broken data line provided in this application has more than the original data line... Figure 1The dashed line AB (i.e., compensation trace L1) shown in the diagram will produce a severe low-pass effect, causing attenuation of high-frequency components in the data display signal. This application places the in-plane compensation module 30 at the receiving end of the data display signal before it enters the data line BC (i.e., the repair line) before it is repaired, and compensates for the high-frequency gain of the data display signal to offset the low-pass effect. Figure 1 The low-pass effect brought about by the dashed line in segment AB effectively suppresses the attenuation of high-frequency components in the data display signal, ensuring that the compensated data display signal can fully meet the charging needs of each pixel unit on the repair line.

[0069] It should be noted that the load removal effect can be understood as the load removal of the original COF output stage by the L1 circuit of the subsequent compensation line, which causes voltage fluctuations when the AC segment data line is connected to the data display signal, resulting in dark lines on the AC segment data line.

[0070] The in-plane isolation module 20 is used to determine the data display signal sent by the data driving module 10 based on the breakpoint fault that occurred in the data line, and to output a data display signal with unchanged signal gain to the compensation trace L1.

[0071] In this embodiment, when a breakpoint fault is determined to occur in the data line of the data driving module 10, the in-plane isolation module 20 provided in this application not only avoids the deload effect of the subsequent compensation trace L1 circuit on the original COF output stage, ensuring the normal display of each pixel unit connected to the normal data line; it also ensures that the data display signal sent by the data driving module 10 will not be interfered with by the breakpoint fault during transmission, and can stably output a data display signal with constant signal gain to the compensation trace L1, thereby ensuring the integrity of the data display signal during the transmission process from the data driving module 10 to the compensation trace L1.

[0072] The in-plane compensation module 30 is used to perform high-frequency gain compensation based on the data display signal after the data display signal flows through the compensation trace L1, and input the compensated data display signal to the repair line, so that the display brightness of each pixel unit electrically connected to the repair line is the same as the display brightness of each pixel unit electrically connected to the normal data line; wherein, the repair line is the data line whose data line break point is not connected to the data driving module 10, and the normal data line is the data line whose data line break point is electrically connected to the data driving module 10.

[0073] In this embodiment, the RC load increases due to the longer signal transmission path of the data display signal from the compensation trace L1 to the repair line. This application effectively compensates the high-frequency gain of the data display signal transmitted via the in-plane isolation module 20 by setting an in-plane compensation module 30, which effectively suppresses the attenuation of high-frequency components in the data display signal and ensures that the compensated data display signal can fully meet the charging requirements of each pixel unit on the repair line. Finally, the compensated data display signal is input to the repair line, so that the pixel units connected to the repaired data line (i.e., the repair line) have the same display brightness as the pixel units connected to the normal data line, ensuring the uniformity of the entire display panel 100 screen display, and thus significantly improving the display quality of the display panel 100 after the broken line is repaired.

[0074] In a specific embodiment, refer to Figure 4 , Figure 4 This is a schematic diagram of the bilateral compensation structure involved in the embodiments of this application. This application can also divide the display panel 100 into two parts along its central axis to obtain a right panel and a left panel. For example, the data driving module 10-1 is disposed on the right panel area of ​​the PCBA board, and the data driving module 10-2 is disposed on the left panel area of ​​the PCBA board. The data lines of the data driving module 10-1 are electrically connected to the compensation trace L1-1 of the in-plane compensation module 30-1 through the in-plane isolation module 20-1, and the data lines of the data driving module 10-2 are electrically connected to the compensation trace L1-1 of the in-plane compensation module 30-2 through the in-plane isolation module 20-2, thereby constructing a bilateral compensation structure. For example, when a data line in the display panel 100 experiences a breakage fault, the target panel area to which the broken data line belongs is determined. If the target panel area is the left panel area, a constant-gain data display signal is output to the compensation trace L1-1 via the in-plane isolation module 20-1, and the data display signal flowing through the compensation trace L1 is connected to the in-plane compensation module 30-1 for high-frequency gain compensation to ensure that the compensated data display signal can fully meet the charging requirements of each pixel unit on the repair line. If the target panel area is the right panel area, a constant-gain data display signal is output to the compensation trace L1-2 via the in-plane isolation module 20-2, and the data display signal flowing through the compensation trace L1 is connected to the in-plane compensation module 30-2 for high-frequency gain compensation to ensure that the compensated data display signal can fully meet the charging requirements of each pixel unit on the repair line. In other words, this application can improve the repair efficiency of broken lines in the display panel 100 by constructing a bilateral compensation structure.

[0075] For example, refer to Figure 4 , Figure 4The compensation trace L1-1 shown is the left-side compensation trace. Figure 4 The compensation traces L1-2 shown are the right-side compensation traces. When a breakpoint C appears in the display panel 100, the AC segment data lines are displayed normally, while the BC segment data lines are dark due to the lack of data input. This application can make a laser connection at the overlap between the left-side compensation traces and the data lines. The data display signal can be sent to the BC segment data lines after passing through the A→B→C isolation compensation connection circuit, so that the pixel units connected by the repair line have the same display brightness as the pixel units connected by the normal data lines, ensuring the uniformity of the entire display panel 100 screen display, and thus significantly improving the display quality of the display panel 100 after the breakpoint repair.

[0076] Furthermore, in some feasible embodiments, reference is made to Figure 5 , Figure 5 This is a schematic diagram of the in-plane isolation module 20 involved in the embodiments of this application. The in-plane isolation module 20 includes a first thin-film transistor T1, a first resistor R1, and a bias voltage terminal VAA; the gate terminal of the first thin-film transistor T1 is electrically connected to the data line, the first path terminal of the first thin-film transistor T1 is electrically connected to the bias voltage terminal VAA, the second path terminal of the first thin-film transistor T1 is electrically connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded; the compensation trace L1 is electrically connected between the second path terminal of the first thin-film transistor T1 and the first terminal of the first resistor R1.

[0077] In this embodiment, the in-plane isolation module 20 provided in this application introduces a VAA signal as the bias voltage of the first thin-film transistor T1. Figure 5 The signal Vd1 shown is the data display signal output by the data driving module 10, also known as the input voltage transmitted from the data driving module 10 to the in-plane isolation module 20. Figure 5 The signal Vd2 shown is a data display signal with constant gain sent by the in-plane isolation module 20 to the compensation trace L1, also known as the output voltage flowing through the in-plane isolation module 20 and the compensation trace L1 into the in-plane compensation module 30. For example, when the voltage value of signal Vd1 increases (decreases), the drain current of the first thin-film transistor T1 increases (decreases), which naturally causes the voltage value of signal Vd2 to also increase (decrease), thus achieving a voltage following effect and ensuring the consistency of the preceding and following signals.

[0078] It should be noted that the first thin-film transistor T1 provided in this application can be replaced by a MOS transistor. The above is only one feasible implementation method of this application, and this application does not make any restrictions here.

[0079] In a specific embodiment, refer to Figure 6 , Figure 6 This is an equivalent signal model diagram of the in-plane isolation module 20 involved in the embodiments of this application. Figure 6 The gm shown is the transconductance of the first thin-film transistor T1. Figure 6 The V1 shown is the voltage Vgs (i.e., bias voltage) of the first thin-film transistor T1. Figure 6 The gmV1 shown is a controlled current source, representing the magnitude of the current from which the controlled current source is located. Since the first thin-film transistor T1 is located in the in-plane isolation module 20, the input section is open-circuited, thus determining that the input impedance Ri is ∞ (infinity). Figure 3 as well as Figure 4 The signal Vd1 connected to the AC segment of the data line shown is not affected by the load of the subsequent compensation trace L1 circuit, ensuring that each pixel unit connected to the AC segment of the data line displays normally. Figure 6 It can be seen that the signal gain of the data signal is as shown in the following formula (1).

[0080]

[0081] Wherein, Gain represents the signal gain of the data display signal, Rs represents the resistance of the first resistor R1, gm represents the transconductance of the first thin-film transistor T1, Vd1 represents signal Vd1, i.e., the input voltage transmitted from the data driving module 10 to the in-plane isolation module 20, and Vd2 represents signal Vd2, i.e., the output voltage flowing through the in-plane isolation module 20, through the compensation trace L1, and into the in-plane compensation module 30. In other words, to ensure that the data display signal sent by the in-plane isolation module 20 to the compensation trace L1 has a constant signal gain, the in-plane isolation module 20 of this application can gradually increase the resistance of the first resistor R1 and the transconductance of the first thin-film transistor T1 until the ratio of the product of the resistance Rs and the transconductance gm to the sum of the product values ​​is within a preset threshold range. Then, a signal Vd2 consistent with signal Vd1 is output to the compensation trace L1, thereby ensuring that the output signal Vd2 is not distorted and has a voltage following effect.

[0082] It should be noted that the preset proportional threshold is 1. That is, when the signal gain Gain of signal Vd2 is approximately 1, the in-plane isolation module 20 provided in this application has a voltage following effect, that is, the output voltage Vd2 can accurately follow the change of the input voltage Vd1, thereby ensuring the consistency between signal Vd1 and signal Vd2.

[0083] Furthermore, in some other feasible embodiments, reference is made to... Figure 7 , Figure 7This is a schematic diagram of the in-plane compensation module 30 according to an embodiment of this application. The in-plane compensation module 30 includes a first capacitive resistor unit RC1, a second capacitive resistor unit RC2, and a second thin-film transistor T2; the gate of the second thin-film transistor T2 constitutes the input terminal of the in-plane compensation module 30 and is electrically connected to the compensation trace L1; the first end of the first capacitive resistor unit RC1 constitutes the connection terminal of the in-plane compensation module 30 and is electrically connected to the first path terminal of the second thin-film transistor T2; the second end of the first capacitive resistor unit RC1 is electrically connected to the power supply terminal; the output terminal of the first capacitive resistor unit RC1 constitutes the output terminal of the in-plane compensation module 30 and is electrically connected to the side of the data driving module 10 where the data line is not connected; the second path terminal of the second thin-film transistor T2 is electrically connected to the input terminal of the second capacitive resistor unit RC2, and the output terminal of the second capacitive resistor unit RC2 is grounded.

[0084] In this embodiment, the gate of the second thin-film transistor T2 is electrically connected to the compensation trace L1 as the input terminal of the in-plane compensation module 30. After the second thin-film transistor T2 is turned on by the data display signal (i.e., signal Vd2) flowing through the compensation trace L1, the signal VAA flows from the first capacitive resistor unit RC1 through the second capacitive resistor unit RC2 to ground, obtaining the DC gain (i.e., low-frequency gain) and high-frequency gain of signal Vd2. Based on the ratio of high-frequency gain to low-frequency gain, the gain compensation factor can be accurately obtained. Next, the high-frequency component in signal Vd2 is amplified by the gain compensation factor to obtain the compensated data display signal (i.e.,... Figure 7 The signal Vr shown is input to the repair line through the output terminal of the first capacitive resistor unit RC1, thereby ensuring that the pixel units connected to the repaired data line (i.e. the repair line) have the same display brightness as the pixel units connected to the normal data line, thus ensuring the uniformity of the display of the entire display panel 100 and significantly improving the display quality of the display panel 100 after the line breakage is repaired.

[0085] Furthermore, in some feasible embodiments, reference is made to Figure 7 The first capacitive-resistive unit RC1 includes a second resistor R2 and a first capacitor C1; the first end of the second resistor R2 constitutes the first end of the first capacitive-resistive unit RC1, and is electrically connected to the first pass terminal of the second thin film transistor T2 and the first end of the first capacitor C1 respectively; the connection point where the first end of the second resistor R2 is electrically connected to the first end of the first capacitor C1 constitutes the output terminal of the first capacitive-resistive unit RC1, and is electrically connected to the side of the data drive module 10 where the data line is not connected; the second end of the second resistor R2 constitutes the second end of the first capacitive-resistive unit RC1, and is electrically connected to the power supply terminal and the second end of the first capacitor C1 respectively.

[0086] Furthermore, in some other feasible embodiments, reference is made to... Figure 7 The second capacitive-resistive unit RC2 includes a third resistor R3 and a second capacitor C2 connected in parallel; the first end of the third resistor R3 and the second capacitor C2 connected in parallel constitutes the input terminal of the second capacitive-resistive unit RC2, which is electrically connected to the second path terminal of the second thin film transistor T2; the second end of the third resistor R3 and the second capacitor C2 connected in parallel constitutes the output terminal of the second capacitive-resistive unit RC2, which is grounded.

[0087] In this embodiment, Figure 7 The third resistor R3 and the second capacitor C2 shown are the source resistor and source capacitor, respectively. Figure 7 The second resistor R2 and the first capacitor C1 shown are the parasitic resistance and capacitance at the output terminal, respectively. Figure 7 The gm1 shown is the transconductance of the second thin-film transistor T2. Figure 7 Vgs1 shown is the bias voltage of the second thin-film transistor T2. Figure 7 The gm1Vgs1 shown also represents a controlled current source. For example, refer to... Figure 8 , Figure 8 This is an equivalent signal model diagram of the in-plane compensation module 30 involved in the embodiments of this application.

[0088] The transfer function of the in-plane compensation module 30 set in this application is shown in formula (2).

[0089]

[0090] Where H(s) is the transfer function of the in-plane compensation module 30; RL is the resistance value of the second resistor R2, i.e., the parasitic resistance value; CL is the capacitance value of the first capacitor C1, i.e., the parasitic capacitance value; Rs1 is the resistance value of the third resistor R3, i.e., the source resistance value; Cs1 is the capacitance value of the second capacitor C2, i.e., the source capacitance value; gm1 is the transconductance of the second thin-film transistor T2; s0 = jw, where w is the signal frequency of signal Vd2, and s0 2 =-1.

[0091] For example, after the second thin-film transistor T2 is connected to the data display signal (i.e., signal Vd2) flowing through the compensation trace L1, the signal VAA flows from the first capacitive resistor unit RC1 through the second capacitive resistor unit RC2 to ground. At this time, the zero point of the signal frequency can be accurately obtained based on the reciprocal of the product of the source resistance and the source capacitance. The product of the transconductance gm1 and the source resistance is superimposed with a constant 1 to obtain the superimposed product data. Based on the ratio between the superimposed product data and the product of the source resistance and the source capacitance, the dominant pole of the signal frequency can be accurately obtained. Then, the DC gain corresponding to the zero point and the high-frequency gain corresponding to the dominant pole can be obtained. Based on the ratio of the high-frequency gain to the low-frequency gain, the gain compensation factor can be accurately obtained. Next, the high-frequency component in the signal Vd2 is amplified by the gain compensation factor to obtain the compensated data display signal (i.e., Vd2). Figures 7 to 8 The signal Vr shown is input to the repair line through the output terminal of the first capacitive resistor unit RC1, thereby ensuring that the pixel units connected to the repaired data line (i.e. the repair line) have the same display brightness as the pixel units connected to the normal data line, thus ensuring the uniformity of the display of the entire display panel 100 and significantly improving the display quality of the display panel 100 after the line breakage is repaired.

[0092] It should be noted that the expression corresponding to the zero point is shown in formula (3), ω z Representing zero point, Rs1 is the resistance value of the third resistor R3, i.e., the source resistance value; Cs1 is the capacitance value of the second capacitor C2.

[0093]

[0094] The expression corresponding to the principal pole is shown in equation (4), ω p1 The dominant pole is represented by Rs1, which is the resistance of the third resistor R3, i.e., the source resistance; Cs1 is the capacitance of the second capacitor C2.

[0095]

[0096] The expression corresponding to the gain compensation factor is shown in formula (5). DC Gain represents the DC gain at the zero point. HF This indicates the high-frequency gain corresponding to the dominant pole, and Peaking indicates the gain compensation factor.

[0097]

[0098] In addition, it should be noted that the dominant pole can be reasonably set by adjusting the value of the third resistor R3 and the second capacitor C2. The node (i.e., the zero point) at which the peak frequency of the gain compensation is set needs to be selected according to the refresh rate of the panel. The frequency of the gain peak position of the circuit should not be lower than the frequency of the data signal to avoid undercompensation. The specific gain compensation multiple is also controlled by the value of the third resistor R3.

[0099] The compensation bandwidth is limited by parasitic poles, primarily by the capacitance CL of the parasitic capacitor at the output. The expression corresponding to the parasitic poles is shown in equation (6), ω p2 The parasitic poles are represented by RL, which is the resistance of the second resistor R2, i.e., the parasitic resistance; and CL is the capacitance of the first capacitor C1, i.e., the parasitic capacitance.

[0100]

[0101] For example, refer to Figure 9 , Figure 9 This is a schematic diagram of the amplitude-frequency response of the compensated data display signal according to an embodiment of this application. After the second thin-film transistor T2 is connected and the data display signal (i.e., signal Vd2) flowing through the compensation trace L1 is turned on, the signal VAA flows from the first capacitive resistor unit RC1 through the second capacitive resistor unit RC2 to ground. At this time, at the zero point ω of the data display signal... z Starting with the gain compensation factor, high-frequency gain compensation is applied to the high-frequency components of the data display signal until the gain compensation factor is increased to the dominant pole ω. p1 The data display signal is transmitted to the repair line as a compensated data display signal, thereby ensuring that the compensated data display signal can fully meet the charging needs of each pixel unit on the repair line.

[0102] In summary, referring to Figure 10 , Figure 10 This is a waveform diagram of the signal state before and after entering the compensation stage in the embodiment of this application. Figure 10 Y0 in the diagram represents the ideal transmission waveform of the data display signal. The compensation trace L1 provided in this application will have more traces than a typical data output trace. Figures 3 to 4 The dashed line AB segment, which results in significant low-pass efficiency, means that the compensation trace L1 of the AB segment acts as a low-pass filter. The signal waveform of the data display signal sent to the repair line via the AB segment is as follows: Figure 10 As shown in Yt, that is Figure 10In the case of a short charging time, the data display signal sent to the repair line via the long AB segment has a delay in the rising edge of the waveform. This results in insufficient charging of each pixel unit on the repair line to the target voltage, leading to linear image distortion. This application places the in-plane compensation module 30 at the receiving end of the BC segment data line (i.e., the repair line) before the data display signal enters. By compensating the high-frequency gain of the data display signal, it counteracts the low-pass effect caused by the long AB compensation trace L1, ensuring that the compensated data display signal can fully meet the charging requirements of each pixel unit on the repair line. Furthermore, the signal transmission waveform corresponding to the compensated data display signal is as follows: Figure 10 The Yr shown represents the data. In other words, by setting a low-cost in-plane compensation module 30 at the receiving end of the repair line to receive the data display signal output via the compensation trace L1, this application can not only achieve the compensation effect of setting an external compensation circuit containing an operational amplifier outside the display panel 100, but also effectively save the cost of repairing the broken line of the display panel 100 and improve the economy of repairing the broken line of the display panel 100.

[0103] Furthermore, in some other feasible embodiments, the display circuit includes a cascaded component when the display panel 100 is in high-frequency refresh mode, the cascaded component being provided with a plurality of the in-plane compensation modules 30; the output terminal of the in-plane compensation module 30 is electrically connected to the input terminal of an adjacent in-plane compensation module 30, and a third capacitor C3 is provided between the output terminal of the in-plane compensation module 30 and the adjacent in-plane compensation module 30; the first terminal of the third capacitor C3 is electrically connected between the output terminal of the in-plane compensation module 30 and the adjacent in-plane compensation module 30, and the second terminal of the third capacitor C3 is electrically connected to the connection terminal of the adjacent in-plane compensation module 30.

[0104] In this embodiment, the high-frequency signal Vr suffers greater loss due to the low-pass characteristics of the channel, requiring higher gain for compensation. The third resistor R3 and the second capacitor C2 need to be made quite large in terms of manufacturing, posing a certain implementation challenge. This application can cascade two- or three-stage in-plane compensation modules 30 to form a cascaded component to achieve higher gain with relatively low implementation difficulty. However, module cascading will also reduce the compensation bandwidth, as the bandwidth of gain compensation will be affected. Figure 9 Parasitic pole ω shown p1Due to the influence of parasitic poles, at high refresh rates, the signal frequency of the data display signal is higher than that of the parasitic pole, thus failing to achieve the compensation effect. Therefore, in the case of module cascading, a third capacitor C3 needs to be introduced to increase the bandwidth of the subsequent compensation stage to meet the requirements of line breakage repair for high refresh rate panels. For example, the output terminal of the in-plane compensation module 30 is electrically connected to the input terminal of an adjacent in-plane compensation module 30, and a third capacitor C3 is provided between the output terminal of the in-plane compensation module 30 and the adjacent in-plane compensation module 30. The first end of the third capacitor C3 is electrically connected between the output terminal of the in-plane compensation module 30 and the adjacent in-plane compensation module 30, and the second end of the third capacitor C3 is electrically connected to the connection terminal of the adjacent in-plane compensation module 30, thereby realizing the construction of cascaded components.

[0105] It should be noted that the third capacitor C3 can be understood as a neutralizing capacitor, also known as a Miller capacitor (CN).

[0106] In a specific embodiment, refer to Figure 11 , Figure 11 This is a schematic diagram of the two-level compensation in-plane structure involved in the embodiments of this application. For example... Figure 11 The in-plane compensation module 3030-11 shown represents the first-level in-plane compensation module; as... Figure 11 The in-plane compensation module 3030-12 shown represents the second-stage in-plane compensation module. The second-stage in-plane compensation module, where other parts are ignored, is equivalent to a simple amplifier. The second capacitive-resistive unit RC2, electrically connected to the second path terminal of the second thin-film transistor T2, is grounded. Av is the amplification factor. (Refer to...) Figure 12 , Figure 12 This is an equivalent signal model diagram corresponding to the two-level compensation in-plane structure involved in the embodiments of this application. From Figure 12 The circuit shown in (a) allows observation of the effect of the introduced third capacitor C3 on the parasitic capacitance at the output terminal (i.e., the first capacitor C1). A current i flows through the third capacitor C3. c As shown in formula (7).

[0107]

[0108] Among them, i c For the current flowing through the third capacitor C3, C N This indicates the capacitance value of the third capacitor, C3.

[0109] Based on the Miller effect of the third capacitor C3, the third capacitor C3 can be equivalent to a capacitor Ci connected in parallel to ground at the amplifier input terminal (i.e., Vr1) and a capacitor Co connected in parallel to ground at the amplifier output terminal (i.e., Vr2). The expression for the Miller effect is shown in formula (8).

[0110]

[0111] For example, based on the Miller effect, the neutralizing capacitor (i.e., the third capacitor C3) can be equivalently represented at the input and output terminals of the amplifier, such as... Figure 12 As shown in (b), the third capacitor C3 is equivalent to the capacitance Ci at node X as (1-AV)CN, and the third capacitor C3 is equivalent to the capacitance Co at node Y as (1-1 / AV)CN. The third capacitor C3 is equivalent to a capacitor Ci connected in parallel to ground at the amplifier input and a capacitor Co connected in parallel to ground at the amplifier output. If the amplifier gain AV is greater than 1, the value of Ci is negative; if the amplifier gain AV is less than 1, the value of Ci is positive; if the amplifier gain AV is between 0 and 1, the value of Co is negative; if the amplifier gain AV is less than 0 or greater than 1, the value of Co is positive. Then the total parallel capacitance at node X is C1+(1-AV)CN. That is, when CN=C1 / (AV-1), the total capacitance at node X is zero. Of course, as long as Av>1, the reduction of parasitic capacitance at the output can be achieved. In other words, by introducing the third capacitor C3, the parasitic capacitance at the output of the first-stage in-plane compensation module 30 (which is also the input capacitance of the second-stage in-plane compensation module 30) is reduced, thereby increasing the parasitic pole frequency of the first-stage compensation stage to compensate for the reduction in bandwidth caused by module cascading and to meet the repair requirements of the high refresh rate panel.

[0112] In summary, this application incorporates an in-plane isolation module 20 with high input impedance, avoiding the problem of dark lines caused by PCBA parasitic parameters affecting the original COF output stage due to deloading, which cannot be solved by traditional external compensation, thus improving the repair effect. Furthermore, by setting an in-plane compensation module 30 at the receiving end of the repair line to connect the data display signal transmitted via compensation trace L1 to the receiving end of the repair line, high-frequency gain compensation for the data display signal transmitted via compensation trace L1 is achieved in-plane using a combination of TFTs and capacitors on the display panel 100. In addition, for the repair of broken lines on high refresh rate panels, the in-plane compensation module 30 in the display circuit can be improved by cascading multiple in-plane compensation modules 30 to form a cascaded component, and a third capacitor C3 (i.e., a neutralizing capacitor) is placed between the output end of the in-plane compensation module 30 and the adjacent in-plane compensation module 30 to expand the bandwidth, ensuring compensation for high-frequency signals, thereby adapting to the bandwidth compensation of high-frequency input data display signals.

[0113] Furthermore, based on the first embodiment of the display circuit of this application, a second embodiment of the display screen control method of the display circuit of this application is proposed.

[0114] The repair method for the display circuit of this application is applied to the display circuit of any of the above claims. The repair method for the display circuit of this application is performed by a terminal device that repairs the broken data line of the display panel. The repair method for the display circuit of this application includes the following implementation steps S10 to S20.

[0115] Step S10: Based on the breakpoint fault that occurred on the data line of the data driving module, the in-plane isolation module determines the data display signal sent by the data driving module, and outputs a data display signal with unchanged signal gain to the compensation trace of the in-plane compensation module.

[0116] In this embodiment, when a breakpoint fault is determined to occur in the data line of the data driving module, the in-plane isolation module provided in this application not only avoids the deload effect of the subsequent compensation routing circuit on the original COF output stage, ensuring the normal display of each pixel unit connected to the normal data line, but also ensures that the data display signal sent by the data driving module will not be interfered with by the breakpoint fault during transmission, and can stably output a data display signal with constant signal gain to the compensation routing, thereby ensuring the integrity of the data display signal in the transmission process from the data driving module to the compensation routing.

[0117] Step S20: After determining that the in-plane compensation module has access to the data display signal flowing through the compensation trace, high-frequency gain compensation is performed based on the data display signal, and the compensated data display signal is input to the repair line, so that the display brightness of each pixel unit electrically connected to the repair line is the same as the display brightness of each pixel unit electrically connected to the normal data line; wherein, the repair line is the data line where the data line break point corresponding to the break point fault is not connected to the data driving module, and the normal data line is the data line where the data line break point is electrically connected to the data driving module.

[0118] In this embodiment, the RC load increases due to the longer signal transmission path of the data display signal from the compensation trace to the repair line. This application effectively compensates the high-frequency gain of the data display signal transmitted via the in-plane isolation module by setting an in-plane compensation module, effectively suppressing the attenuation of high-frequency components in the data display signal and ensuring that the compensated data display signal can fully meet the charging requirements of each pixel unit on the repair line. Finally, the compensated data display signal is input to the repair line, so that the pixel units connected to the repaired data line (i.e., the repair line) have the same display brightness as the pixel units connected to the normal data line, ensuring the uniformity of the entire display panel screen display and thus significantly improving the display quality after the display panel is repaired.

[0119] Furthermore, in some other feasible embodiments, the method for repairing the display circuit includes the following steps B10 to B20.

[0120] Step B10: When the display panel is in high-frequency refresh mode, a cascaded component is constructed based on each of the in-plane compensation modules and the third capacitor set between each of the in-plane compensation modules and the adjacent in-plane compensation modules.

[0121] In this embodiment, when the display panel is in high-frequency refresh mode, a cascaded assembly is constructed by utilizing the in-plane compensation module of each stage and the third capacitor set between it and the adjacent module. That is, the third capacitor in the cascaded assembly reduces the parasitic capacitance at the output of the previous stage in-plane compensation module (which is also the input capacitance of the second stage in-plane compensation module), thereby increasing the parasitic pole frequency of the first-stage compensation stage. This compensates for the bandwidth reduction caused by module cascading to meet the repair requirements of the high refresh rate panel.

[0122] Step B20: Based on the response of the high-frequency refresh mode, determine the ideal bandwidth corresponding to the high-frequency refresh mode, and perform bandwidth compensation on the data display signal flowing through the compensation line through the cascaded component until the actual bandwidth of the data display signal is the same as the ideal bandwidth, and then output the data display signal to the repair line.

[0123] In this embodiment, by using cascaded components to respond to the high-frequency refresh mode, the ideal bandwidth corresponding to the high-frequency refresh mode can be accurately obtained. The bandwidth of the data display signal flowing through the compensation line is compensated by the cascaded components until the actual bandwidth of the data display signal is the same as the ideal bandwidth. Then, the data display signal is output to the repair line, thereby significantly improving the response speed and display effect of the display panel in the high-frequency refresh mode.

[0124] In summary, this application provides a display circuit and its repair method, a display panel, and a display device. By integrating an in-plane isolation module and an in-plane compensation module into the display circuit, the data lines of the interrupted data driving module are repaired, significantly improving the display quality of the display panel after the interruption is repaired. Specifically, the data lines of the data driving module are routed with the compensation traces of the in-plane compensation module, and an in-plane isolation module is provided between the data lines and the in-plane compensation module. When a breakpoint fault is detected in the data line of the data driver module, the in-plane isolation module provided in this application ensures that the data display signal sent by the data driver module is not interfered with. This allows the output of a data display signal with constant gain to the compensation trace, thus ensuring the integrity of the data display signal during its transmission from the data driver module to the compensation trace. Next, because the signal transmission path of the data display signal to the repair line becomes longer via the compensation trace, leading to an increased RC load, this application provides effective high-frequency gain compensation for the data display signal transmitted via the in-plane isolation module using an in-plane compensation module. This effectively suppresses the attenuation of high-frequency components in the data display signal, ensuring that the compensated data display signal can fully meet the charging requirements of each pixel unit on the repair line. Finally, the compensated data display signal is input to the repair line, ensuring that the pixel units connected to the repaired data line (i.e., the repair line) maintain the same display brightness as those connected to the normal data line, guaranteeing the uniformity of the entire display panel image and significantly improving the display quality after the broken line is repaired.

[0125] In addition, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the display circuit of any of the above.

[0126] In addition, this application also provides a display device. Please refer to... Figure 13 , Figure 13 This is a schematic diagram of the display device involved in the embodiments of this application. Specifically, the display device in the embodiments of this application may be a device for a repair method that locally runs the display circuit.

[0127] like Figure 13As shown, the display device in this embodiment may include: the display panel described above; or, a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0128] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk storage device. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0129] Those skilled in the art will understand that Figure 13 The display device structure shown does not constitute a limitation on the display device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0130] like Figure 13 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a repair program for the display circuit of a display device.

[0131] exist Figure 13 In the display device shown, the processor 1001 can be used to call the repair program of the display circuit of the display device stored in the memory 1005, and execute the steps of the display screen control method as described above.

[0132] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0133] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0134] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0135] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display circuit, characterized in that, The display circuit includes a data driving module, as well as an in-plane isolation module and an in-plane compensation module disposed in the non-display area of ​​the display panel; The data line of the data driving module is electrically connected to the compensation trace of the in-plane compensation module, and the in-plane isolation module is provided between the data line and the in-plane compensation module. The in-plane isolation module is used to determine the data display signal sent by the data driving module based on the breakpoint fault that occurred in the data line, and to output a data display signal with unchanged signal gain to the compensation trace; The in-plane compensation module is used to perform high-frequency gain compensation based on the data display signal after it flows through the compensation trace, and input the compensated data display signal to the repair line, so that the display brightness of each pixel unit electrically connected to the repair line is the same as the display brightness of each pixel unit electrically connected to the normal data line; wherein... The repair line is the data line where the breakpoint fault corresponds to the data line that is not connected to the data driver module, and the normal data line is the data line where the data line breakpoint is electrically connected to the data driver module. The in-plane isolation module includes a first thin-film transistor, a first resistor, and a bias voltage terminal; the gate terminal of the first thin-film transistor is electrically connected to the data line, the first path terminal of the first thin-film transistor is electrically connected to the bias voltage terminal, the second path terminal of the first thin-film transistor is electrically connected to the first terminal of the first resistor, and the second terminal of the first resistor is grounded; the compensation trace is electrically connected between the second path terminal of the first thin-film transistor and the first terminal of the first resistor. The in-plane isolation module is configured to set the transconductance of the first thin-film transistor and the resistance value of the first resistor, until... When the signal is within the threshold range corresponding to a preset proportional threshold, a data display signal with constant output gain is sent to the compensation trace. The transconductance of the first thin-film transistor, the The resistance value of the first resistor; The in-plane compensation module includes a first capacitive resistor unit, a second capacitive resistor unit, and a second thin-film transistor. The gate of the second thin-film transistor forms the input terminal of the in-plane compensation module and is electrically connected to the compensation trace. The first end of the first capacitive resistor unit forms the connection terminal of the in-plane compensation module and is electrically connected to the first path terminal of the second thin-film transistor. The second end of the first capacitive resistor unit is electrically connected to the power supply terminal. The output terminal of the first capacitive resistor unit forms the output terminal of the in-plane compensation module and is electrically connected to the side of the data drive module where the data line is not connected. The second path terminal of the second thin-film transistor is electrically connected to the input terminal of the second capacitive resistor unit, and the output terminal of the second capacitive resistor unit is grounded. The transfer function of the in-plane compensation module is: in, This represents the transfer function of the in-plane compensation module. Indicates the parasitic resistance value; Indicates the parasitic tolerance value; To represent the source resistance value; To represent the source capacitance value; This represents the transconductance of the second thin-film transistor; , The signal frequency of the data is displayed with constant signal gain. ; The in-plane compensation module is configured to pass through the transfer function at the zero point of the signal frequency. The dominant pole of the signal frequency The gain compensation factor generated between them is used to perform high-frequency gain compensation on the data display signal flowing through the compensation trace, and the zero point The principal pole The gain compensation factor refers to the zero point. The ratio between the DC gain and the high-frequency gain of the dominant pole.

2. The display circuit as described in claim 1, characterized in that, The first capacitive-resistive unit includes a second resistor and a first capacitor; The first end of the second resistor forms the first end of the first capacitive-resistive unit, and is electrically connected to the first pass terminal of the second thin-film transistor and the first end of the first capacitor, respectively. The connection point where the first end of the second resistor is electrically connected to the first end of the first capacitor forms the output terminal of the first capacitive-resistive unit, and is electrically connected to the side of the data drive module where the break point of the data line is not connected. The second end of the second resistor forms the second end of the first capacitive-resistive unit, and is electrically connected to the power supply terminal and the second end of the first capacitor, respectively.

3. The display circuit as described in claim 1, characterized in that, The second capacitive-resistive unit includes a third resistor and a second capacitor connected in parallel; The first end of the third resistor connected in parallel with the second capacitor constitutes the input terminal of the second capacitive-resistive unit, and is electrically connected to the second path terminal of the second thin-film transistor. The second end of the third resistor connected in parallel with the second capacitor forms the output terminal of the second capacitive-resistive unit, which is then grounded.

4. The display circuit as described in claim 1, characterized in that, The display circuit includes a cascaded component when the display panel is in high-frequency refresh mode, and the cascaded component is provided with a plurality of the in-plane compensation modules; The output terminal of the in-plane compensation module is electrically connected to the input terminal of the adjacent in-plane compensation module, and a third capacitor is provided between the output terminal of the in-plane compensation module and the adjacent in-plane compensation module. The first end of the third capacitor is electrically connected between the output end of the in-plane compensation module and the adjacent in-plane compensation module, and the second end of the third capacitor is electrically connected to the connection end of the adjacent in-plane compensation module.

5. A method for repairing a display circuit, characterized in that, The method for repairing a display circuit is applied to the display circuit as described in any one of claims 1 to 4, wherein the method for repairing the display circuit includes: Based on the breakpoint fault that occurred on the data line of the data driver module, the in-plane isolation module determines the data display signal sent by the data driver module, and outputs a data display signal with unchanged signal gain to the compensation trace of the in-plane compensation module. After determining that the in-plane compensation module has access to the data display signal flowing through the compensation trace, high-frequency gain compensation is performed based on the data display signal, and the compensated data display signal is input to the repair line, enabling the display brightness of each pixel unit electrically connected to the repair line to be the same as the display brightness of each pixel unit electrically connected to the normal data line; wherein... The repair line is the data line where the breakpoint fault corresponds to the data line that is not connected to the data driver module, and the normal data line is the data line where the data line breakpoint is electrically connected to the data driver module. The in-plane isolation module includes a first thin-film transistor, a first resistor, and a bias voltage terminal; the gate terminal of the first thin-film transistor is electrically connected to the data line, the first path terminal of the first thin-film transistor is electrically connected to the bias voltage terminal, the second path terminal of the first thin-film transistor is electrically connected to the first terminal of the first resistor, and the second terminal of the first resistor is grounded; the compensation trace is electrically connected between the second path terminal of the first thin-film transistor and the first terminal of the first resistor. The in-plane isolation module is configured to set the transconductance of the first thin-film transistor and the resistance value of the first resistor, until... When the signal is within the threshold range corresponding to a preset proportional threshold, a data display signal with constant output gain is sent to the compensation trace. The transconductance of the first thin-film transistor, the The resistance value of the first resistor; The in-plane compensation module includes a first capacitive resistor unit, a second capacitive resistor unit, and a second thin-film transistor. The gate of the second thin-film transistor forms the input terminal of the in-plane compensation module and is electrically connected to the compensation trace. The first end of the first capacitive resistor unit forms the connection terminal of the in-plane compensation module and is electrically connected to the first path terminal of the second thin-film transistor. The second end of the first capacitive resistor unit is electrically connected to the power supply terminal. The output terminal of the first capacitive resistor unit forms the output terminal of the in-plane compensation module and is electrically connected to the side of the data drive module where the data line is not connected. The second path terminal of the second thin-film transistor is electrically connected to the input terminal of the second capacitive resistor unit, and the output terminal of the second capacitive resistor unit is grounded. The transfer function of the in-plane compensation module is: in, This represents the transfer function of the in-plane compensation module. Indicates the parasitic resistance value; Indicates the parasitic tolerance value; To represent the source resistance value; To represent the source capacitance; gm1 is the transconductance of the second thin-film transistor; , The signal frequency of the data is displayed with constant signal gain. ; The in-plane compensation module is configured to pass through the transfer function at the zero point of the signal frequency. The dominant pole of the signal frequency The gain compensation factor generated between them is used to perform high-frequency gain compensation on the data display signal flowing through the compensation trace, and the zero point The principal pole The gain compensation factor refers to the zero point. The ratio between the DC gain and the high-frequency gain of the dominant pole.

6. The method for repairing the display circuit as described in claim 5, characterized in that, The repair method for the display circuit includes: When the display panel is in high-frequency refresh mode, a cascaded component is constructed based on each of the in-plane compensation modules and the third capacitor set between each of the in-plane compensation modules and the adjacent in-plane compensation modules. Based on the response of the high-frequency refresh mode, the ideal bandwidth corresponding to the high-frequency refresh mode is determined, and the bandwidth of the data display signal flowing through the compensation line is compensated by the cascaded component until the actual bandwidth of the data display signal is the same as the ideal bandwidth, and then the data display signal is output to the repair line.

7. A display panel, characterized in that, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes the display circuit according to any one of claims 1 to 4.

8. A display device, characterized in that, The display device includes at least: The display panel as described in claim 7; or, A processor, a memory, and a repair program for a display circuit stored in the memory that can be executed by the processor, wherein when the repair program for the display circuit is executed by the processor, it implements the steps of the repair method for the display circuit as described in any one of claims 5 to 6.

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