Shifting register unit, driving method, gate driving circuit and display panel

Abstract

The embodiment of the invention provides a shifting register unit, a driving method, a gate driving circuit and a display panel, and the shifting register unit comprises a first shifting register circuit which is configured to respond to a signal of a first input signal end and output a cascade signal through a cascade output end; the second shift register circuit is configured to respond to a signal of a second input signal end and output a gate driving signal through a driving output end; and the switching circuit is connected between the cascade output end and the second input signal end, and the switching circuit is configured to respond to a signal of the gating control signal end and conduct the cascade output end and the second input signal end.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a driving method, a gate driving circuit, and a display panel. Background Art

[0002] Usually, the display panel is refreshed in a full-screen refresh mode. When a local display area of ​​the display panel needs to be refreshed, a black screen is used to cover the display area that does not need to be refreshed. However, the display panel still updates the image of the entire screen in a full-screen refresh mode. This refresh mode will cause unnecessary power consumption. Summary of the invention

[0003] The present disclosure provides a shift register unit, comprising:

[0004] A first shift register circuit is configured to output a cascade signal through a cascade output terminal in response to a signal at a first input signal terminal;

[0005] a second shift register circuit configured to output a gate drive signal through a drive output terminal in response to a signal at a second input signal terminal;

[0006] The switch circuit is connected between the cascade output terminal and the second input signal terminal, and is configured to connect the cascade output terminal and the second input signal terminal in response to a signal of a selection control signal terminal.

[0007] In some possible implementations, the switching circuit includes at least one first transistor, a first electrode of the first transistor is coupled to the cascade output terminal, a second electrode of the first transistor is coupled to the second input signal terminal, and a control electrode of the first transistor is coupled to the selection control signal terminal.

[0008] In some possible implementations, the first shift register circuit is further connected to a first clock signal terminal and a first reset signal terminal, and is configured to provide a signal from the first input signal terminal to a first node in response to a signal from the first input signal terminal, provide a signal from the first clock signal terminal to the cascade output terminal in response to a signal from the first node, and provide a signal from the first reference signal terminal to the first node and the cascade output terminal in response to a signal from the first reset signal terminal;

[0009] The second shift register circuit is also connected to a second clock signal terminal and a second reset signal terminal, and is configured to provide the signal of the second input signal terminal to a second node in response to a signal of the second input signal terminal, provide the signal of the second clock signal terminal to the driving output terminal in response to a signal of the second node, and provide the signal of the second reference signal terminal to the second node and the driving output terminal in response to a signal of the second reset signal terminal.

[0010] In some possible implementations, the first clock signal terminal and the second clock signal terminal are different signal terminals.

[0011] In some possible implementations, the first reference signal terminal and the second reference signal terminal are the same signal terminal.

[0012] In some possible implementations, the first shift register circuit and the second shift register circuit have the same structure.

[0013] The disclosed embodiment also provides a gate driving circuit, comprising a plurality of the above-mentioned shift register units connected in cascade;

[0014] The first input signal terminal of the first shift register circuit in the first-stage shift register unit is connected to the frame trigger signal terminal;

[0015] The cascade output end of the first shift register circuit in the nth-stage shift register unit is connected to the first input signal end of the first shift register circuit in the n+mth-stage shift register unit, and the first reset signal end of the first shift register circuit in the nth-stage shift register unit is connected to the cascade output end of the first shift register circuit in the n+ith-stage shift register unit; wherein m, n, and i are all positive integers.

[0016] In some possible implementations, the gating control signal terminals connected to the switch circuits in each level of the shift register units are the same signal terminal.

[0017] In some possible implementations, the second reset signal terminal of the second shift register circuit in the nth stage shift register unit is connected to the cascade output terminal of the first shift register circuit in the n+kth stage shift register unit; wherein k is a positive integer.

[0018] The embodiment of the present disclosure further provides a driving method of the above-mentioned shift register unit, comprising:

[0019] The first shift register circuit outputs a cascade signal through a cascade output terminal in response to a signal at a first input signal terminal;

[0020] The switch circuit connects the cascade output terminal and the second input signal terminal in response to the signal at the gate control signal terminal, and the second shift register circuit outputs a gate drive signal through the drive output terminal in response to the signal at the second input signal terminal;

[0021] Alternatively, the switch circuit disconnects the cascade output terminal from the second input signal terminal in response to a signal at the selection control signal terminal.

[0022] The embodiment of the present disclosure further provides a driving method of the above-mentioned gate driving circuit, comprising:

[0023] In one frame time, the first shift register circuit in each level of shift register units responds to the signal at the first input signal terminal and outputs a cascade signal through the cascade output terminal;

[0024] The switching circuit in at least one shift register unit responds to the signal at the selection control signal terminal to connect the cascade output terminal in the at least one shift register unit and the second input signal terminal in the at least one shift register unit, and the second shift register circuit in the at least one shift register unit responds to the signal at the second input signal terminal to output a gate drive signal through the driving output terminal.

[0025] The embodiment of the present disclosure also provides a display panel, comprising a plurality of gate lines and the above-mentioned gate driving circuit;

[0026] The driving output end of the x-th stage shift register unit in the gate driving circuit is connected to the y-th gate line among the plurality of gate lines, and x and y are both positive integers.

[0027] The embodiment of the present disclosure also provides a display device, including the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Some structural schematic diagrams of shift register units provided in the embodiments of the present disclosure;

[0029] Figure 2 Some further structural schematic diagrams of shift register units provided in the embodiments of the present disclosure;

[0030] Figure 3 A schematic diagram of the steps of a driving method of a shift register unit provided in an embodiment of the present disclosure;

[0031] Figure 4 Some signal timing diagrams of the shift register unit provided in the embodiment of the present disclosure;

[0032] Figure 5 Some structural schematic diagrams of gate drive circuits provided in embodiments of the present disclosure;

[0033] Figure 6 Some further structural schematic diagrams of gate drive circuits provided in the embodiments of the present disclosure;

[0034] Figure 7-10 Some signal timing diagrams of the gate drive circuit provided in the embodiments of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0036] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0037] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0038] Typically, the gate drive circuit may include a plurality of cascaded shift register units, the input signal end of the first-stage shift register unit is connected to the frame trigger signal end STV, and the input signal end of the current-stage shift register unit is connected to the signal output end of the previous-stage shift register unit. That is, the first-stage shift register unit can be controlled by the frame trigger signal stv, and starting from the second-stage shift register unit, the input signal end is controlled by the signal of the signal output end of the previous-stage shift register unit, thereby outputting signals step by step and driving the pixels in the display panel row by row. This results in that the gate drive circuit can only control the shift register units at each stage to output the gate drive signal step by step when working, and cannot control only some of the shift register units to output the gate drive signal, resulting in that the display panel can only refresh the entire screen, and cannot refresh partially, causing unnecessary power consumption.

[0039] In order to solve the above problems, an embodiment of the present disclosure provides a shift register unit, which can control the on-off of the cascade output terminal of the first shift register circuit and the second input signal terminal of the second shift register circuit based on a switching circuit, and then control the second shift register circuit to output or not output a gate drive signal, so that the corresponding pixels can be selectively driven to achieve partial refresh of the display panel screen and save power consumption.

[0040] In the embodiments of the present disclosure, Figure 1 As shown, the shift register unit may include: a first shift register circuit 10 , a second shift register circuit 20 and a switch circuit 30 .

[0041] The first shift register circuit 10 is configured to output a cascade signal through a cascade output terminal O(n) in response to a signal at a first input signal terminal INPUT1;

[0042] The second shift register circuit 20 is configured to output a gate driving signal through the driving output terminal G(n) in response to the signal of the second input signal terminal INPUT2;

[0043] The switch circuit 30 is connected between the cascade output terminal O(n) and the second input signal terminal INPUT2. The switch circuit 30 is configured to connect the cascade output terminal O(n) and the second input signal terminal INPUT2 in response to the signal of the enable control signal terminal EN.

[0044] The above-mentioned shift register unit provided in the embodiment of the present disclosure, through a switching circuit, turns on or off the cascade output terminal and the second input signal terminal, so that the signal of the cascade output terminal can be selectively provided to the second input signal terminal to control the second shift register circuit to output or not output the gate drive signal, and then can selectively drive the corresponding pixels to achieve partial refresh of the display panel screen and save power consumption.

[0045] In some embodiments of the present disclosure, Figure 2 As shown, the switch circuit 30 includes at least one first transistor T, a first electrode of the first transistor T is coupled to the cascade output terminal O(n), a second electrode of the first transistor T is coupled to the second input signal terminal INPUT2, and a control electrode of the first transistor T is coupled to the enable control signal terminal EN.

[0046] Exemplarily, the first transistor T is turned on under the control of the effective level of the signal at the gate control signal terminal, and is turned off under the control of the ineffective level of the signal at the gate control signal terminal. Figure 2 As shown, the first transistor T can be an N-type transistor, then the effective level of the signal at the gate control signal end is a high level, and the invalid level is a low level. Of course, the first transistor T can also be a P-type transistor, then the effective level of the signal at the gate control signal end is a low level, and the invalid level is a high level. In practical applications, the specific implementation of the first transistor T can be determined according to the needs of the practical application, and is not limited here.

[0047] In some embodiments of the present disclosure, Figure 1 As shown, the first shift register circuit 10 can also be connected to the first clock signal terminal CK1 and the first reset signal terminal RESET1, and is configured to provide the signal of the first input signal terminal INPUT1 to the first node in response to the signal of the first input signal terminal INPUT1, provide the signal of the first clock signal terminal CK1 to the cascade output terminal O(n) in response to the signal of the first node, and provide the signal of the first reference signal terminal VSS1 to the first node and the cascade output terminal O(n) in response to the signal of the first reset signal terminal RESET1.

[0048] The second shift register circuit 20 can also be connected to the second clock signal terminal CK2 and the second reset signal terminal RESET2, and is configured to provide the signal of the second input signal terminal INPUT2 to the second node in response to the signal of the second input signal terminal INPUT2, provide the signal of the second clock signal terminal CK2 to the driving output terminal G(n) in response to the signal of the second node, and provide the signal of the second reference signal terminal VSS2 to the second node and the driving output terminal G(n) in response to the signal of the second reset signal terminal RESET2.

[0049] In some embodiments of the present disclosure, the first clock signal terminal CK1 and the second clock signal terminal CK2 are different signal terminals and provide different clock signals. Exemplarily, the phase of the signal at the first clock signal terminal CK1 is opposite to that of the signal at the second clock signal terminal CK2.

[0050] In some embodiments of the present disclosure, the first reference signal terminal VSS1 and the second reference signal terminal VSS2 may be the same signal terminal. Of course, the first reference signal terminal VSS1 and the second reference signal terminal VSS2 may also be different signal terminals.

[0051] Exemplarily, the signal at the first reference signal terminal VSS1 and the signal at the second reference signal terminal VSS2 are both low level signals.

[0052] In some embodiments of the present disclosure, Figure 2 As shown, the first shift register circuit 10 and the second shift register circuit 20 have the same structure.

[0053] Exemplarily, the first shift register circuit and the second shift register circuit may both be 4T1C circuits, 4T2C circuits, 8T1C circuits, 12T3C circuits, etc., which are not limited herein.

[0054] For example, Figure 2 As shown, the first shift register circuit and the second shift register circuit may include transistors T1-T4 and capacitor C1, and the types of transistors T1-T4 may be N-type transistors or P-type transistors. In the first shift register circuit, the gate and the first electrode of transistor T1 are coupled to the first input signal terminal INPUT1, and the second electrode is coupled to the first node Q1; the gate of transistor T2 is coupled to the first node Q1, the first electrode is coupled to the first clock signal terminal CK1, and the second electrode is coupled to the cascade output terminal O(n); the gate of transistor T3 is coupled to the first reset signal terminal RESET1, the first electrode is coupled to the first reference signal terminal VSS1, and the second electrode is coupled to the first node Q1; the gate of transistor T4 is coupled to the first reset signal terminal RESET1, the first electrode is coupled to the first reference signal terminal VSS1, and the second electrode is coupled to the cascade output terminal O(n); the first electrode of capacitor C1 is coupled to the first node Q1, and the second electrode is coupled to the cascade output terminal O(n).

[0055] In the second shift register circuit, the gate and the first electrode of the transistor T1 are coupled to the second input signal terminal INPUT2, and the second electrode is coupled to the second node Q2; the gate of the transistor T2 is coupled to the second node Q2, the first electrode is coupled to the second clock signal terminal CK2, and the second electrode is coupled to the drive output terminal G(n); the gate of the transistor T3 is coupled to the second reset signal terminal RESET2, the first electrode is coupled to the second reference signal terminal VSS2, and the second electrode is coupled to the second node Q2; the gate of the transistor T4 is coupled to the second reset signal terminal RESET2, the first electrode is coupled to the second reference signal terminal VSS2, and the second electrode is coupled to the drive output terminal G(n); the first electrode of the capacitor C1 is coupled to the second node Q2, and the second electrode is coupled to the drive output terminal G(n).

[0056] For example, according to the type of transistor and the signal of its gate, the first electrode of the transistor can be used as its source and the second electrode can be used as its drain; or, conversely, the first electrode of the transistor can be used as its drain and the second electrode can be used as its source. This can be designed and determined according to the actual application environment, and no specific distinction is made here.

[0057] The disclosed embodiment also provides a driving method of the shift register unit, such as Figure 3 As shown, the following steps may be included:

[0058] S101, the first shift register circuit outputs a cascade signal through a cascade output terminal in response to a signal at a first input signal terminal;

[0059] S102, the switch circuit responds to the signal at the enable control signal terminal to connect the cascade output terminal and the second input signal terminal, and the second shift register circuit responds to the signal at the second input signal terminal to output the gate drive signal through the driving output terminal; or, the switch circuit responds to the signal at the enable control signal terminal to disconnect the cascade output terminal from the second input signal terminal.

[0060] The driving method of the shift register unit provided in the embodiment of the present disclosure loads high and low level signals to the selection control signal terminal to connect or disconnect the cascade output terminal and the second input signal terminal, so that the signal of the cascade output terminal can be selectively provided to the second input signal terminal to control the second shift register circuit to output or not output the gate drive signal, and then the corresponding pixels can be selectively driven to achieve partial refresh of the display panel screen and save power consumption.

[0061] Below Figure 2 Take the shift register unit shown in the figure as an example, combined with Figure 4 The signal timing diagram shown describes the working process of the above-mentioned shift register unit provided by the embodiment of the present disclosure.

[0062] Specifically, select Figure 4 The first, second and third phases of the signal timing diagram shown. It should be noted that Figure 4 The signal timing diagram shown is only the working process of a certain shift register unit in one frame time. The working process of the shift register unit in other frames is basically the same as the working process in this frame, and will not be repeated here.

[0063] In the first stage T1, the signal input1 at the first input signal terminal is at a high level, the signal ck1 at the first clock signal terminal is at a low level, the signal reset1 at the first reset signal terminal is at a low level, the signal en at the selection control signal terminal is at a high level, the signal ck2 at the second clock signal terminal is at a low level, and the signal reset2 at the second reset signal terminal is at a low level;

[0064] The first shift register circuit responds to the signal input1 at the first input signal terminal, provides the high-level signal input1 at the first input signal terminal to the first node Q1, and responds to the signal at the first node Q1, provides the low-level signal ck1 at the first clock signal terminal to the cascade output terminal O(n), and the cascade output terminal O(n) outputs the low-level cascade signal output.

[0065] In response to the signal en at the selection control signal terminal, the switch circuit conducts the cascade output terminal O(n) and the second input signal terminal INPUT2, and provides the low-level cascade signal output to the second input signal terminal INPUT2.

[0066] In the second stage T2, the signal input1 at the first input signal terminal is at a low level, the signal ck1 at the first clock signal terminal is at a high level, the signal reset1 at the first reset signal terminal is at a low level, the signal en at the selection control signal terminal is at a high level, the signal ck2 at the second clock signal terminal is at a low level, and the signal reset2 at the second reset signal terminal is at a low level;

[0067] In the first shift register circuit, due to the bootstrap effect of the capacitor C1, the first node Q1 is kept at a high level. In response to the signal of the first node Q1, the first shift register circuit provides the high-level signal ck1 of the first clock signal terminal to the cascade output terminal O(n), and the cascade output terminal O(n) outputs a high-level cascade signal output.

[0068] In response to the signal en at the selection control signal terminal, the switch circuit conducts the cascade output terminal O(n) and the second input signal terminal INPUT2, and provides the high-level cascade signal output to the second input signal terminal INPUT2.

[0069] The second shift register circuit responds to the signal of the second input signal terminal INPUT2 by providing a high-level signal of the second input signal terminal INPUT2 to the second node Q2, and responds to the signal of the second node Q2 by providing a low-level signal ck2 of the second clock signal terminal to the driving output terminal G(n), and the driving output terminal G(n) outputs a low-level gate driving signal gate.

[0070] In the third stage T3, the signal input1 at the first input signal terminal is at a low level, the signal ck1 at the first clock signal terminal is at a low level, the signal reset1 at the first reset signal terminal is at a high level, the signal en at the selection control signal terminal is at a high level, the signal ck2 at the second clock signal terminal is at a high level, and the signal reset2 at the second reset signal terminal is at a low level;

[0071] The first shift register circuit provides a low level signal of the reference signal terminal VSS to the first node Q1 and the cascade output terminal O(n) in response to the signal reset1 at the first reset signal terminal, and the cascade output terminal O(n) outputs a low level cascade signal output.

[0072] In response to the signal of the selection control signal terminal, the switch circuit conducts the cascade output terminal O(n) and the second input signal terminal INPUT2, and provides the low-level cascade signal output to the second input signal terminal INPUT2.

[0073] In the second shift register circuit, due to the bootstrap effect of capacitor C1, the second node Q2 is kept at a high level. The second shift register circuit responds to the signal of the second node Q2 and provides the high-level signal ck2 of the second clock signal terminal to the driving output terminal G(n). The driving output terminal G(n) outputs a high-level gate driving signal gate.

[0074] In the above second stage T2, if the signal en at the selection control signal end is low level, when the cascade output end outputs the high level cascade signal output, the switch circuit responds to the signal at the selection control signal end, disconnects the cascade output end O(n) from the second input signal end INPUT2, and the high level cascade signal output cannot be provided to the second input signal end INPUT2, and controls the transistor T1 in the second shift register circuit to be cut off, so that the second node Q2 cannot be charged. Then, in the third stage T3, even if the signal at the selection control signal end is high level, since the output of the cascade output end O(n) in this working stage is The low-level cascade signal output is provided to the second input signal terminal INPUT2 as a low-level signal, which controls the transistor T1 in the second shift register circuit to be cut off. The second node Q2 is not at a high level, and the control transistor T2 is cut off, so that the signal ck2 at the second clock signal terminal cannot be provided to the driving output terminal G(n); at the same time, the signal reset1 at the second reset signal terminal RESET2 in the second shift register circuit is at a low level, and the control transistor T4 is cut off, so that the signal of the second reference signal terminal VSS2 cannot be provided to the driving output terminal G(n), resulting in no gate driving signal output at the driving output terminal G(n).

[0075] The disclosed embodiment also provides a gate drive circuit, such as Figure 5 As shown, the gate drive circuit may include a plurality of cascaded Figure 1The shift register unit shown in FIG. ck represents the signal at the first clock signal end, xck represents the signal at the second clock signal end, vss1 represents the signal at the first reference signal end, vss2 represents the signal at the second reference signal end, and en represents the signal at the selection control signal end; Q(n) represents the cascade output end of the n-th stage shift register unit S(n), and G(n) represents the driving output end of the n-th stage shift register unit S(n).

[0076] The first input signal terminal INPUT1 of the first shift register circuit in the first stage shift register unit is connected to the frame trigger signal terminal STV ( Figure 5 not shown);

[0077] The cascade output terminal O(n) of the first shift register circuit in the n-th shift register unit is connected to the first input signal terminal of the first shift register circuit in the n+m-th shift register unit, and the first reset signal terminal of the first shift register circuit in the n-th shift register unit is connected to the cascade output terminal O(n+i) of the first shift register circuit in the n+i-th shift register unit; wherein m, n, and i are all positive integers.

[0078] Exemplarily, m and i can be natural numbers such as 1, 2, 3, 4, etc. Exemplarily, m and i can be the same or different. For example, m and i are both 1, and in two adjacent shift register units, the signal of the first input signal end of the next shift register unit is provided by the cascade output end of the previous shift register unit, and the signal of the first reset signal end of the previous shift register unit is provided by the cascade output end of the next shift register unit. For example, m and i are both 2, the cascade output end of the n-2 shift register unit is connected to the first input signal end of the n-1 shift register unit, and the cascade output end of the n-1 shift register unit is connected to the first input signal end of the n+1 shift register unit; the first reset signal end of the n-2 shift register unit is connected to the cascade output end of the n-1 shift register unit, and the first reset signal end of the n+1 shift register unit is connected to the cascade output end of the n+1 shift register unit; the other shift register units at all levels have the same connection logic, which will not be repeated here.

[0079] Specifically, in the above-mentioned gate driving circuit provided by the embodiment of the present disclosure, the signals of the first reference signal terminal of each level of shift register unit are all provided by the same first DC signal terminal, and the signals of the second reference signal terminal of each level of shift register unit are all provided by the same second DC signal terminal. Exemplarily, the first DC signal terminal and the second DC signal terminal can be the same DC signal terminal.

[0080] In the embodiments of the present disclosure, Figure 5As shown, the gating control signal terminals connected to the switch circuits in each level of the shift register unit are the same signal terminals.

[0081] In the disclosed embodiment, the second reset signal terminal of the second shift register circuit in the nth stage shift register unit is connected to the cascade output terminal O(n+k) of the first shift register circuit in the n+kth stage shift register unit; wherein k is a positive integer.

[0082] Exemplarily, k can be a natural number such as 2, 3, or 4. For example, k is 2, the second reset signal end of the n-1th shift register unit is connected to the cascade output end of the n+1th shift register unit; the second reset signal end of the nth shift register unit is connected to the cascade output end of the n+2th shift register unit; the second reset signal end of the n+1th shift register unit is connected to the cascade output end of the n+3th shift register unit, and the other shift register units have the same connection logic, which will not be repeated here.

[0083] In the embodiment of the present disclosure, in the above-mentioned gate drive circuit, the first clock signal end of the first shift register circuit in the odd-numbered shift register unit and the second clock signal end of the second shift register circuit in the even-numbered shift register unit are connected to the same first clock signal, and the first clock signal end of the first shift register circuit in the even-numbered shift register unit and the second clock signal end of the second shift register circuit in the odd-numbered shift register unit are connected to the same second clock signal.

[0084] For example, Figure 5 As shown, in the n-th level shift register unit, the first clock signal end of the first shift register circuit is connected to the first clock signal ck, and the second clock signal end of the second shift register circuit is connected to the second clock signal xck; in the n+1-th level shift register unit, the first clock signal end of the first shift register single circuit is connected to the second clock signal xck, and the second clock signal end of the second shift register circuit is connected to the first clock signal ck.

[0085] It should be noted that the transistors mentioned in the above embodiments of the present disclosure may be TFTs or metal oxide semiconductor field effect transistors (MOS), which are not limited here.

[0086] In order to simplify the preparation process, in the specific implementation, in the embodiment of the present disclosure, as Figure 1 As shown, all transistors can be N-type transistors. Of course, all transistors can also be P-type transistors, which is not limited here.

[0087] The above is only an example to illustrate the specific structure of the gate drive circuit provided in the embodiment of the present disclosure. In specific implementation, the specific structure of the above circuits is not limited to the above structure provided in the embodiment of the present disclosure, and can also be other structures known to those skilled in the art, which is not limited here.

[0088] The disclosed embodiments also provide a driving method for a gate driving circuit, which may include the following steps: within a frame time, the first shift register circuit in each stage of the shift register unit responds to a signal at a first input signal terminal and outputs a cascade signal through a cascade output terminal; the switching circuit in at least one shift register unit responds to a signal at a selection control signal terminal to connect the cascade output terminal in at least one shift register unit with the second input signal terminal in at least one shift register unit; the second shift register circuit in at least one shift register unit responds to a signal at a second input signal terminal and outputs a gate driving signal through a driving output terminal.

[0089] The driving method of the gate driving circuit provided by the embodiment of the present disclosure can selectively connect the cascade output terminal of some shift register units with the second input signal terminal by loading an effective level signal to some selection control signal terminals, thereby controlling the second shift register circuit of some shift register units to output a gate driving signal, and further selectively driving the corresponding pixels to achieve partial refresh of the display panel screen and save power consumption.

[0090] Below Figure 6 The gate drive circuit shown in the figure is taken as an example, combined with Figure 7-10 The signal timing diagram shown describes the working process of the above-mentioned gate driving circuit provided by the embodiment of the present disclosure.

[0091] Specifically, Figure 6 In the gate driving circuit shown, the first input signal terminal of the second-stage shift register unit S(2) is connected to the cascade output terminal O(1) of the first-stage shift register unit S(1), and the first input signal terminal of the third-stage shift register unit S(3) is connected to the cascade output terminal O(2) of the second-stage shift register unit S(2); the first reset signal terminal of the first-stage shift register unit S(1) is connected to the cascade output terminal O(2) of the second-stage shift register unit S(2), and the first reset signal terminal of the second-stage shift register unit S(2) is connected to the cascade output terminal O(3) of the third-stage shift register unit S(3); the second reset signal terminal of the first-stage shift register unit S(1) is connected to the cascade output terminal O(3) of the third-stage shift register unit S(3), and the second reset signal terminal of the second-stage shift register unit S(2) is connected to the cascade output terminal O(4) of the fourth-stage shift register unit S(4). The other shift register units at various levels have the same connection logic, which will not be described in detail here.

[0092] Specifically, select Figure 7 The first stage, the second stage, the third stage, the fourth stage, and the fifth stage in the signal timing diagram shown. It should be noted that Figure 7 The signal timing diagram shown is only the working process of the gate driving circuit in one frame time. The working process of the gate driving circuit in other frames is basically the same as the working process in this frame, and will not be repeated here.

[0093] In the first stage T1, the signal stv at the frame trigger signal end is at a high level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a low level;

[0094] In the first-stage shift register unit, the first shift register circuit responds to the signal stv at the frame trigger signal terminal to provide the high-level signal stv at the frame trigger signal terminal to the first node Q1, and responds to the signal at the first node Q1 to provide the low-level signal ck at the first clock signal terminal to the cascade output terminal O(1), and the cascade output terminal O(1) outputs the low-level cascade signal o(1); the switch circuit responds to the signal en at the selection control signal terminal to connect the cascade output terminal and the second input signal terminal, and provide the low-level cascade signal o(1) to the second input signal terminal.

[0095] In the second stage T2, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a high level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a low level;

[0096] In the first-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal ck of the first clock signal terminal to the cascade output terminal O(1). The cascade output terminal O(1) outputs a high-level cascade signal o(1). The switch circuit responds to the signal of the selection control signal terminal and provides the high-level cascade signal o(1) to the second input signal terminal. The second shift register circuit responds to the signal of the second input signal terminal and provides the high-level signal of the second input signal terminal to the second node Q2.

[0097] In the second-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(1) and provides the signal of the cascade output terminal O(1) of a high level to the first node Q1.

[0098] In the third stage T3, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a high level;

[0099] In the first-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the second shift register circuit, the second node Q2 is kept at a high level. The second shift register circuit responds to the signal at the second node Q2 and provides the high-level signal xck at the second clock signal terminal to the driving output terminal G(1). The driving output terminal G(1) outputs a high-level gate driving signal g(1).

[0100] In the second-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal xck at the second clock signal terminal to the cascade output terminal O(2). The cascade output terminal O(2) outputs a high-level cascade signal o(2). The switch circuit responds to the signal of the selection control signal terminal and provides the high-level cascade signal o(2) to the second input signal terminal. The second shift register circuit responds to the signal of the second input signal terminal and provides the high-level signal of the second input signal terminal to the second node Q2.

[0101] In the third stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(2) and provides the signal of the cascade output terminal O(2) of high level to the first node Q1.

[0102] In the first-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(2) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(1), and the cascade output terminal O(1) outputs a low-level cascade signal o(1).

[0103] In the fourth stage T4, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a high level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a low level;

[0104] In the second-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the second shift register circuit, the second node Q2 is kept at a high level. The second shift register circuit responds to the signal of the second node Q2 and provides the high-level signal ck at the first clock signal terminal to the driving output terminal G(2). The driving output terminal G(2) outputs a high-level gate driving signal g(2).

[0105] In the third-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal ck at the first clock signal terminal to the cascade output terminal O(3). The cascade output terminal O(3) outputs a high-level cascade signal o(3). The switch circuit responds to the signal of the selection control signal terminal and provides the high-level cascade signal o(3) to the second input signal terminal. The second shift register circuit responds to the signal of the second input signal terminal and provides the high-level signal of the second input signal terminal to the second node Q2.

[0106] In the fourth stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(3) and provides the signal of the cascade output terminal O(3) of high level to the first node Q1.

[0107] In the second-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(3) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(2), and the cascade output terminal O(2) outputs a low-level cascade signal o(2).

[0108] In the fifth stage T5, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a high level;

[0109] In the third-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the second shift register circuit, the second node Q2 is kept at a high level. The second shift register circuit responds to the signal at the second node Q2 and provides the high-level signal xck at the second clock signal terminal to the driving output terminal G(3). The driving output terminal G(3) outputs a high-level gate driving signal g(3).

[0110] In the 4th stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal xck at the second clock signal terminal to the cascade output terminal O(4). The cascade output terminal O(4) outputs a high-level cascade signal o(4). The switch circuit responds to the signal of the selection control signal terminal and provides the high-level cascade signal o(4) to the second input signal terminal. The second shift register circuit responds to the signal of the second input signal terminal and provides the high-level signal of the second input signal terminal to the second node Q2.

[0111] In the fifth stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(4) and provides the signal of the cascade output terminal O(4) of a high level to the first node Q1.

[0112] In the third-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(4) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(3), and the cascade output terminal O(3) outputs a low-level cascade signal o(3).

[0113] By using the driving method of the gate driving circuit, the shift register units at each level in the gate driving circuit can output gate driving signals step by step to drive all pixels, thereby achieving full-screen refresh of the display panel screen.

[0114] Specifically, select Figure 8 The first stage, the second stage, the third stage, the fourth stage, and the fifth stage in the signal timing diagram shown. It should be noted that Figure 8 The signal timing diagram shown is only the working process of the gate driving circuit in one frame time. The working process of the gate driving circuit in other frames is basically the same as the working process in this frame, and will not be repeated here.

[0115] In the first stage T1, the signal stv at the frame trigger signal end is at a high level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a low level, and the signal xck at the second clock signal end is at a low level;

[0116] In the first-stage shift register unit, the first shift register circuit responds to the signal stv at the frame trigger signal terminal to provide the high-level signal stv at the frame trigger signal terminal to the first node Q1, and responds to the signal at the first node Q1 to provide the low-level signal ck at the first clock signal terminal to the cascade output terminal O(1), and the cascade output terminal O(1) outputs a low-level cascade signal o(1); the switch circuit responds to the signal en at the selection control signal terminal to disconnect the cascade output terminal from the second input signal terminal.

[0117] In the second stage T2, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a high level, the signal en at the selection control signal end is at a low level, and the signal xck at the second clock signal end is at a low level;

[0118] In the first-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal ck of the first clock signal terminal to the cascade output terminal O(1). The cascade output terminal O(1) outputs a high-level cascade signal o(1). The switch circuit responds to the signal of the selection control signal terminal to disconnect the cascade output terminal from the second input signal terminal. The cascade signal o(1) cannot be provided to the second input signal terminal, and the second node Q2 cannot be charged.

[0119] In the second-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(1) and provides the signal of the cascade output terminal O(1) of a high level to the first node Q1.

[0120] In the third stage T3, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a low level, and the signal xck at the second clock signal end is at a high level;

[0121] In the first stage shift register unit, since the second node Q2 is not at a high level, the transistor T2 in the second shift register circuit is controlled to be turned off, thereby driving the output terminal G(1) to output no gate drive signal g(1).

[0122] In the second-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal xck at the second clock signal terminal to the cascade output terminal O(2). The cascade output terminal O(2) outputs a high-level cascade signal o(2). The switch circuit responds to the signal at the selection control signal terminal and disconnects the cascade output terminal from the second input signal terminal.

[0123] In the third stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(2) and provides the signal of the cascade output terminal O(2) of high level to the first node Q1.

[0124] In the first-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(2) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(1), and the cascade output terminal O(1) outputs a low-level cascade signal o(1).

[0125] In the fourth stage T4, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a high level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a low level;

[0126] In the second stage shift register unit, since the second node Q2 is not at a high level, the transistor T2 in the second shift register circuit is controlled to be turned off, thereby driving the output terminal G(2) to output no gate drive signal g(2).

[0127] In the third-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal ck at the first clock signal terminal to the cascade output terminal O(3). The cascade output terminal O(3) outputs a high-level cascade signal o(3). The switch circuit responds to the signal of the selection control signal terminal and provides the high-level cascade signal o(3) to the second input signal terminal. The second shift register circuit responds to the signal of the second input signal terminal and provides the high-level signal of the second input signal terminal to the second node Q2.

[0128] In the fourth stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(3) and provides the signal of the cascade output terminal O(3) of high level to the first node Q1.

[0129] In the second-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(3) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(2), and the cascade output terminal O(2) outputs a low-level cascade signal o(2).

[0130] In the fifth stage T5, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a high level;

[0131] In the third-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the second shift register circuit, the second node Q2 is kept at a high level. The second shift register circuit responds to the signal at the second node Q2 and provides the high-level signal xck at the second clock signal terminal to the driving output terminal G(3). The driving output terminal G(3) outputs a high-level gate driving signal g(3).

[0132] In the 4th stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal xck at the second clock signal terminal to the cascade output terminal O(4). The cascade output terminal O(4) outputs a high-level cascade signal o(4). The switch circuit responds to the signal of the selection control signal terminal and provides the high-level cascade signal o(4) to the second input signal terminal. The second shift register circuit responds to the signal of the second input signal terminal and provides the high-level signal of the second input signal terminal to the second node Q2.

[0133] In the fifth stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(4) and provides the signal of the cascade output terminal O(4) of a high level to the first node Q1.

[0134] In the third-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(4) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(3), and the cascade output terminal O(3) outputs a low-level cascade signal o(3).

[0135] Through the driving method of the gate driving circuit, the gate driving circuit outputs the gate driving signal step by step starting from the third-stage shift register unit to drive the corresponding pixels, thereby realizing partial refresh of the display panel screen and saving power consumption.

[0136] Specifically, select Fig. 9 The first stage, the second stage, the third stage, the fourth stage, the fifth stage, and the sixth stage in the signal timing diagram shown. It should be noted that Fig. 9 The signal timing diagram shown is only the working process of the gate driving circuit in one frame time. The working process of the gate driving circuit in other frames is basically the same as the working process in this frame, and will not be repeated here.

[0137] In the first stage T1, the signal stv at the frame trigger signal end is at a high level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a low level;

[0138] In the first-stage shift register unit, the first shift register circuit responds to the signal stv at the frame trigger signal terminal to provide the high-level signal stv at the frame trigger signal terminal to the first node Q1, and responds to the signal at the first node Q1 to provide the low-level signal ck at the first clock signal terminal to the cascade output terminal O(1), and the cascade output terminal O(1) outputs the low-level cascade signal o(1); the switch circuit responds to the signal en at the selection control signal terminal to connect the cascade output terminal and the second input signal terminal, and provide the low-level cascade signal o(1) to the second input signal terminal.

[0139] In the second stage T2, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a high level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a low level;

[0140] In the first-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal ck of the first clock signal terminal to the cascade output terminal O(1). The cascade output terminal O(1) outputs a high-level cascade signal o(1). The switch circuit responds to the signal of the selection control signal terminal and provides the high-level cascade signal o(1) to the second input signal terminal. The second shift register circuit responds to the signal of the second input signal terminal and provides the high-level signal of the second input signal terminal to the second node Q2.

[0141] In the second-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(1) and provides the signal of the cascade output terminal O(1) of a high level to the first node Q1.

[0142] In the third stage T3, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a high level;

[0143] In the first-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the second shift register circuit, the second node Q2 is kept at a high level. The second shift register circuit responds to the signal at the second node Q2 and provides the high-level signal xck at the second clock signal terminal to the driving output terminal G(1). The driving output terminal G(1) outputs a high-level gate driving signal g(1).

[0144] In the second-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal xck at the second clock signal terminal to the cascade output terminal O(2). The cascade output terminal O(2) outputs a high-level cascade signal o(2). The switch circuit responds to the signal of the selection control signal terminal and provides the high-level cascade signal o(2) to the second input signal terminal. The second shift register circuit responds to the signal of the second input signal terminal and provides the high-level signal of the second input signal terminal to the second node Q2.

[0145] In the third stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(2) and provides the signal of the cascade output terminal O(2) of high level to the first node Q1.

[0146] In the first-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(2) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(1), and the cascade output terminal O(1) outputs a low-level cascade signal o(1).

[0147] In the fourth stage T4, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a high level, the signal en at the selection control signal end is at a low level, and the signal xck at the second clock signal end is at a low level;

[0148] In the second-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the second shift register circuit, the second node Q2 is kept at a high level. The second shift register circuit responds to the signal of the second node Q2 and provides the high-level signal ck at the first clock signal terminal to the driving output terminal G(2). The driving output terminal G(2) outputs a high-level gate driving signal g(2).

[0149] In the third-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal ck of the first clock signal terminal to the cascade output terminal O(3). The cascade output terminal O(3) outputs a high-level cascade signal o(3). The switch circuit responds to the signal of the selection control signal terminal to disconnect the cascade output terminal from the second input signal terminal. The high-level cascade signal o(3) cannot be provided to the second input signal terminal.

[0150] In the fourth stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(3) and provides the signal of the cascade output terminal O(3) of high level to the first node Q1.

[0151] In the second-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(3) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(2), and the cascade output terminal O(2) outputs a low-level cascade signal.

[0152] In the fifth stage T5, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a low level, and the signal xck at the second clock signal end is at a high level;

[0153] In the third stage shift register unit, since the second node Q2 is not at a high level, the transistor T2 in the second shift register circuit is controlled to be turned off, thereby driving the output terminal G(3) to output no gate drive signal g(3).

[0154] In the 4th stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal xck at the second clock signal terminal to the cascade output terminal O(4). The cascade output terminal O(4) outputs a high-level cascade signal o(4). The switch circuit responds to the signal at the selection control signal terminal to disconnect the cascade output terminal from the second input signal terminal. The high-level cascade signal o(4) cannot be provided to the second input signal terminal.

[0155] In the fifth stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(4) and provides the signal of the cascade output terminal O(4) of a high level to the first node Q1.

[0156] In the third-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(4) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(3), and the cascade output terminal O(3) outputs a low-level cascade signal o(3).

[0157] In the sixth stage T6, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a high level, the signal en at the selection control signal end is at a low level, and the signal xck at the second clock signal end is at a low level;

[0158] In the 4th stage shift register unit, since the second node Q2 is not at a high level, the transistor T2 in the second shift register circuit is controlled to be turned off, thereby driving the output terminal G(4) to output no gate drive signal g(4).

[0159] In the fifth-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal ck of the first clock signal terminal to the cascade output terminal O(5). The cascade output terminal O(5) outputs a high-level cascade signal o(5). The switch circuit responds to the signal of the selection control signal terminal to disconnect the cascade output terminal from the second input signal terminal. The high-level cascade signal o(5) cannot be provided to the second input signal terminal.

[0160] In the sixth stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(5) and provides the signal of the cascade output terminal O(5) of high level to the first node Q1.

[0161] In the 4th stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(5) by providing the signal of the low level reference signal terminal to the first node Q1 and the cascade output terminal O(4), and the cascade output terminal O(4) outputs a low level cascade signal o(4).

[0162] By using the driving method of the gate driving circuit, the gate driving circuit outputs no gate driving signal starting from the third-stage shift register unit to drive the corresponding pixels, thereby realizing partial refresh of the display panel screen and saving power consumption.

[0163] Specifically, select Fig.10 The first stage, second stage, third stage, fourth stage, fifth stage, and sixth stage in the signal timing diagram shown. It should be noted that Fig.10 The signal timing diagram shown is only the working process of the gate driving circuit in one frame time. The working process of the gate driving circuit in other frames is basically the same as the working process in this frame, and will not be repeated here.

[0164] In the first stage T1, the signal stv at the frame trigger signal end is at a high level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a low level, and the signal xck at the second clock signal end is at a low level;

[0165] In the first-stage shift register unit, the first shift register circuit responds to the signal stv at the frame trigger signal terminal to provide the high-level signal stv at the frame trigger signal terminal to the first node Q1, and responds to the signal at the first node Q1 to provide the low-level signal ck at the first clock signal terminal to the cascade output terminal O(1), and the cascade output terminal O(1) outputs a low-level cascade signal o(1); the switch circuit responds to the signal en at the selection control signal terminal to disconnect the cascade output terminal from the second input signal terminal.

[0166] In the second stage T2, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a high level, the signal en at the selection control signal end is at a low level, and the signal xck at the second clock signal end is at a low level;

[0167] In the first-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal ck of the first clock signal terminal to the cascade output terminal O(1). The cascade output terminal O(1) outputs a high-level cascade signal o(1). The switch circuit responds to the signal of the selection control signal terminal to disconnect the cascade output terminal from the second input signal terminal, and the high-level cascade signal o(1) cannot be provided to the second input signal terminal.

[0168] In the second-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(1) and provides the signal of the cascade output terminal O(1) of a high level to the first node Q1.

[0169] In the third stage T3, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a high level;

[0170] In the first stage shift register unit, since the second node Q2 is not at a high level, the transistor T2 in the second shift register circuit is controlled to be turned off, thereby driving the output terminal G(1) to output no gate drive signal g(1).

[0171] In the second-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal xck at the second clock signal terminal to the cascade output terminal O(2). The cascade output terminal O(2) outputs a high-level cascade signal o(2). The switch circuit responds to the signal of the selection control signal terminal and provides the high-level cascade signal o(2) to the second input signal terminal. The second shift register circuit responds to the signal of the second input signal terminal and provides the high-level signal of the second input signal terminal to the second node Q2.

[0172] In the third stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(2) and provides the signal of the cascade output terminal O(2) of high level to the first node Q1.

[0173] In the first-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(2) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(1), and the cascade output terminal O(1) outputs a low-level cascade signal o(1).

[0174] In the fourth stage T4, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a high level, the signal en at the selection control signal end is at a low level, and the signal xck at the second clock signal end is at a low level;

[0175] In the second-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the second shift register circuit, the second node Q2 is kept at a high level. The second shift register circuit responds to the signal of the second node Q2 and provides the high-level signal ck at the first clock signal terminal to the driving output terminal G(2). The driving output terminal G(2) outputs a high-level gate driving signal g(2).

[0176] In the third-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal ck of the first clock signal terminal to the cascade output terminal O(3). The cascade output terminal O(3) outputs a high-level cascade signal o(3). The switch circuit responds to the signal of the selection control signal terminal to disconnect the cascade output terminal from the second input signal terminal. The high-level cascade signal o(3) cannot be provided to the second input signal terminal.

[0177] In the fourth stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(3) and provides the signal of the cascade output terminal O(3) of high level to the first node Q1.

[0178] In the second-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(3) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(2), and the cascade output terminal O(2) outputs a low-level cascade signal o(2).

[0179] In the fifth stage T5, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a low level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a high level;

[0180] In the third stage shift register unit, since the second node Q2 is not at a high level, the transistor T2 in the second shift register circuit is controlled to be turned off, thereby driving the output terminal G(3) to output no gate drive signal g(3).

[0181] In the 4th stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal xck at the second clock signal terminal to the cascade output terminal O(4). The cascade output terminal O(4) outputs a high-level cascade signal o(4). The switch circuit responds to the signal of the selection control signal terminal and provides the high-level cascade signal o(4) to the second input signal terminal. The second shift register circuit responds to the signal of the second input signal terminal and provides the high-level signal of the second input signal terminal to the second node Q2.

[0182] In the fifth stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(4) and provides the signal of the cascade output terminal O(4) of a high level to the first node Q1.

[0183] In the third-stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(4) by providing the signal of the low-level reference signal terminal to the first node Q1 and the cascade output terminal O(3), and the cascade output terminal O(3) outputs a low-level cascade signal o(3).

[0184] In the sixth stage T6, the signal stv at the frame trigger signal end is at a low level, the signal ck at the first clock signal end is at a high level, the signal en at the selection control signal end is at a high level, and the signal xck at the second clock signal end is at a low level;

[0185] In the 4th-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the second shift register circuit, the second node Q2 is kept at a high level. The second shift register circuit responds to the signal at the second node Q2 and provides the high-level signal ck at the first clock signal terminal to the driving output terminal G(4). The driving output terminal G(4) outputs a high-level cascade signal g(4).

[0186] In the fifth-stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept at a high level. The first shift register circuit responds to the signal of the first node Q1 and provides the high-level signal ck of the first clock signal terminal to the cascade output terminal O(5). The cascade output terminal O(5) outputs a high-level cascade signal o(5). The switch circuit responds to the signal of the selection control signal terminal and provides the high-level cascade signal o(5) to the second input signal terminal. The second shift register circuit responds to the signal of the second input signal terminal and provides the high-level signal of the second input signal terminal to the second node Q2.

[0187] In the sixth stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(5) and provides the signal of the cascade output terminal O(5) of high level to the first node Q1.

[0188] In the 4th stage shift register unit, the first shift register circuit responds to the signal of the cascade output terminal O(5) by providing the signal of the low level reference signal terminal to the first node Q1 and the cascade output terminal O(4), and the cascade output terminal O(4) outputs a low level cascade signal o(4).

[0189] Through the driving method of the gate driving circuit described above, the 2nd and 4th to Nth shift register units in the gate driving circuit output gate driving signals to drive corresponding pixels, thereby realizing partial refresh of the display panel screen and saving power consumption.

[0190] The embodiment of the present disclosure also provides a display panel, including a plurality of gate lines and the above-mentioned gate driving circuit.

[0191] The driving output end of the x-th stage shift register unit in the gate driving circuit is connected to the y-th gate line among the plurality of gate lines, and x and y are both positive integers.

[0192] Exemplarily, the display panel includes: an LCD display panel, an OLED display panel, an LED display panel, and an MLED display panel.

[0193] The embodiment of the present disclosure also provides a display device, including the above-mentioned display panel.

[0194] Specifically, the display device may further include a control mainboard, which is used to obtain the image to be displayed, determine the image data of the image to be displayed according to the image to be displayed, and send the image data to the display panel. The display panel determines the target gate line that needs to be loaded with the gate drive signal according to the image data, adjusts the time period for loading the effective level at the gate control signal end, drives the shift register unit connected to the target gate line in the gate drive circuit to output the gate drive signal, so as to drive the pixel row connected to the target gate line to emit light, and display the image to be displayed.

[0195] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0196] The shift register unit and driving method, gate driving circuit, and display panel provided in the embodiments of the present disclosure control the conduction between the cascade output terminal and the second input signal terminal in all or part of the shift register units through the switching circuits in the shift register units at each level, so that the driving output terminals of all or part of the shift register units can output gate driving signals to drive the corresponding pixels, thereby realizing full-screen refresh or partial refresh of the display panel screen and saving power consumption.

[0197] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0198] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A shift register unit, characterized in that: include: A first shift register circuit is configured to output a cascade signal through a cascade output terminal in response to a signal at a first input signal terminal; a second shift register circuit configured to output a gate drive signal through a drive output terminal in response to a signal at a second input signal terminal; The switch circuit is connected between the cascade output terminal and the second input signal terminal, and is configured to connect the cascade output terminal and the second input signal terminal in response to a signal of a selection control signal terminal.

2. The shift register unit according to claim 1, characterized in that: The switch circuit includes at least one first transistor, a first electrode of the first transistor is coupled to the cascade output terminal, a second electrode of the first transistor is coupled to the second input signal terminal, and a control electrode of the first transistor is coupled to the selection control signal terminal.

3. The shift register unit according to claim 1, characterized in that: The first shift register circuit is also connected to a first clock signal terminal and a first reset signal terminal, and is configured to provide a signal from the first input signal terminal to a first node in response to a signal from the first input signal terminal, provide a signal from the first clock signal terminal to the cascade output terminal in response to a signal from the first node, and provide a signal from the first reference signal terminal to the first node and the cascade output terminal in response to a signal from the first reset signal terminal; The second shift register circuit is also connected to a second clock signal terminal and a second reset signal terminal, and is configured to provide the signal of the second input signal terminal to a second node in response to a signal of the second input signal terminal, provide the signal of the second clock signal terminal to the driving output terminal in response to a signal of the second node, and provide the signal of the second reference signal terminal to the second node and the driving output terminal in response to a signal of the second reset signal terminal.

4. The shift register unit according to claim 3, characterized in that: The first clock signal terminal and the second clock signal terminal are different signal terminals.

5. The shift register unit according to claim 3, characterized in that: The first reference signal terminal and the second reference signal terminal are the same signal terminal.

6. The shift register unit according to claim 1, characterized in that: The first shift register circuit and the second shift register circuit have the same structure.

7. A gate drive circuit, characterized in that: A shift register unit comprising a plurality of cascaded shift register units according to any one of claims 1 to 6; The first input signal terminal of the first shift register circuit in the first-stage shift register unit is connected to the frame trigger signal terminal; The cascade output end of the first shift register circuit in the nth-stage shift register unit is connected to the first input signal end of the first shift register circuit in the n+mth-stage shift register unit, and the first reset signal end of the first shift register circuit in the nth-stage shift register unit is connected to the cascade output end of the first shift register circuit in the n+ith-stage shift register unit; wherein m, n, and i are all positive integers.

8. The gate driving circuit according to claim 7, characterized in that: The gating control signal terminals connected to the switch circuits in each level of the shift register unit are the same signal terminal.

9. The gate driving circuit according to claim 7, characterized in that: The second reset signal terminal of the second shift register circuit in the nth stage shift register unit is connected to the cascade output terminal of the first shift register circuit in the n+kth stage shift register unit; wherein k is a positive integer.

10. A driving method of a shift register unit according to any one of claims 1 to 6, characterized in that: include: The first shift register circuit outputs a cascade signal through a cascade output terminal in response to a signal at a first input signal terminal; The switch circuit connects the cascade output terminal and the second input signal terminal in response to the signal at the gate control signal terminal, and the second shift register circuit outputs a gate drive signal through the drive output terminal in response to the signal at the second input signal terminal; Alternatively, the switch circuit disconnects the cascade output terminal from the second input signal terminal in response to a signal at the selection control signal terminal.

11. A driving method of a gate driving circuit according to any one of claims 7 to 9, characterized in that: include: In one frame time, the first shift register circuit in each level of shift register units responds to the signal at the first input signal terminal and outputs a cascade signal through the cascade output terminal; The switching circuit in at least one shift register unit responds to the signal at the selection control signal terminal to connect the cascade output terminal in the at least one shift register unit and the second input signal terminal in the at least one shift register unit, and the second shift register circuit in the at least one shift register unit responds to the signal at the second input signal terminal to output a gate drive signal through the driving output terminal.

12. A display panel, characterized in that: comprising a plurality of gate lines and a gate driving circuit as claimed in any one of claims 7 to 9; The driving output end of the x-th stage shift register unit in the gate driving circuit is connected to the y-th gate line among the plurality of gate lines, and x and y are both positive integers.

13. A display device, characterized in that: Comprising the display panel as claimed in claim 12.

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