Semiconductor circuit and device and operation method thereof

Abstract

The invention provides a semiconductor circuit, a semiconductor device, and an operation method of a general purpose memory. A general purpose memory device includes an array of general purpose memory cells. Each general memory cell includes a write transistor and a read transistor. The write transistor has a gate terminal for receiving a gate voltage to turn on or off the write transistor, a first terminal for receiving a write voltage, and a second terminal coupled to the gate terminal of the read transistor. The read transistor includes a charge trapping layer at a gate terminal of the read transistor. The charge trapping layer is configured to be invariable when a first write voltage is applied to a first terminal of the write transistor and variable when a second write voltage is applied to the first terminal of the write transistor to alter a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.

Description

Technical Field

[0001] The technical field to which the present disclosure relates is memory, for example, for in-memory computing (IMC). Background Art

[0002] The operation of the artificial intelligence (AI) model includes a training mode and an inference mode. In the training mode, as a memory that needs to be repeatedly programmed and erased to change weights, a memory with high durability is desired. In the inference mode, as a memory that needs to retain weights used for inference calculations, a memory with high data retention is desired. Summary of the invention

[0003] The present disclosure describes methods, circuits, devices, systems, and techniques for providing a universal memory, such as for IMC, wherein the universal memory can be used to operate in both a dynamic random access memory (DRAM) mode with high endurance for AI training and a nonvolatile memory (NVM) mode with high data retention for AI reasoning.

[0004] One aspect of the present disclosure features a semiconductor circuit including a first transistor and a second transistor. The first transistor has a gate terminal for receiving a gate voltage to turn the first transistor on or off, a first terminal for receiving a write voltage, and a second terminal coupled to the gate terminal of the second transistor. The second transistor includes a charge trapping layer at the gate terminal of the second transistor. The charge trapping layer is configured to be immutable when a first write voltage is applied to the first terminal of the first transistor, and to be variable to change a threshold voltage of the second transistor when a second write voltage is applied to the first terminal of the first transistor, the second write voltage being greater than the first write voltage.

[0005] In some embodiments, the second programming voltage is a voltage high enough to achieve Fowler-Nordheim tunneling and hot carrier injection in the charge trapping layer of the second transistor.

[0006] In some embodiments, one of the first terminal and the second terminal is a drain terminal, and the other of the first terminal and the second terminal is a source terminal.

[0007] In some embodiments, a semiconductor circuit is used to: operate in a first mode, wherein a storage potential of a storage node between a second terminal of the first transistor and a gate terminal of the second transistor is determined according to a first write voltage applied to a first terminal of the first transistor when the first transistor is turned on, a threshold voltage of the second transistor is maintained unchanged, and the storage potential of the storage node is repeatedly variable according to the first write voltage, and operate in a second mode, wherein the second transistor is programmed or erased to have a specific threshold voltage according to a second write voltage applied to the first terminal of the first transistor when the first transistor is turned on, and the specific threshold voltage is adjustable according to the second write voltage.

[0008] In some embodiments, the first mode includes a training mode of an AI (artificial intelligence) model or a DRAM (dynamic random access memory)-like mode, and the second mode includes an inference mode of the AI ​​model or a NVM (non-volatile memory)-like mode.

[0009] In some embodiments, the storage potential of the storage node corresponds to an adjustable weight in the first mode, and the specific threshold voltage of the second transistor corresponds to a fixed weight in the second mode.

[0010] In some embodiments, the specific threshold voltage of the second transistor corresponds to a binary weighted logic 1 or a binary weighted logic 0 in the second mode.

[0011] In some embodiments, the specific threshold voltage of the second transistor corresponds to the analog weight in the second mode, and the specific threshold voltage is adjustable between a minimum threshold voltage and a maximum threshold voltage.

[0012] In some embodiments, the second transistor is used to be operated in a saturation region, and in the second mode the storage potential of the storage node is greater than the saturation voltage associated with the second transistor, and the second transistor is used to receive a binary input signal at the first terminal of the second transistor, wherein if the binary input signal has a voltage greater than the voltage difference between the storage potential of the storage node and the minimum threshold voltage, the binary input signal is represented as a logic 1, and if the binary input signal has a voltage equal to 0V, the binary input signal is represented as a logic 0.

[0013] In some embodiments, the second transistor is used to be operated in a triode region, and in a second mode the storage potential of the storage node is less than a saturation voltage associated with the second transistor, and the second transistor is used to receive an analog input signal at a first terminal of the second transistor, wherein the analog input signal has a voltage in a range between 0V and a voltage difference between the storage potential of the storage node and a maximum threshold voltage.

[0014] In some embodiments, the second transistor includes a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) transistor, and the first transistor includes a MOS (Metal Oxide Semiconductor) transistor or a SONOS transistor.

[0015] Another aspect of the present disclosure features a semiconductor circuit including a first transistor and a second transistor. The first transistor has a gate terminal for receiving a gate voltage to turn the first transistor on or off, a first terminal for receiving a write voltage, and a second terminal coupled to the gate terminal of the second transistor. The semiconductor circuit can be used to: operate in a first mode, wherein a storage potential of a storage node between the second terminal of the first transistor and the gate terminal of the second transistor is determined according to a first write voltage applied to the first terminal of the first transistor when the first transistor is turned on, a threshold voltage of the second transistor is maintained unchanged, and the storage potential of the storage node is repeatedly variable according to the first write voltage, and operate in a second mode, wherein the second transistor is programmed or erased to have a specific threshold voltage according to a second write voltage applied to the first terminal of the first transistor when the first transistor is turned on, and the specific threshold voltage is adjustable according to the second write voltage.

[0016] Another aspect of the present disclosure features a semiconductor device including a plurality of memory cells. At least one of the memory cells includes a write transistor and a read transistor. The write transistor has a gate terminal for receiving a gate voltage to turn the write transistor on or off, a first terminal for receiving the write voltage, and a second terminal coupled to the gate terminal of the read transistor. The read transistor includes a charge trapping layer at the gate terminal of the read transistor. The charge trapping layer is configured to be immutable when a first write voltage is applied to the first terminal of the write transistor, and to be variable to change a threshold voltage of the read transistor when a second write voltage is applied to the first terminal of the write transistor, the second write voltage being greater than the first write voltage.

[0017] Another aspect of the present disclosure features a semiconductor device comprising: an array of multiple memory cells; one or more write word lines (WWLs); one or more write bit lines (WBLs); one or more read word lines (RWLs); and one or more read bit lines (RBLs). Each memory cell of the array of multiple memory cells comprises: a write transistor and a read transistor. The write transistor comprises a gate terminal coupled to the corresponding write word line, a first terminal coupled to the corresponding write bit line, and a second terminal coupled to the gate terminal of the read transistor, and wherein the read transistor comprises a first terminal coupled to the corresponding read bit line and a second terminal coupled to the corresponding read word line. The read transistor comprises a charge trapping layer at the gate terminal of the read transistor. The charge trapping layer is configured to be immutable when a first write voltage is applied to the first terminal of the write transistor through the corresponding write bit line, and to be variable when a second write voltage is applied to the first terminal of the write transistor through the corresponding write bit line to change a threshold voltage of the read transistor, the second write voltage being greater than the first write voltage.

[0018] In some embodiments, an array of a plurality of memory cells is arranged in an area, the area being defined by a first direction and a second direction perpendicular to the first direction. Each of the one or more write word lines is coupled to the multiple gate terminals of the multiple write transistors of the multiple first memory cells along the first direction, each of the one or more write bit lines is coupled to the multiple first terminals of the multiple write transistors of the multiple second memory cells along the second direction, each of the one or more read bit lines is coupled to the multiple first terminals of the multiple read transistors of the multiple third memory cells along the first direction, and each of the one or more read word lines is coupled to the multiple second terminals of the multiple read transistors of the multiple fourth memory cells along the second direction.

[0019] In some embodiments, a memory cell is configured to: operate in a first mode, wherein a storage potential of a storage node between a second terminal of the write transistor and a gate terminal of a read transistor is determined according to a first write voltage applied to a first terminal of the write transistor when the write transistor is turned on by applying a gate voltage to the gate terminal of the write transistor, a threshold voltage of the read transistor is maintained unchanged, and the storage potential of the storage node is repeatedly variable according to the first write voltage, and operate in a second mode, wherein the read transistor is programmed or erased to have a specific threshold voltage according to a second write voltage applied to the first terminal of the write transistor when the write transistor is turned on, and the specific threshold voltage is adjustable according to the second write voltage.

[0020] In some embodiments, the first mode includes a training mode of an AI (artificial intelligence) model or a DRAM (dynamic random access memory)-like mode, and the second mode includes an inference mode of the AI ​​model or a NVM (non-volatile memory)-like mode.

[0021] In some implementations, the semiconductor device is configured to function as a DRAM in a first mode and as a NVM in a second mode.

[0022] In some embodiments, the storage potential of the storage node corresponds to an adjustable weight in the training mode, and the specific threshold voltage of the read transistor corresponds to a fixed weight in the inference mode.

[0023] In some implementations, a particular threshold voltage of the read transistor corresponds to a binary weighted logic 1 or a binary weighted logic 0 in the inference mode.

[0024] In some embodiments, the specific threshold voltage of the read transistor corresponds to the analog weight in the inference mode, and the specific threshold voltage is adjustable between a minimum threshold voltage and a maximum threshold voltage.

[0025] In some embodiments, the analog weight is associated with a voltage difference between a storage potential of a storage node and a specific threshold voltage.

[0026] In some embodiments, the read transistor is configured to be operated in a saturation region, and the storage potential of the storage node is greater than a saturation voltage associated with the read transistor in an inference mode. The read transistor is configured to receive a binary input signal at a first terminal of the read transistor via a corresponding read bit line, wherein if the binary input signal has a voltage greater than a voltage difference between the storage potential of the storage node and a minimum threshold voltage, the binary input signal represents a logic 1, and if the binary input signal has a voltage equal to 0V, the binary input signal represents a logic 0.

[0027] In some embodiments, the read transistor is configured to be operated in a triode region, and the storage potential of the storage node is less than a saturation voltage associated with the read transistor in an inference mode. The read transistor is configured to receive an analog input signal at a first terminal of the read transistor via a corresponding read bit line, wherein the analog input signal has a voltage ranging from 0V to a voltage difference between the storage potential of the storage node and a maximum threshold voltage.

[0028] In some embodiments, a semiconductor device is used to perform a multiply-accumulate (MAC) operation using an array of multiple memory cells. The semiconductor device further includes a sense amplifier coupled to a corresponding read word line, and the corresponding read word line is coupled to multiple second terminals of multiple read transistors of multiple corresponding memory cells. The sense amplifier is used to receive a summed current I from the corresponding read word line, and the formula for the summed current I is I=∑ i (w i ×X i )=∑ i (G i ×V i ), where x i represents an input signal received by a memory cell i of a plurality of corresponding memory cells, G i represents the conductivity of the read transistor of the memory cell i and Vi represents the input voltage at the first terminal of the read transistor of the memory cell i through the corresponding read bit line.

[0029] In some embodiments, the read transistor includes a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) transistor. In some embodiments, the write transistor includes a MOS (Metal Oxide Semiconductor) transistor or a SONOS transistor.

[0030] Another aspect of the present disclosure is to provide a method for performing in-memory operations. An operating method of a universal memory of IMC (integrated computing), the operating method comprising: executing a training mode of an AI (artificial intelligence) model in the universal memory, wherein the universal memory comprises at least one memory cell having a write transistor and a read transistor, wherein the write transistor has a gate terminal for receiving a gate voltage to turn on or off the write transistor, a first terminal for receiving the write voltage, and a second terminal coupled to the gate terminal of the read transistor, and wherein, during the training mode, according to a first write voltage applied to the first terminal of the write transistor when the write transistor is turned on by applying the gate voltage to the gate terminal of the write transistor, a storage potential of a storage node between the second terminal of the write transistor and the gate terminal of the read transistor is determined, a threshold voltage of the read transistor is maintained unchanged, and the storage potential of the storage node is repeatedly variable according to the first write voltage; and executing an inference mode of the AI ​​model in the universal memory, wherein, in the inference mode, according to a second write voltage applied to the first terminal of the write transistor when the write transistor is turned on, the read transistor is programmed or erased to have a specific threshold voltage, and the specific threshold voltage is adjustable according to the second write voltage.

[0031] In some embodiments, the training mode includes a weight modification step, a weight storage step, and a read operation step. The inference mode includes a weight modification step, a weight storage step, and a read operation step.

[0032] In some embodiments, the storage potential of the storage node corresponds to an adjustable weight in the training mode, and the specific threshold voltage of the read transistor corresponds to a fixed weight in the inference mode.

[0033] In some implementations, a particular threshold voltage of the read transistor corresponds to a binary weighted logic 1 or a binary weighted logic 0 in the inference mode.

[0034] In some embodiments, the specific threshold voltage of the read transistor corresponds to the analog weight in the inference mode, and the specific threshold voltage is adjustable between a minimum threshold voltage and a maximum threshold voltage.

[0035] In some embodiments, the analog weight is associated with a voltage difference between a storage potential of a storage node and a specific threshold voltage.

[0036] In some embodiments, an inference mode of executing an AI (artificial intelligence) model in a general purpose memory includes: operating a read transistor in a saturation region, wherein a storage potential of a storage node in the inference mode is greater than a saturation voltage associated with the read transistor; and receiving a binary input signal at a first terminal of the read transistor, wherein if the binary input signal has a voltage greater than a voltage difference between the storage potential of the storage node and a minimum threshold voltage, the binary input signal is represented as a logic 1, and if the binary input signal has a voltage equal to 0V, the binary input signal is represented as a logic 0.

[0037] In some embodiments, an inference mode of executing an AI (artificial intelligence) model in a general purpose memory includes: operating a read transistor in a triode region, wherein a storage potential of a storage node in the inference mode is less than a saturation voltage associated with the read transistor; and receiving an analog input signal at a first terminal of the read transistor, wherein the analog input signal has a voltage in a range between 0V and a voltage difference between the storage potential of the storage node and a maximum threshold voltage.

[0038] In some embodiments, the operation method includes: performing a multiply-accumulate (MAC) operation of the AI ​​model in a general purpose memory, wherein the MAC operation is performed in a training mode and an inference mode respectively. Performing the MAC operation includes: generating a summed current I from corresponding read word lines serially coupled to a plurality of memory cell combinations, and the formula for the summed current I is I=∑ i (w i × i )=∑ i (Gi ×V i ), where x i represents the input signal received by the memory cell i in the combination of multiple memory cells, G j represents the conductivity of the read transistor of memory cell i and V i represents the input voltage at the first terminal of the read transistor of the memory cell i through the corresponding read bit line.

[0039] In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings. Other features, aspects and advantages will become apparent from the description, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1A and Figure 1B A schematic diagram of an example of an artificial neural network (ANN) and an expanded diagram of a neuron of the ANN are shown respectively.

[0041] Figure 2 A schematic diagram of an example memory for performing a multiply-accumulate (MAC) operation.

[0042] Figure 3A is a schematic diagram of an example system for performing a training mode.

[0043] Figure 3B is a schematic diagram of an example system for executing an inference mode.

[0044] Figure 4 is a schematic diagram of an example of a general memory cell.

[0045] Figure 5A is a schematic diagram of an example general purpose memory.

[0046] Figure 5B For use Figure 5A Schematic diagram of an example generic memory implementation MAC operation.

[0047] Figure 6 A flowchart of an example process for operating a universal memory is shown.

[0048] Fig. 7A Graph showing characteristic curves of a write transistor in a training mode or a DRAM mode.

[0049] Figure 7B Graph showing characteristic curves of a read transistor in a training mode or a DRAM mode.

[0050] Fig. 8AGraph showing characteristic curves of a write transistor in inference mode or NVM mode.

[0051] Figure 8B A graph showing a series of characteristic curves of a read transistor in either inference mode or NVM mode.

[0052] Fig. 9 FIG. 4 is a graph showing the relationship between current and voltage for reading a bit line.

[0053] Fig. 10A is a schematic diagram of an example operation in the saturation region of a read transistor.

[0054] Fig. 10B is a schematic diagram of an example operation in the triode region of a read transistor.

[0055] Like reference numbers and designations in the various drawings represent like elements.It should also be understood that the various exemplary embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale.

[0056] Description of Reference Numerals

[0057] 100: ANN

[0058] 200, 310, 360, 500: Memory

[0059] 210, 220, 230, 240, 320 ij ,370 ij : Memory unit

[0060] 211, 221, 231, 241, 322 ij , 372 ij :resistance

[0061] 300, 350: System

[0062] 302: DAC

[0063] 303, BL2: bit line

[0064] 304: Sampling and storage unit

[0065] 305, WL2: word line

[0066] 306: ADC

[0067] 400: General purpose memory unit

[0068] 402: Storage Node

[0069] 410: Write transistor

[0070] 412, 422: Gate terminal

[0071] 413, 423: Charge trapping layer

[0072] 414, 424: First terminal

[0073] 416, 426: Second terminal

[0074] 420: Read transistor

[0075] 502: Sense Amplifier

[0076] 512, WWL, WWL1, WWL2, WWLn: Write word line

[0077] 514, WBL, WBL1, WBL2, WBLm: write bit lines

[0078] 522, RWL, RWL1, RWL2, RWLm: Read word line

[0079] 524, RBL, RBL1, RBL2, RBLn: read bit line

[0080] 600: Procedure

[0081] 610: Training Mode

[0082] 612, 614, 616, 622, 624, 626: Steps

[0083] 620: Reasoning Mode

[0084] 700, 710, 800, 810, 900: Chart

[0085] CVi: Curve

[0086] G1, G2, G3, G4, G i , G ij : Conductivity

[0087] I, 11, I2, I3, I4, Ii: current

[0088] L0, L1, L2: Layers

[0089] N0, N1, N2, N3, N4, N5, N6, N7, N8: Neurons

[0090] V1, V2, V3, V4, Vn: voltage

[0091] w i , w ij : Weight

[0092] x i :Signal DETAILED DESCRIPTION

[0093] Various embodiments of the present disclosure provide methods, circuits, devices, systems, and techniques for providing a universal memory for in-memory operations. In some embodiments, the universal memory is used to operate in both a DRAM-like (dynamic random access memory) mode with high durability and an NVM-like (non-volatile memory) mode with high data retention. Here, the universal memory can integrate multiple functions of multiple memories of different categories, including memories with high reliability (such as DRAM) and memories with high data retention (such as NVM). The universal memory can be applied to in-memory operations (IMC), which enables a large number of parallel dot products while maintaining a set of operands in the memory. For example, the universal memory can be used for AI applications with computational needs, such as deep neural networks (DNNs) and recurrent neural networks (RNNs).

[0094] The universal memory can be used to perform both AI training and AI reasoning, such as in multiply-accumulate (MAC) calculations or multiply-add (MAD) operations. All operations can be performed in the universal memory, and no data is transferred between different memories or between computing resources (such as computing processing units (CPUs) or processors) and data memories, which can reduce or eliminate the Von-Neumann bottleneck problem to reduce substantial latency and significantly reduce energy dissipation or power consumption, improve processing speed and efficiency, and simplify the system for AI applications, thereby improving the overall performance of the system for AI applications.

[0095] In some embodiments, the universal memory includes an array of multiple memory cells. Each memory cell can be a universal memory cell for performing DRAM-like operations such as training in AI computing, and NVM-like operations such as inference in simulation mode. The universal memory can have high durability (e.g., near infinite durability) to handle a large number of weight updates during training of big data, and can also have non-volatility and high data retention to keep weights fixed with low power consumption.

[0096] The universal memory may be used to perform dual-mode operation in a two-transistor (2T) charge trapping memory cell. In some embodiments, the universal memory cell includes a write transistor and a read transistor. The write transistor is coupled to a write word line WWL and a write bit line WBL, while the read transistor is coupled to a read word line RWL and a read bit line RBL. The read transistor may be a charge trap transistor (CTT) including a charge trapping layer having charge storage capability. In some examples, the read transistor is a SONOS field-effect transistor (FET), and the nitride layer is the charge trapping layer. The write transistor may be a transistor having charge storage capability, such as a SONOS FET, or a transistor without charge storage capability, such as a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0097] In some embodiments, in a DRAM-like mode, the write transistor is turned on by a write voltage on the write word line WWL to charge or discharge the gate node (or storage node) of the read memory with a write voltage on the write bit line WBL, and the logic state of the memory cell is based on the write voltage on the write bit line WBL to the write transistor. The storage mode of the memory cell can be at least partially similar to the storage mode of a DRAM memory cell. When the write voltage on the write bit line WBL is low, the charge trapping layer is not programmed / erased. Therefore, the read transistor can have high durability, and multiple memory cells operating in a DRAM-like mode can be used for in-memory operations in AI training.

[0098] In some embodiments, in NVM-like mode, FN tunneling and hot carrier ejection mechanisms (+FN / -FN) can be used to modify the amount of charge in the charge trapping layer of the read transistor. Therefore, the read transistor can be programmed / erased (e.g., with +FN / -FN with high voltage) to have a multi-level threshold voltage Vt and non-volatile capability, for example, Vt can be adjustable. Multiple Vt levels can be used to determine the logical state of the memory cell. Multiple memory cells operating in NVM mode can be used for in-memory operations for AI reasoning, where Vt can be used as a fixed weight. The read transistor can be operated in both the triode region and the saturation region. Under the condition of adjustable Vt for the read transistor, the write bit line WBL read voltage can be constant at the same level.

[0099] The logic state in the universal memory cell operating in DRAM mode can be determined by the stored charge in the sense node of the memory cell for short-time memory (e.g., data retention less than 104 seconds) through low voltage operation (e.g., less than 3V). Therefore, the universal memory cell can act like a DRAM memory cell. Compared with the known DRAM memory cell with a single transistor and a single capacitor (1T1C) structure, the universal memory cell has a dual transistor and no capacitor (2T0C) structure, which can have a more compact structure, simplified process and cost efficiency. The logic state can be stored in the read memory (and / or write memory) through FN programming / erasing in NVM operation. Further, the universal memory cell can be applied to AI model training through in-memory computing (IMC) in DRAM mode, and reasoning can be done through IMC in NVM mode with fixed weights. Multiple Vt values ​​in the read transistor (and / or write transistor) can be used as multiple weights for MAC operation, which can be implemented in a memory array of multiple universal memory cells through Ohmic and Kirchoff's laws.

[0100] In some embodiments, the universal memory cell has an analog current-to-voltage (IV) curve or characteristic in the read transistor, which enables analog operations (e.g., analog training or inference) in the universal memory cell. Analog training or inference can be more efficient than binary training or inference. In some cases, the universal memory cell is used with analog weights Vt and binary inputs (from the voltage Vt for the read transistor on the read bit line). RBL In some cases, a universal memory cell is used with analog weight Vt and analog input V RBL operation, and the read transistor is operated in the triode region.

[0101] This technology can be applied to any suitable charge trapping-based memory device, such as a silicon-oxide-nitride-oxide-silicon (SONOS) memory device. This technology can be applied to a 2-dimensional (2D) memory device or a 3-dimensional (3D) memory device. This technology can be applied to a variety of memory types, such as a single-level cell (SLC) device, a multi-level cell (MLC) device such as a double-level cell (2-level cell) device, a triple-level cell (TLC) device, a quad-level cell (QLC) device, or a penta-level cell (PLC) device.

[0102] The technology can be applied to various types of storage systems, such as storage class memory (SCM), storage systems based on various types of memory devices, such as static random access memory (SRAM), dynamic random access memory (DRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), phase change memory (PCM), or others. Additionally and alternatively, the technology can be applied to systems based on, for example, NAND flash memory or NOR flash memory, such as universal flash storage (UFS), peripheral component interconnect express (PCIe) storage, embedded multimedia cards (eMMC) storage, storage in dual in-line memory modules (DIMM), or others. The technology can also be applied to magnetic disks, optical disks, or others. The technology can be applied to any suitable application, such as an application using AI mechanisms such as ANNs for deep learning. These applications may include games, natural language processing, expert systems, vision systems, speech recognition, handwriting recognition, smart robots, data centers, cloud computing services, in-vehicle applications, and others.

[0103] Figure 1A and Figure 1B An example of an artificial neural network (ANN 100) and an expanded diagram of a neuron N6 of the ANN 100 are shown respectively. Figure 1A As shown in , ANN 100 is a collection of connected units or nodes, such as neuron N0, neuron N1, neuron N2, neuron N3, neuron N4, neuron N5, neuron N6, neuron N7 and neuron N8, all of which are called artificial neurons. Multiple artificial neurons are organized in multiple layers. For example, layer L0 includes neuron N0, neuron N1 and neuron N2; layer L1 includes neuron N3, neuron N4, neuron N5 and neuron N6; and layer L2 includes neuron N7 and neuron N8.

[0104] In some embodiments, multiple different layers of an ANN perform different types of transformations on their inputs. One of the multiple different layers is the first or input layer of the ANN, such as layer L0, while another layer is the last or output layer of the ANN, such as layer L2. The ANN includes one or more internal layers, such as layer L1, between the input layer and the output layer. After one or more round trips to the internal layers, the signal moves from the input layer to the output layer.

[0105] In some embodiments, at each connection point between artificial neurons, such as a connection point from neuron N2 to neuron N6, or a connection point from neuron N6 to neuron N8, a signal can be transmitted from one to another. The artificial neuron that receives the signal can process the signal, and then the signal artificial neuron is connected to the signal. In some embodiments, the signals at the connection points between multiple artificial neurons are real numbers, and the output of each artificial neuron is calculated as a nonlinear function of the sum of its inputs. Each connection point can have a weight that is adjusted as the learning process progresses. The weight increases or decreases the strength of the signal at the connection point.

[0106] In some embodiments, a combination of input data (e.g., from various samples) is presented to the ANN, such as at an input layer such as layer L0. A series of operations are performed at each subsequent layer such as layer L1. Figure 1A In the fully connected network shown in , the output operation from each node is presented to all nodes in the subsequent layer. The final layer of a trained ANN, such as layer L2, can be associated with judging the classification that matches the input data, for example from a fixed combination of multiple labeled candidates, which can be regarded as "supervised learning".

[0107] Figure 1B An expanded diagram of the operation performed on artificial neuron N6, which is represented as an example of an artificial neuron in an ANN. Input signals x0, x1, and x2 from other artificial neurons of the ANN 100, such as from artificial neuron N0, neuron N1, and neuron N2, are transmitted to artificial neuron N6. Each input signal is weighted by the weight associated with the corresponding connection point, and the weighted signal is received and processed by the artificial neuron. For example, the connection point from artificial neuron N0 to artificial neuron N6 has a weight w0, and the weighted signal is transmitted from neuron N0 to neuron N6 through the connection point, resulting in the value of the signal received and processed by neuron N6 being w0 x0. Similarly, multiple connection points from artificial neuron N1 and neuron N2 to artificial neuron N6 have weights w1 and w2, respectively, resulting in the values ​​of multiple signals received and processed by neuron N6 from neuron N1 and neuron N2 being w1 x1 and w2 x2, respectively.

[0108] The artificial neuron processes weighted input signals internally, such as by changing its internal state (deemed as activation) in accordance with the input, and generates an output signal in accordance with the input and activation. For example, artificial neuron N6 generates an output signal that is a result of an output function f, which is applied to a weighted combination of multiple input signals received by artificial neuron N6. In this manner, the artificial neurons of ANN 100 form a graph with weights directed that connects multiple outputs of some neurons to multiple inputs of other neurons. In some embodiments, any combination of multiple weights, activation functions, output functions, or these parameters of artificial neurons can be modified by a learning process, such as deep learning.

[0109] In some embodiments, the operation is a multiply-accumulate (MAC) calculation, which may be an action in an AI operation. Figure 1B As shown in FIG. , each data value x of multiple input signals i by its associated weight w i The products are then summed to get ∑ i w i x i , and finally the bias value b can be added to obtain the calculated value z=(∑ i w i x i + b). Then, the operation value z is calculated by the activation function f to obtain the output value a=f(∑ i w i x i + b). The output value a can be provided as a node output (or output signal) to the next layer as input.

[0110] For example, the AI ​​model of ANN 100 can be operated in training mode and inference mode. For the AI ​​model to provide answers to questions, multiple connection points between answers and questions can be strengthened by repeatedly performing network training. In training mode, initially, a combination of test data with correct labels known as training data is given to the AI ​​model. Then, the reasoning of the AI ​​model generated by the combination of test data is monitored, and the AI ​​model can respond true or false. The goal of the learning method is to detect patterns, and what the AI ​​model does in this case is to search and classify data based on data similarity. The AI ​​training model can be similar to training in multimedia data processing. Mathematically, in training mode, multiple weights in the AI ​​model are adjusted to maximize output. In inference mode, the AI ​​model is placed in practice based on what is learned in training. The AI ​​model can generate an inference model with training and fixed weights to classify, solve, and / or answer questions.

[0111] Figure 2An example memory 200 for performing multiply-accumulate (MAC) is shown. The memory 200 may be a general purpose memory as described in the present disclosure, for example, FIG. 5A to FIG. 5B The memory 200 includes, for example, a memory unit 210, a memory unit 220, a memory unit 230, and a memory unit 240. The memory unit may include a general memory unit, for example, Figure 4 The memory cell 210, the memory cell 220, the memory cell 230 and the memory cell 240 respectively include, for example, a resistor 211, a resistor 221, a resistor 231 and a resistor 241. The resistor 211, the resistor 221, the resistor 231 and the resistor 241 have conductivity G1, conductivity G2, conductivity G3 and conductivity G4, respectively.

[0112] When voltage V1, voltage V2, voltage V3 and voltage V4 are respectively input to bit line BL2, a plurality of corresponding read currents I1, current I2, current I3 and current I4 flow into word line WL2. Read current I1 is equal to the product of voltage V1 and conductivity G1; read current I2 is equal to the product of voltage V2 and conductivity G2; read current I3 is equal to the product of voltage V3 and conductivity G3; read current I4 is equal to the product of voltage V4 and conductivity G4. The total current I is equal to the sum of the products of voltage V1, voltage V2, voltage V3 and voltage V4 and conductivity G1, conductivity G2, conductivity G3 and conductivity G4. If voltage V1, voltage V2, voltage V3 and voltage V4 are represented as input signal x i The conductivity G1, conductivity G2, conductivity G3 and conductivity G4 are expressed as weight w i , then the total current I is expressed as the input signal x i and weight w i The sum of the products is as follows:

[0113]

[0114] Through Figure 2 With the memory 200 in the AI ​​operation, the MAC can be implemented.

[0115] Figure 3A An example system 300 for performing a training mode is shown. The system 300 includes a memory 310 including, for example, a plurality of memory cells 320 arranged in a matrix. ij The system 300 may further include a plurality of digital-to-analog converters (DACs 302), each coupled to a corresponding bit line 303 (eg, Figure 2 Each DAC 302 is used to convert an input digital signal, such as a voltage, into a bit line BL2. Figure 2 The voltages V1, V2, V3 and V4 are converted into analog voltage signals. The system 300 may also include a plurality of sampling and holding units 304 (S&H units), each of which is coupled to a corresponding word line 305 (eg Figure 2 The analog-to-digital converter (ADC 306) is coupled to the plurality of sampling and saving units 304. Each sampling and saving unit 304 may include one or more logic units and / or circuits for sampling and saving the summed current analog signal (e.g., Figure 2 ), and the ADC 306 can be used to sum the summed current analog signals from each word line 305 and convert the final summed result from an analog signal to a digital signal for further processing.

[0116] Each memory unit 320 ij May have, for example, an adjustable resistor 322 ij . Each adjustable resistor 322 ij With conductivity G ij ,For example Figure 2 The conductivity G1 of the resistor 211, the conductivity G2 of the resistor 221, the conductivity G3 of the resistor 231, and the conductivity G4 of the resistor 241. ij Can be used to represent the weight w ij ,For example Figure 1B The weight w shown in i When the memory 310 executes the training mode, the weight W ij needs to be continuously updated so that the adjustable resistor 322 ij The memory 310 can be smoothly used to perform training mode. Therefore, a memory 310 with near-infinite durability that can handle a large number of weight updates during training of large data is desired.

[0117] Figure 3B An example system 350 for executing the inference mode is shown. System 350 is similar to system 300 and includes DAC 302, sample and hold unit 304, and ADC 306. Figure 3A In the system 300, the system 350 includes a memory 360, which is different from the memory 310. The memory 360 includes, for example, a plurality of memory cells 370 arranged in a matrix. ij Each memory unit 370 ij may have, for example, a fixed resistor 372 ij , unlike the adjustable resistor 322 ij The memory unit 320 ij . Each fixed resistor 372ij With fixed conductivity G ij These conductivity G ij Can be used to represent fixed weights w ij In the process of executing the inference mode, the weight w ij has been set and will not be changed arbitrarily, for example according to Figure 3A The trained G ij , so that the fixed resistor 372 ij The memory 360 can be smoothly used to execute the inference mode. Therefore, it is desirable to have non-volatility and good data retention for AI inference to keep the weights in a fixed memory 360 with low power consumption.

[0118] As mentioned above, the requirements of the training mode and the inference mode are different. For example, the memory 310 executing the training mode needs to have high durability to load the weights w ij The memory 360 for executing the inference mode needs to have non-volatility and high data retention, so that the weight w ij can be kept at low power consumption. These two types of memory are usually quite different. Figure 3A The memory 310 and Figure 3B The memory 360 in the embodiment uses a completely different resistor (adjustable resistor 322 ij And fixed resistor 372 ij ).

[0119] As described in more detail below, various embodiments of the present disclosure provide universal memory for operating in both a DRAM-like mode with high endurance and an NVM-like mode with high non-volatility and high data retention. Here, the universal memory may integrate multiple functions of different types of memory, including memory with high reliability and memory with high data retention. The universal memory may be applied with in-memory computing (IMC). In-memory computing may also be referred to as computing in-memory, in-memory processing, or processing in-memory (PIM) or processing in memory (PIM).

[0120] In some embodiments, the universal memory includes a plurality of universal memory cells. As discussed in more detail below, each universal memory cell can be used to have a first parameter (e.g., a voltage at a storage node) that can be adjusted for a training mode, and a second parameter (e.g., a threshold voltage of a read transistor) that can be fixed for an inference mode. The second parameter can be based on the first parameter.

[0121] Figure 4 An example of a general purpose memory cell 400 is shown. The general purpose memory cell 400 may be used for in-memory computing (IMC). In some embodiments, such as Figure 4 As shown in FIG. 4 , the universal memory cell 400 includes a write transistor 410 and a read transistor 420 coupled to the write transistor 410. Since the universal memory cell 400 is composed of two transistors, it can also be referred to as a 2T structure.

[0122] The write transistor 410 includes a gate terminal 412, a first terminal 414, and a second terminal 416. One of the first terminal 414 and the second terminal 416 is a drain terminal, and the other of the first terminal 414 and the second terminal 416 is a source terminal. Similarly, the read transistor 420 includes a gate terminal 422, a first terminal 424, and a second terminal 426. One of the first terminal 424 and the second terminal 426 is a drain terminal, and the other of the first terminal 424 and the second terminal 426 is a source terminal. The second terminal 416 of the write transistor 410 is coupled to the gate terminal 422 of the read transistor 420. The storage node 402 (SN) is coupled between the second terminal 416 and the gate terminal 422.

[0123] Unlike a conventional memory cell having a single transistor coupled to a word line and a bit line, the universal memory cell 400 has two transistors coupled to two word lines and two bit lines. Figure 4 As shown in FIG. 4 , the gate terminal 412 of the write transistor 410 is coupled to the write word line WWL for receiving the gate voltage V WWL , and the first terminal 414 of the write transistor 410 is coupled to the write bit line WBL for receiving a write voltage (or a read voltage) V WBL The first terminal 424 of the read transistor 420 is coupled to the read bit line RBL for receiving a read voltage V RBL , and the second terminal 426 of the read transistor 420 is coupled to the read word line RWL for receiving the write voltage (or read voltage) V RWL .

[0124] The read transistor 420 can be configured to have an adjustable threshold voltage so that the universal memory cell 400 can be used in an inference mode to set a fixed weight each time. In some embodiments, the read transistor 420 includes a charge trapping layer 423 at the gate terminal 422. The charge trapping layer 423 can be considered a charge storage layer or a charge trapping layer. According to the FN tunneling and hot carrier ejection mechanism, when a high voltage (e.g., a positive voltage similar to +FN or a negative voltage similar to -FN5) is applied to the gate terminal 422, the high voltage (e.g., +FN / -FN) can modify the amount of charge stored in the charge trapping layer 423, thereby changing the threshold voltage of the read transistor 420. The threshold voltage of the read transistor 420 can be changed according to the value of the high voltage applied to the gate terminal 422 and the length of time the high voltage is applied. Here, the threshold voltage of the read transistor 420 can be adjustable from a minimum threshold voltage V tmin To the maximum threshold voltage V tmax range (such as Figure 8B As discussed below, due to the charge trapping layer 423, the read transistor 420 can be programmed or erased to have multiple voltage Vt levels to determine corresponding logic gates and / or set multiple fixed weights (eg, digital weights or analog weights).

[0125] In some embodiments, the read transistor 420 includes a SONOS field-effect transistor (FET), whose nitride (e.g., silicon nitride (SiN) layer) is a charge trapping layer 423. In some embodiments, the write transistor 410 is a transistor without charge storage capability, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Here, the threshold voltage of the write transistor 410 is fixed and / or preset to be unchangeable. In some embodiments, the write transistor 410 also includes a charge trapping layer 413, such as Figure 4 As shown in FIG. 4 , the threshold voltage of the write transistor 410 can be adjusted according to the operation. The write transistor 410 can also be a SONOS FET.

[0126] The read transistor 420 may have a low off current to ensure good data retention. In some examples, the channel layer of the read transistor 420 includes indium gallium zinc oxide (IGZO), indium oxide (In2O3), silicon (Si), germanium (Ge), or a trivalent-pentavalent (III-V) material. In some examples, the write transistor 410 may have a high on current to ensure read accuracy. The channel layer of the write transistor 410 includes indium gallium zinc oxide (IGZO), indium oxide (In2O3), silicon (Si), germanium (Ge), or a trivalent-pentavalent material.

[0127] Figure 5A The example general purpose memory 500 is shown to include Figure 4 The universal memory 500 includes an array of universal memory cells 400. Each universal memory cell 400 includes a write transistor 410 and a read transistor 420 coupled to each other. The universal memory 500 includes one or more write word lines 512, one or more read word lines 522, one or more write bit lines 514, and one or more read bit lines 524.

[0128] In each universal memory cell 400, a gate terminal 412 of a write transistor 410 is connected to a corresponding write word line 512, a first terminal 414 (one of a drain terminal and a source terminal) of the write transistor 410 is connected to a corresponding write bit line 514, and a second terminal 416 (the other of a drain terminal and a source terminal) of the write transistor 410 is connected to a gate terminal 422 of a read transistor 420. A first terminal 424 (one of a drain terminal and a source terminal of the read transistor 420) is connected to a corresponding read bit line 524, and a second terminal 426 (the other of a drain terminal and a source terminal of the read transistor 420) is connected to a read word line 522.

[0129] Each write word line 512 is connected to a plurality of gate terminals 412 of a plurality of write transistors 410 of a plurality of corresponding universal memory cells 400 along a first direction, and each write bit line 514 is connected to a plurality of first terminals 414 of a plurality of write transistors 410 of a plurality of corresponding universal memory cells 400 along a second direction, which may be perpendicular to the first direction. Similarly, each read bit line 524 is connected to a plurality of first terminals 424 of a plurality of read transistors 420 of a plurality of corresponding universal memory cells 400 along a first direction in parallel with the write word line 512, and each read word line 522 is connected to a plurality of second terminals 426 of a plurality of read transistors 420 of a plurality of corresponding universal memory cells 400 along a second direction in parallel with the write bit line 514.

[0130] In some embodiments, the universal memory 500 includes a plurality of sense amplifiers 502 (SA). Each sense amplifier 502 is coupled to a corresponding read word line 522 and is configured to receive a sum of a plurality of read currents from a plurality of memory cells coupled to the corresponding read word line 522, for example, Figure 2 as shown in .

[0131] In some embodiments, the universal memory 500 can be applied to both the training mode and the inference mode of the AI ​​model. When the universal memory 500 is executed in the training mode, it can provide high reliability, similar to or the same as DRAM, to meet the large number of update actions on the weights. The universal memory 500 in the training mode can be implemented as Figure 3AWhen the general purpose memory 500 is executed in the inference mode, the general purpose memory 500 can provide non-volatility and high data retention, similar to or the same as NVM, so that the weights can be well maintained with low power consumption. The general purpose memory 500 in the inference mode can be implemented as Figure 3B 360 of memory.

[0132] The universal memory 500 may be used to implement one or more operations of the AI ​​model, such as a multiply-accumulate (MAC) operation. The MAC operation is based on Ohmic and Kirchoff's laws. Figure 5B The MAC operation is shown to be implemented using a general purpose memory 500. A series of input signals x i For example, voltage V1, voltage V2, and voltage Vn are applied to corresponding read bit lines RBL1, RBL2, and RBLn, respectively. The amount of read current Ii (eg, 0 or 1) from each universal memory cell 400 is equal to the input signal x i and weight w i (eg, 0 or 1). Accordingly, at each read word line 522, the total current I received by the sense amplifier 502 can be calculated according to the above formula (1):

[0133] Among them G i Corresponding to the weight w i , represents the conductivity of the read transistor 420 .

[0134] As discussed below, the weight w of the general memory cell 400 is i It can be a digital or binary weight, such as a logical 1 or a logical 0. In some cases, the weight w i The storage potential V of the storage node 402 between the write transistor 410 and the read transistor 420 may be SN Indicates, for example, Fig. 7A and Figure 7B In some cases, the weight w of the universal memory cell 400 is i It can be represented by the threshold voltage of the read transistor 420, for example Fig. 8A and Figure 8B Inference mode or NVM mode as described in .

[0135] The weight w of the general memory cell 400 i It may be an analog weight, for example represented by an adjustable threshold voltage of the read transistor 420, for example Fig. 10A and Fig. 10BIn some cases, the universal memory cell 400 can be operated with analog weights and binary (1 or 0) input signals, such as Fig. 10A In some cases, the universal memory cell 400 can be operated with analog weights and analog input signals, such as Fig. 10B in the triode region shown in .

[0136] Figure 6 A flowchart of an example process 600 for operating a general purpose memory, such as for training and reasoning of an AI model, is shown. The general purpose memory may be Figure 5A and Figure 5B The universal memory 500 in the embodiment of the present invention comprises universal memory units (e.g. Figure 4 Each universal memory cell includes a write transistor (e.g. Figure 4 The write transistor 410) and the read transistor (eg Figure 4 As mentioned above, in the training mode 610, the universal memory (and the universal memory cell) is used to operate in the DRAM mode or the DRAM-like mode; in the inference mode 620, the universal memory (and the universal memory cell) is used to operate in the NVM mode or the NVM-like mode.

[0137] like Figure 6 As shown in FIG. 6 , the training mode 610 includes a weight modification step 612, a weight storage step 614, and a read operation step 616. The weight modification step 612 is used to modify the weight w i (For example Figure 2 The conductivity G i or Figure 3A The conductivity G ij ). The weight saving step 614 is used to temporarily keep the weight w i The read operation step 616 is used to read the weight w i In the training mode 610, the weight modification step 612, the weight storage step 614 and the read operation step 616 may be repeatedly performed to continuously adjust the weight w i To optimize the AI ​​model.

[0138] like Figure 6 As shown in FIG. 6 , the inference mode 620 includes a weight setting step 622, a weight saving step 624, and a read operation step 626. The weight setting step 622 is used to set the fixed weight w according to the training mode 610. i The weight saving step 624 is used to maintain the weight w iThe read operation step 626 is used to read the weight w i and perform a product operation (e.g., a MAC operation) at the same time. In inference mode 620, the weight w i Is fixed and usually does not change.

[0139] Next, the operations of the write transistor and the read transistor of the universal memory cell of the universal memory in the training mode 610 (or DRAM mode) are respectively corresponding to Fig. 7A and Figure 7B For purposes of illustration, a universal memory, a universal memory cell, a write transistor, and a read transistor are illustrated corresponding to the universal memory 500, the universal memory cell 400, the write transistor 410, and the read transistor 420, respectively.

[0140] Fig. 7A Graph 700 shows a characteristic curve of the write transistor 410 in the training mode 610 or DRAM mode. Fig. 7A As shown in WWL is applied to the gate terminal 412 of the write transistor 410, the write transistor 410 may be turned off, for example, during the weight saving step 614 and the read operation step 616. WWL is applied to the gate terminal 412 of the write transistor 410, the write transistor 410 may be turned on, for example during the weight change step 612, and a voltage may be applied to the first terminal 414 of the write transistor 410 to charge or discharge the storage node 402 coupled between the second terminal 416 of the write transistor 410 and the gate terminal 422 of the read transistor 420.

[0141] Figure 7B A characteristic curve graph 710 of the read transistor 420 in the training mode 610 or DRAM mode is shown. In the training mode 610, the charge trapping layer 423 of the read transistor 420 remains unchanged, so that the threshold voltage Vt of the read transistor 420 remains unchanged. When the gate terminal 422 of the read transistor 420 has a higher storage voltage Vt than the threshold voltage Vt, the charge trapping layer 423 of the read transistor 420 remains unchanged. SN When the gate terminal 422 of the read transistor 420 has a lower storage voltage Vt than the threshold voltage Vt, the read transistor 420 can be turned on. SN When , the read transistor 420 can be turned off.

[0142] In the training mode 610, a high voltage signal (eg, V RBL) may be applied to the first terminal 424 of the read transistor 420, and a low voltage signal (e.g., VSS) or ground (e.g., 0) may be applied to the second terminal 426 of the read transistor 420. When the read transistor 420 is turned on, the logic state of the stored data in the storage node 402 may be read as a bit logic 1. When the read transistor 420 is turned off, the logic state of the stored data in the storage node 402 may be read as a bit logic 0. Therefore, in the training mode 610, the storage node 402 may be immediately charged or discharged to a higher storage potential or a lower storage potential to further determine the logic state of the read data that can be used as the weight value of the universal memory cell 400. Even, the charge capture layer 423 of the read transistor 420 remains unchanged. Therefore, the universal memory cell 400 may have high durability (e.g., nearly infinite durability), which is suitable for training AI models.

[0143] The weight w corresponding to logic 0 and logic 1 i The operation of the universal memory unit 400 in the training mode 610 is described in more detail below. In the training mode 610, the weights w i is stored in the storage node 402 between the write transistor 410 and the read transistor 420 .

[0144] When the universal memory cell 400 is to be written with a weight w of logic 0 during the weight modification step 612 of the training mode 610 i When the write word line WWL is applied with a higher voltage V WWL (e.g., 3V) to turn on the write transistor 410, and the write bit line WBL is applied to a lower bias voltage V WBL0 (eg, 0V). Since the write transistor 410 is turned on, the voltage V inputted from the write bit line WBL is WBL can be input to the storage node 402, so that the storage node 402 has a storage potential V SN0 (eg, 0V), which is lower than the threshold voltage Vt of the read transistor 420. The storage potential V SN0 The weight w of the logic 0 of the general memory cell 400 may be represented by i .

[0145] During the weight saving step 614 of the training mode 610, the universal memory unit 400 intentionally temporarily saves the weight w during the training mode 610. i , the lower voltage V WWL (eg, 0V) is applied to the write word line WWL to turn off the write transistor 410. Since the write transistor 410 is turned off, the storage potential V SN0 Keep it unchanged.

[0146] During the read operation step 616 of the training mode 610, when the weight w of the universal memory cell 400 is i To be read and then multiplied, the write word line WWL is applied to a lower voltage V WWL (eg, 0V) to turn off the write transistor 410, and the read bit line RBL is applied with the input voltage signal Vi (eg, 0.8V). i The storage potential V SN Below the threshold voltage Vt of the read transistor 420, the read transistor 420 is turned off and no read current Ii is generated on the read bit line RBL. The amount of the read current Ii (eg, 0) is equal to the weight w of the input signal Vi and logic 0. i The product of .

[0147] When the universal memory cell 400 is written with a weight w of logic 1 during the weight modification step 612 of the training mode 610 i When the write word line WWL is applied with a higher voltage V WWL (e.g., 3V) to turn on the write transistor 410, and the write bit line WBL is applied with a high voltage V WBL (eg, 1V). Since the write transistor 410 is turned on, the voltage V inputted by the write bit line WBL WBL can be input to the storage node 402, so that the storage node 402 has a storage potential V SN1 (eg, 1V), which is higher than the threshold voltage Vt of the read transistor 420. The storage potential V SN1 The weight w of the logic 1 of the general memory cell 400 may be represented by i As described above, in the weight modification step 612 of the training mode 610, when the weight w i When t is changed, the threshold voltage Vt of the read transistor 420 does not change.

[0148] During the weight saving step 614 of the training mode 610, the universal memory unit 400 intentionally temporarily saves the weight w during the training mode 610. i , the lower voltage V WWL (eg, 0V) is applied to the write word line WWL to turn off the write transistor 410. Since the write transistor 410 is turned off, the storage potential V SN1 Keep it unchanged.

[0149] During the read operation step 616 of the training mode 610, when the weight w of the universal memory cell 400 is i To be read and then multiplied, the write word line WWL is applied to a lower voltage V WWL(eg, 0V) to turn off the write transistor 410, and the read bit line RBL is applied to the input voltage signal V i (For example, 0.8V). SN When the voltage Vt is higher than the threshold voltage Vt of the read transistor 420, the read transistor 420 is turned on and a read current Ii is generated on the read bit line RBL. The amount of the read current Ii (eg, 0) is equal to the input signal V i and the weight W of logical 1 i The product of .

[0150] The above operations of the general memory cell 400 in the training mode 610 or the DRAM mode can be summarized as shown in Table 1. It should be noted that Table 1 only shows examples of multiple values ​​and is not intended to limit the present disclosure.

[0151] Table 1: Multiple values ​​for DRAM mode operation

[0152] Write logic 0 Write logic 1 Keep Read <![CDATA[V WWL ]]> 3V 3V 0V 0V <![CDATA[V WBL ]]> 0V 1V Don't care 0V <![CDATA[V RWL ]]> 0V 0V 0V 0V <![CDATA[V RBL ]]> 0V 0V 0V 0.8V

[0153] Next, the operations of the write transistor and the read transistor of the universal memory cell of the universal memory in the inference mode 620 (or NVM mode) are respectively corresponding to Fig. 8A and Figure 8B For purposes of illustration, a universal memory, a universal memory cell, a write transistor, and a read transistor are illustrated corresponding to the universal memory 500, the universal memory cell 400, the write transistor 410, and the read transistor 420, respectively.

[0154] In the inference mode 620 or NVM mode, a high voltage (e.g., +FN / -FN) may be applied to the gate terminal 422 of the read transistor 420 to charge or discharge the charge trapping layer 423 of the read transistor 420, thereby changing the threshold voltage Vt of the read transistor 420. The threshold voltage Vt may be fixed, for example, for long-term data retention, to set a specific weight value in the general memory cell 400, which may be applied in the inference mode 620 of the AI ​​model. By applying a high voltage (e.g., +FN / -FN) to the gate terminal 422 of the read transistor 420 to change the threshold voltage Vt, the weight value may be reset, for example, based on the value of the high voltage and the length of time the high voltage is applied.

[0155] Fig. 8A A characteristic curve graph 800 of the write transistor 410 in the inference mode 620 or NVM mode is shown. Fig. 8A As shown in WWL is applied to the gate terminal 412 of the write transistor 410, the write transistor 410 can be turned off. WWLis applied to the gate terminal 412 of the write transistor 410, the write transistor 410 can be turned on. During the weight setting step 622 of the inference mode 620, the FN high voltage (e.g., +FN / -FN such as +20V / -20V) is applied to the first terminal 414 of the write transistor 410, so that the storage potential at the storage node 402 can be charged or discharged to a voltage corresponding to (or the same as) the high voltage (e.g., +FN / -FN). The voltage at the gate terminal 422 of the read transistor 420 is the same as the storage potential V of the storage node 402. SN Therefore, the FN high voltage can change the threshold voltage Vt of the read transistor 420. During the read operation step 626 of the inference mode 620, the read voltage V read (eg, 0.8 V) is applied to the first terminal 414 of the write transistor 410, which can be used as an input signal for a general purpose memory cell 400, such as described in more detail in FIG. 10 .

[0156] Figure 8B Graph 810 of characteristic curves of read transistor 420 in inference mode 620 or NVM mode is shown. Each characteristic curve corresponds to a threshold voltage Vt of read transistor 420, such as the characteristic curve of read transistor 420 in graph 710. As mentioned above, by applying a high voltage (e.g., +FN / -FN) to the write bit line, the threshold voltage Vt can be set. The value of the threshold voltage Vt can be based on the amount of charge in the charge trapping layer 423 of the read transistor 420, and the amount of charge depends on the value of the high voltage and the length of time the high voltage is applied. Therefore, the value of the threshold voltage Vt can be adjustable, such as at a minimum threshold voltage Vt. tmin With the maximum threshold voltage V tmax Between Figure 8B as shown in .

[0157] During the weight setting step 622, after the threshold voltage Vt is set, the voltage V read (e.g., 0.8V) is applied to the first terminal 414 of the write transistor 410, which can charge the storage node 402 to the high storage voltage V SN . It is equivalent to the storage voltage V SN The read transistor 420 may be turned on and the supply voltage V applied to the first terminal 424 of the read transistor 420 is higher than the set threshold voltage Vt. dd A higher current Ii can be generated, corresponding to data logic 1. When the storage voltage V SN Below the set threshold voltage Vt, the read transistor 420 can be turned off, corresponding to data logic 0. The read voltage V applied to the write bit line WBL read The minimum threshold voltage Vtmin With the maximum threshold voltage V tmax Therefore, in the inference model 620, the weight w of the universal memory unit 400 is i It is represented by the set threshold voltage Vt of the read transistor 420.

[0158] The weight w corresponding to logic 0 and logic 1 i The operation of the universal memory cell 400 in the inference mode 620 is described in more detail below. The read transistor 420 includes a charge trapping layer 423 that can be charged or discharged to adjust the threshold voltage Vt of the read transistor 420 .

[0159] When the universal memory cell 400 is written with a weight w of logic 0 during the weight setting step 622 of the inference mode 620 i When the write word line WWL is applied with a voltage V ON (e.g., 1V) higher than the threshold voltage of the write transistor 410 to turn on the write transistor 410, and the write bit line WBL is applied with a positive high FN voltage (e.g., +FN). Since the write transistor 410 is turned on, the positive high FN voltage inputted from the write bit line WBL can be inputted to the storage node 402, so that the storage node 402 has a high storage potential V SN0 (e.g., +FN), which can charge the charge trapping layer 423 of the read transistor 420 to change the threshold voltage Vt of the read transistor 420, such as increasing it to a higher Vt. The higher Vt of the read transistor 420 can represent a weight w of logic 0 for the universal memory cell 400. i .

[0160] During the weight saving step 624 of the inference mode 620, the universal memory unit 400 intentionally fixes the weight w during the inference mode 620. i , the lower voltage V WWL (eg, 0 V) ​​is applied to the write word line WWL to turn off the write transistor 410 .

[0161] During the read operation step 626 of the inference mode 620, when the weight w of the universal memory cell 400 i To be read and then multiplied, the write word line WWL is applied to a lower voltage V WWL (e.g., 0V) to turn off the write transistor 410, and the read bit line RBL is applied with a voltage V ON (eg, 1V) is higher than the threshold voltage of the write transistor 410 to turn on the write transistor 410, and the read bit line RBL is applied with an input voltage signal Vi (eg, V DD ). The write bit line WBL is applied with a read voltage V read(eg, 1V). Since the read transistor 420 is set to have a higher Vt, it can be higher than the read voltage V read , the read transistor 420 is turned off, and no read current Ii is generated on the read bit line RBL. The amount of the read current Ii (eg, 0) is equal to the weight w of the input signal Vi and the logic 0. i The product of .

[0162] When the universal memory cell 400 is written with a weight w of logic 1 during the weight setting step 622 of the inference mode 620 i When the write word line WWL is applied with a voltage V ON The write transistor 410 is turned on by a voltage higher than the threshold voltage of the write transistor 410, and the write bit line WBL is applied with a negative high FN voltage (e.g. -FN). Since the write transistor 410 is turned on, the negative high FN voltage inputted from the write bit line WBL can be inputted to the storage node 402, so that the storage node 402 has a negative high storage potential V SN1 (e.g., -FN), which can discharge the charge trapping layer 423 of the read transistor 420 to change the threshold voltage Vt of the read transistor 420, such as to reduce it to a lower Vt. The lower Vt of the read transistor 420 can represent a weight w of the logic 1 of the universal memory cell 400. i .

[0163] During the weight saving step 624 of the inference mode 620, the universal memory unit 400 intentionally fixes the weight w during the inference mode 620. i , the lower voltage V WWL (eg, 0 V) ​​is applied to the write word line WWL to turn off the write transistor 410 .

[0164] During the read operation step 626 of the inference mode 620, when the weight w of the universal memory cell 400 i To be read and then multiplied, the write word line WWL is applied with a voltage V ON (eg, 1V) is higher than the threshold voltage of the write transistor 410 to turn on the write transistor 410, and the read bit line RBL is applied with the input voltage signal Vi (eg, V DD ). The write bit line WBL is applied with a read voltage V read (eg, 1V). Since the read transistor 420 is set to have a lower Vt, it may be lower than the read voltage V read , the read transistor 420 is turned on, and a read current Ii is generated on the read bit line RBL. The amount of the read current Ii is equal to the input signal Vj and the weight w of the logic 1. i The product of .

[0165] The above operations of the general memory cell 400 in the inference mode 620 or the NVM mode can be summarized as the following Table 2. It should be noted that Table 2 only shows examples of multiple values ​​and is not intended to limit the present disclosure. It should be noted that the read voltage V applied to the write bit line WBL is read is the minimum threshold voltage V of the read transistor 420 tmin With the maximum threshold voltage V tmax between.

[0166] Table 2: Multiple values ​​for NVM mode operation

[0167] Write logic 0 Write logic 1 Keep Read <![CDATA[V WWL ]]> <![CDATA[V ON ]]> <![CDATA[V ON ]]> 0V <![CDATA[V ON ]]> <![CDATA[V WBL ]]> +FN -FN Don't care <![CDATA[V read ]]> <![CDATA[V RWL ]]> 0V 0V 0V 0V <![CDATA[V RBL ]]> 0V 0V 0V <![CDATA[V DD ]]>

[0168] The universal memory 500 can be used to implement one or more operations of the AI ​​model, such as a multiply-accumulate (MAC) operation. The MAC operation is based on Ohmic and Kirchoff's laws. Figure 5B As shown in FIG. 6 , in the inference mode 620 , a series of input voltages V1 , V2 , and Vn are applied to the corresponding read bit lines RBL1 , RBL2 , and RBLn, respectively. As mentioned above, the weight w for each universal memory cell 400 is i The value is represented by the threshold voltage Vt of the read transistor 420 of the universal memory cell 400. The amount (eg, 0 or 1) of the read current Ii from each universal memory cell 400 is equal to the input signal Vi and the weight w i (eg, 0 or 1). Accordingly, at each read word line 522, the total current I received by the sense amplifier 502 can be calculated according to the above formula (1): Among them G i Corresponding to the threshold voltage Vt or weight w of the read transistor 420 i , represents the conductivity of the read transistor 420 .

[0169] The above weight w i The two bit values ​​taken from logic 0 and logic 1 are described as an example. In some embodiments, the weight w i may also be analog values. As discussed in more detail below, read transistor 420 may be operated in a triode region or a saturation region. Universal memory cell 400 may be operated with analog weights and a binary (1 or 0) input signal, such as in a saturation region, or with analog weights and an analog input signal, such as in a triode region.

[0170] Fig. 9 Graph 900 shows the relationship between the current and voltage on the read bit line RBL. The current-voltage curve CVi corresponds to different gate overdrive voltages Vd . Gate overvoltage drive voltage V d is the storage potential V SN The voltage difference between the threshold voltage Vt of the read transistor 420. Corresponding to different threshold voltages Vt, the overvoltage driving voltage V d Can be formed to varying degrees. Fig. 9 The upper curve CV i Corresponding to a higher overvoltage drive voltage V d The current formed on the read bit line RBL is positively correlated with the overvoltage drive voltage V d , for example d ∝(V N -V t ). Here, when V SN The current formed on the read bit line RBL is negatively correlated with the threshold voltage Vt. Therefore, the multiple levels of the threshold voltage Vt of the read transistor 420 may result in a weight w i Different levels with analog values.

[0171] Based on the voltage of the gate terminal 422 of the read transistor 420 (eg, V SN ) and the saturation voltage VSAT, the current-voltage curve CV i can be divided. When V SN Greater than V SAT , the read transistor 420 is operated in the saturation region, and the universal memory cell 400 can be connected with the analog weight Wi and binary (1 or 0) input signal operations, such as Fig. 10A As shown in V SN is less than VSAT, the read transistor 420 is operated in the triode region, and the universal memory cell 400 can be operated with analog weights and analog input signals, such as Fig. 10B as shown in .

[0172] Fig. 10A Example operation is shown in the saturation region of the read transistor 420, for example, at V SN The threshold voltage Vt of the read transistor 420 can be analog, and the voltage V RBL The input signal is applied to the read bit line RBL and can have a bit value of logic 1 or logic 0. When the voltage V RBL Corresponding to a logic 0, for example 0V, no current is formed. RBL Corresponding to the logic 1 bit, the current is formed and at (V sN -Vt). To ensure a logic 1 input, the voltage V RBL Not less than (V SN-Vt). When V applied to the write bit line WBL SN Equal to V WBL , which can be kept constant, (V SN -Vt) is equal to the maximum value of (V SN -V tmin ) maximum value, where V tmin The minimum threshold voltage of the transistor 420 is read in the saturation region, for example Fig. 10A as shown in .

[0173] The operation of the general memory cell 400 in the inference mode 620 or NVM mode and the saturation region of the read transistor 420 can be summarized as shown in Table 3. It should be noted that Table 3 only shows examples of multiple values ​​and is not intended to limit the present disclosure.

[0174] Table 3: Multiple values ​​for NVM mode operation in the saturation region

[0175]

[0176] As shown in Table 3, during the weight setting step 622 of the inference mode 620, as Vt rises, the write transistor 410 increases with the voltage V ON is turned on, the voltage V ON Higher than the threshold voltage of write transistor 410 applied to write word line WWL. In some cases, a positive high FN voltage (e.g., +FN) is applied to write bit line WBL, V applied to read word line RWL and read bit line RBL. RWL and V RBL Both are equal to 0V, so the storage potential at storage node 402 is increased to a positive high FN voltage, which can charge the charge trapping layer 423 of the read transistor 420 to increase the threshold voltage Vt of the read transistor 420. In some cases, a low voltage (e.g., 0) is applied to the write bit line WBL (V WBL =0V), V applied to the read word line RWL and the read bit line RBL RWL and V RBL Both are equal to −FN, and the voltage potential between the gate terminal 422 and the second terminal 426 is +FN, which can also charge the charge trapping layer 423 of the read transistor 420 to increase the threshold voltage Vt of the read transistor 420 .

[0177] Similarly, during the weight setting step 622 of the inference mode 620, as Vt decreases, the write transistor 410 decreases with the voltage V ON is turned on, the voltage V ONHigher than the threshold voltage of write transistor 410 applied to write word line WWL. In some cases, a negative high FN voltage (e.g., -FN) is applied to write bit line WBL, V applied to read word line RWL and read bit line RBL. RWL and V RBL Both are equal to 0V, so the storage potential at the storage node 402 is reduced to a negative high FN voltage (e.g., -FN), which can discharge the charge trapping layer 423 of the read transistor 420 to reduce the threshold voltage Vt of the read transistor 420. In some cases, a low voltage (e.g., 0) is applied to the write bit line WBL (V WBL =0V), V applied to the read word line RWL and the read bit line RBL RWL and V RBL Both are equal to +FN, and the voltage potential between the first terminal 424 and the gate terminal 422 is +FN, which can also discharge the charge trapping layer 423 of the read transistor 420 to reduce the threshold voltage Vt of the read transistor 420 .

[0178] During the weight saving step 624 of the inference mode 620, V WWL = 0V to turn off the write transistor 410, V WBL Can be any value, such as 0V. RWL and V RBL It can also be equal to 0V, so no current is formed, and the threshold voltage Vt of the read transistor 420 remains unchanged and can be fixed for a long time to determine a specific weight value of the universal memory cell 400.

[0179] During the read operation step 626 of the inference mode 620, the write transistor 410 is driven by the voltage V ON is turned on, the voltage V ON Higher than the threshold voltage of the write transistor 410 applied to the write word line WWL. The read voltage V WBL is applied to the write bit line WBL, which may be no greater than the supply voltage V DD The second terminal 426 of the read transistor 420 is coupled to ground, for example, 0V, and the first terminal 424 of the read transistor 420 is applied to the input signal V RBL , which is greater than V dd -V tmin This ensures that the read transistor 420 operates in the saturation region.

[0180] The universal memory 500 may be used to implement one or more operations of the AI ​​model, such as a multiply-accumulate (MAC) operation. The MAC operation is based on Ohmic and Kirchoff's laws. Figure 5BAs shown in FIG. 6 , in the inference mode 620 , a series of input voltages V1 , V2 , and Vn are applied to the corresponding read bit lines RBL1 , RBL2 , and RBLn , respectively. As mentioned above, the weights w for each universal memory cell 400 are simulated. i The threshold voltage Vt of the read transistor 420 of the universal memory cell 400 is represented by the value of the read current Ii (eg, 0 or 1) from each universal memory cell 400, which is equal to the input signal Vi (eg, 0 or 1) and the analog weight w i Therefore, at each read word line 522, the total current I received by the sense amplifier 502 can be calculated according to the above formula (1): Where V SN To keep constant, (V SN -V t ) corresponds to the simulated weight w of the general memory cell 400 i .

[0181] Fig. 10B Example operation is shown in the triode region of the read transistor 420, for example, at V SN The threshold voltage Vt of the read transistor 420 can be analog, and multiple Vt can be used as multiple analog weights. RBL The input signal is applied to the read bit line RBL and meets the requirements to ensure that the read transistor 420 is in the triode region. Therefore, the voltage V RBL The analog input range is 0 <= V RBL <=V SN -V tmax , for example Fig. 10B as shown in .

[0182] The operation of the general memory cell 400 in the inference mode 620 or NVM mode and the triode region of the read transistor 420 can be summarized as shown in Table 4. It should be noted that Table 4 only shows examples of values ​​and is not intended to limit the present disclosure.

[0183] Table 4 Multiple values ​​in the transistor region for NVM mode operation

[0184]

[0185] As shown in Table 4, during the weight setting step 622 of the inference mode 620, as Vt rises, the write transistor 410 increases with the voltage V ON is turned on, the voltage V ONHigher than the threshold voltage of write transistor 410 applied to write word line WWL. In some cases, a positive high FN voltage (e.g., +FN) is applied to write bit line WBL, V applied to read word line RWL and read bit line RBL. RWL and V RBL Both are equal to 0V, so the storage potential at storage node 402 is increased to a positive high FN voltage, which can charge the charge trapping layer 423 of the read transistor 420 to increase the threshold voltage Vt of the read transistor 420. In some cases, a low voltage (e.g., 0) is applied to the write bit line WBL (V WBL =0V), V applied to the read word line RWL and the read bit line RBL RWL and V RBL Both are equal to −FN, and the voltage potential between the gate terminal 422 and the second terminal 426 is +FN, which can also charge the charge trapping layer 423 of the read transistor 420 to increase the threshold voltage Vt of the read transistor 420 .

[0186] Similarly, during the weight setting step 622 of the inference mode 620, as Vt decreases, the write transistor 410 decreases with the voltage V ON is turned on, the voltage V ON Higher than the threshold voltage of write transistor 410 applied to write word line WWL. In some cases, a negative high FN voltage (e.g., -FN) is applied to write bit line WBL, V applied to read word line RWL and read bit line RBL. RWL and V RBL Both are equal to 0V, so the storage potential at the storage node 402 is reduced to a negative high FN voltage (e.g., -FN), which can discharge the charge trapping layer 423 of the read transistor 420 to reduce the threshold voltage Vt of the read transistor 420. In some cases, a low voltage (e.g., 0) is applied to the write bit line WBL (V WBL =0V), V applied to the read word line RWL and the read bit line RBL RWL and V RBL Both are equal to +FN, and the voltage potential between the first terminal 424 and the gate terminal 422 is +FN, which can also discharge the charge trapping layer 423 of the read transistor 420 to reduce the threshold voltage Vt of the read transistor 420 .

[0187] During the weight saving step 624 of the inference mode 620, V WWL = 0V to turn off the write transistor 410, V WBL Can be any value, such as 0V. RWL and V RBLIt can also be equal to 0V, so no current is formed, and the analog threshold voltage Vt of the read transistor 420 remains unchanged and can be fixed for a long time to determine the specific weight value of the universal memory cell 400.

[0188] During the read operation step 626 of the inference mode 620, the write transistor 410 is driven by the voltage V ON is turned on, the voltage V ON Higher than the threshold voltage of the write transistor 410 applied to the write word line WWL. The read voltage V WBL is applied to the write bit line WBL, which may be no greater than the supply voltage V DD The second terminal 426 of the read transistor 420 is coupled to ground, for example, 0V, and the first terminal 424 of the read transistor 420 is applied to the input signal V RBL , which is less than V dd -V tmax This ensures that the read transistor 420 operates in the triode region.

[0189] The universal memory 500 may be used to implement one or more operations of the AI ​​model, such as a multiply-accumulate (MAC) operation. The MAC operation is based on Ohmic and Kirchoff's laws. Figure 5B As shown in FIG. 6 , in the inference mode 620 , a series of input voltages V1 , V2 , and Vn are applied to the corresponding read bit lines RBL1 , RBL2 , and RBLn , respectively. As mentioned above, the weights w for each universal memory cell 400 are simulated. i The threshold voltage Vt of the read transistor 420 of the universal memory cell 400 is represented by the read current Ii from each universal memory cell 400. The amount of the read current Ii is equal to the analog input signal Vi (e.g., between 0 and V dd -V tmax range) and the simulation weight w i Therefore, at each read word line 522, the total current I received by the sense amplifier 502 can be calculated according to the above formula (1): Where V SN To keep constant, (V SN -V t ) corresponds to the simulated weight w of the general memory cell 400 i , and Vi is the analog input signal.

[0190] The present disclosure and other examples may be implemented as one or more computer program products, for example, one or more modules of computer program instructions encoded on a computer-readable medium that are executed by a data processing device or control the operation of the data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or one or more combinations thereof. The term "data processing device" includes all devices, equipment, and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, this device may include program code that establishes the execution environment of the computer program in question, such as program code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0191] The system may include all devices, equipment and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. In addition to hardware, the system may include program code that establishes the execution environment of the computer program in question, for example, program code constituting processor firmware, protocol stack, database management system, operating system or one or more combinations thereof.

[0192] A computer program (also referred to as a program, software, software application, instruction code, or program code) may be written in any form of programming language, including compiled or interpreted languages, and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored as part of a file that stores other programs or data (e.g., one or more instruction codes stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or portions of program code). A computer program may be configured to execute on one computer or on multiple computers. The multiple computers may be located at one location or distributed across multiple locations and interconnected by a communications network.

[0193] The procedures and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The procedures and logic flows may also be performed by special purpose logic circuitry, and the apparatus may also be implemented by special purpose logic circuitry, for example, a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0194] Processors suitable for executing computer programs include, for example, both general-purpose microprocessors and special-purpose microprocessors, and any one or more processors of any type of digital computer. Generally speaking, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer may also include or be operably coupled to one or more mass storage devices for storing data to receive data from the one or more mass storage devices, or to transmit data to the one or more mass storage devices, or both. Examples of the one or more mass storage devices are magnetic disks, magneto-optical disks, or optical disks. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data may include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks. The processor and memory may be supplemented by or incorporated into a dedicated logic circuit.

[0195] Although many details may be described herein, these details should not be interpreted as limitations on the claimed or claimable scope of the present invention, but rather as descriptions of features for specific embodiments. Certain features described herein in separate multiple embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination. Furthermore, although multiple features may be described above as acting in certain combinations and even initially claimed as such, one or more features from the claimed combination may be excluded from the combination in some cases, and the claimed combination may be for sub-combinations or variations of sub-combinations. Similarly, although multiple operations are depicted in a particular order in the accompanying drawings, it should not be understood that these operations must be performed in the particular order shown or in a sequential order, or that all described operations must be performed to achieve the desired result.

[0196] Only a few examples and implementations are described. Variations, modifications, and enhancements based on the examples and implementations and other implementations may be accomplished based on what is disclosed.

[0197] In summary, although the present invention has been disclosed above with preferred embodiments and exemplary details, it is to be understood that these examples are intended to illustrate rather than to limit the present invention. Those skilled in the art of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended claims.

Claims

1. A semiconductor circuit comprising: a first transistor; as well as a second transistor, The first transistor has a gate terminal for receiving a gate voltage to turn on or off the first transistor, a first terminal for receiving a write voltage, and a second terminal coupled to a gate terminal of the second transistor, and The second transistor includes a charge trapping layer at the gate terminal of the second transistor, and the charge trapping layer is used for: When a first write voltage is applied to the first terminal of the first transistor, it is not variable, and When a second write voltage is applied to the first terminal of the first transistor, it can be changed to modify a threshold voltage of the second transistor, and the second write voltage is greater than the first write voltage.

2. The semiconductor circuit according to claim 1, wherein the semiconductor circuit is used for: Operates in a first mode, wherein According to the first write voltage applied to the first terminal of the first transistor when the first transistor is turned on, a storage potential of a storage node between the second terminal of the first transistor and the gate terminal of the second transistor is determined, the threshold voltage of the second transistor is kept unchanged, and the storage potential of the storage node is repeatedly variable according to the first write voltage, and The second transistor is operated in a second mode, wherein, according to the second write voltage applied to the first terminal of the first transistor when the first transistor is turned on, the second transistor is programmed or erased to have a specific threshold voltage, and the specific threshold voltage is adjustable according to the second write voltage.

3. The semiconductor circuit according to claim 2, wherein the first mode comprises a training mode of an artificial intelligence (AI) model or a type of dynamic random access memory (DRAM) mode, and the second mode comprises an inference mode of the AI ​​model or a type of non-volatile memory (NVM) mode. 4 . The semiconductor circuit according to claim 2 , wherein the storage potential of the storage node corresponds to an adjustable weight in the first mode, and the specific threshold voltage of the second transistor corresponds to a fixed weight in the second mode. 5 . The semiconductor circuit of claim 2 , wherein the specific threshold voltage of the second transistor corresponds to a binary weighted logic 1 or a binary weighted logic 0 in the second mode. 6 . The semiconductor circuit according to claim 2 , wherein the specific threshold voltage of the second transistor corresponds to an analog weight in the second mode, and the specific threshold voltage is adjustable between a minimum threshold voltage and a maximum threshold voltage.

7. The semiconductor circuit according to claim 6, wherein the second transistor is operable to be operated in a saturation region, and the storage potential of the storage node in the second mode is greater than a saturation voltage associated with the second transistor, and in, The second transistor is used to receive a binary input signal at the first terminal of the second transistor, wherein if the binary input signal has a voltage greater than a voltage difference between the storage potential of the storage node and the minimum threshold voltage, the binary input signal is represented as a logic 1, and if the binary input signal has a voltage equal to 0V, the binary input signal is represented as a logic 0.

8. The semiconductor circuit of claim 6, wherein the second transistor is operable in a triode region, and the storage potential of the storage node in the second mode is less than a saturation voltage associated with the second transistor, and in, The second transistor is used for receiving an analog input signal at the first terminal of the second transistor, wherein the analog input signal has a voltage in a range from 0V to a voltage difference between the storage potential of the storage node and the maximum threshold voltage.

9. The semiconductor circuit of claim 6, wherein the second transistor comprises a silicon-oxide-nitride-oxide-silicon SONOS transistor, and The first transistor includes a metal oxide semiconductor (MOS) transistor or a SONOS transistor.

10. A semiconductor device comprising: an array of a plurality of memory cells; one or more write word lines; one or more write bit lines; one or more read word lines; as well as one or more read bit lines; Each memory cell of the array of memory cells comprises: a write transistor; and A read transistor, wherein the write transistor includes a gate terminal coupled to a corresponding write word line, a first terminal coupled to a corresponding write bit line, and a second terminal coupled to a gate terminal of the read transistor, and wherein the read transistor includes a first terminal coupled to a corresponding read bit line and a second terminal coupled to a corresponding read word line, and The read transistor includes a charge trapping layer at the gate terminal of the read transistor, and the charge trapping layer is used for: is not variable when a first write voltage is applied to the first terminal of the write transistor through the corresponding write bit line, and A second write voltage is applied to the first terminal of the write transistor through the corresponding write bit line and is variable to change a threshold voltage of the read transistor, the second write voltage being greater than the first write voltage.

11. The semiconductor device according to claim 10, wherein the array of memory cells is arranged in a region defined by a first direction and a second direction perpendicular to the first direction, and in: Each of the one or more write word lines is coupled to a plurality of gate terminals of a plurality of write transistors of a plurality of first memory cells along the first direction, Each of the one or more write bit lines is coupled to a plurality of first terminals of a plurality of write transistors of a plurality of second memory cells along the second direction, Each of the one or more read bit lines is coupled to a plurality of first terminals of a plurality of read transistors of a plurality of third memory cells along the first direction, and Each of the one or more read word lines is coupled to a plurality of second terminals of a plurality of read transistors of a plurality of fourth memory cells along the second direction.

12. The semiconductor device according to claim 10, wherein the memory cell is used for: Operates in a first mode, wherein According to a first write voltage applied to the first terminal of the write transistor when the write transistor is turned on by applying a gate voltage to the gate terminal of the write transistor, a storage potential of a storage node between the second terminal of the write transistor and the gate terminal of the read transistor is determined, the threshold voltage of the read transistor is kept unchanged, and the storage potential of the storage node is repeatedly variable according to the first write voltage, and Operating in a second mode, wherein, according to the second write voltage applied to the first terminal of the write transistor when the write transistor is turned on, the read transistor is programmed or erased to have a specific threshold voltage, the specific threshold voltage being adjustable according to the second write voltage. 13 . The semiconductor device according to claim 12 , wherein the first mode comprises a training mode of an AI model or a DRAM-like mode, and the second mode comprises an inference mode of the AI ​​model or a NVM-like mode. 14 . The semiconductor device according to claim 13 , wherein the storage potential of the storage node corresponds to an adjustable weight in the training mode, and the specific threshold voltage of the read transistor corresponds to a fixed weight in the inference mode. 15 . The semiconductor device of claim 14 , wherein the specific threshold voltage of the read transistor corresponds to a binary weighted logic 1 or a binary weighted logic 0 in the inference mode. 16 . The semiconductor device according to claim 14 , wherein the specific threshold voltage of the read transistor corresponds to an analog weight in the inference mode, and the specific threshold voltage is adjustable between a minimum threshold voltage and a maximum threshold voltage.

17. The semiconductor device according to claim 16, wherein the read transistor is operable in a saturation region, and the storage potential of the storage node in the inference mode is greater than a saturation voltage associated with the read transistor, and in, The read transistor is used to receive a binary input signal at the first terminal of the read transistor through a corresponding read bit line, wherein if the binary input signal has a voltage greater than a voltage difference between the storage potential of the storage node and the minimum threshold voltage, the binary input signal is represented as a logic 1, and if the binary input signal has a voltage equal to 0V, the binary input signal is represented as a logic 0.

18. The semiconductor device of claim 16, wherein the read transistor is operable in a triode region, and the storage potential of the storage node is less than a saturation voltage associated with the read transistor in the inference mode, and in, The read transistor is used to receive an analog input signal at the first terminal of the read transistor through a corresponding read bit line, wherein the analog input signal has a voltage ranging from 0V to a voltage difference between the storage potential of the storage node and the maximum threshold voltage.

19. The semiconductor device according to claim 12, wherein the semiconductor device is used to perform a multiplication-accumulation operation using the array of memory cells, The semiconductor device further includes a sense amplifier coupled to a corresponding read word line, wherein the corresponding read word line is coupled to a plurality of second terminals of a plurality of read transistors of a plurality of corresponding memory cells, The sense amplifier is used to receive a summed current I from the corresponding read word line, and The formula for the total current I is I = ∑ i (w i × i )=∑ i (G i ×V i ), where x i represents an input signal received by a memory cell i of these corresponding memory cells, G i represents a conductivity of the read transistor of the memory cell i and V i represents an input voltage at the first terminal of the read transistor of the memory cell i through a corresponding read bit line.

20. A method for operating a general memory for in-memory computing, the method comprising: executing a training mode of an artificial intelligence model in the general purpose memory, The universal memory includes at least one memory cell having a write transistor and a read transistor, wherein the write transistor has a gate terminal for receiving a gate voltage to turn on or off the write transistor, a first terminal for receiving a write voltage, and a second terminal coupled to a gate terminal of the read transistor, and wherein, during the training mode, a storage potential of a storage node between the second terminal of the write transistor and the gate terminal of the read transistor is determined according to a first write voltage applied to the first terminal of the write transistor when the write transistor is turned on by a gate voltage applied to the gate terminal of the write transistor, a threshold voltage of the read transistor is maintained without change, and the storage potential of the storage node is repeatedly changeable according to the first write voltage; and An inference mode of the AI ​​model is executed in the universal memory, wherein, in the inference mode, according to a second write voltage applied to the first terminal of the write transistor when the write transistor is turned on, the read transistor is programmed or erased to have a specific threshold voltage, and the specific threshold voltage is adjustable according to the second write voltage.

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