Method for testing error correction capability of LDPC of storage device

Abstract

The invention discloses a method for testing the error correction capability of a storage device LDPC (Low Density Parity Check), which comprises a hard decision error correction capability testing method and a soft decision error correction capability testing method.According to the method, the error correction capability of hard decision and soft decision is measured through the number of error bits, and the error correction capability of the hard decision and soft decision of the LDPC is quantitatively measured, so that the error correction capability of the LDPC is improved. Theoretical reference is provided for evaluating the service life of the storage device, and whether the LDPC error correction algorithm or the parameters of the current hard decision and soft decision meet the requirements of the current flash memory particles or not can be quickly determined in the early stage of a project by quantitatively measuring the error correction capability of the LDPC hard decision and soft decision.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and more specifically, to a method for testing the LDPC error correction capability of a storage device. Background Art

[0002] The main control chip and flash memory particles are important components of storage devices. During use, the error correction algorithm in the main control chip is needed to ensure the reliability of flash memory data, thereby extending the service life of the storage device. The mainstream error correction algorithm on storage devices is the LDPC error correction algorithm. There are two types of LDPC error correction algorithms, one is hard decision and the other is soft decision. Hard decision takes a short time, but the decoding ability is weak, while soft decision has strong decoding ability but takes a long time. Generally, hard decision will be used first in storage devices. If it cannot be corrected, soft decision will be made. The LDPC error correction capability directly affects the service life of the storage device, but the current existing technology lacks a method for testing the LDPC error correction capability on the storage device.

[0003] Therefore, it is necessary to invent a method for testing the LDPC error correction capability of a storage device to solve the above problems. Summary of the invention

[0004] In order to overcome the above defects of the prior art, the present invention provides a method for testing the LDPC error correction capability of a storage device to solve the problem in the prior art mentioned in the above background technology that there is a lack of a method for testing the LDPC error correction capability of a storage device.

[0005] In order to achieve the above object, the present invention provides the following technical solution: a method for testing the LDPC error correction capability of a storage device, including a hard decision error correction capability testing method and a soft decision error correction capability testing method, wherein the hard decision error correction capability testing method comprises the following steps: S1, selecting a flash block group from a flash memory particle, the flash block group including one or more flash blocks, performing an erase operation on all flash blocks in the flash block group, and then performing a write operation on the flash block to fill it with data; S2. Select and set a read voltage, and perform a read operation on N flash memory pages of the flash memory block, as follows: S21. Among the N flash memory pages, each flash memory page corresponds to multiple levels. One level Li is selected, and its read voltage is set to Vs. The read voltages of other levels are fixed. The read voltages of other levels can be set to default values ​​or to optimal read voltage values. S22, the read voltage of Li is shifted with Vs as the starting read voltage and Vd as the step size, and the read voltages of other levels can be set to the default value or the optimal read voltage value; read operations are performed on N flash memory pages respectively, and the read status and the number of error bits are obtained from the corresponding LDPC register; S3, repeat the operation in step S2 multiple times to perform a read operation; S4. When a read error occurs after M consecutive reads, or the number of offsets exceeds a threshold value T, the test is stopped, where M and T are given by the technician based on experience; S5, performing corresponding statistical operations on the number of error bits successfully read back for the last time before the N flash memory page read errors, including but not limited to taking the mean or median, and the obtained value is the error correction capability of the hard decision; The soft decision error correction capability testing method comprises the following steps: B1. Selecting a flash block group from a flash memory particle, the flash block group including one or more flash blocks, and causing flash memory pages of the flash blocks in the flash block group to have different degrees of read errors by using a corresponding method; B2. Different levels are assigned to flash memory pages with different degrees of read errors. Each level has one or more flash memory pages. The more serious the read error is, the higher the level is. Different soft decision parameters are provided for different levels. B3, starting from the highest-level flash memory page, soft decision is performed to obtain the read status, number of error bits, and number of iterations from the corresponding LDPC register; B4, if the read is successful, record the number of error bits and the number of iterations and continue to make soft decisions on other flash memory pages in the level; if the read fails, continue to make soft decisions on other flash memory pages in the level; if at least one flash memory page in the level can be read successfully, stop; if all flash memory pages in the level fail to read, start soft decisions on the flash memory pages of the next level, and obtain the read status, number of error bits and number of iterations from the corresponding LDPC register; if the read fails, repeat B4; B5. Perform statistical calculations on the number of error bits of all flash memory pages that can be read back at the current level, including but not limited to taking the mean or median, and the obtained value is the error correction capability of the soft decision.

[0006] As a further description of the above technical solution, the erase operation and write operation in step S1 can be either the SLC mode or the highest mode. The modes of the erase operation and the write operation need to be consistent. The same is true for the subsequent read operation. The highest mode of SLC flash memory particles is the SLC mode, the highest mode of MLC flash memory particles is the MLC mode, the highest mode of TLC flash memory particles is the TLC mode, and the highest mode of QLC flash memory particles is the QLC mode.

[0007] As a further description of the above technical solution, in step S2, N is a positive integer not less than 1 and not greater than the number of flash memory pages in the flash memory block.

[0008] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a theoretical reference for evaluating the service life of storage devices by quantitatively measuring the error correction capabilities of LDPC hard decisions and soft decisions. 2. The present invention can quantitatively measure the error correction capabilities of LDPC hard decisions and soft decisions, and can quickly determine whether the LDPC error correction algorithm or the current hard decision and soft decision parameters meet the current flash memory particle requirements in the early stage of the project. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0010] Figure 1 A flow chart of a method for testing the error correction capability of a hard decision process provided by the present invention; Figure 2 An implementation diagram of a hard decision process error correction capability testing method provided by the present invention; Figure 3 A flow chart of a method for testing the error correction capability of a soft decision process is provided for the present invention; Figure 4 An implementation diagram of soft decision flash memory page level division provided by the present invention; Figure 5 The present invention provides soft decision parameter tables of different levels. DETAILED DESCRIPTION

[0011] The following is a description of the implementation of the present invention by specific embodiments. People familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0012] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0013] Storage device LDPC error correction capability test method, such as Figure 1 — Figure 5As shown, it includes a hard decision error correction capability test method and a soft decision error correction capability test method.

[0014] See attached Figure 1-5 A method for testing the LDPC error correction capability of a storage device is provided, which is used to solve the problem that the prior art lacks a method for testing the LDPC error correction capability of a storage device, and includes a hard decision error correction capability testing method and a soft decision error correction capability testing method.

[0015] See attached Figure 1 , the hard decision error correction capability testing method comprises the following steps: S1. Select a flash block group from a flash memory particle. The flash block group includes one or more flash blocks. Perform an erase operation on all flash blocks in the flash block group. Then perform a write operation on the flash block to fill it with data. The erase operation and the write operation can be either an SLC mode or a maximum mode. The erase operation and the write operation mode need to be consistent. The same is true for the subsequent read operation. The maximum mode of the SLC flash memory particle is the SLC mode, the maximum mode of the MLC flash memory particle is the MLC mode, the maximum mode of the TLC flash memory particle is the TLC mode, and the maximum mode of the QLC flash memory particle is the QLC mode. S2. Select and set a read voltage, and perform a read operation on N (N is a positive integer not less than 1 and not greater than the number of flash memory pages in the flash memory block) flash memory pages of the flash memory block, as follows: S21. Among the N flash memory pages, each flash memory page corresponds to multiple levels. One level Li is selected, and its read voltage is set to Vs. The read voltages of other levels are fixed. The read voltages of other levels can be set to default values ​​or to optimal read voltage values. S22, the read voltage of Li is shifted with Vs as the starting read voltage and Vd as the step size, and the read voltages of other levels can be set to the default value or the optimal read voltage value; read operations are performed on N flash memory pages respectively, and the read status and the number of error bits are obtained from the corresponding LDPC register; S3, repeat the operation in step S2 multiple times to perform a read operation; S4. When a read error occurs after M consecutive reads, or the number of offsets exceeds a threshold value T, the test is stopped, where M and T are given by the technician based on experience; S5. Perform corresponding statistical operations on the number of error bits successfully read back for the last time before the N flash memory page read errors, including but not limited to taking the mean or median, and the obtained value is the error correction capability of the hard decision.

[0016] Therefore, for different types of flash memory particles, such as SLC, MLC, TLC, QLC, etc., the number of levels corresponding to a flash memory page is different. The error correction capability test method of this solution is applicable to different types of flash memory particles; Taking the low flash page of TLC as an example, the low flash page contains two levels. The read voltage of one level is fixed as the default voltage. The other level starts with 0xE0 and is offset by 0x2. The obtained read status and error bit number change with the read voltage as shown in the attached figure. Figure 2 As shown, attached Figure 2 The values ​​of the ordinates corresponding to the two circles are the number of error bits successfully read back for the last time for the flash memory page. The corresponding statistical operations are performed on the number of error bits successfully read back for the last time before the N flash memory page read errors, including but not limited to taking the mean or median, and the obtained value is the error correction capability of the hard decision.

[0017] See attached Figure 3 , the soft decision error correction capability testing method comprises the following steps: B1. Select a flash block group from a flash memory particle, the flash block group including one or more flash blocks, and make the flash memory pages of the flash blocks in the flash block group have different degrees of read errors by the following two methods; Applicable to flash memory chips of MLC and above: 1. All flash blocks in the flash block group are erased with the highest mode and then the flash pages are written with the highest mode. The highest mode of MLC flash particles is MLC mode, the highest mode of TLC flash particles is TLC mode, and the highest mode of QLC flash particles is QLC mode; 2. Use SLC to erase all flash blocks in the flash block group and write the flash page using the highest mode. The write data pattern is the same as the data pattern in (1).

[0018] Applicable to all types of flash memory particles: 1. The flash block of channel 1 in the flash block group is erased with the highest mode and then written with the highest mode. After the execution is completed, the flash page is rewritten with the highest mode. The writing execution is suspended at t1. 2. The flash block of channel 2 in the flash block group is erased with the highest mode and then written with the highest mode. After the execution is completed, the flash page is rewritten with the highest mode. The writing execution is suspended at t2. 3. Execute all channels in sequence. The flash block of channel K in the flash block group is erased with the highest mode and then written with the highest mode. After the execution is completed, the flash page is rewritten with the highest mode. The writing execution is suspended when tK is reached; Among them, t1, t2, ..., tK can be given according to actual results or according to the experience of technicians.

[0019] B2. Different levels are provided for flash memory pages with different degrees of read errors. Each level has one or more flash memory pages. The more serious the read error is, the higher the level is. For example, an implementation of the level division is as follows: Figure 5As shown, the horizontal axis is the index of different flash memory pages, and the vertical axis is the number of error bits. Different soft decision parameters are provided for different levels. The hard decision threshold, soft decision threshold, optimal voltage, offset voltage and LLR value in the soft decision parameter table are a priori values, which can be obtained according to experiments or given by technicians according to experience. B3, starting from the highest-level flash memory page, soft decision is performed to obtain the read status, number of error bits, and number of iterations from the corresponding LDPC register; B4, if the read is successful, record the number of error bits and the number of iterations and continue to make soft decisions on other flash memory pages in the level; if the read fails, continue to make soft decisions on other flash memory pages in the level; if at least one flash memory page in the level can be read successfully, stop; if all flash memory pages in the level fail to read, start soft decisions on the flash memory pages of the next level, and obtain the read status, number of error bits and number of iterations from the corresponding LDPC register; if the read fails, repeat B4; B5. Perform statistical calculations on the number of error bits of all flash memory pages that can be read back at the current level, including but not limited to taking the mean or median, and the obtained value is the error correction capability of the soft decision.

[0020] Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for testing the LDPC error correction capability of a storage device, including a hard decision error correction capability testing method and a soft decision error correction capability testing method, characterized in that: The hard decision error correction capability testing method comprises the following steps: S1, selecting a flash block group from a flash memory particle, the flash block group including one or more flash blocks, performing an erase operation on all flash blocks in the flash block group, and then performing a write operation on the flash block to fill it with data; S2. Select and set a read voltage, and perform a read operation on N flash memory pages of the flash memory block, as follows: S21. Among the N flash memory pages, each flash memory page corresponds to multiple levels, one level Li is selected, its read voltage is set to Vs, the read voltages of other levels are fixed, and the read voltages of other levels are set to default values ​​or optimal read voltage values; S22, the read voltage of Li is shifted with Vs as the starting read voltage and Vd as the step size, and the read voltages of other levels are set to default values ​​or optimal read voltage values; read operations are performed on N flash memory pages respectively, and the read status and the number of error bits are obtained from the corresponding LDPC register; S3, repeat the operation in step S2 multiple times to perform a read operation; S4. When a read error occurs after M consecutive reads, or the number of offsets exceeds a threshold value T, the test is stopped, where M and T are given by the technician based on experience; S5, performing corresponding statistical operations on the number of error bits successfully read back for the last time before the N flash memory page read errors, including but not limited to taking the mean or median, and the obtained value is the error correction capability of the hard decision; The soft decision error correction capability testing method comprises the following steps: B1. Selecting a flash block group from a flash memory particle, the flash block group including one or more flash blocks, and causing flash memory pages of the flash blocks in the flash block group to have different degrees of read errors by using a corresponding method; B2. Different levels are assigned to flash memory pages with different degrees of read errors. Each level has one or more flash memory pages. The more serious the read error is, the higher the level is. Different soft decision parameters are provided for different levels. B3, starting from the highest-level flash memory page, soft decision is performed to obtain the read status, number of error bits, and number of iterations from the corresponding LDPC register; B4, if the read is successful, record the number of error bits and the number of iterations and continue to make soft decisions on other flash memory pages in the level; if the read fails, continue to make soft decisions on other flash memory pages in the level; if at least one flash memory page in the level can be read successfully, stop; if all flash memory pages in the level fail to read, start soft decisions on the flash memory pages of the next level, and obtain the read status, number of error bits and number of iterations from the corresponding LDPC register; if the read fails, repeat B4; B5. Perform statistical calculations on the number of error bits of all flash memory pages that can be read back at the current level, including but not limited to taking the mean or median, and the obtained value is the error correction capability of the soft decision.

2. The method for testing the LDPC error correction capability of a storage device according to claim 1, wherein: The erase operation and write operation in step S1 can be either the SLC mode or the highest mode. The modes of the erase operation and the write operation need to be consistent. The same is true for the subsequent read operation. The highest mode of SLC flash memory particles is the SLC mode, the highest mode of MLC flash memory particles is the MLC mode, the highest mode of TLC flash memory particles is the TLC mode, and the highest mode of QLC flash memory particles is the QLC mode.

3. The method for testing the LDPC error correction capability of a storage device according to claim 2, wherein: In step S2, N is a positive integer not less than 1 and not greater than the number of flash memory pages in the flash memory block.

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