Test access for stacked semiconductor devices and associated systems and methods

Abstract

The invention relates to test access for stacked semiconductor devices and associated systems and methods. High bandwidth memory (HBM) devices and associated systems and methods are disclosed herein. In some embodiments, the HBM device includes a first die (e.g., an interface die), a plurality of second dies (e.g., memory dies) carried by the first die that may be communicatively coupled to the first die through a plurality of HBM buses through substrate vias (TSVs). The HBM device also includes an HBM test component at least partially carried by an upper surface of an uppermost second die. The HBM test component provides access to the first die and the second die through an uppermost surface of the HBM device to test the HBM device during fabrication. For example, the HBM test assembly allows the first die and the second die to be tested after the HBM device is mounted to a base substrate of a system-in-package without requiring any footprint for access pins on the base substrate.

Description

Technical Field

[0001] The present technology relates generally to vertically stacked semiconductor memory devices, and more particularly, to systems and methods for accessing and testing high bandwidth memory devices in a system-in-package. Background Art

[0002] Microelectronic devices, such as memory devices, microprocessors, and other electronic devices, typically include one or more semiconductor dies mounted to a substrate and enclosed in a protective covering. The semiconductor die includes functional features, such as memory cells, processor circuits, imager devices, interconnect circuitry, etc. In order to meet the ongoing demand for reduced size, wafers, individual semiconductor dies, and / or active components are typically batch-fabricated, singulated, and then stacked on an interposer and / or a supporting substrate, such as a printed circuit board (PCB) or other suitable substrate. The stacked dies may then be coupled to an interposer and / or a supporting substrate (sometimes also referred to as a package substrate) by bonding wires and / or through-substrate vias (TSVs) between the die and the supporting substrate in a shingled stack of dies (e.g., dies stacked with an offset for each die). Summary of the invention

[0003] In one aspect, the present disclosure relates to a high bandwidth memory (HBM) device comprising: a first die; a plurality of second dies carried by the first die, the plurality of second dies including an uppermost die, wherein each of the plurality of second dies is communicatively coupled to the first die through a plurality of active through substrate vias (TSVs); and an HBM test component at least partially carried by an upper surface of the uppermost die and positioned to be communicatively coupled to the first die.

[0004] In another aspect, the present disclosure relates to a system-in-package (SiP) device, comprising: an interposer substrate; a processing unit carried by the interposer substrate; and a high-bandwidth memory (HBM) device carried by the interposer substrate, wherein the HBM device is coupled to the processing unit via an interposer bus, and wherein the HBM device comprises: an interface die carried by the interposer substrate; a plurality of memory dies carried by the interface die, wherein the plurality of memory dies are communicatively coupled to the interface die; and an HBM test component at least partially carried by an upper surface of an uppermost memory die, the HBM test component being positioned to be communicatively coupled to the interface die to provide access to the interface die at the uppermost surface of the HBM device.

[0005] In another aspect, the present disclosure relates to a method for manufacturing a system-in-package (SiP) device, comprising: forming a high bandwidth memory (HBM) device, the HBM device comprising: an interface die; a plurality of memory dies; and an HBM test component accessible at an outer surface of the HBM device; attaching an inner surface of the HBM device to an interposer; accessing one or more circuits in the HBM device through the HBM test component to test one or more test metrics of the HBM device; and attaching one or more additional components to the interposer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram illustrating an environment incorporating a high bandwidth memory architecture.

[0007] Figure 2 is a partial schematic cross-sectional view of a system-in-package device.

[0008] Figure 3 is a partially schematic cross-sectional diagram of a high bandwidth memory device configured in accordance with some embodiments of the present technology.

[0009] Figure 4 is a schematic circuit diagram of access points of a high bandwidth memory test assembly configured in accordance with further embodiments of the present technology.

[0010] Figure 5 is a partially schematic cross-sectional diagram of a high bandwidth memory device configured in accordance with further embodiments of the present technology.

[0011] Fig. 6A is a partially schematic cross-sectional diagram of a high bandwidth memory device configured in accordance with further embodiments of the present technology.

[0012] Figure 6B is a partially schematic top view of an HBM test assembly configured in accordance with some embodiments of the present technology.

[0013] Figure 7 is a flow chart of a process for fabricating a SiP device according to some embodiments of the present technology.

[0014] The drawings are not necessarily drawn to scale. In addition, it will be understood that several drawings have been drawn schematically and / or partially schematically. Similarly, for the purpose of discussing some embodiments of the present technology, some components and / or operations may be separated into different blocks or combined into a single block. In addition, although the present technology may have various modifications and alternative forms, specific embodiments have been shown in the drawings by way of example and are described in detail below. However, it is not desired to limit the present technology to the specific embodiments described. DETAILED DESCRIPTION

[0015] High data reliability, high memory access speed, lower power consumption and reduced chip size are the features required of semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by vertically stacking memory dies and interconnecting the dies using through-silicon (or through-substrate) vias (TSVs). The advantages of 3D memory devices include shorter interconnects (which reduce circuit delays and power consumption), a large number of vertical pathways between layers (which allow wide bandwidth buses between functional blocks (such as memory dies) in different layers), and a much smaller footprint. Therefore, 3D memory devices help to increase memory access speed, reduce power consumption and reduce chip size. Example 3D memory devices include hybrid memory cubes (HMCs) and high bandwidth memories (HBMs). For example, HBM is a vertically stacked memory including dynamic random access memory (DRAM) dies and interface dies (which, for example, provide an interface between the DRAM dies of the HBM device and a host device).

[0016] In a system-in-package (SiP) configuration, the HBM device can be integrated with a host device (e.g., a GPU and / or CPU) using a base substrate (e.g., a silicon interposer, a substrate of organic material, a substrate of inorganic material, and / or any other suitable material that provides interconnection between a graphics processing unit (GPU) / computer processing unit (CPU) and the HBM device and / or provides mechanical support for components of the SiP device), through which the HBM device communicates with the host. Since the traffic between the HBM device and the host device resides within the SiP (e.g., using signals routed through the silicon interposer), a higher bandwidth can be achieved between the HBM device and the host device than in conventional systems. In other words, the TSVs that interconnect the DRAM dies within the HBM device, and the silicon interposer that integrates the HBM device with the host device, are capable of routing more signals (e.g., a wider data bus) than are typically found between a packaged memory device and a host device (e.g., through a printed circuit board (PCB)). The high-bandwidth interface within the SiP enables large amounts of data to be quickly moved between the host device (e.g., GPU / CPU) and the HBM device during operation. For example, the high bandwidth channel may be approximately 1000 gigabytes per second (GB / s, sometimes also referred to as gigabits (Gb)). It will be appreciated that such high bandwidth data transfer between the GPU / CPU and the memory of the HBM device may be advantageous in various high performance computing applications such as video rendering, high resolution graphics applications, artificial intelligence and / or machine learning (AI / ML) computing systems and other complex computing systems, and / or various other computing applications.

[0017] However, HBM devices may present certain challenges. One such challenge is that after the HBM device is integrated with the SiP (e.g., soldered to a base substrate), the space available on the base substrate to set pins to access and test the HBM device is limited. Therefore, after the HBM device is integrated with the base substrate, it may be difficult to evaluate various test metrics (e.g., functionality, performance, and other aspects of the HBM device (and / or the SiP as a whole based on aspects of one or more HBM devices)). For example, it may be difficult to test the functionality of the HBM device (e.g., whether the HBM device produces expected results and / or effects given an input, responds to a given input, and / or the like), check the integration process for defects (e.g., broken signal lines), evaluate the condition of the HBM device over time, measure various categories of performance (e.g., signal speed, bandwidth, and / or the like), and / or the like. Therefore, described herein are systems and associated methods for improving access to HBM devices after the HBM devices are stacked and integrated with a base substrate.

[0018] Figure 1 is a schematic diagram illustrating an environment 100 incorporating a high bandwidth memory architecture. Figure 1 As illustrated in FIG. 1 , environment 100 includes a SiP device 110 having one or more processing devices 120 ( 120 ) integrated with a silicon interposer 112 (or any other suitable base substrate). Figure 1 1 and 120, sometimes referred to herein as one or more "hosts") and one or more HBM devices 130 ( Figure 11 ). The environment 100 additionally includes a storage device 140 coupled to the SiP device 110. The processing device 120 may include one or more CPUs and / or one or more GPUs, referred to as processing units 122, each of which may include registers 124 and a first level cache 126. The first level cache 126 (also referred to herein as an "L1 cache") is communicatively coupled to a second level cache 128 (also referred to herein as an "L2 cache") via a first communication path 152. In the illustrated embodiment, the L2 cache 128 is incorporated into the processing device 120. However, it will be understood that the L2 cache 128 may be integrated into the SiP device 110 separately from the processing device 120. By way of example only, the processing device 120 may be carried by a base substrate (e.g., silicon interposer 112, a package substrate carrying silicon interposer 112, another suitable organic substrate, an inorganic substrate, and / or any other suitable material) adjacent to the L2 cache 128 and communicate with the L2 cache 128 via one or more signal lines (or other suitable signal routing lines) in the base substrate. The L2 cache 128 may be shared by one or more of the processing devices 120 (and the processing units 122 therein). During operation of the SiP device 110, the processing unit 122 may use the registers 124 and the L1 cache 126 to complete processing operations, and whenever a cache miss occurs in the L1 cache 126, attempt to retrieve data from the larger L2 cache 128. Thus, the multi-level cache may help speed up the average time required for the processing device 120 to access data, thereby speeding up the overall processing rate.

[0019] like Figure 1 As further described in FIG. 1 , the L2 cache 128 is communicatively coupled to the HBM device 130 via a second communication channel 154. As described, the processing device 120 and the HBM device 130 are carried by and electrically coupled to (e.g., integrated by) the silicon interposer 112. The second communication channel 154 is provided by the silicon interposer 112 (e.g., the silicon interposer includes and routes interface signals that form the second communication channel, such as through one or more redistribution layers (RDLs)). Figure 1140. As further illustrated in FIG. 14 , the L2 cache 128 is also communicatively coupled to the memory device 140 via a third communication channel 156. As illustrated, the memory device 140 is located outside of the SiP device 110 and utilizes signal routing components that are not included within the silicon interposer 112 (e.g., between the packaged SiP device 110 and the packaged memory device 140). For example, the third communication channel 156 may be a peripheral bus, such as a peripheral component interconnect express (PCIe) bus, for connecting components on a motherboard or PCB. Thus, during operation of the SiP device 110, the processing device 120 may read data from and / or write data to the HBM device 130 and / or the memory device 140 via the L2 cache 128.

[0020] In the illustrated environment 100, the HBM device 130 includes an interface die 132 coupled to a second communication channel 154 and one or more stacked memory dies 134 (e.g., DRAM dies, Figure 1 110 ). As described above, the HBM device 130 may be positioned on the silicon interposer 112, and the processing device 120 is also positioned on the silicon interposer 112. Thus, the second communication channel 154 may provide a high bandwidth (e.g., approximately 1000 GB / s) channel through the silicon interposer 112. In addition, as described above, each HBM device 130 may provide a high bandwidth channel (not shown) between the interface die 132 and / or the memory die 134 therein. Thus, data may be communicated at high speed between the processing device 120 and the HBM device 130 (and its components), which may be advantageous for data-intensive processing operations. By way of example only, the interface die 132 may be a logic die that receives various read / write requests from the processing device 120, reads / writes to the memory die 134 in response to the request, performs any necessary processing, and responds to the processing device 120. During each read / write operation, SiP device 110 uses a high bandwidth communication channel, allowing read / write requests to be delivered and responded to in milliseconds (eg, real time).

[0021] Figure 2 is a partial schematic cross-sectional view of SiP device 200. Figure 2, the SiP device 200 includes a base substrate 210 (e.g., a silicon interposer, another organic interposer, an inorganic interposer, and / or any other suitable base substrate), and a processing device 220 and an HBM device 230 each integrated with an upper surface 212 of the base substrate 210. In addition, the base substrate 210 is carried by (and coupled to) a packaging substrate 270. In the illustrated environment, the processing device 220 and associated components (e.g., a processing unit (e.g., CPU / GPU), registers, L1 cache, and the like) are illustrated as a single package, and the HBM device 230 includes a semiconductor die stack. The semiconductor die stack in the HBM device 230 includes an interface die 232 and one or more memory dies 234 ( Figure 2 Six memory dies 234 are illustrated in FIG. 2 ). The processing device 220 is coupled to the HBM device 230 via an HBM bus 242 and a substrate bus 244 (together forming the high bandwidth bus 240). The HBM bus 242 includes a plurality of active through substrate vias (“active TSVs”) extending from a metallization layer 233 in the interface die 232 to a metallization layer 235 in the uppermost memory die 234a. The active TSVs in the HBM bus 242 allow each of the dies in the HBM device 230 to transfer data at a relatively high rate (e.g., approximately 1000 GB / s or greater) (e.g., between a memory die 234 (e.g., a DRAM die) and an interface die 232). The substrate bus 244 includes one or more routing lines ( Figure 2 In various embodiments, the routing lines of the substrate bus 244 may include one or more metallization layers formed in one or more RDL layers of the base substrate 210 and / or one or more vias interconnecting the metallization layers. Figure 2 As further schematically illustrated in , the processing device 220 and the HBM device 230 may each be coupled to the substrate bus 244 via solder structures (e.g., solder balls), metal-metal bonds, and / or any other suitable conductive bonds. Thus, the components of the HBM device 230 and the processing device 220 may transfer data at a relatively high rate (e.g., approximately 1000 GB / s or greater).

[0022] like Figure 2 As further described in the accompanying drawings, the base substrate 210 may further include one or more external TSVs 262 (hereinafter referred to as "inner surfaces") extending from the upper surface 212 of the base substrate 210 to the lower surface 214 of the base substrate 210 (hereinafter referred to as "inner surfaces"). Figure 22. The four external TSVs 262 are illustrated in FIG. 2. The external TSVs 262 may couple the processing device 220, the HBM device 230, and / or the substrate bus 244 to a package interconnect 264 (e.g., a solder structure, a bonding pad, and / or the like). The package interconnect 264 is coupled between the base substrate 210 and the package substrate, thereby physically and electrically coupling the SiP device 200 to the package substrate 270.

[0023] During the manufacture of the SiP device 200, the processing device 220 and the HBM device 230 are each stacked on and coupled to the base substrate 210, which is then stacked on and coupled to the packaging substrate. Each stacking process includes steps that may damage the functionality of the HBM device 230 (e.g., by damaging components of the HBM bus 242, circuits in the interface die 232 and / or memory die 234, and the like, such that the HBM device 230 does not respond to inputs, does not respond as expected, and / or responds to inputs slower than expected (or required)). Therefore, it may be advantageous to test the HBM device 230 (and / or the processing device 220) after each manufacturing stage to ensure that the HBM device 230 is functioning properly. If the HBM device 230 is not functioning properly, the HBM device 230 may be replaced and / or the SiP device 200 may be recycled, thereby avoiding further processing of the SiP device 200 when the SiP device 200 will not comply with proper operation. However, industry demands continue to drive computing power density. As a result, the footprint of SiP device 200 continues to shrink. Additionally or alternatively, the space on base substrate 210 is increasingly occupied by routing lines in substrate bus 244 and / or other active components of SiP device 200. As a result, the space on base substrate 210 for pins to access and test HBM device 230 becomes smaller.

[0024] Disclosed herein are HBM devices and associated systems and methods that address the shortcomings discussed above. For example, the HBM device may include a first die (e.g., an interface die), a plurality of second dies (e.g., memory dies) carried by the first die and communicatively coupled to the first die via a plurality of HBM bus through substrate vias (TSVs). The HBM device also includes an HBM test component at least partially carried by the upper surface of the uppermost second die. The HBM test component provides access to the first and second dies (and components therein) through the outer surface (e.g., the uppermost surface) of the HBM device. For example, as described herein, the uppermost surface of the HBM test component may include bonding pads communicatively coupled to one or more locations inside the HBM device (e.g., circuits of the first and second dies). Thus, the HBM test component allows the HBM device to be tested at various stages of manufacturing and / or integration. For example, the HBM test component allows the HBM device to be tested after the HBM device is mounted to a base substrate (e.g., Figure 2 The operation of the first and second dies (and the connections of the dies) can then be tested without requiring additional occupied area for access pins on the base substrate 210 .

[0025] In some embodiments, the HBM test component is a passive component that establishes a communication route between the outer surface of the HBM device and the first and second dies. In such embodiments, an external test component (e.g., a processing unit or other controller) can access the components of the HBM device through the passive communication route to evaluate the HBM device (e.g., observation / detection values ​​inside the HBM device, and / or setting values). In some such embodiments, the HBM test component may include a redistribution layer carried by (and / or formed on) the upper surface of the uppermost second die and a test TSV extending from the redistribution layer to the active circuit area of ​​the first die. The test TSV may be able to be communicatively coupled to one or more circuits in the active circuit area (e.g., test circuits, active circuits, and / or the like). In addition, the HBM test component may also include a bonding pad carried by the outermost surface of the redistribution layer, thereby establishing access to the circuit in the active circuit area at the outermost surface of the HBM device. In some embodiments, the HBM test component includes a through die attached to the upper surface of the uppermost second die. The pass-through die may include redistribution layers, allowing the pass-through die (and redistribution layers) to be separated from the second die and / or mass-produced without requiring modifications to the manufacturing process of the second die.

[0026] In some embodiments, the HBM test component may include one or more active circuits and / or other active elements. For example, the HBM test component may include a copy of at least some circuits of the interface die, one or more test drive circuits, and / or the like. The copy of the circuits from the interface die may allow the HBM test component to directly access and evaluate the memory die in the HBM device (e.g., check the response time of each of the memory dies, confirm the functionality of the HBM bus, and / or the like). Additionally or alternatively, if the circuits in the interface die are damaged, the copy of the circuits from the interface die may allow the HBM test component to act as a backup interface die.

[0027] Additional details regarding systems and methods for improving access to vertically stacked memory devices (e.g., HBM devices) are set forth below. For ease of reference, semiconductor systems (and components thereof) are sometimes described herein with reference to front and back, top and bottom, up and down, upward and downward, and / or horizontal planes, xy planes, vertical or z directions relative to the spatial orientation of the embodiments shown in the figures. However, it should be understood that the semiconductor systems (and components thereof) may be moved to and used in different spatial orientations without changing the structure and / or functionality of the disclosed embodiments of the present technology.

[0028] Additionally, although the semiconductor systems disclosed herein are primarily discussed in the context of accessing HBM devices, those skilled in the art will appreciate that the scope of the present technology is not limited thereto. For example, the systems and methods disclosed herein may also be deployed to improve access to active components and / or functional dies in other stacked semiconductor devices, to improve access to other components of a SiP, and the like.

[0029] Figure 3 is a partially schematic cross-sectional view of an HBM device 300 configured in accordance with some embodiments of the present technology. Figure 3 As described in FIG. 1 , the HBM device 300 is substantially similar to Figure 2 For example, the HBM device 300 includes an interface die 310 and a plurality of memory dies 320 carried by the interface die 310. The HBM device 300 also includes a plurality of bus TSVs 340 that each extend from a metallization layer 312 in the interface die 310 to a metallization layer 332 in an uppermost memory die 330. As discussed above, the bus TSVs 340 establish a high-bandwidth HBM bus that interconnects each of the memory dies 320 with the interface die 310.

[0030] In the illustrated embodiment, the HBM device 300 also includes an HBM test component 350 positioned to provide access to the interface die 310 through the uppermost surface 302 of the HBM device 300. In the illustrated embodiment, the HBM test component 350 (also sometimes referred to herein as an "access component," "test unit," and / or the like) includes a redistribution layer 352 carried by the upper surface 334 of the uppermost memory die 330 and one or more test TSVs 354 extending from the redistribution layer 352 through the memory die 320 to the circuit region 314 in the interface die 310. In the interface die 310, the test TSVs 354 (also sometimes referred to herein as "access TSVs") may be coupled to one or more circuits (e.g., active and / or critical circuits of the interface die, test circuits, and / or any other suitable circuits) and / or one or more signal routing lines in the circuit region 314. At the redistribution layer 352, the test TSV 354 can be coupled to one or more routing lines 356 (one routing line 356 is schematically illustrated). The routing line 356 can be coupled to one or more bonding pads 358 ( Figure 3 3. Through these connections, the HBM test component 350 provides access and / or control to components in the circuit area 314 of the interface die 310 through the uppermost surface 302 of the HBM device 300.

[0031] Thus, the HBM test component 350 may allow various suitable components to test various components of the HBM device 300. For example, the HBM test component 350 may allow the controller (or processor) to access test circuits, functional circuits, etc. in the interface die 310 to observe the signals of the accessed circuits and ensure that the accessed circuits are in contact with the HBM device 300 and the base substrate (e.g., Figure 2 The controller may be able to evaluate the operation of the HBM device 300 and the interface die 310 therein by observing a specific circuit (e.g., a test circuit, a functional circuit, etc.) using the HBM test component 350. In addition, in some embodiments, the controller may extrapolate the observed functionality and / or performance of a subset of circuits on the HBM device 300 (e.g., a test circuit) to the estimated functionality and / or performance of other circuits on the HBM device 300 (e.g., functional circuits, critical circuits, etc.). In another example, the HBM test component 350 may allow the controller (or processor) to directly access and test one or more of the critical circuits (e.g., send signals to and receive signals from them). In yet another example, the HBM test component 350 may provide access to one or more signal routing lines within the HBM device 300 (e.g., within the metallization layer 312 in the interface die 310, a line forming part of the HBM bus, and / or the like) to observe (e.g., passively read signals) the signal routing lines. In this example, HBM test assembly 350 allows one or more measurement devices to read signals in signal routing lines while HBM device 300 is operated by a processing unit (e.g., Figure 2 220) to confirm that the HBM device 300 is responding appropriately to the processing unit.

[0032] In each of the examples discussed above, access and testing is accomplished through the uppermost surface 302 of the HBM device 300. Thus, after the HBM device 300 is mounted to a base substrate, the base substrate (e.g., Figure 2 No additional space is required on the base substrate 210 of the HBM device 300 for additional access pins to test the HBM device 300. In addition, the access provided by the HBM test component 350 can be relatively high bandwidth access (e.g., on the order of hundreds or thousands of Gb / s) compared to the access available through the pins on the base substrate. Thus, the HBM test component 350 can help increase access to components of the HBM device 300 after the HBM device 300 is mounted to the base substrate and help reduce the overall footprint of the base substrate (and corresponding SiP device).

[0033] The HBM test assembly 350 can take advantage of the space available on the upper surface 334 of the top memory die 330 to provide access to the HBM device 300 at a relatively low cost. For example, the redistribution layer 352 can be formed on the upper surface 334 of the top memory die 330 during wafer-level processing without requiring significant changes to the manufacturing process. In addition, the test TSVs 354 can be formed during wafer-level processing, with the only change being the addition of segments to the top memory die 330. Thus, when the bus TSVs 340 extend to a first height within the top memory die 330 (e.g., the height of the metallization layer 332 in the top memory die 330), the test TSVs 354 extend to a second height above the first height. In addition, as Figure 3 As illustrated in , the second height may be at (or above) the upper surface 334 of the uppermost memory die 330 .

[0034] like Figure 3 As further schematically illustrated in , the HBM device 300 may also include a coupling mechanism 362 at an access point 360 between the test TSV 354 and a component in the circuit region 314 (e.g., a circuit node to be observed and / or controlled). In various embodiments, the coupling mechanism 362 may be a fuse, a fuse switch disconnector, a mask editable component, and / or any other suitable component. The coupling mechanism 362 may disconnect the test TSV 354 from the component in the circuit region 314 to avoid parasitic loading of the component caused by the test TSV after the HBM device 300 has been tested (e.g., to avoid loading the component during normal use of the HBM device 300 and the corresponding SiP device). Thus, the coupling mechanism 362 may help reduce deleterious effects (if any) associated with including the HBM test component 350.

[0035] Figure 4 4 is a schematic circuit diagram of an access point 400 of an HBM test assembly configured according to another embodiment of the present technology. The access point 400 is a test TSV 420 (e.g., Figure 3 ) is coupled to an interface die (e.g., Figure 3410 in the interface die 310). In the illustrated embodiment, the test TSV 420 is coupled to the routing line between the first node 412 and the second node 414. The first node is coupled to the circuit 410 (e.g., a test circuit, a critical circuit, a peripheral circuit, and / or any other suitable circuit manufactured in the interface die), and the second node 414 may be coupled to the signal routing line and / or one or more additional circuits. Therefore, the test TSV 420 may write a signal to the routing line between the first node 412 and the second node 414 (e.g., to control the circuit 410 and / or any other suitable component). In addition, the test TSV 420 may read the signal moving between the first node 412 and the second node 414 (e.g., to measure the activity in the circuit 410 when the corresponding HBM device is operating). However, even when the test TSV is not used (e.g., not used to control or observe a value), the connectivity of the test TSV 420 may apply a small parasitic load to the routing line between the first node 412 and the second node 414. The load may in turn require additional power during operation of the HBM device, thereby reducing the efficiency of the HBM device, increasing heat in the HBM device, and / or shortening the life of components of the HBM device (e.g., circuit 410, HBM bus, and the like). Additionally, the load may add delay to functional paths associated with circuit 410 (which may, for example, extend the critical path).

[0036] Therefore, it may be advantageous to disconnect the test TSV 420 from the circuit 410 (and / or other components of the HBM device) after testing has occurred. Therefore, an HBM device configured according to some embodiments of the present technology may include one or more mechanisms to disconnect, decouple, etc. the test TSV 420 from the circuit 410. For example, the access point 400 in the illustrated embodiment includes a fuse 430. After testing has occurred, the test component and / or the HBM device may overdrive the fuse 430 (e.g., by applying a signal having a current above a predetermined threshold), thereby destroying the fuse 430 and disconnecting the test TSV 420 from the circuit 410 (and / or other components of the HBM device). Therefore, the test TSV 420 will no longer apply a parasitic load to the HBM device. In some embodiments, fuse 430 may initially be open (eg, causing test TSV 420 to be disconnected from circuit 410 ), and the test component and / or HBM device may drive a signal to close the fuse (eg, establishing a connection between the test TSV and the circuit).

[0037] In another example (not illustrated), the access point 400 may include a fuse switch disconnector (sometimes also referred to as a fused disconnect switch). The fuse switch disconnector allows the test TSV 420 to be disconnected from the circuit 410 (and / or other components of the HBM device) after testing is complete and reconnected at a later time (e.g., when a failed SiP is diagnosed). In addition, if a signal with sufficient current is loaded onto the test TSV 420, the fuse switch disconnector will disconnect, thereby helping to protect the components of the HBM device during testing (e.g., from accidental overdriving). In another example, the access point 400 may include a pass-gate transistor coupled between the test TSV 420 and the circuit 410. Similar to a fuse switch, enabling and disabling the pass-gate transistor may allow the test TSV 420 to be selectively disconnected and reconnected from the circuit 410.

[0038] In yet another example, the access point 400 may include a mask editable component that can be altered to disconnect the test TSV 420 from the circuit 410 (and / or other components of the HBM device). For example, a SiP device having multiple HBM devices (or a broader system having multiple SiP devices) may include one or more test-specified HBM devices and one or more non-test HBM devices. During manufacturing, components for test TSVs may be created in each semiconductor die, allowing the test-specified HBM devices to be constructed with test TSVs. However, additional processes may be implemented on one or more of the dies of the non-test HBM devices to remove the connection between the test TSV and the local circuit on the interface die at the access point 400 in the non-test HBM device. Therefore, the test-specified HBM device can be used to access the HBM device and / or evaluate various test metrics. Then, the test metrics can be extrapolated to each of the HBM devices, allowing the test metrics of the non-test HBM devices to be evaluated without generating parasitic losses associated with the test TSVs.

[0039] Figure 5 is a partially schematic cross-sectional view of an HBM device 500 configured in accordance with another embodiment of the present technology. Figure 5 The HBM device 500 is substantially similar to the HBM device 500 described above with reference to Figure 3 The HBM device 300 discussed. For example, the HBM device 500 includes an interface die 510, a plurality of memory dies 520 carried by the interface die 510, a plurality of bus TSVs 540 extending from the interface die 510 to an uppermost memory die 530, and an HBM test component 550 positioned to be communicatively coupled to the interface die 510.

[0040] In the illustrated embodiment, the HBM test assembly 550 includes a through die 552 carried by the upper surface 534 of the uppermost memory die 530 and one or more test TSVs 554 ( 555A ) coupled between the circuit area 514 of the interface die 510 and the through die 552. Figure 5 554). The through die 552 is a passive die having little (or no) circuitry for testing the interface die 510 (and / or any other suitable components). Instead, the through die 552 includes one or more routing lines 556 (e.g., a redistribution layer formed on the through die 552) and one or more bonding pads 558 coupled to the routing lines 556. The test TSVs 554 extend to (and / or at least partially extend through) the through die 552 and are coupled to the routing lines 556 (e.g., coupled to a height above the upper surface 534 of the uppermost memory die 530), thereby establishing a conductive path between the bonding pads 558 and the circuit area 514 in the interface die 510 and providing access to the circuit area 514 through the uppermost surface 502 of the HBM device 500. Thus, the HBM test component 550 may allow various suitable components to test various components of the HBM device 500. For example, similar to Figure 3 The HBM test component 350, the HBM test component 550 may allow a controller (or processor) to access the test circuit in the interface die 510 to ensure that the test circuit is intact; allow a controller (or processor) to directly access and test one or more of the critical circuits; provide access to one or more signal routing lines within the HBM device to observe the signal routing lines; and / or the like.

[0041] Including a separate die for the pass-through die 552 (e.g., as opposed to forming a redistribution layer on the upper surface 534 of the uppermost memory die 530) can help speed up manufacturing. For example, the pass-through die 552 can be manufactured in a separate wafer-level process simultaneously with any of the memory dies 520, rather than requiring additional wafer-level processing stages when forming the uppermost memory die 530. Thus, while the pass-through die 552 may increase cost (compared to forming a redistribution layer on the upper surface 534 of the uppermost memory die 530), the pass-through die 552 can increase the throughput of the manufacturing process.

[0042] like Figure 5 As further illustrated in FIG. 5 , the HBM device 500 may also include a coupling mechanism 562 at an access point 560 between the test TSV 554 and the components in the circuit area 514. As discussed above, the coupling mechanism 562 may include a fuse, a fuse switch disconnector, a mask editable component, and / or any other suitable component to controllably decouple the test TSV 554 from the components in the circuit area 514.

[0043] In each of the embodiments discussed above, the HBM test component (e.g., Figure 3 The HBM test assembly 350 and Figure 5 ) is a passive component that provides access to circuits and other components of the interface die through the top surface of the HBM device. The passive HBM test component allows an external test component to couple to and / or control the HBM device through the top surface (e.g., it provides signal access to the internals of the HBM device and some other active components). However, in some embodiments, the HBM test component may include one or more active circuits. Fig. 6A is a partially schematic cross-sectional view of an HBM device 600 configured in accordance with some such embodiments of the present technology. Fig. 6A The HBM device 600 is substantially similar to the above reference Figure 3 and 5 The HBM devices 300, 500 discussed. For example, the HBM device 600 includes an interface die 610, a plurality of memory dies 620 carried by the interface die 610, a plurality of bus TSVs 640, and an HBM test component 650 positioned to be communicatively coupled to the interface die 610.

[0044] However, in the illustrated embodiment, the HBM test assembly 650 includes an additional die 652 carried by the upper surface 634 of the uppermost memory die 630. The additional die 652 includes various built-in circuits 654, one or more metallization layers 656 (one metallization layer 656 is illustrated) coupled to the built-in circuits 654, and one or more external bonding pads 658 (eight external bonding pads 658 are illustrated) carried by the top surface 659 of the additional die 652 and coupled to the metallization layer 656. In addition, the bus TSV 640 extends from the metallization layer 612 in the interface die 610 through the uppermost memory die 630 to one of the metallization layers 656 in the additional die 652 (e.g., to a height above the upper surface 634 of the uppermost memory die 630). Thus, the built-in circuits 654 in the additional die 652 access each of the memory dies 620 and / or components of the interface die 610 through the bus TSV 640.

[0045] The built-in circuit 654 may include various circuits designed to test components of the HBM device 600, copies of one or more (including all) circuits in the interface die, circuits that measure the activity of the HBM device when operating, and / or any other suitable circuits. In a specific non-limiting example, the built-in circuit 654 includes a copy of each of the critical circuits (sometimes also referred to herein as "critical circuits" and / or "functional circuits") in the interface die. In this example, the processing unit (or other controller) may be coupled to the external bonding pad 658 to access and indicate the built-in circuit 654. Then, the built-in circuit 654 may send and receive messages from one or more (or all) memory dies 620, perform various processing functions, and the like to confirm the operability of the built-in circuit 654 and / or other components of the HBM device 600. When the built-in circuit 654 is sufficiently intact (e.g., meets various test metrics), the processing unit may assume that the critical circuits on the interface die 610 are also intact (e.g., because they are subjected to the same manufacturing process). Additionally, in this example, built-in circuitry 654 can provide backup for critical circuitry on interface die 610 (eg, when critical circuitry is damaged, when critical circuitry wears out over time, and the like).

[0046] While the inclusion of the additional die 652 may increase manufacturing costs (e.g., by requiring the formation and inclusion of the additional die), the functionality of the additional die 652 may improve both access to components of the HBM device 600 during manufacturing and the life of the HBM device 600. For example, as discussed above, the built-in circuits 654 in the additional die 652 may provide backup for critical circuits in the interface die 610. Additionally or alternatively, the built-in circuits 654 may periodically test components of the HBM device 600 and report their status (e.g., to a processing unit on a corresponding SiP device), thereby allowing the HBM device 600 to receive maintenance for damaged components and / or to remove damaged components from service.

[0047] like Fig. 6A As further described in the accompanying drawings, the HBM test assembly 650 may include one or more test TSVs 651 (one test TSV 651 is illustrated) coupled to the active circuit area 614 of the interface die 610 at the access point 660. The test TSVs 651 may supplement the access provided by the bus TSVs 640 and / or provide direct access to one or more circuits in the circuit area 614. For example, the direct access may allow the test circuits in the built-in circuits 654 to observe the operation of the key circuits in the circuit area 614 while the HBM device 600 is operating. The observation may allow the built-in circuits to evaluate the interface die 610 during the test phase and / or to periodically measure the condition of the interface die 610 during the life of the HBM device 600. As shown in FIG. Fig. 6AAs further illustrated in FIG. 6 , similar to the access point discussed above, the access point 660 includes a coupling mechanism 662 between the test TSV 651 and the components in the circuit region 614 , which controllably decouples the test TSV 651 from the components in the circuit region 614 .

[0048] Figure 6B is a description of some embodiments of the present technology Fig. 6A 650. As discussed above, the HBM test assembly 650 may include an additional die 652 and one or more test TSVs 651 ( Figure 6B In addition, as shown in FIG. Figure 6B , the additional die 652 may include built-in circuits 654 (e.g., active test circuits), PHY components 655 (e.g., transceiver and receiver components), a bus region 657, and a plurality of external bonding pads 658. The bus TSVs 640 extend into (and / or through) the additional die 652 in the bus region 657 and are coupled to the PHY components 655. The PHY components 655 are in turn coupled to the built-in circuits 654 and / or the external bonding pads 658 to route signals through and / or out of the additional die 652. For example, during a test phase, a processing unit (or other suitable controller) may be coupled to one or more of the external bonding pads 658. The PHY component 655 may receive commands from the processing unit via the external bonding pads 658, and then route appropriate signals to the built-in circuits 654 and / or through the bus TSVs 640 toward other components of the HBM device (e.g., toward Fig. 6A One or more of the memory dies 620) are routed.

[0049] In the illustrated embodiment, the bus region 657 is positioned in a central portion of the additional die 652, with the PHY components 655 and external bonding pads 658 positioned at the periphery of the bus region 657 and the built-in circuit 654 positioned at the periphery of the PHY components 655. However, it will be understood that the components of the additional die 652 may be arranged in any other suitable layout. By way of example only, the external bonding pads 658 may trace the entire periphery of the additional die 652 to increase the number of possible external connections. In another example, the PHY components 655 may be at least partially integrated with the built-in circuit 654, such that both the PHY components 655 and the built-in circuit 654 are formed within a longitudinal space on the additional die 652.

[0050] like Figure 6BAs further illustrated in FIG. 1 , the test TSV 651 may be positioned to at least partially (or completely) align with (and within the footprint of) the built-in circuit 654. In such embodiments, as discussed above, the test TSV 651 may couple the built-in circuit 654 directly to other components of the HBM device (e.g., to Fig. 6A However, in various other embodiments, the test TSVs 651 may be aligned with the PHY components 655, with one or more of the external bonding pads 658, and / or not aligned with any components in the additional die 652. In a specific non-limiting example, the test TSVs 651 may be directly coupled to a subset of the external bonding pads 658 to provide external test equipment with access to other components of the HBM device (e.g., Fig. 6A Direct access (e.g., not through PHY component 655 and / or any other routing components) to the circuit area 614 of the storage device.

[0051] Figure 7 is a flow chart of a process 700 for fabricating a SiP device according to some embodiments of the present technology. The process 700 may be performed by a single fabrication tool and / or split between multiple fabrication tools to construct and test the SiP device.

[0052] The process 700 begins at block 702 by forming an HBM device having a plurality of HBM devices that may be formed on an outer surface (eg, Figure 3 The HBM test component (e.g., having one or more external bonding pads or other conductive links) accessed on the uppermost surface 302 of the memory die. Forming the HBM component may include stacking each of the plurality of memory dies on the interface die and bonding the die stacks together. In various embodiments, the dies may be bonded by a plurality of solder structures, metal-metal bonds between conductive structures (e.g., segments of TSVs and the like), hybrid bonds (sometimes also referred to as direct bonds), die attach films, and / or the like.

[0053] As discussed above, the HBM test components may include a redistribution layer formed on the upper surface of the uppermost memory die, an additional passive die carried by and coupled to the uppermost memory die, and / or an additional active die carried by and coupled to the uppermost memory die. In embodiments with additional active dies, forming the HBM device at block 702 may include forming an active die with appropriate circuitry (e.g., a copy of critical circuitry in a related interface die, test circuitry, and / or the like).

[0054] At block 704, the process 700 includes attaching the HBM device to a base substrate (e.g., a silicon interposer, another organic interposer, an inorganic interposer, and / or any other suitable base substrate) of the SiP. Attaching the HBM device to the base substrate may include reflowing one or more solder structures between a lower (or inner) surface of the HBM device and the base substrate, forming one or more metal-metal bonds between the lower (or inner) surface and the base substrate, forming one or more hybrid bonds between the lower (or inner) surface and the base substrate, and / or the like. Thus, the attachment process may include applying heat and / or pressure to the HBM device, which may break bonds between dies formed therein and / or otherwise damage structures in the HBM device.

[0055] Thus, at block 706, process 700 includes accessing and testing the HBM device through an HBM test component at an outer surface of the HBM device. The testing process may include performing one or more read / write operations to store and retrieve data from a memory die, one or more data processing requests (e.g., in an interface die and / or an additional active die), and / or the like. Testing allows a processing unit (or other controller) to measure various test metrics, such as whether the HBM device operates properly (e.g., whether the HBM device produces an expected result and / or a given effect given an input), the speed at which the HBM device responds to a read / write request, the operating temperature of the HBM device, and / or any other suitable operating parameter. Thus, testing allows the processing unit to confirm that the HBM device meets one or more predetermined test metric requirements and / or is not damaged during the attachment process at block 704.

[0056] At optional block 708, process 700 includes disconnecting (or partially disconnecting) the HBM test component from the circuit (or other component) in the interface die. As discussed above, the disconnection may be implemented by a fuse, a fuse switch disconnector, a switch, a mask editable component, and / or any other suitable component coupled between the test TSV and the interface die. By way of example only, the processing unit may drive a current above a predetermined threshold through the fuse, thereby opening the fuse and disconnecting the test TSV from the interface die.

[0057] In some embodiments, process 700 skips optional block 708 and / or implements optional block 708 later in the process. For example, as discussed below, additional rounds of testing may be performed after mounting other components to the SiP to ensure that the additional attachment process does not cause damage to the HBM device beyond an acceptable level. In another example, the load applied to the interface die by the test TSV may be negligible and therefore a disconnection process is not required.

[0058] At block 710, process 700 includes attaching additional components of the SiP to a base substrate, such as a processing unit (eg, Figure 2 220), additional HBM devices, and / or any other suitable components. Similar to process 700 at block 704, the attachment at block 710 may include reflowing one or more solder structures, forming one or more metal-metal bonds, forming one or more hybrid bonds, and / or the like. Thus, the attachment process may include applying heat and / or pressure in the vicinity of the HBM device, which may break the bonds between the dies formed therein and / or otherwise damage structures in the HBM device. Thus, in some embodiments, process 700 may return to block 706 to access and test the HBM device via the HBM test assembly.

[0059] By testing the HBM device after each component of the SiP is individually attached, the process 700 can avoid performing manufacturing steps on the SiP device when the HBM device is damaged. For example, by testing the HBM device after attaching the HBM device to the base substrate, the process 700 can detect a faulty HBM device before attaching the processing unit to the base substrate. The detection can then simply replace the HBM device and / or save the processing unit (e.g., when the SiP must be discarded), thereby reducing manufacturing costs. However, it will be understood that in some embodiments, the process 700 may perform block 706 to test the HBM device only after all components of the SiP have been attached to the base substrate, thereby testing the HBM device only once. By delaying the test, the process 700 can help simplify the manufacturing process for each SiP device, thereby increasing the throughput of the manufacturing process.

[0060] From the foregoing, it will be understood that the specific embodiments of the present technology have been described herein for illustrative purposes, but the well-known structures and functions have not been shown or described in detail to avoid unnecessary confusion in the description of the embodiments of the present technology. To the extent that any material incorporated herein by reference conflicts with the present disclosure, the present disclosure shall prevail. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. In addition, unless the word "or" is explicitly limited to only a single item and excludes other items when it comes to a list of two or more items, the use of "or" in this list should be interpreted as including any single item in the (a) list, all items in the (b) list, or any combination of items in the (c) list. In addition, as used herein, the phrase "and / or" as in "A and / or B" refers to A alone, B alone, and both A and B. In addition, the use of the terms "including", "comprising", "having" and "having" throughout the text means including at least the features so that any larger number of identical features and / or other features of additional types are not excluded. Additionally, the terms "substantially," "approximately," and "about" are used herein to mean within at least 10% of a given value or limit. By way of example only, an approximate ratio means within 10% of a given ratio.

[0061] Several implementations of the disclosed technology are described above with reference to the figures. A computing device on which the described technology may be implemented may include one or more central processing units, memory, input devices (e.g., keyboards and pointer devices), output devices (e.g., display devices), storage devices (e.g., disk drives), and network devices (e.g., network interfaces). Memory and storage devices are computer-readable storage media that can store instructions that implement at least part of the described technology. In addition, data structures and message structures may be stored or transmitted via data transmission media (e.g., signals on a communication link). Therefore, computer-readable media may include computer-readable storage media (e.g., "non-transitory" media) and computer-readable transmission media.

[0062] It will also be appreciated that various modifications may be made without departing from the disclosure of the present disclosure or the present technology. For example, the interface die of the HBM device may be positioned in any other suitable location in the stack. In another example, the HBM test process may be implemented only after all components of the SiP device are attached to the base substrate (e.g., rather than after each attachment). In addition, one of ordinary skill in the art will appreciate that the various components of the present technology may be further divided into subcomponents, or the various components and functions of the present technology may be combined and integrated. In addition, certain aspects of the present technology described in the context of a particular embodiment may also be combined or eliminated in other embodiments.

[0063] In addition, although the advantages associated with certain embodiments of the present technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily need to exhibit such advantages to fall within the scope of the present technology. Therefore, the present disclosure and associated technology may encompass other embodiments not explicitly shown or described herein.

Claims

1. A high bandwidth memory HBM device, comprising: First bare film; a plurality of second dies carried by the first die, the plurality of second dies including an uppermost die, wherein each of the plurality of second dies is communicatively coupled to the first die through a plurality of active through substrate vias (TSVs); as well as An HBM test assembly is carried at least in part by an upper surface of the uppermost die and is positioned to be communicatively coupled to the first die.

2. The HBM device according to claim 1, wherein the HBM test assembly comprises: a redistribution layer carried by the upper surface of the uppermost die; a test TSV extending from the redistribution layer to an active circuit region of the first die to be communicatively coupled to one or more test circuits in the active circuit region; and A bond pad is carried by an outermost surface of the redistribution layer, wherein the bond pad is communicatively coupled to the redistribution layer to provide access to the one or more test circuits in the active circuit area at the outermost surface.

3. The HBM device according to claim 1, wherein the HBM test assembly comprises: a through die carried by the upper surface of the uppermost die, wherein the through die comprises a redistribution layer and an outermost surface; a test TSV extending from the redistribution layer of the through-die to an active circuit region of the first die to be communicatively coupled to one or more test circuits in the active circuit region; and Bond pads are carried by the outermost surface of the through-die, wherein the bond pads are communicatively coupled to the redistribution layer to provide access to the one or more test circuits in the active circuit area at the outermost surface.

4. The HBM device of claim 1 , wherein the first die comprises a plurality of active circuits, and wherein the HBM test assembly comprises: a test die carried by the upper surface of the uppermost die, the test die including a replica of the plurality of active circuits in the first die; and bond pads carried by an outermost surface of the test die, wherein the bond pads are communicatively coupled to the copies of the plurality of active circuits to provide access to the copies of the plurality of active circuits at the outermost surface, in: The plurality of active TSVs extend from a first metallization layer in the first die to a second metallization layer in the test die; and Each of the plurality of second dies is further communicatively coupled to the test die through the plurality of active TSVs to establish a communication path between the copies of the plurality of active circuits and the plurality of second dies.

5. The HBM device of claim 4, wherein the test die includes a copy of each active component in the first die.

6. The HBM device of claim 4 , wherein the HBM test assembly further comprises a test TSV extending from the first metallization layer to the second metallization layer to communicatively couple between one or more test circuits in the first die and the test die to provide access to the one or more test circuits at the outermost surface.

7. The HBM device according to claim 1, wherein the HBM test assembly comprises: a test TSV extending from a metallization layer in the first die to a height above the upper surface of the uppermost die; and A fuse is communicatively coupled between the test TSV and the metallization layer. The HBM device of claim 7 , wherein the fuse is open.

9. The HBM device according to claim 1, wherein the HBM test assembly comprises: a test TSV extending from a metallization layer in the first die to a height above the upper surface of the uppermost die; and A fuse switch is communicatively coupled between the test TSV and the metallization layer.

10. A system-in-package SiP device, comprising: Interposer substrate; a processing unit carried by the interposer substrate; and a high bandwidth memory HBM device carried by the interposer substrate, wherein the HBM device is coupled to the processing unit through an interposer bus, and wherein the HBM device comprises: an interface die carried by the interposer substrate; a plurality of memory dies carried by the interface die, wherein the plurality of memory dies are communicatively coupled to the interface die; and An HBM test component is carried at least in part by an upper surface of an uppermost memory die, the HBM test component being positioned to be communicatively coupled to the interface die to provide access to the interface die at an uppermost surface of the HBM device.

11. The SiP device of claim 10 , wherein the plurality of memory dies are communicatively coupled to the interface die by a plurality of signal through substrate vias (TSVs) extending from the interface die to a first height within the uppermost memory die, and wherein the HBM test assembly includes access TSVs extending from the interface die to a second height at or above the upper surface of the uppermost memory die.

12. The SiP device of claim 10 , wherein the HBM test component comprises an access through substrate via (TSV) extending from the interface die to a height at or above the upper surface of the uppermost memory die, the access TSV being positioned to be communicatively coupled to one or more test circuits in the interface die.

13. The SiP device of claim 10, wherein the HBM test assembly comprises an additional die carried by the upper surface of the uppermost memory die and access through substrate vias (TSVs) extending from the interface die into a height within the additional die.

14. The SiP device of claim 13, wherein the HBM test assembly further comprises one or more bond pads carried by an outer surface of the additional die and one or more redistribution layers communicatively coupling the one or more bond pads to the access TSVs.

15. The SiP device of claim 10, wherein the HBM test assembly comprises one or more redistribution layers formed on the upper surface of the uppermost memory die.

16. A method for manufacturing a system-in-package (SiP) device, comprising: A high bandwidth memory (HBM) device is formed, the HBM device comprising: Interface die; a plurality of memory dies; and an HBM test assembly accessible at an outer surface of the HBM device; attaching an inner surface of the HBM device to an interposer; Accessing one or more circuits in the HBM device through the HBM test component to test one or more test metrics of the HBM device; and One or more additional components are attached to the interposer. 17 . The method of claim 16 , further comprising disconnecting the HBM test component from the one or more circuits after accessing the one or more circuits to test the one or more test metrics. 18 . The method of claim 17 , wherein disconnecting the HBM test component comprises overdriving a fuse communicatively coupled between the HBM test component and the one or more circuits.

19. The method of claim 17, wherein forming the HBM device comprises: forming the HBM test assembly on an upper surface of an uppermost memory die from among the plurality of memory die; and The plurality of memory dies are stacked on the interface die with the uppermost memory die on top.

20. The method of claim 17, wherein forming the HBM memory comprises: stacking the plurality of memory dies on the interface die; and stacking an additional die on an uppermost memory die from the plurality of memory die, Wherein the additional die includes at least one redistribution layer that communicatively couples bond pads on an outermost surface of the additional die to through-substrate via structures in the additional die.

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