A compensation method, system, medium and product based on a crystal back compensation model

Abstract

The present invention relates to the field of semiconductor technology, and particularly relates to a compensation method, system, medium and product based on a backside compensation model, including: obtaining a stack parameter combination of a first stack layer, which includes: a first data type, which includes: the thickness and size of the first stack layer, and the size of the crystal grains; a second data type, which includes: the first grinding thickness of the uppermost wafer layer of the first stack layer, and the first curvature of the first stack layer; inputting the stack parameter combination into a pre-constructed backside compensation model, and correspondingly obtaining the second grinding thickness of the next wafer layer. The compensation method provided by the present invention can perform gradient correction on the grinding thickness based on the type of semiconductor device and the current stacking state.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly relates to a compensation method, system, medium and product based on a backside compensation model. Background Art

[0002] Integrated circuits in semiconductor devices are generally fabricated on a wafer and then diced into individual small dies. Due to the need for mass production to reduce costs, the size of wafers has gradually developed from the early 4-inch and 6-inch to 8-inch, 12-inch, and even 16-inch. Also, after the integrated circuits are completed, backside grinding is often required and then diced into dies, and the thickness of the dies can be reduced to meet the specification requirements of high-density or thin packaging. The yield of wafers is crucial for the working performance of semiconductor devices. However, the wafers are prone to form edge bending problems during the production stacking process, which will lead to an increase in defects on the wafers.

[0003] Referring to the patent application "Optimization Method for Wafer Bending Degree" with the application publication number CN108110043A, it discloses an optimization method for wafer bending degree. The method is as follows: providing a wafer, a front surface of the wafer is formed with a front surface SiN, and a back surface of the wafer is formed with a backside SiN, and the front surface SiN and the backside SiN are formed in the same furnace tube process; processing the front surface of the wafer to form a protective layer resistant to acid solution corrosion on the front surface; under the protection of the protective layer, using an acid solution to remove at least a part of the backside SiN. This method adjusts the bending degree of the wafer, and then hopes to improve the quality of subsequent bonding and other process steps by reducing the adjustment of the wafer bending degree.

[0004] However, the applicant notices that although the traditional solutions have optimized the wafer processing technology, with the continuous development of semiconductor technology, especially when the number of wafer layers of semiconductor devices reaches a certain number and the circuit structure on the wafers becomes more and more complex, it is still very easy to generate bending on the edges and thus cause defects.

[0005] Therefore, there is a need for a method that can reduce bending defects during the stacking process. Summary of the Invention

[0006] The purpose of the present invention is to provide a compensation method and system for backside grinding, which can partially solve or alleviate the above deficiencies in the prior art, and can control the degree of bending deformation during the stacking process through gradient grinding thickness adjustment.

[0007] In order to solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions:

[0008] In a first aspect of the present invention, there is provided a compensation method for backside grinding, including:

[0009] S101, Stack at least one first wafer layer on the layer to be stacked to form a first stacked layer; wherein, the wafer layer includes: multiple columns of die arranged at intervals;

[0010] S102, Monitor at least one first bending value and at least one second bending value of the first stacked layer in a first target area and a second target area respectively; wherein, the first target area is located in the peripheral area of the wafer layer, the second target area is located in the central area of the wafer layer, and there is an intermediate area between the first target area and the second target area, and multiple columns of die are arranged around the intermediate area;

[0011] S103, Use a first discrimination model to calculate a grinding compensation index based on the first bending value and the second bending value; wherein, the first discrimination model includes:

[0012] L1 = aX 1 + bY 1 ; wherein, L1 is the grinding compensation index, a is the first weight, b is the second weight, X 1 is the first bending degree, Y 1 is the second bending degree; wherein, the first bending degree is the eigenvalue of the at least one first bending value, the second bending degree is the eigenvalue of the at least one second bending value, and the eigenvalue includes one or more of the following types: average value, median, mode or maximum value;

[0013] S104, When the grinding compensation index is greater than a set first compensation threshold, reduce the grinding thickness of the next layer of the wafer layer.

[0014] In some embodiments, it further includes the step:

[0015] S105, Stack at least one second wafer layer on the first stacked layer to obtain a second stacked layer;

[0016] S106, Monitor at least one third bending value and / or at least one fourth bending value of the second stacked layer in the first target area and / or the second target area respectively;

[0017] S107, Use a second discrimination model to calculate a bending trend based on at least one set of bending values; wherein, the second discrimination model includes:

[0018] L2 = α(X 2 - X 1 ) / t + β(Y 2 - Y 1 ) / t; wherein, L2 is the bending trend, α is the third weight, β is the fourth weight, X 1 、X 2The first bending degrees of the first wafer layer and the second wafer layer are Y 1、 Y 2 The second bending degrees of the first wafer layer and the second wafer layer respectively; t is the interval time between two monitors;

[0019] S108. When the bending trend is greater than a set bending threshold, reduce the grinding thickness of the next wafer layer.

[0020] In some embodiments, it further includes the steps of:

[0021] S109. Obtain the exceeding index at which the bending trend exceeds the bending threshold within the first time period. The exceeding index can be the exceeding frequency or the exceeding duration;

[0022] S110. When the exceeding index is greater than a preset first exceeding threshold, correct the first discrimination model.

[0023] In some embodiments, the step of correcting the first discrimination model includes:

[0024] Increase the value of the first weight and / or decrease the value of the second weight.

[0025] In some embodiments, the grinding thickness of the second wafer layer is less than or equal to the grinding thickness of the first wafer layer.

[0026] In some embodiments, the calculation model of the grinding thickness of the current wafer layer includes:

[0027] Th n =Th n-1 +λ; where Th n is the grinding thickness of the current wafer layer, Th n-1 is the grinding thickness of the previous wafer layer, and λ is a preset compensation thickness.

[0028] In some embodiments, after the step of reducing the grinding thickness of the next wafer layer, it further includes:

[0029] S111. Use the second discrimination model to calculate the first bending trend in the first time period and the second bending trend in the second time period respectively;

[0030] S112. Determine whether the difference between the second bending trend and the first bending trend belongs to a set threshold range. If not, send a corresponding prompt signal.

[0031] The present invention also provides a compensation system for back grinding of wafers, including:

[0032] The first stacking module is used to stack at least one layer of the first wafer layer on the layer to be stacked to form a first stacked layer; wherein, the wafer layer includes: multiple columns of die arranged at intervals;

[0033] The first monitoring module is used to monitor at least one first bending value and at least one second bending value of the first stacked layer in a first target area and a second target area respectively; wherein, the first target area is located in the peripheral area of the wafer layer, the second target area is located in the central area of the wafer layer, and there is an intermediate area between the first target area and the second target area, and multiple columns of die are arranged around the intermediate area;

[0034] The first discrimination module is used to calculate a grinding compensation index according to the first bending value and the second bending value by using a first discrimination model; wherein, the first discrimination model includes:

[0035] L1 = aX 1 + bY 1 ; wherein, L1 is the grinding compensation index, a is the first weight, b is the second weight, X 1 is the first bending degree, Y 1 is the second bending degree; wherein, the first bending degree is the eigenvalue of the at least one first bending value, the second bending degree is the eigenvalue of the at least one second bending value, and the eigenvalue includes one or more of the following types: average value, median, mode or maximum value;

[0036] The compensation module is used to reduce the grinding thickness of the next layer of the wafer layer when the grinding compensation index is greater than a set first compensation threshold.

[0037] In some embodiments, it includes:

[0038] The second stacking module is used to stack at least one layer of the second wafer layer on the first stacked layer to obtain a second stacked layer;

[0039] The second monitoring module is used to monitor at least one third bending value and / or at least one fourth bending value of the second stacked layer in the first target area and / or the second target area respectively;

[0040] The second discrimination module is used to calculate a bending trend according to at least one set of bending values by using a second discrimination model; wherein, the second discrimination model includes:

[0041] L2 = α(X 2 - X 1 ) / t + β(Y 2 - Y 1 ) / t; wherein, L2 is the bending trend, α is the third weight, β is the fourth weight, X 1 、X2 The first bending degrees of the first wafer layer and the second wafer layer respectively, Y 1、 Y 2 The second bending degrees of the first wafer layer and the second wafer layer respectively; t is the time interval between two monitors;

[0042] A bending trend determination module, configured to reduce the grinding thickness of the next layer of the wafer layer when the bending trend is greater than a set bending threshold.

[0043] In some embodiments, it further includes:

[0044] An over - index determination module, configured to obtain an over - index when the bending trend exceeds the bending threshold within a first time period, and the over - index may be the frequency of exceeding or the duration of exceeding;

[0045] A model correction module, configured to correct the first discrimination model when the over - index is greater than a preset first over - threshold.

[0046] Beneficial technical effects:

[0047] To address the possible edge curling problem during the stacking process, the present invention provides a solution for rolling - type adjustment of the grinding thickness of grains based on partition detection of the bending degree (i.e., a gradient - type adjustment solution based on partition detection). Specifically, the present invention comprehensively analyzes the bending values (i.e., the degree of deformation) of the edge regions with relatively high stress and the central regions affected by the stress at the edges and the wafer layer size, so as to comprehensively evaluate the bending deformation degree through distributed point - position measurement, and timely determine whether it is necessary to initiate correction of the grinding thickness of the grains.

[0048] Furthermore, to avoid excessive delay in the gradient adjustment solution, a collaborative evaluation will also be performed through the bending change trend to advance the correction of the grinding thickness as much as possible in the early stage when the bending deformation rapidly expands. And this evaluation of the bending deformation trend is also beneficial for evaluating the timeliness of the first discrimination model. For example, if it is detected that the bending deformation trend is too large, the first discrimination model can also be adjusted in reverse.

[0049] Furthermore, after correcting the grinding thickness based on the evaluation result of the first or second discrimination model, it is also possible to detect the change in the bending trend after correction to determine whether the correction result is reliable through the change in the bending trend.

[0050] Furthermore, for this gradient adjustment scheme based on partition detection, the present invention also provides a backside compensation model. This backside compensation model comprehensively analyzes the critical factors such as the thickness of the stacked layer, the grinding thickness of the upper layer of grains, and the curvature (i.e., the overall thickness of the semiconductor at present, the grinding thickness in the previous gradient interval, and the main dimensions such as the degree of deformation), as well as the type of semiconductor device (such as the grain size, the size of the stacked layer) to predict the grinding thickness of the next gradient for the corrected grinding thickness.

[0051] In other words, the present invention collaboratively processes the bending situation of the semiconductor by the stacking type of the semiconductor device and the current stacking state of the semiconductor device, so as to perform a gradient adjustment of the precise grinding thickness for a specific semiconductor type. Thus, by utilizing the gradient-limited grinding thickness adjustment, the overall yield of the semiconductor device is improved. And this limited grinding thickness adjustment can, on the one hand, reduce the difficulty of the grinding process (that is, make the grinding process as unified as possible), and at the same time can avoid the overall grinding thickness being too small to avoid the increase of defects in a single grain due to the change of the grinding process.

[0052] Preferably, in the present invention, the backside compensation model is only activated to correct the grinding thickness when it is monitored that the gradient adjustment needs to be started. This staged correction can also reduce the frequency of grinding correction to simplify the correction process. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale. Obviously, the following-described drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0054] Figure 1 Schematic structural diagram of a wafer layer in an exemplary embodiment of the present invention;

[0055] Figure 2 Schematic diagram of the structural disassembly of a packaging system in an exemplary embodiment of the present invention;

[0056] Figure 3 Top view structural diagram of a packaging system in an exemplary embodiment of the present invention;

[0057] Figure 4 Schematic diagram of the bending data of a packaging system in an exemplary embodiment;

[0058] Figure 5Schematic diagram of the method flow in an exemplary embodiment of the present invention;

[0059] Figure 6 Schematic diagram of the method flow in another exemplary embodiment of the present invention.

[0060] Reference numerals: first target area 10, intermediate area 20, second target area 30, crystal grain 40; first measurement point 11, second measurement point 31; mother wafer 01, first stacking portion 02, first edge crystal grain 021, first central crystal grain 023, first spaced crystal grain 022; second stacking portion 03, second edge crystal grain 031, second central crystal grain 033, second spaced crystal grain 032, center point O. Detailed implementation manners

[0061] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0062] In this article, suffixes such as "module", "component", or "unit" used to represent elements are only for the convenience of describing the present invention, and have no specific meaning in themselves. Therefore, "module", "component", or "unit" can be used interchangeably.

[0063] In this article, terms such as "upper", "lower", "inner", "outer", "front", "rear", "one end", "the other end", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0064] In this article, unless otherwise clearly specified and limited, terms such as "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0065] In this article, "and / or" includes any and all combinations of one or more of the listed related items.

[0066] As used herein, "a plurality of" means two or more, i.e., it includes two, three, four, five, etc.

[0067] As used in this specification, the term "about" typically represents + / - 5% of the value, more typically + / - 4% of the value, more typically + / - 3% of the value, more typically + / - 2% of the value, even more typically + / - 1% of the value, and even more typically + / - 0.5% of the value.

[0068] In this specification, certain embodiments may be disclosed in a format within a certain range. It should be understood that this description of "within a certain range" is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and the individual numerical values within this range. For example, the description of the range 1 - 6 should be regarded as having specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as the individual numbers within this range, such as 1, 2, 3, 4, 5, and 6. The above rules apply regardless of the breadth of the range.

[0069] As used herein, a wafer refers to a silicon wafer used for fabricating silicon semiconductor circuits. A "die" can be a small piece cut from a wafer and is also referred to as a "Die". A "die" with a circuit structure processed thereon can also be referred to as a "chip".

[0070] Generally, it is necessary to stack a plurality of dies to package them into a complete semiconductor device. For example, on a mother wafer (for example, it can be a packaging substrate, i.e., Substrate (abbreviated as SUB)), or it can be a packaging substrate with multiple wafer layers stacked in sequence. Among them, one wafer layer includes a plurality of dies). Among them, when the number of stacked layers gradually increases, the packaging structure may curl due to the accumulation of tension, thereby generating defects and reducing the yield, as Figure 4 shown. The first curve S2 and the second curve S3 respectively show schematic diagrams of the bending values of different layers in an exemplary semiconductor device.

[0071] In this regard, it may be necessary to reduce the grinding thickness on the back side of the die (i.e., perform a back grinding operation on the die). For example, the thickness of the die after production and processing is approximately 700 - 800 μm, and it may be necessary to perform back grinding on it during the stacking process to reduce its thickness to approximately 70 - 80 μm.

[0072] Currently, a standardized backside grinding treatment method is usually adopted, that is, a standardized grinding thickness is used to uniformly process multiple layers of grains. However, the applicant has noticed that when the number of layers of semiconductor devices is too large and the area of the wafer layer is relatively large, there are still relatively large problems in overall reliability and yield with this standardized treatment method.

[0073] In response to this, contrary to the traditional standardized process, the present application proposes a rolling differential grinding compensation scheme for a multi-layer packaging structure. This rolling grinding compensation scheme can perform compensation processing on the grinding thickness of grains in different layer regions, and this differential compensation processing can avoid the grinding thickness from becoming too small, increasing the difficulty of the grinding process (it should be noted that the smaller the thickness of the grains, the more defects are likely to occur during the preparation process, and the higher the technical requirements for the grinding process).

[0074] In this article, different terms are used for the curling situation of the stacked structure, such as "curvature" and "degree of curvature", mainly to facilitate the distinction of different compensation systems in different embodiments. In the embodiments of the present invention, the degree of curvature or curvature is mainly a characterization index used to describe the curling deformation degree of the stacked structure. For example, it can be the upward deformation degree or downward deformation degree at different diameter positions, or it can be the bending angle at different positions. As long as it can characterize the bending deformation degree, it can be applicable to the present invention and should also be within the protection scope of the present invention.

[0075] Embodiment 1

[0076] See Figure 5 As shown, the present invention provides a compensation method for backside grinding, including:

[0077] S101, stacking at least one first wafer layer on the layer to be stacked to form a first stacked layer; wherein, the wafer layer includes: multiple columns of grains arranged at intervals;

[0078] In some embodiments, the layer to be stacked includes: a mother wafer, and multiple wafer layers provided on the mother wafer.

[0079] In particular, in some embodiments, at the initial moment of stacking, the layer to be stacked refers to the mother wafer.

[0080] In some embodiments, the wafer layer includes: at least one layer of grains. In particular, the wafer layer includes: one layer of grains, that is, when stacking each new layer of grains, data such as its current bending value can be collected.

[0081] S102. Monitor at least one first bending value and at least one second bending value of the first stacked layer in the first target area and the second target area respectively; wherein, the first target area is located in the peripheral area of the wafer layer, the second target area is located in the central area of the wafer layer, and there is an intermediate area between the first target area and the second target area, and multiple columns of grains are arranged around the intermediate area.

[0082] See Figure 3 , multiple grains are successively stacked on the master wafer 01, and in the direction from the edge of the master wafer to the center point O, a first target area 10, an intermediate area 20, and a second target area 30 are successively arranged, and multiple columns of grains 40 are respectively arranged in each area.

[0083] In some embodiments, a column of grains refers to a circle of grains arranged around the center point O. Alternatively, in some embodiments, a column of grains refers to a row of grains arranged along the radial direction of the master wafer or along a direction parallel to the radial direction.

[0084] Preferably, the measurement scheme of the bending value is as Figure 1 shown. Select multiple first measurement points 11 on the first target area 10 and multiple second measurement points 31 on the second target area 30. Among them, the bending value of the measurement point is the distance between this point and the reference line S, such as the first bending value Z2 and the second bending value Z1. Among them, the reference line S can be a straight line where the ideal positions corresponding to multiple measurement points are located in the ideal state where the grains do not curl during the stacking process, or the reference line can be set by the user himself / herself, as long as it can be used to standardize the relative bending degree of the measurement points at different positions.

[0085] For example, the bending degree can be the difference between the ordinate of the measurement point and the standard line. Take any straight line (or a straight line parallel or approximate to it) in the plane where the master wafer is located at the initial moment as the abscissa, and take any straight line in the direction perpendicular to it as the ordinate.

[0086] S103. Calculate the grinding compensation index according to the first bending value and the second bending value by using the first discrimination model; wherein, the first discrimination model includes:

[0087] L1 = aX 1 + bY 1 ; wherein, L1 is the grinding compensation index, a is the first weight, b is the second weight, X 1 is the first bending degree, Y 1 is the second bending degree; wherein, the first bending degree is the eigenvalue of the at least one first bending value, the second bending degree is the eigenvalue of the at least one second bending value, and the eigenvalue includes one or more of the following types: average value, median, mode or maximum value.

[0088] Preferably, the average value of the plurality of bending values corresponding to the plurality of first measurement points 11 can be calculated. Preferably, the bending value can take an absolute value.

[0089] In particular, when there is only one bending value, the degree of bending can be directly characterized by the bending value.

[0090] S104. When the polishing compensation index is greater than the set first compensation threshold, the polishing thickness of the next layer of the wafer layer is reduced.

[0091] That is to say, in this embodiment, when the polishing compensation index measured by combining the first target area and the second target area is large, preferably, the polishing thickness of the next layer of the wafer layer is reduced to control the overall degree of bending deformation.

[0092] In some embodiments, it further includes the steps:

[0093] S105. Stack at least one second wafer layer on the first stacked layer to obtain a second stacked layer; similarly, the second wafer layer includes a plurality of die.

[0094] S106. Monitor at least one third bending value and / or at least one fourth bending value of the second stacked layer in the first target area and / or the second target area respectively.

[0095] S107. Use a second discrimination model to calculate the bending trend according to at least one set of bending values; wherein, the second discrimination model includes:

[0096] L2 = α(X 2 - X 1 ) / t + β(Y 2 - Y 1 ); wherein, L2 is the bending trend, α is the third weight, β is the fourth weight, X 1 , X 2 are the first bending degrees of the first wafer layer and the second wafer layer respectively, Y 1、 , Y 2 are the second bending degrees of the first wafer layer and the second wafer layer respectively; t is the time interval between two monitors.

[0097] S108. When the bending trend is greater than the set bending threshold, the polishing thickness of the next layer of the wafer layer is reduced.

[0098] Preferably, in some embodiments, the bending values of the first target area and the second target area at multiple moments are synchronously used to calculate their change trend over a period of time.

[0099] For example, in some embodiments, for the convenience of unified comparison, the degree of bending is taken as a positive value. When the wafer layer includes a single layer of die, the first degree of bending X is correspondingly calculated 1 , and the first degree of bending X of the second wafer layer 2 , and the second degree of bending Y of the first wafer layer and the second wafer layer is correspondingly calculated 1、 Y 2 . Among them, the third weight and the fourth weight can be independently set by the user, and t is the difference between the corresponding measurement times of the first wafer layer and the second wafer layer. In this embodiment, when the bending difference between two measurements is large, a new compensation correction will continue to be performed on the next wafer layer, that is, the grinding thickness of the next wafer layer will continue to be reduced.

[0100] That is to say, in this embodiment, the second discrimination model can actually be used to calculate the first degree of bending of the first wafer layer at the first moment and the first degree of bending of the second wafer layer at the second moment to compare the change of the degree of bending.

[0101] In some embodiments, at least one set of bending values includes: the first degree of bending of the first wafer layer and the second wafer layer; and / or, the second degree of bending of the first wafer layer and the second wafer layer.

[0102] For example, in some embodiments, the degree of bending is also taken as a positive number. When the wafer layer includes multiple layers of die, correspondingly, when measuring the first wafer layer, the bending values of multiple layers of die will be correspondingly obtained, and the degree of bending can be the characteristic value of the degree of bending at multiple moments.

[0103] Preferably, the characteristic value of the degree of bending can be the average value, median, average value or maximum value of multiple bending values; or, the characteristic value of the degree of bending can also be the difference between the initial measurement moment and the end measurement moment during a measurement process. That is, the time factor is further introduced into the degree of bending, which can describe the bending change trend of the wafer layer over a period of time. Correspondingly, when the difference in the bending change trends of the first and second wafer layers is small, the corrected grinding thickness is considered to be reliable; on the contrary, when the difference between the two is large, a new compensation correction will continue to be performed on the next wafer layer, that is, the grinding thickness of the next wafer layer will continue to be reduced.

[0104] For example, in some embodiments, the first wafer layer and the second wafer layer can be two adjacent wafer layers. Or, at least one third wafer layer can be interposed between them.

[0105] For example, in some embodiments, the first discrimination model or the second discrimination model can be used independently to judge whether to start the correction step of the grinding thickness.

[0106] In some embodiments, it further includes the steps of:

[0107] S109. Obtain an exceeding index indicating that the bending trend exceeds the bending threshold within the first time period. The exceeding index can be the frequency of exceeding or the duration of exceeding. For example, a corresponding exceeding signal can be sent to prompt the user to pay attention to whether the current compensation process is reliable.

[0108] S110. When the exceeding index is greater than a preset first exceeding threshold, correct the first discrimination model.

[0109] In some embodiments, the step of correcting the first discrimination model includes:

[0110] Increase the value of the first weight and / or decrease the value of the second weight.

[0111] Preferably, the first weight and the second weight can have an initial value set by the user or set by default. As the stacking process gradually changes, feedback adjustment can be performed on them in combination with the correction effect.

[0112] Preferably, when exceeding signals indicating that the bending trend exceeds the bending threshold are frequently detected within a long time, such as the number of exceeding signals is greater than a set number or the duration of the exceeding signal exceeds a set duration, the weight relationship of the first discrimination model will be adjusted.

[0113] In this embodiment, through the evaluation of the bending trend, the applicability of the first discrimination model can also be adjusted before compensation correction. For example, when the bending degree increases rapidly and the first discrimination model has not made a feedback yet, its weight setting will be adjusted to improve the sensitivity of the first discrimination model. Thus, through the pre-adjustment of sensitivity, excessive delay in compensation adjustment can be avoided.

[0114] In some embodiments, the grinding thickness of the second wafer layer is less than or equal to the grinding thickness of the first wafer layer.

[0115] In some embodiments, the calculation model of the grinding thickness of the current wafer layer includes:

[0116] Th n = Th n-1 + λ; where Th n is the grinding thickness of the current wafer layer, Th n-1 is the grinding thickness of the upper wafer layer, and λ is a preset compensation thickness.

[0117] For example, if Th n-1 is the grinding thickness of the first wafer layer, then Th nis the grinding thickness of the second wafer layer.

[0118] For example, in some embodiments, the compensation thickness may have a preset default reference value. For example, for semiconductor devices of different thicknesses and sizes, it may combine the user's engineering experience or historical stacking data to set the corresponding default compensation thickness. Or, the compensation thickness can also be obtained by AI calculation based on a compensation model.

[0119] In some embodiments, after the step of reducing the grinding thickness of the next wafer layer, it further includes:

[0120] S111, using the second discrimination model to calculate the first bending trend in the first time period and the second bending trend in the second time period respectively;

[0121] S112, determining whether the difference between the second bending trend and the first bending trend belongs to a set threshold range, if not, sending a corresponding prompt signal.

[0122] Preferably, in this embodiment, when the model is corrected in combination with the discrimination result of the first discrimination model, the correction reliability can also be verified by the continuous change of the bending trend.

[0123] Correspondingly, the present invention also provides a compensation system for back grinding of wafers, including:

[0124] A first stacking module for stacking at least one first wafer layer on a layer to be stacked to form a first stacked layer; wherein, the wafer layer includes: multiple columns of grains arranged at intervals;

[0125] A first monitoring module for monitoring at least one first bending value and at least one second bending value of the first stacked layer in at least one of a first target area and a second target area; wherein, the first target area is located in the peripheral area of the wafer layer, the second target area is located in the central area of the wafer layer, and there is an intermediate area between the first target area and the second target area, and multiple columns of grains are arranged around the intermediate area;

[0126] A first discrimination module for using a first discrimination model to calculate a grinding compensation index according to the first bending value and the second bending value; wherein, the first discrimination model includes:

[0127] L1 = aX 1 + bY 1 ; wherein, L1 is the grinding compensation index, a is the first weight, b is the second weight, X 1 is the first degree of bending, Y 1is the second degree of bending; wherein, the first degree of bending is an eigenvalue of the at least one first bending value, the second degree of bending is an eigenvalue of the at least one second bending value, and the eigenvalue includes one or more of the following types: average, median, mode or maximum value;

[0128] A compensation module, configured to reduce the grinding thickness of the next layer of the wafer layer when the grinding compensation index is greater than a set first compensation threshold.

[0129] In some embodiments, it further includes:

[0130] A second stacking module, configured to stack at least one second wafer layer on the first stacking layer to obtain a second stacking layer;

[0131] A second monitoring module, configured to monitor at least one third bending value and / or at least one fourth bending value of the second stacking layer in a first target area and / or a second target area respectively;

[0132] A second discrimination module, configured to calculate a bending trend according to at least one set of bending values by using a second discrimination model; wherein, the second discrimination model includes:

[0133] L2 = α(X 2 - X 1 ) / t + β(Y 2 - Y 1 ); wherein, L2 is the bending trend, α is the third weight, β is the fourth weight, X 1 , X 2 are respectively the first degrees of bending of the first wafer layer and the second wafer layer, Y 1、 Y 2 are respectively the second degrees of bending of the first wafer layer and the second wafer layer; t is the time interval between two monitors;

[0134] A bending trend determination module, configured to reduce the grinding thickness of the next layer of the wafer layer when the bending trend is greater than a set bending threshold.

[0135] In some embodiments, it further includes:

[0136] An over - index determination module, configured to obtain an over - index that the bending trend exceeds the bending threshold within a first time period, and the over - index may be the frequency of exceeding or the duration of exceeding;

[0137] A model correction module, configured to correct the first discrimination model when the over - index is greater than a preset first over - threshold.

[0138] Embodiment Two

[0139] See Figure 6 As shown, the present invention also provides a compensation method based on a backside compensation model, including:

[0140] S201. Obtain a stack parameter combination of a first stack layer, where the first stack layer includes: a master wafer, and at least one wafer layer disposed on the master wafer, and the wafer layer has a plurality of die. Correspondingly, the stack parameter combination includes:

[0141] A first data type, which includes: the thickness of the first stack layer (for example, the thickness of the first stack layer is the overall thickness of the master wafer and the wafer layer thereon), the size of the first stack layer (such as dimensions of the radius, diameter, etc. of the master wafer), the size of the die (such as dimensions of the radius, diameter, etc. of the die);

[0142] A second data type, which includes: the first grinding thickness of the uppermost wafer layer of the first stack layer (such as the thickness of the die), the first curvature of the first stack layer;

[0143] S202. Input the stack parameter combination into a pre-constructed backside compensation model, and correspondingly obtain the second grinding thickness of the next wafer layer; wherein, the steps of constructing the backside compensation model include:

[0144] S21. Obtain a training sample set, where the training sample set includes: a plurality of sample points, and the sample points are associated with a first historical stack parameter combination and a second historical stack parameter combination collected according to a historical stack layer. Among them, the historical stack layer includes: a first historical stack layer; a second historical stack layer obtained by stacking at least one historical wafer layer on the first historical stack layer; Correspondingly, the first historical stack parameter combination includes:

[0145] A first historical data type, which includes: the thickness of the first historical stack layer, the size of the historical stack layer, the size of the die;

[0146] A second historical data type, which includes: the first historical grinding thickness of the uppermost wafer layer of the first historical stack layer, the first historical curvature of the first historical stack layer;

[0147] The second historical stack parameter combination includes:

[0148] The second grinding thickness of the current at least one historical wafer layer, and the second historical curvature of the second historical stack layer;

[0149] In this embodiment, the difference between the first historical curvature and the second historical curvature can be used to evaluate the influence of the second historical stack layer on the subsequent layers.

[0150] That is to say, one sample point in this embodiment corresponds to a semiconductor device at one encapsulation moment.

[0151] S22. Input the training sample set into a neural network model to correspondingly obtain the back grinding compensation model. The input layer of the neural network model includes the first historical stacking parameter combination and the second historical curvature, and the output layer includes the second grinding thickness.

[0152] In some embodiments, according to different types of semiconductor devices (for example, semiconductor devices of different functional types or different size scales), different neural network models can be used for model training. For example, the selectable neural network models include BP neural network, fully connected neural network (FCN), deep feedforward neural network (DNN), etc.

[0153] In some embodiments, the back grinding compensation model can output the second grinding thickness under a specific bending adjustment degree. The bending adjustment degree (which is also equivalent to the bending adjustment speed) is the difference between the first curvature at the current moment and the predicted curvature (or the target curvature) at the next moment. At least one corrected wafer layer with the second grinding thickness is stacked on the first stacking layer to obtain the second stacking layer, and the predicted curvature of the second stacking layer is the second curvature.

[0154] It can be understood that the specific bending adjustment degree set in the model can be set by the user himself, and it can be used as the initial speed of the back grinding compensation model.

[0155] For another example, in some embodiments, the back grinding compensation model can also output multiple second grinding thicknesses corresponding to multiple bending adjustment degree conditions, and the user can freely select according to the multiple second grinding thicknesses.

[0156] In some embodiments, the curvature can be the first bending degree measured in the first target area.

[0157] Or, the curvature can also be the second bending degree measured in the second target area.

[0158] Or, the curvature can be the grinding compensation index obtained by synthesizing the first target area and the second target area.

[0159] Or, the curvature can also be multiple bending values of multiple measurement points in the first target area and the second target area, that is, the input combination of the back grinding compensation model also includes the bending values of multiple measurement points.

[0160] In some embodiments, it includes:

[0161] Modify the grinding thickness of the next wafer layer to the second grinding thickness (i.e., this wafer layer is also referred to as the modified wafer layer);

[0162] Stack the next wafer layer on the first stacked layer to obtain a second stacked layer correspondingly;

[0163] Monitor the second curvature of the second stacked layer (one or more);

[0164] Calculate the curvature change trend based on the first curvature and the second curvature;

[0165] When the curvature change trend is less than the set curvature trend, it is considered that the current second grinding thickness meets the compensation requirement.

[0166] For example, in some embodiments, for the convenience of unified calculation, the absolute value of the curvature is taken. During the actual stacking correction process, due to the relatively limited compensation amount, there may also be a certain delay in the adjustment of the curvature, that is, after reducing the grinding thickness of the next wafer layer, its curvature may still continue to increase. In this regard, calculate the difference in curvature before and after stacking (equivalent to the curvature change trend). When the difference between the curvature after stacking and the curvature at the previous moment is relatively small, it is considered that the curvature change trend decreases and the correction feedback is more effective. Otherwise, it is considered that the correction speed is too slow or the correction is invalid, and a prompt signal can be sent to the user for manual verification and checking.

[0167] Preferably, in some embodiments, the curvature trend can be the actual change trend of the curvature before correction.

[0168] Alternatively, in some other embodiments, the curvature trend can be set by the user himself.

[0169] In some embodiments, the curvature change trend can be calculated through the curvature of the edge region between two moments.

[0170] In some embodiments, a central grain, spaced grains, and edge grains are sequentially arranged in the region of the wafer layer from its center to the edge. The first historical stacking parameter combination further includes: a third historical data type, and the third historical data type includes: the historical aperture of the edge grains, the historical aperture of the spaced grains, and the historical aperture of the edge grains. That is, this historical aperture can also be used as the data of the input layer for model training. Correspondingly, the stacking parameter combination can further include: the historical aperture of the edge grains, the historical aperture of the spaced grains, and the historical aperture of the edge grains. That is to say, the backside compensation model in this embodiment can comprehensively estimate the optimized grinding thickness of the next layer of grains by combining the grinding thickness of the stacked grains and the via hole sizes of grains in different regions.

[0171] In some embodiments, the first historical stack parameter combination further includes: the historical column number of the edge grains, the historical column number of the spacer grains, and the historical column number of the edge grains. That is to say, in some embodiments, the above column numbers can also be used as the data of the input layer for model training.

[0172] The present invention also correspondingly provides a compensation system based on a backside compensation model, including:

[0173] A stack parameter acquisition module, configured to acquire a stack parameter combination of a first stack layer, where the first stack layer includes: a mother wafer, and at least one wafer layer disposed on the mother wafer, and the wafer layer has a plurality of grains. Correspondingly, the stack parameter combination includes:

[0174] A first data type, where the first data type includes: the thickness of the first stack layer, the size of the first stack layer, and the size of the grains;

[0175] A second data type, where the second data type includes: the first grinding thickness of the uppermost wafer layer of the first stack layer, and the first curvature of the first stack layer;

[0176] An input module, configured to input the stack parameter combination into a pre-constructed backside compensation model, and correspondingly obtain the second grinding thickness of the next wafer layer; where the backside compensation model is trained by using a model training module; where the model training module includes:

[0177] A sample set acquisition unit, configured to acquire a training sample set, where the training sample set includes: a plurality of sample points, and the sample points are associated with a first historical stack parameter combination and a second historical stack parameter combination collected according to a historical stack layer, where the historical stack layer includes: a first historical stack layer; a second historical stack layer obtained by stacking at least one historical wafer layer on the first historical stack layer; Correspondingly,

[0178] The first historical stack parameter combination includes: a first historical data type, which includes: the thickness of the first historical stack layer, the size of the historical stack layer, and the size of the grains; a second historical data type, which includes: the first historical grinding thickness of the uppermost wafer layer of the first historical stack layer, and the first historical curvature of the first historical stack layer;

[0179] The second historical stack parameter combination includes: the second grinding thickness of the current at least one historical wafer layer, and the second historical curvature of the second historical stack layer;

[0180] A training unit for inputting the training sample set into a neural network model for training, and correspondingly obtaining the backside compensation model; wherein, the input layer of the neural network model includes: the first historical stacking parameter combination, the second historical curvature, and the output layer includes: the second grinding thickness.

[0181] In some embodiments, it further includes: a monitoring module, and the monitoring module includes:

[0182] A correction unit for correcting the grinding thickness of the next wafer layer to the second grinding thickness;

[0183] A stacking unit for stacking the next wafer layer onto the first stacking layer to correspondingly obtain a second stacking layer;

[0184] A monitoring unit for monitoring the (one or more) second curvatures of the second stacking layer;

[0185] A trend calculation unit for calculating the bending change trend according to the (one or more) first curvatures and the (one or more) second curvatures;

[0186] An evaluation unit for determining that the current second grinding thickness meets the compensation requirement when the bending change trend is less than the set bending trend.

[0187] In some embodiments, a central grain, spaced grains, and edge grains are sequentially arranged in a region from the center to the edge of the wafer layer, and the first historical stacking parameter combination further includes: a third historical data type, and the third historical data type includes: the historical aperture of the edge grains, the historical aperture of the spaced grains, and the historical aperture of the edge grains.

[0188] In some embodiments, the first historical stacking parameter combination further includes: the historical number of columns of the edge grains, the historical number of columns of the spaced grains, and the historical number of columns of the edge grains.

[0189] In some embodiments, the apertures in different regions can be set differently.

[0190] See Figure 2 As shown, the semiconductor device includes:

[0191] A master wafer 01, on which a plurality of transmission interfaces (such as I / O interfaces) are spacedly arranged, and the transmission interfaces are used for electrically connecting to the through holes (such as TSVs, i.e., through-silicon vias) of the grains stacked thereon, and adjacent two layers of grains are electrically connected through the through holes;

[0192] The first stacking portion 02 disposed on the master wafer, wherein the first stacking portion 02 includes: multiple layers of first die layers, and one die layer includes: multiple die spaced apart; the first die layer includes: a first edge region arranged along the edge of the master wafer, and a first central region arranged along the central region of the master wafer, wherein at least one column of first edge dies 021 is provided in the first edge region, at least one column of first central dies 023 is provided in the first central region, and multiple columns of first spaced dies 022 are arranged at intervals between the first edge region and the first central region;

[0193] The second stacking portion 03 disposed on the first stacking portion, wherein the second stacking portion includes: multiple layers of second die layers, the second die layer includes: a second edge region arranged along the edge of the master wafer, and a second central region arranged along the central region, wherein at least one column of second edge dies 031 is provided in the second edge region, at least one column of second central dies 033 is provided in the second central region, and multiple columns of second spaced dies 032 are arranged at intervals between the second edge region and the second central region;

[0194] In this article, different nouns are used for the structural layers formed by one layer of dies, such as "die layer" and "wafer layer", mainly to facilitate the distinction of different stacking structures or semiconductor devices in different embodiments.

[0195] The present invention also provides a computer-readable storage medium, in which a program or instruction is stored, and when the program or instruction is run, the method in any one of the embodiments is implemented.

[0196] The present invention also provides a computer program product, in which a program or instruction is stored, and when the program or instruction is run, the method in any one of the embodiments is implemented.

[0197] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including that element.

[0198] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described example methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such an understanding, the technical solution of the present invention, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions for causing a computer terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of the present invention.

[0199] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the spirit of the present invention and the scope protected by the claims. All of these are within the protection scope of the present invention.

Claims

1. A compensation method based on a wafer back compensation model, characterized in that: include: S201, obtaining a stacking parameter combination of a first stacking layer, wherein the first stacking layer includes: a mother wafer, and at least one wafer layer disposed on the mother wafer, and the wafer layer has a plurality of crystal grains. Correspondingly, the stacking parameter combination includes: A first data type, the first data type comprising: a thickness of the first stacked layer, a size of the first stacked layer, and a size of the grain; A second data type, the second data type comprising: a first grinding thickness of the uppermost wafer layer of the first stacked layer, and a first curvature of the first stacked layer; S202, inputting the stacking parameter combination into a pre-constructed back surface compensation model, and correspondingly obtaining a second grinding thickness of the next wafer layer; wherein the step of constructing the back surface compensation model includes: S21, obtaining a training sample set, the training sample set comprising: a plurality of sample points, the sample points being associated with a first historical stacking parameter combination collected according to a historical stacking layer, and a second historical stacking parameter combination, wherein the historical stacking layer comprises: a first historical stacking layer; a second historical stacking layer obtained by stacking at least one historical wafer layer on the first historical stacking layer; correspondingly, the first historical stacking parameter combination comprises: The first historical data type includes: the thickness of the first historical stacking layer, the size of the historical stacking layer, and the size of the grain; Second historical data type: first historical grinding thickness of the uppermost wafer layer of the first historical stacking layer, first historical curvature of the first historical stacking layer; The second historical stacking parameter combination includes: a second grinding thickness of the at least one historical wafer layer, and a second historical curvature of the second historical stack layer; S22, inputting the training sample set into the neural network model for training, and obtaining the corresponding crystal back compensation model; wherein the input layer of the neural network model includes: the first historical stacking parameter combination, the second historical curvature, and the output layer includes: the second grinding thickness.

2. The compensation method based on the wafer back compensation model according to claim 1, characterized in that: include: Correcting the grinding thickness of the next wafer layer to the second grinding thickness; Stacking the next wafer layer onto the first stacking layer, and correspondingly obtaining a second stacking layer; monitoring a second curvature of the second stacked layer; Calculating a bending change trend according to the first curvature and the second curvature; When the bending change trend is smaller than the set bending trend, it is considered that the current second grinding thickness meets the compensation requirement.

3. The compensation method based on the wafer back compensation model according to claim 1, characterized in that: The wafer layer is provided with central grains, spacer grains and edge grains in sequence along the area from the center to the edge thereof, and the first historical stacking parameter combination also includes: a third historical data type, and the third historical data type includes: a historical aperture of the edge grains, a historical aperture of the spacer grains, and a historical aperture of the edge grains.

4. The compensation method based on the wafer back compensation model according to claim 3 is characterized in that: The first historical stacking parameter combination further includes: the historical column number of the edge grains, the historical column number of the spacer grains, and the historical column number of the edge grains.

5. A compensation system based on a wafer back compensation model, characterized in that: include: The stacking parameter acquisition module is used to acquire a stacking parameter combination of a first stacking layer, wherein the first stacking layer includes: a mother sheet, and at least one wafer layer arranged on the mother sheet, and the wafer layer has a plurality of grains. Correspondingly, the stacking parameter combination includes: A first data type, the first data type comprising: a thickness of the first stacked layer, a size of the first stacked layer, and a size of the grain; A second data type, the second data type comprising: a first grinding thickness of the uppermost wafer layer of the first stacked layer, and a first curvature of the first stacked layer; An input module is used to input the stacking parameter combination into a pre-built back surface compensation model, and correspondingly obtain the second grinding thickness of the next wafer layer; wherein the back surface compensation model is constructed by training with a model training module; wherein the model training module includes: The sample set acquisition unit is used to acquire a training sample set, wherein the training sample set includes: a plurality of sample points, wherein the sample points are associated with a first historical stacking parameter combination and a second historical stacking parameter combination collected according to a historical stacking layer, wherein the historical stacking layer includes: a first historical stacking layer; a second historical stacking layer obtained by stacking at least one historical wafer layer on the first historical stacking layer; and correspondingly, The first historical stacking parameter combination includes: The first historical data type includes: the thickness of the first historical stacking layer, the size of the historical stacking layer, and the size of the grain; A second historical data type, comprising: a first historical grinding thickness of the uppermost wafer layer of the first historical stacking layer, a first historical curvature of the first historical stacking layer; The second historical stacking parameter combination includes: a second grinding thickness of the at least one historical wafer layer, and a second historical curvature of the second historical stacking layer; A training unit is used to input the training sample set into a neural network model, and correspondingly obtain the crystal back compensation model; wherein the input layer of the neural network model includes: the first historical stacking parameter combination, the second historical curvature, and the output layer includes: the second grinding thickness.

6. The compensation system according to claim 5, characterized in that: Also includes: A monitoring module, the monitoring module comprising: A correction unit, used for correcting the grinding thickness of the next wafer layer to the second grinding thickness; A stacking unit, used for stacking the next wafer layer onto the first stacking layer, and correspondingly obtaining a second stacking layer; A monitoring unit, configured to monitor a second curvature of the second stacked layer; a trend calculation unit, configured to calculate a bending change trend according to the first curvature and the second curvature; The evaluation unit is used for considering that the current second grinding thickness meets the compensation requirement when the bending change trend is less than the set bending trend.

7. The compensation system according to claim 6, characterized in that The wafer layer is provided with central grains, spacer grains and edge grains in sequence along the area from the center to the edge thereof, and the first historical stacking parameter combination also includes: a third historical data type, and the third historical data type includes: a historical aperture of the edge grains, a historical aperture of the spacer grains, and a historical aperture of the edge grains.

8. The compensation system according to claim 7, characterized in that The first historical stacking parameter combination further includes: the historical column number of the edge grains, the historical column number of the spacer grains, and the historical column number of the edge grains.

9. A computer-readable storage medium, characterized in that: The storage medium stores a program or an instruction, and when the program or the instruction is executed, the method according to any one of claims 1 to 4 is implemented.

10. A computer program product, characterized in that The computer program product stores a program or an instruction, and when the program or the instruction is executed, the method according to any one of claims 1 to 4 is implemented.

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