Silicon carbide wafer level packaging structure and manufacturing method thereof

Abstract

The invention discloses a silicon carbide wafer level packaging structure and a manufacturing method thereof, the silicon carbide wafer level packaging structure comprises a silicon carbide chip, under-bump metal, a first insulating material, a second insulating material, a third insulating material, a first metal bump and a second metal bump, and the second metal bump is matched with an electrode metal structure on the lower surface of the silicon carbide chip. The outer end of the first metal bump is provided with a third metal bump, the outer end of the second metal bump is provided with a fourth metal bump, and the outer side of the silicon carbide chip is provided with a fourth insulating material. According to the invention, the size of the silicon carbide device is optimized, no connecting lead is arranged, stray inductance caused by packaging is low, the transmission speed is high, and the silicon carbide device is suitable for high-frequency application; the wafer-level operation is short in production cycle, packaging cost is saved, the distance between the chip and the pins is short, heat dissipation is good, lead heating is avoided, and the packaging structure is suitable for high-temperature working conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power device packaging, and more specifically, to a silicon carbide wafer-level packaging structure and a manufacturing method thereof. Background Art

[0002] The main component material of silicon carbide devices is silicon carbide. Compared with ordinary silicon materials, the breakdown field strength of silicon carbide can reach 3.5 (MV / cm), which is about 10 times that of silicon. Therefore, the thickness of the drift layer required for withstand voltage is reduced, and it has the characteristics of high withstand voltage, low on-resistance, and low on-thermal resistance. The thermal conductivity of silicon carbide can reach 4.0 (W / cm·K), which is about 3 times that of silicon. It is suitable for high temperature conditions. The saturated electron drift rate of silicon carbide can reach 2.0*10 7 (cm / s), which is about twice that of silicon, enabling high-frequency applications.

[0003] For silicon carbide devices, traditional packaging requires cutting the silicon carbide wafer into individual chips, then welding the chips to the substrate, welding the leads on the front of the chip, and then placing the chip in a mold for plastic sealing and curing, pin electroplating, and rib cutting and forming. This traditional packaging method has many steps, a lot of manual work, low efficiency, large stray inductance, slow heat dissipation and other problems. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the problems existing in the prior art, the present invention provides a silicon carbide wafer-level packaging structure and a manufacturing method thereof to solve the technical problems mentioned in the background technology.

[0006] (II) Technical solution

[0007] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a silicon carbide wafer-level packaging structure and a manufacturing method thereof. In the first aspect, the present invention provides a silicon carbide wafer-level packaging structure, including a silicon carbide chip, an under-bump metal is provided at the upper end of the silicon carbide chip, the under-bump metal cooperates with the electrode metal structure on the upper surface of the silicon carbide chip, a first insulating material is provided above the silicon carbide chip and on both sides of the under-bump metal, a second insulating material is provided at the upper end of the first insulating material, a third insulating material is provided at the lower end of the silicon carbide chip, and a first metal structure is provided at the upper end of the under-bump metal. A second metal bump is provided at the lower end of the silicon carbide chip, the second metal bump cooperates with the electrode metal structure on the lower surface of the silicon carbide chip, a third metal bump is provided at the outer end of the first metal bump, a fourth metal bump is provided at the outer end of the second metal bump, a fourth insulating material is provided on the outer side of the silicon carbide chip, the silicon carbide chip, the metal under the bump, the first insulating material, the second insulating material, the third insulating material, the first metal bump and the second metal bump are all located in the fourth insulating material, and the outer ends of the third metal bump and the fourth metal bump protrude from the fourth insulating material.

[0008] The present invention is further configured such that the constituent materials of the silicon carbide chip include silicon carbide MOSFET, silicon carbide diode, silicon carbide JFET, silicon carbide IGBT, silicon carbide BJT, silicon carbide GTO, and the thickness of the silicon carbide chip is 100-400um.

[0009] The present invention is further configured such that the metal material under the bump is titanium, nickel, vanadium, silver, nickel, gold or nickel, palladium, and gold, and if it is titanium, nickel, vanadium, and silver, the thickness of the metal titanium is less than 0.5um, the thickness of the metal nickel and vanadium is less than 1um, and the thickness of the metal silver is 1-10um; if it is nickel, gold or nickel, palladium, and gold, the thickness of the metal nickel is 1-10um, the thickness of the metal palladium is less than 1um, and the thickness of the metal gold is less than 0.5um.

[0010] The present invention is further configured such that the first insulating material is made of silicon oxide or silicon nitride with a thickness of 0.1-10 um, while the second insulating material and the third insulating material are made of baked and cured polyimide with a thickness of 10-200 um.

[0011] The present invention is further configured such that the metal material of the first metal bump and the second metal bump is copper with a thickness of 30-200um, and the metal material of the third metal bump and the fourth metal bump includes tin-lead alloy, tin-copper alloy, tin-silver alloy, tin-antimony alloy and tin-bismuth alloy with a thickness of 100-300um.

[0012] In a second aspect, the present invention provides a method for manufacturing a silicon carbide wafer-level packaging structure, the method comprising:

[0013] Step 1:

[0014] Prepare under-bump metallization on the silicon carbide chip by evaporation lift-off or chemical plating;

[0015] Step 2:

[0016] Then, a first insulating material is formed by depositing and photolithography etching on the front side of the wafer, and then a second insulating material is formed by spraying and photolithography baking and curing on the front side of the wafer, and a third insulating material is formed by spraying and photolithography baking and curing on the back side of the wafer;

[0017] Step 3:

[0018] The first metal bump and the second metal bump are respectively prepared on the front and back sides of the wafer by the electroplating stripping process, and then the third metal bump and the fourth metal bump are prepared on the front and back sides of the wafer by the laser ball implantation process or the pillar implantation process.

[0019] Step 4:

[0020] The wafer is cut into individual chips and placed in a packaging mold for packaging. A fourth insulating material in a hot melt state is injected. After the fourth insulating material cools and solidifies, the chip is wrapped and packaged. The packaging mold is removed to complete the packaging.

[0021] The present invention is further configured such that the packaging mold is composed of a block-level upper mold and a block-level lower mold, and the block-level upper mold and the block-level lower mold are provided with a block-level third metal bump snap-in, a block-level fourth metal bump snap-in and a block-level feed port, and the wafer is cut into single chips and then placed in the packaging mold, and the fourth insulating material is injected through the block-level feed port.

[0022] The present invention is further configured such that the packaging mold is composed of a board-level upper mold and a board-level lower mold, and the board-level upper mold and the board-level lower mold are provided with a board-level third metal bump snap-in, a board-level fourth metal bump snap-in and a board-level feed port, the wafer is cut into single chips and arranged in order in the packaging mold, the fourth insulating material is injected through the board-level feed port for packaging, and then the board-level arranged devices are cut into single devices.

[0023] (III) Beneficial effects

[0024] Compared with the prior art, the present invention provides a silicon carbide wafer-level packaging structure and a manufacturing method thereof, which have the following beneficial effects:

[0025] 1. Through wafer-level operations, the packaging efficiency is improved and the device size is reduced; polyimide insulation layers are made on the front and back of the wafer, which have good insulation support and a thermal expansion coefficient that matches the chip, which can reduce the risk of cracking and delamination in high-temperature working environments and improve device reliability; metal bumps are used instead of leads, and there are no connecting leads, which reduces stray inductance and improves transmission speed, making it suitable for high-frequency applications; the distance between the chip and the pin is short, the metal bump is thin, the heat dissipation is good, and there is no lead heating, which is suitable for high-temperature working conditions; the area of ​​the packaged device is close to 1:1 with the chip area, the thickness is about 0.5-2mm, and the overall size is small, which is suitable for the future development trend of miniaturization and integration of packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the front structure of a silicon carbide wafer-level packaging structure and a manufacturing method thereof in the present invention;

[0027] Figure 2 This is a schematic diagram of the structure of the silicon carbide wafer before it is split in the present invention;

[0028] Figure 3 It is a schematic diagram of the matching structure of the block-level upper half mold and the block-level lower half mold in the present invention;

[0029] Figure 4 It is a schematic diagram of the matching structure of the plate-level upper mold and the plate-level lower mold in the present invention.

[0030] In the figure: 1. silicon carbide chip; 2. metal under the bump; 3. first insulating material; 4. second insulating material; 5. third insulating material; 6. first metal bump; 7. second metal bump; 8. third metal bump; 9. fourth metal bump; 10. fourth insulating material; 11. silicon carbide wafer; 12. block-level upper mold; 13. block-level lower mold; 14. block-level third metal bump socket; 15. block-level fourth metal bump socket; 16. block-level feed port; 17. board-level upper mold; 18. board-level lower mold; 19. board-level third metal bump socket; 20. board-level fourth metal bump socket; 21. board-level feed port. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] It should be noted that, unless otherwise specified, all technical and scientific terms used in this application have the same meanings as commonly understood by ordinary technicians in the technical field to which this application belongs.

[0033] In the present invention, unless otherwise specified, the directions used, such as "up" and "down", usually refer to the directions shown in the drawings, or to the vertical, perpendicular or gravity directions; similarly, for ease of understanding and description, "left" and "right" usually refer to the left and right shown in the drawings; "inside" and "outside" refer to the inside and outside relative to the outline of each component itself, but the above-mentioned directions are not used to limit the present invention.

[0034] See also Figure 1 A silicon carbide wafer-level packaging structure and a manufacturing method thereof, comprising a silicon carbide chip 1, an under-bump metal 2 is provided at the upper end of the silicon carbide chip 1, the under-bump metal 2 cooperates with the electrode metal structure on the upper surface of the silicon carbide chip 1, a first insulating material 3 is provided above the silicon carbide chip 1 and on both sides of the under-bump metal 2, a second insulating material 4 is provided at the upper end of the first insulating material 3, a third insulating material 5 is provided at the lower end of the silicon carbide chip 1, a first metal bump 6 is provided at the upper end of the under-bump metal 2, a second metal bump 7 is provided at the lower end of the silicon carbide chip 1, and the second metal bump 8 is provided at the lower end of the silicon carbide chip 1. The metal bump 7 cooperates with the electrode metal structure on the lower surface of the silicon carbide chip 1, a third metal bump 8 is provided at the outer end of the first metal bump 6, a fourth metal bump 9 is provided at the outer end of the second metal bump 7, and a fourth insulating material 10 is provided on the outer side of the silicon carbide chip 1. The silicon carbide chip 1, the metal under the bump 2, the first insulating material 3, the second insulating material 4, the third insulating material 5, the first metal bump 6 and the second metal bump 7 are all located in the fourth insulating material 10, and the outer ends of the third metal bump 8 and the fourth metal bump 9 protrude from the fourth insulating material 10.

[0035] In this embodiment, the under-bump metal 2 on the front electrode of the silicon carbide chip 1 can improve the adhesion between the chip and the metal bump. The first insulating material 3, the second insulating material 4 and the third insulating material 5 between the under-bump metal 2 form various insulating layers to cooperate with each other to play an electrical isolation role. The first metal bump 6, the second metal bump 7, the third metal bump 8 and the fourth metal bump 9 on the front and back sides of the silicon carbide chip 1 cooperate to provide electrical connection and heat dissipation channels. The insulating layer package formed by the fourth insulating material 10 between the metal bumps plays an electrical isolation and support role.

[0036] See also Figure 1 and Figure 2As an implementation method of the wafer-level packaging structure: the constituent materials of the silicon carbide chip 1 include silicon carbide MOSFET, silicon carbide diode, silicon carbide JFET, silicon carbide IGBT, silicon carbide BJT, silicon carbide GTO, and the thickness of the silicon carbide chip 1 is 100-400um, and the material of the metal under the bump 2 is titanium nickel vanadium silver, nickel gold or nickel palladium gold, and if it is titanium nickel vanadium silver, the thickness of the metal titanium is less than 0.5um, the thickness of the metal nickel vanadium is less than 1um, the thickness of the metal silver is 1-10um, and if it is nickel gold or nickel palladium gold, the thickness of the metal nickel is 1-10u m, the thickness of metal palladium is less than 1um, the thickness of metal gold is less than 0.5um, the material of the first insulating material 3 is silicon oxide or silicon nitride, and the thickness is 0.1-10um, and the material of the second insulating material 4 and the third insulating material 5 is polyimide after baking and curing, and the thickness is 10-200um, the metal material of the first metal bump 6 and the second metal bump 7 is copper, and the thickness is 30-200um, and the metal material of the third metal bump 8 and the fourth metal bump 9 includes tin-lead alloy, tin-copper alloy, tin-silver alloy, tin-antimony alloy and tin-bismuth alloy, and the thickness is 100-300um.

[0037] See also Figure 1-Figure 2 The present invention provides a method for manufacturing a silicon carbide wafer-level packaging structure, the method comprising:

[0038] Step 1:

[0039] The under-bump metallization 2 is prepared on the silicon carbide chip 1 by evaporation stripping or chemical plating;

[0040] Step 2:

[0041] Then, the first insulating material 3 is formed by deposition and photolithography etching on the front side of the wafer, and then the second insulating material 4 is formed by spraying, photolithography baking and curing on the front side of the wafer, and the third insulating material 5 is formed by spraying, photolithography baking and curing on the back side of the wafer;

[0042] Step 3:

[0043] The first metal bump 6 and the second metal bump 7 are respectively prepared on the front and back sides of the wafer by the electroplating stripping process, and then the third metal bump 8 and the fourth metal bump 9 are prepared on the front and back sides of the wafer by the laser ball implantation process or the pillar implantation process.

[0044] Step 4:

[0045] The wafer is cut into individual chips and placed in a packaging mold for packaging. The fourth insulating material 10 in a hot melt state is injected. After the fourth insulating material 10 is cooled and solidified, the chips are wrapped and packaged. The packaging mold is removed to complete the packaging.

[0046] Specifically, during the manufacturing process, the silicon carbide wafer 11 is marked with a reference numeral 11 for easy identification in the drawings and the specification. The silicon carbide wafer 11 includes a plurality of silicon carbide chips 1. The under-bump metal 2 is prepared by evaporation stripping or chemical plating. If the evaporation stripping method is adopted, the contact area between the front electrode metal and the under-bump metal 2 is first defined by photolithography on the front side of the silicon carbide wafer 11, and then the under-bump metal 2 is evaporated on the front side of the silicon carbide wafer 11. Then, the photoresist and the metal thereon are removed by using a stripping solution, and then, the front side and the bump of the silicon carbide wafer 11 are separated by a stripping solution. A first insulating material 3 is deposited on the surface of the metal under the bump 2, and then the metal under the bump 2 opening area is defined by photolithography, and then the photoresist is removed, and then polyimide is sprayed on the front and back sides of the silicon carbide wafer 11, respectively, and then the metal under the bump 2 opening area and the metal opening area of ​​the electrode on the back side of the silicon carbide wafer 11 are defined by photolithography, and the insulating material made of polyimide is formed by baking and curing to become the second insulating material 4 and the third insulating material 5, and the polyimide provides good insulating support, and the thermal expansion coefficient and Good moisture-proof performance can reduce the risk of device cracking and delamination in high-temperature working environments, and reduce the risk of moisture entering the chip and causing failure in high-humidity working environments, so as to improve device reliability. Then, the first metal bump 6 and the second metal bump 7 are prepared on the front and back sides of the silicon carbide wafer 11 through an electroplating stripping process, and a seed copper layer is sputtered on the front and back sides of the silicon carbide wafer 11. Then, the metal 2 opening area under the wafer front bump and the metal opening area of ​​the wafer back electrode are defined by photolithography on the front and back sides of the wafer. Further, the front and back electrodes of the wafer are formed. The copper layer is plated, and then the photoresist and the upper metal on the front and back of the wafer are removed by stripping liquid, and then the excess seed copper layer is etched away. The size of the metal bumps can be flexibly adjusted according to the specific device electrode metal size, and then the third metal bump 8 and the fourth metal bump 9 are prepared by laser ball planting or column planting process, the metal is melted by heating, and then the molten metal is accurately planted above the first metal bump 6 on the front of the silicon carbide wafer 11 and below the second metal bump 7 on the back of the silicon carbide wafer 11 through computer positioning, and finally the packaging is completed through the packaging mold.

[0047] In addition, when the UBM 2 is prepared by chemical plating, the silicon carbide wafer 11 is placed in a chemical plating solution to form the UBM 2 on the front electrode metal of the silicon carbide wafer 11 through a replacement reaction.

[0048] See also Figure 3 As a further implementation method of the packaging mold: the packaging mold consists of a block-level upper mold 12 and a block-level lower mold 13, and the block-level upper mold 12 and the block-level lower mold 13 are provided with a block-level third metal bump socket 14, a block-level fourth metal bump socket 15 and a block-level feed port 16. The wafer is cut into single chips and placed in the packaging mold, and the fourth insulating material 10 is injected through the block-level feed port 16.

[0049] Specifically, during packaging, the silicon carbide wafer 11 is cut into single chips, and then the cut single chips are placed in a plastic packaging mold. The mold consists of a block-level upper mold and a block-level lower mold. The block-level fourth metal bump snap-in 15 below the mold is matched and fixed with the fourth metal bump 9 below, and then the block-level third metal bump snap-in 14 above the mold is aligned with the third metal bump 8 and fixed, and then the hot-melt fourth insulating material 10 is injected through the block-level feed port 16. After the fourth insulating material 10 is cooled and solidified, the mold is removed to complete the packaging. In addition, the fourth insulating material 10 contains epoxy resin, silicone gel, polymer, and polymer of bisphenol F epichlorohydrin, and the thickness after curing is 100-300um.

[0050] See also Figure 4 As a further implementation method of the packaging mold: the packaging mold is composed of a board-level upper mold 17 and a board-level lower mold 18, and the board-level upper mold 17 and the board-level lower mold 18 are provided with a board-level third metal bump socket 19, a board-level fourth metal bump socket 20 and a board-level feed port 21. The wafer is cut into single chips and arranged in order in the packaging mold, and the fourth insulating material 10 is injected through the board-level feed port 21 for packaging, and then the board-level arranged devices are cut into single chips.

[0051] Specifically, after the wafer is cut into single chips, the single chips are further arranged in order in the board-level packaging mold, and the third metal bump 8 is aligned and matched with the board-level third metal bump socket 19 of the board-level upper mold 17, and the fourth metal bump 9 is aligned and matched with the board-level fourth metal bump socket 20 of the board-level lower mold 18. After fixation, the hot melt fourth insulating material 10 is injected through the board-level feed port 21. After the fourth insulating material 10 is cooled and solidified, the mold is removed, and then the devices arranged at the board level are cut into single devices. The use of board-level packaging molds further improves operating efficiency and reduces time costs.

[0052] In summary, when manufacturing a silicon carbide wafer-level packaging structure;

[0053] The silicon carbide wafer 11 is marked with reference numeral 11 for easy identification in the attached drawings. The silicon carbide wafer 11 includes a plurality of silicon carbide chips 1. Both the front and back sides of the silicon carbide chips 1 have electrode metals, including silicon carbide MOSFET, silicon carbide diode, silicon carbide JFET, silicon carbide IGBT, silicon carbide BJT, and silicon carbide GTO, with a thickness of 100-400um. The under-bump metal 2 is prepared by evaporation stripping or chemical plating. If the evaporation stripping method is adopted, the contact area between the front electrode metal and the under-bump metal 2 is first defined by photolithography on the front side of the silicon carbide wafer 11, and then the silicon carbide wafer 11 is The metal under the bump 2 is deposited on the front side, and then the photoresist and the metal thereon are removed by stripping liquid, wherein the metal material of the metal under the bump 2 can be titanium, nickel, vanadium, and silver, wherein the thickness of the metal titanium is less than 0.5um, the thickness of the metal nickel and vanadium is less than 1um, and the thickness of the metal silver is 1-10um, and then the first insulating material 3 is deposited on the front side of the silicon carbide wafer 11 and the surface of the metal under the bump 2, and then the metal under the bump 2 opening area is defined by photolithography and etching, and then the photoresist is removed, and the material of the first insulating material 3 is composed of one or more stacks of silicon oxide, silicon nitride, and silicon oxynitride, and the material thickness is 0.1-10um, then spray polyimide on the front and back of the silicon carbide wafer 11 respectively, and then photolithography is used to define the metal opening area 2 under the bump and the metal opening area of ​​the electrode on the back of the silicon carbide wafer 11. By baking and curing, the insulating material made of polyimide is formed into a second insulating material 4 and a third insulating material 5 with a thickness of 10-200um. The polyimide provides good insulating support, a thermal expansion coefficient matching the silicon carbide chip 1, and good moisture resistance, which can reduce the device under high temperature working environment. The risk of cracking and delamination is reduced, and the risk of moisture entering the chip and causing failure in a high-humidity working environment is reduced to improve device reliability. Then, the first metal bump 6 and the second metal bump 7 are prepared on the front and back sides of the silicon carbide wafer 11 through an electroplating stripping process, and a seed copper layer is sputtered on the front and back sides of the silicon carbide wafer 11. Then, the metal 2 opening area under the wafer front bump and the metal opening area of ​​the wafer back electrode are defined by photolithography on the front and back sides of the wafer, and a copper layer is further electroplated on the front and back sides of the wafer, and then the front and back sides of the wafer are photolithographically processed. The glue and the upper metal are removed by stripping liquid, and then the redundant seed copper layer is etched away. The first metal bump 6 and the second metal bump 7 are made of copper. The first metal bump 6 is 200-500um long and wide, and the thickness is 30-200um. The second metal bump 7 is 200-1000um long and wide, and the thickness is 30-200um. The size of the metal bump can be flexibly adjusted according to the specific device electrode metal size. Then, the third metal bump 8 and the fourth metal bump 9 are prepared by laser ball planting or column planting process. The third metal bump The metal materials of 8 and the fourth metal bump 9 include tin-lead alloy, tin-copper alloy, tin-silver alloy, tin-antimony alloy, and tin-bismuth alloy. The metal is melted by heating, and then the molten metal is accurately planted above the first metal bump 6 on the front side of the silicon carbide wafer 11 and below the second metal bump 7 on the back side of the silicon carbide wafer 11 through computer positioning. The third metal bump 8 is 200-500um long and wide, 100-300um thick, and the fourth metal bump 9 is 200-1000um long and wide, and 100-300um thick.

[0054] In addition, when the under-bump metal 2 is prepared by chemical plating, the silicon carbide wafer 11 is placed in a chemical plating solution to form the under-bump metal 2 on the front electrode metal of the silicon carbide wafer 11 through a replacement reaction. At this time, the metal material of the under-bump metal 2 can be nickel-gold or nickel-palladium-gold, wherein the thickness of the metal nickel is 1-10um, the thickness of the metal palladium is less than 1um, and the thickness of the metal gold is less than 0.5um.

[0055] During packaging, the silicon carbide wafer 11 is cut into individual chips, and then the cut individual chips are placed in a plastic packaging mold, the mold comprising a block-level upper mold 12 and a block-level lower mold 13, so that the block-level fourth metal bump bayonet 15 below the mold is matched and fixed with the fourth metal bump 9 below, and then the block-level third metal bump bayonet 14 above the mold is aligned with the third metal bump 8 and fixed, and then the fourth insulating material 10 in a hot melt state is injected through the block-level feed port 16, and the mold is removed after the fourth insulating material 10 is cooled and solidified to complete the packaging. In addition, the fourth insulating material 10 includes epoxy resin, silicone gel, polymer, and a polymer of bisphenol F epichlorohydrin. The compound has a thickness of 100-300um after solidification. After the wafer is cut into single chips, the single chips can be further arranged in order in the board-level packaging mold, and the third metal bump 8 is aligned with the board-level third metal bump socket 19 of the board-level upper mold 17, and the fourth metal bump 9 is aligned with the board-level fourth metal bump socket 20 of the board-level lower mold 18. After fixing, the hot melt fourth insulating material 10 is injected through the board-level feed port 21. After the fourth insulating material 10 is cooled and solidified, the mold is removed, and then the devices arranged at the board level are cut into single devices. The use of the board-level packaging mold further improves the operating efficiency and reduces the time cost.

[0056] When a device with a silicon carbide wafer-level packaging structure is used, the under-bump metal 2 on the front electrode of the silicon carbide chip 1 can improve the adhesion between the chip and the metal bump. The first insulating material 3, the second insulating material 4 and the third insulating material 5 between the under-bump metal 2 form various insulating layers to cooperate with each other to play an electrical isolation role. The first metal bump 6, the second metal bump 7, the third metal bump 8 and the fourth metal bump 9 on the front and back sides of the silicon carbide chip 1 cooperate to provide electrical connection and heat dissipation channels. The insulating layer packaging formed by the fourth insulating material 10 between the metal bumps plays an electrical isolation and support role.

[0057] In all the schemes mentioned above, although the embodiments of the present invention have been shown and described, it is understandable to those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A silicon carbide wafer-level packaging structure, comprising a silicon carbide chip (1), characterized in that: The upper end of the silicon carbide chip (1) is provided with an under-bump metal (2), and the under-bump metal (2) cooperates with the electrode metal structure on the upper surface of the silicon carbide chip (1). A first insulating material (3) is provided above the silicon carbide chip (1) and on both sides of the under-bump metal (2), and a second insulating material (4) is provided on the upper end of the first insulating material (3). The lower end of the silicon carbide chip (1) is provided with a third insulating material (5), and the upper end of the under-bump metal (2) is provided with a first metal bump (6), and the lower end of the silicon carbide chip (1) is provided with a second metal bump (7), and the second metal bump (7) is connected to the silicon carbide chip (1). The electrode metal structure on the lower surface is matched, the outer end of the first metal bump (6) is provided with a third metal bump (8), the outer end of the second metal bump (7) is provided with a fourth metal bump (9), the outer side of the silicon carbide chip (1) is provided with a fourth insulating material (10), the silicon carbide chip (1), the under-bump metal (2), the first insulating material (3), the second insulating material (4), the third insulating material (5), the first metal bump (6) and the second metal bump (7) are all located in the fourth insulating material (10), and the outer ends of the third metal bump (8) and the fourth metal bump (9) protrude from the fourth insulating material (10).

2. The silicon carbide wafer-level packaging structure according to claim 1, characterized in that: The constituent materials of the silicon carbide chip (1) include silicon carbide MOSFET, silicon carbide diode, silicon carbide JFET, silicon carbide IGBT, silicon carbide BJT, and silicon carbide GTO, and the thickness of the silicon carbide chip (1) is 100-400 um.

3. The silicon carbide wafer-level packaging structure according to claim 1, characterized in that: The material of the metal (2) under the bump is titanium, nickel, vanadium, silver, nickel gold or nickel palladium gold. If it is made of titanium, nickel, vanadium, silver, the thickness of the metal titanium is less than 0.5um, the thickness of the metal nickel vanadium is less than 1um, and the thickness of the metal silver is 1-10um. If it is made of nickel gold or nickel palladium gold, the thickness of the metal nickel is 1-10um, the thickness of the metal palladium is less than 1um, and the thickness of the metal gold is less than 0.5um.

4. The silicon carbide wafer-level packaging structure according to claim 1, characterized in that: The first insulating material (3) is made of silicon oxide or silicon nitride, with a thickness of 0.1-10 um, while the second insulating material (4) and the third insulating material (5) are made of baked and cured polyimide, with a thickness of 10-200 um.

5. The silicon carbide wafer-level packaging structure according to claim 1, characterized in that: The metal material of the first metal bump (6) and the second metal bump (7) is copper, with a thickness of 30-200 um; the metal material of the third metal bump (8) and the fourth metal bump (9) includes tin-lead alloy, tin-copper alloy, tin-silver alloy, tin-antimony alloy and tin-bismuth alloy, with a thickness of 100-300 um.

6. The method for manufacturing a silicon carbide wafer-level packaging structure according to claim 1, characterized in that: The method comprises: Step 1: Preparing an under-bump metal (2) on a silicon carbide chip (1) by evaporation stripping or chemical plating; Step 2: Then, a first insulating material (3) is formed by depositing and photolithography etching on the front side of the wafer, a second insulating material (4) is formed by spraying and photolithography baking and curing on the front side of the wafer, and a third insulating material (5) is formed by spraying and photolithography baking and curing on the back side of the wafer; Step 3: A first metal bump (6) and a second metal bump (7) are respectively prepared on the front and back sides of a wafer by an electroplating stripping process, and then a third metal bump (8) and a fourth metal bump (9) are prepared on the front and back sides of the wafer by a laser ball implantation process or a column implantation process. Step 4: The wafer is cut into individual chips and placed in a packaging mold for packaging. A fourth insulating material (10) in a hot melt state is injected. After the fourth insulating material (10) is cooled and solidified, the chip is wrapped and packaged. The packaging mold is removed to complete the packaging.

7. The method for manufacturing a silicon carbide wafer-level packaging structure according to claim 6, characterized in that: The packaging mold is composed of a block-level upper mold (12) and a block-level lower mold (13), and the block-level upper mold (12) and the block-level lower mold (13) are provided with a block-level third metal bump clamp (14), a block-level fourth metal bump clamp (15) and a block-level feed port (16). A wafer is cut into individual chips, which are placed in the packaging mold, and a fourth insulating material (10) is injected through the block-level feed port (16).

8. The method for manufacturing a silicon carbide wafer-level packaging structure according to claim 6, wherein: The packaging mold is composed of a board-level upper mold (17) and a board-level lower mold (18), and the board-level upper mold (17) and the board-level lower mold (18) are provided with a board-level third metal bump clamp (19), a board-level fourth metal bump clamp (20) and a board-level feed port (21). The wafer is cut into individual chips and arranged in order in the packaging mold, and a fourth insulating material (10) is injected through the board-level feed port (21) for packaging, and then the board-level arranged devices are cut into individual devices.

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