Integrated device and forming method thereof

Abstract

Some embodiments relate to an integrated device comprising: a substrate comprising at least one active component; the interconnection structure is arranged on the substrate; a bonding layer disposed over the interconnect structure; a carrier substrate disposed over the interconnect structure; the heat dissipation module is arranged above the carrier substrate; and a first thermal control layer disposed between the carrier substrate and the heat dissipation module, the bonding layer and the interconnection structure, or between the carrier substrate and the bonding layer, the first thermal control layer including a phase change material (PCM). The embodiment of the invention also relates to a method for forming the integrated circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated devices and methods of forming the same. Background Art

[0002] Circuit components within an integrated device generate heat during operation. The generated heat can damage the components, leading to loss of efficiency or potential failure of the integrated device. Various methods have been developed to disperse or transfer heat from circuit elements, including using materials with higher thermal conductivity than silicon dioxide, forming vias that extend through the device and conduct heat to the outer sidewalls of the semiconductor package. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, an integrated device is provided, comprising: a substrate comprising at least one active component; an interconnect structure disposed on the substrate; a bonding layer disposed above the interconnect structure; a carrier substrate disposed above the interconnect structure; a heat dissipation module disposed above the carrier substrate; and a first thermal control layer disposed between the carrier substrate and the heat dissipation module, the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer, the first thermal control layer comprising a phase change material (PCM).

[0004] According to one aspect of an embodiment of the present application, an integrated device is provided, comprising: a substrate; an active component located on the substrate; an interconnect structure coupled to the active component; a heat dissipation module disposed above the interconnect structure; and a first thermal control layer disposed between the interconnect structure and the heat dissipation module, wherein the first thermal control layer comprises a phase change material (PCM).

[0005] According to another aspect of an embodiment of the present application, a method for forming an integrated device is provided, comprising: providing a substrate; forming an active component on the substrate; forming an interconnect structure on the substrate; joining a carrier substrate above the interconnect structure; forming a thermal interface material above the carrier substrate; positioning a heat dissipation module above the carrier substrate, wherein the thermal interface material thermally couples the carrier substrate to the heat dissipation module; and forming a first thermal control layer on the interconnect structure or the carrier substrate after forming the interconnect structure and before positioning the heat dissipation module. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of integrated devices are shown in which one or more thermal control layers are disposed between an interconnect structure and an upper surface of a semiconductor package.

[0008] Figure 2 An example graph showing the temperature variation of the thermal control layer during a phase change.

[0009] Figure 3 Cross-sectional views of some embodiments of an integrated device having one or more thermal control layers disposed between an interconnect structure and an outer sidewall of a semiconductor package, and also including a heat sink within the interconnect structure are shown.

[0010] Figure 4 Cross-sectional views of some embodiments of integrated devices having one or more thermal control layers, where the thermal control layers are patterned, are shown.

[0011] Figure 5 Cross-sectional views of some embodiments of integrated devices having one or more thermal control layers coupled with one or more high thermal conductivity layers to increase heat transfer through the device are shown.

[0012] Figure 6A-6B Cross-sectional views of some embodiments of integrated devices having one or more thermal control layers patterned and coupled to one or more high thermal conductivity layers to increase heat transfer through the device are shown.

[0013] Figure 7-Figure 8 , Fig.9A , Fig. 9B and Figure 10-13 A series of cross-sectional views illustrating some embodiments of methods of forming an integrated device having one or more thermal control layers disposed between an interconnect structure and an outer sidewall of a semiconductor package.

[0014] Figure 14-18 A series of cross-sectional views illustrating some embodiments of methods of forming one or more patterned thermal control layers disposed between an interconnect structure and an outer sidewall of a semiconductor package.

[0015] Fig.19 A flow chart illustrating some embodiments of a method of forming one or more patterned thermal control layers disposed between an interconnect structure and an outer sidewall of a semiconductor package. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0018] An integrated device may include a semiconductor substrate, a plurality of semiconductor devices, and an interconnect structure overlying the semiconductor devices. The semiconductor devices perform many operations that are important to the function of the integrated device, such as computation and data retention. During operation, the resistance within the plurality of semiconductor devices and other components causes thermal energy within the integrated device to accumulate as heat. The accumulation of heat increases the resistance of many materials and may reduce the efficiency of device operation, resulting in performance degradation and possibly causing failure of the integrated device.

[0019] In some embodiments, a number of technological developments are combined to reduce the impact of heat on the function of semiconductor devices and disperse the heat into the surrounding environment outside the integrated device, thereby reducing the damage caused. Some of these developments include the use of materials with high thermal conductivity to transfer heat at a higher rate, which reduces the amount of heat that can accumulate on the semiconductor device. In addition, the use of thermal interface materials (TIMs) and heat dissipation modules also transfer heat away from semiconductor devices. In some embodiments, semiconductor devices are modified to distribute heat throughout the device or to be more resilient to potentially damaging temperatures. Currently, dynamic solutions for transferring heat from semiconductor devices include the use of microchannels and liquid cooling. However, these solutions are complex and expensive.

[0020] The above developments can be used to improve thermal management within integrated circuits, but in some embodiments, the integrated circuits are in a dormant state for longer periods separated by periods of activity, resulting in rapid transient temperature spikes. Rapid transient temperature spikes can overwhelm the heat transfer capabilities of the above developments, rapidly introducing large amounts of thermal energy that can damage semiconductor devices even with the improved heat transfer rates of the TIM, high thermal conductivity materials, and heat sinks. Therefore, a method is needed to reduce the effects of rapid transient temperature increases on integrated devices.

[0021] The present invention provides an integrated device with a thermal control layer. The thermal control layer is a phase change material (PCM) that has a large heat capacity relative to other thermally conductive materials and additionally absorbs thermal energy as latent heat (e.g., energy that causes a phase change rather than a temperature change) near the phase change temperature of the material. The increase in heat capacity and energy absorption causes the thermal control layer to absorb thermal energy and reduce the overall temperature increase caused by fast transient spikes. The absorbed thermal energy is then released during a long period of dormancy, and the release rate is slower than the rate at which the thermal energy is absorbed. The slower release of thermal energy at a slower rate is dispersed by the TIM and the heat dissipation module. Therefore, the introduction of the thermal control layer effectively reduces the temperature increase within the integrated device during fast transient spikes, thereby giving the semiconductor device a longer life and reducing the risk of failure during operation. The thermal characteristics of the thermal control layer can be changed by adjusting the composition and doping of the layer, thereby obtaining various phase change temperatures and hysteresis curves by introducing a passive component.

[0022] Figure 1 A cross-sectional view 100 of some embodiments of an integrated device having one or more thermal control layers disposed between an interconnect structure and an upper surface of a semiconductor package is shown.

[0023] like Figure 1 As shown in the cross-sectional view 100 of FIG. 1 , a plurality of semiconductor devices 104 are disposed on a substrate 102. In some embodiments, the plurality of semiconductor devices 104 may include transistor devices (e.g., planar FETs, FinFETs (fin field effect transistors), gate-all-around (GAA) devices, etc.). The plurality of semiconductor devices 104 are coupled to an interconnect structure 106 through a plurality of contacts 108. The interconnect structure 106 couples the plurality of semiconductor devices 104 to each other and / or to a plurality of back-end-of-line (BEOL) devices (not shown). The interconnect structure 106 and the plurality of semiconductor devices 104 are surrounded by an interlayer dielectric 107.

[0024] The carrier substrate 110 is coupled to the interconnect structure 106 through a bonding layer 112. The carrier substrate 110 is also coupled to a heat dissipation module 114 through a thermal interface material (TIM) 116. The heat dissipation module 114 is, for example, a thermally conductive housing surrounding the integrated device, or a heat sink coupled to the thermally conductive housing. In some embodiments, the heat dissipation module 114 may include a heat sink including a plurality of fins protruding outward from a horizontally extending surface away from the carrier substrate 110.

[0025] One or more thermal control layers 118 are arranged on the interconnect structure 106. In some embodiments, the one or more thermal control layers 118 may be padded on the surface of the carrier substrate 110 or the bonding layer 112. In some embodiments, the thermal control layer 118 is or includes a shape memory alloy (SMA) material, a solid-solid phase change (SS PCM) material, etc. In various embodiments, the one or more thermal control layers 118 may include one or more of the following: a first thermal control layer 118a disposed between the bonding layer 112 and the interconnect structure 106, a second thermal control layer 118b disposed between the carrier substrate 110 and the bonding layer 112, and a third thermal control layer 118c disposed between the carrier substrate 110 and the heat dissipation module 114.

[0026] The positioning of one or more thermal control layers 118 within the semiconductor package results in a reduction in peak temperature during fast transient temperature spikes. The material of the thermal control layer 118 is selected to have a phase change region within a temperature band in which the integrated circuit can safely operate. When the temperature of the thermal control layer 118 is within the phase change region, the thermal control layer 118 absorbs thermal energy as latent heat. Because latent heat is energy that causes transitions between different phases, the absorption of thermal energy does not increase the temperature, thereby reducing the rate of temperature increase within the integrated device and the peak temperature reached. By reducing the peak temperature, the internal resistance is lower when the peak temperature is reached. Lower internal resistance improves the efficiency of the integrated circuit and reduces degradation (e.g., performance degradation) of multiple semiconductor devices 104, thereby extending the life of the integrated device.

[0027] Figure 2 An example graph 200 showing temperature changes of a thermal control layer during a phase change is shown.

[0028] Graph 200 shows the thermal control layer (see FIG. 200 ) during a heating phase 202 (e.g., a fast transient temperature spike) and a cooling phase 204 (e.g., a long sleep period). Figure 1 During the first portion 208 of the heating phase 202, the material of the thermal control layer (see Figure 1118) is mainly in the first phase, and the temperature change of the thermal control layer is approximately the same as the temperature change of the material 206 without phase change. During the second part 210 of the heating stage 202, the temperature is within the first phase change region 209, and the material begins to change from the first phase to the second phase. The transition from the first phase to the second phase absorbs the heat added during the entire fast transient temperature spike, reducing the overall increase in temperature compared to the temperature change of the material 206 without phase change.

[0029] During the cooling phase, the thermal control layer (see Figure 1 118) is primarily in the second phase. In some embodiments, the second phase change region 213 has the same temperature or temperature range as the first phase change region 209. In other embodiments, the second phase change region 213 is at a lower temperature than the first phase change region 209 or is centered at a lower temperature than the first phase change region 209. During the first portion 212 of the cooling phase 204, the temperature decreases at a rate comparable to the temperature change of the material 206 without phase change and a material of similar specific heat capacity. During the second portion 214 of the cooling phase 204, the temperature is within the second phase change region 213 and the material begins to transform from the second phase to the first phase. The transition from the second phase to the first phase releases the heat absorbed during the fast transient temperature spike and reduces the rate of temperature reduction compared to the temperature change in the material 206 without phase change. That is, the transition from the second phase to the first phase and the resulting heat release is a gradual process that takes longer than a similar temperature change in the material 206 without phase change. The release of heat occurs at a temperature at which the semiconductor device can operate without damage, reducing the performance degradation that can occur during fast transient temperature spikes by lowering the maximum temperature reached.

[0030] The difference in the rate of temperature increase at different temperatures is due to the latent heat used by the material during the phase change process. When the thermal control layer 118 transitions between the first phase and the second phase, the latent heat absorbed by the thermal control layer 118 does not increase the temperature of the thermal control layer 118, thereby resulting in a reduction in the overall temperature increase that may occur during the fast transient temperature spike.

[0031] Figure 3 A cross-sectional view 300 of some embodiments of an integrated device having one or more thermal control layers disposed between an interconnect structure and an outer sidewall of a semiconductor package, and also including a heat sink within the interconnect structure, is shown.

[0032] In some embodiments, the integrated device includes a plurality of stacked chips. The substrate 102 can be coupled to a multilayer board 320 through a second substrate 301. The second substrate 301 is coupled to the multilayer board 320 using a ball grid array 316. A controlled collapse chip connection 302 overlies the second substrate 301. The controlled collapse chip connection 302 couples a second interconnect structure 303 of the second substrate 301 to a bonding pad layer 304. The second interconnect structure 303 is coupled to the bonding pad layer 304 using a plurality of solder balls 308. The solder balls are separated by gap fillers and form a controlled collapse chip connection (C4) layer 310.

[0033] The heat sink 306 overlies the bonding pad layer 304. The heat sink 306 includes a high thermal conductivity material, such as diamond, etc. The back metal layer 305 separates the heat sink 306 from the substrate 102. The bonding pad layer 304 and the back metal layer 305 each include a second plurality of conductive lines, which are electrically coupled through a second plurality of vias 314 extending through the heat sink 306.

[0034] The substrate 102 and the interconnect structure 106 include multiple logic layers 307 within the integrated device. The uppermost layer of the interconnect structure 106 is a top metal layer 317. The top metal layer 317 has a wiring layer 318 that is thicker than the wiring layer of the rest of the interconnect structure 106.

[0035] Figure 4 A cross-sectional view 400 of some embodiments of an integrated device having one or more thermal control layers, wherein the thermal control layers are patterned, is shown.

[0036] In some embodiments, one or more thermal control layers 118 include a plurality of grooves and protrusions. The plurality of grooves and protrusions increase the surface area of ​​the thermal control layer 118, increasing the heat transfer rate between layers coupled to the thermal control layer 18. The plurality of grooves are formed by the sidewalls and horizontally extending surfaces of the one or more thermal control layers 118. In some embodiments, the sidewalls of the one or more thermal control layers 118 contact the sidewalls of the carrier substrate 110. In some embodiments (not shown), a respective one of the one or more thermal control layers 118 may include grooves and protrusions along opposite sides of the thermal control layer (e.g., along the top and bottom of the thermal control).

[0037] The plurality of recesses are formed by one of two methods: etching a plurality of recesses into a lower layer (e.g., interlayer dielectric 107, bonding layer 112, or carrier substrate 110) and forming thermal control layer 118 within the recesses, or etching a plurality of trenches into thermal control layer 118 and forming an upper layer within the recesses. Either or both of these processes may be used to pattern thermal control layer 118. For example, in Figure 4In the embodiment, before bonding the carrier substrate 110 to the bonding layer 112, the first, second and third thermal control layers 118a, 118b, 118c are patterned by etching the lower layer (e.g., the interlayer dielectric 107 under the first thermal control layer 118a and the carrier substrate 110 under the second and third thermal control layers 118b, 118c), and the first, second and third thermal control layers 118a, 118b, 118c are formed over the patterned lower layer. In some embodiments, the first surface of the carrier substrate 110 is etched, and the second thermal control layer 118b is formed in the resulting opening. Subsequently, the second surface of the carrier substrate is etched, and the third thermal control layer 118c is formed in the resulting opening. In other embodiments, both the first surface and the second surface are etched before forming the second thermal control layer 118b and the third thermal control layer 118c.

[0038] Figure 5 A cross-sectional view of some embodiments of an integrated device 500 having one or more thermal control layers coupled with one or more high thermal conductivity layers to increase heat transfer through the device is shown.

[0039] In some embodiments, the thermal control layer 118 is coupled to the high thermal conductivity layer 502 to increase heat transfer through the integrated device. The high thermal conductivity layer 502 includes a high thermal conductivity material, such as diamond, etc. The presence of the high thermal conductivity layer 502 enhances the heat transfer coefficient of the integrated device near the thermal control layer 118, thereby resulting in greater reactivity and increased ability of the thermal control layer 118 to absorb or release heat from the surrounding layers. The high thermal conductivity layer 502 further improves the heat distribution of the entire device and reduces the heat remaining in the area where high heat is generated (for example, near high power devices, etc.). In other words, the high thermal conductivity layer 502 redistributes the generated heat and alleviates the heat accumulation at the hot spots in the integrated device. The high thermal conductivity layer 502 is disposed between the coupled thermal control layer 118 and the semiconductor device 104, resulting in the heat generated by the active components being distributed on the surface of the thermal control layer 108. In some embodiments, the thickness of the high thermal conductivity layer 502 is between about 200 nanometers and 5 micrometers, about 300 nanometers and 4 micrometers, about 100 nanometers and 4.5 micrometers, etc. In some embodiments, the ratio of the thickness of the thermal control layer 118 to the thickness of the high thermal conductivity layer 502 is between about 1:1 and about 1:10.

[0040] Figure 6A-6B Cross-sectional views 600a, 600b of some embodiments of an integrated device having one or more thermal control layers patterned and coupled to one or more high thermal conductivity layers to increase heat transfer through the device are shown.

[0041] In some embodiments, high thermal conductivity layer 502 is used with patterned thermal control layer 118 to further enhance the thermal conductivity of the device and improve the effectiveness of thermal control layer 118. When thermal control layer 118 has a patterned surface in contact with high thermal conductivity layer 502, the increased surface area at the interface further increases the amount of heat that can be absorbed by thermal control layer 118. Figure 6B As shown, one or more high thermal conductivity layers 502 are omitted. That is, in some embodiments, the integrated device may have a greater number of thermal control layers 118 than the number of high thermal conductivity layers 502.

[0042] Figure 7-Figure 8 , Fig.9A , Fig. 9B and Figure 10-13 A series of cross-sectional views 700-1300 illustrate some embodiments of methods of forming an integrated device having one or more thermal control layers disposed between an interconnect structure and an outer sidewall of a semiconductor package. Figure 7-Figure 13 Described as a series of actions, it should be understood that these actions are not limiting, because the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0043] like Figure 7 As shown in the cross-sectional view 700 of , a substrate 102 is provided, and a plurality of semiconductor devices 104 are formed on the provided substrate 102. The substrate 102 may be any suitable type of substrate and / or may be, for example, a semiconductor wafer, one or more dies on a wafer, or any other suitable type of semiconductor body and / or epitaxial layer. In some embodiments, the substrate 102 is or includes silicon, sapphire, etc., or any combination of the foregoing materials. In some embodiments, the plurality of semiconductor devices 104 is or includes one or more layers, including a first gate, a first dielectric, and a source / drain region. The first gate is or includes a conductive material, such as copper (Cu), titanium (Ti), aluminum (Al), doped polysilicon, etc., or a combination of the foregoing materials. In some embodiments, the first dielectric is or includes an insulator, such as silicon dioxide (SiO 2 ), high-k dielectrics, etc. The source / drain regions are or include a high dopant concentration (e.g., greater than 10 15 Atom / cm 3 ) region, resulting in a high carrier concentration in the source / drain region.

[0044] like Figure 8As shown in the cross-sectional view 800 of , the interconnect structure 106 is formed above the substrate 102. In some embodiments, the interconnect structure 106 is or includes a conductive material, such as copper (Cu), titanium (Ti), aluminum (Al), etc., or a combination of the above materials. The interconnect structure includes a plurality of wiring layers 106a and a plurality of via layers 106b. The interconnect structure 106 is formed by depositing a layer of an interlayer dielectric 107, etching a plurality of openings in the interlayer dielectric 107, and filling the openings with a conductive material. The above process is repeated until the interconnect structure is completed. In some embodiments, a plurality of contacts 108, a plurality of wiring layers 106a, and a plurality of via layers 106b are formed using a single damascene process. In other embodiments, a plurality of dual damascene processes may be used to simultaneously form pairs of wiring layers 106a and via layers 106b. Before forming the wiring layers 106a and the via layers 106b, a plurality of contacts 108 are formed in the first layer of the interlayer dielectric 107. The plurality of contacts 108 couple the plurality of semiconductor devices 104 to the interconnect structure 106.

[0045] like Fig.9A As shown in the cross-sectional view 900a of FIG. 1 , the first thermal control layer 118a is formed on the interlayer dielectric 107 above the interconnect structure 106. In some embodiments, the first thermal control layer is omitted. In some embodiments, the first thermal control layer 118a is or includes a shape memory alloy, such as nickel titanium alloy (NiTi), nickel titanium hafnium alloy (NiTiHf), nickel copper titanium alloy (NiCuTi), nickel copper titanium hafnium alloy (NiCuTiHf), nickel titanium vanadium alloy (NiTiV), etc. In other embodiments, the first thermal control layer 118a includes a solid-solid PCM that is not a shape memory alloy, such as vanadium oxide (VO 2 ) and the like. In further embodiments, the first thermal control layer 118a may include a solid-liquid PCM, such as paraffin, etc. Embodiments utilizing solid-liquid PCM also include microchannels, or another method in which the PCM is in a liquid state. In some embodiments, the first thermal control layer 118a may include a latent heat between about 10 joules / gram (J / g) and about 150 J / g, between about 5 J / g and about 145 J / g, or other similar values. In some embodiments, the first thermal control layer 118a is formed using one of ALD, CVD, PVD, and the like. In some embodiments, the first thermal control layer 118a has a first thickness between about 0.1 microns and 5 microns, between about 0.5 microns and 4 microns, between about 0.2 microns and 4.5 microns, and the like.

[0046] In some embodiments, Fig. 9B As shown in the cross-sectional view 900b, when forming the first thermal control layer (see Fig.9A118a), before forming the first high thermal conductivity layer 502a in the high thermal conductivity layer 502 on the interlayer dielectric 107. The high thermal conductivity layer 502 includes a high thermal conductivity material, such as diamond, cubic boron nitride (BN), etc. In some embodiments, the first high thermal conductivity layer 502a is formed at less than 400 degrees Celsius using a microwave plasma enhanced chemical vapor deposition (MPCVD) process. In a further embodiment, the first high thermal conductivity layer 502a includes a seed layer formed before the MPCVD process. The seed layer can be or include diamond nanoparticles, cubic boron nitride (BN) film or nanoparticles, cubic boron phosphide film or nanoparticles, etc. The last part of the first thermal control layer 118a is formed by applying the MPCVD process to the seed layer. In some embodiments, the first high thermal conductivity layer 502a has a second thickness between about 200 nanometers to 5 micrometers, about 300 nanometers to 4 micrometers, about 100 nanometers to 4.5 micrometers, etc. In some embodiments, the second thickness of the first high thermal conductivity layer 502a is about the same as the first thermal control layer (see Fig.9A The ratio of the first thickness of 118a) is between about 1:1 and about 1:10.

[0047] like Fig.10 As shown in the cross-sectional view 1000 of , the bonding layer 112 is formed above the first thermal control layer 118a, and the second and third thermal control layers 118b and 118c are formed on the carrier substrate 110. In some embodiments, the bonding layer 112 is formed using a spin coating process, a spray coating process, etc. In some embodiments, the bonding layer 112 includes an adhesive material, such as benzocyclobutene (BCB), etc. The first hardness of the bonding layer 112 is lower than the second hardness of the thermal control layer 118. The first thermal control layer 118a can expand and contract when undergoing a phase change. The placement of the bonding layer 112 in contact with the first thermal control layer 118a results in lower stress generated by the contraction or expansion of the first thermal control layer 118a within the integrated device.

[0048] In some embodiments, the second thermal control layer 118b and / or the third thermal control layer 118c are omitted. The second and third thermal control layers 118b, 118c are formed on opposite sides of the carrier substrate 110. In some embodiments, the second and third thermal control layers 118b, 118c are formed using one of ALD, CVD, PVD, etc. In some embodiments, the second and third thermal control layers 118b, 118c are or include the same material as the first thermal control layer 118a. In other embodiments, the second and third thermal control layers 118b, 118c are or include a PCM different from the first thermal control layer 118a. In some embodiments, the second and third thermal control layers 118b, 118c have a second thickness between about 0.1 micron and 5 microns, between about 0.5 micron and 4 microns, between about 0.2 micron and 4.5 microns, etc.

[0049] In some embodiments, after or before forming the second thermal control layer 118b and the third thermal control layer 118c, a high thermal conductivity layer (see Figure 5 In other words, the second high thermal conductivity layer can be formed after the second thermal control layer 118b, and the third high thermal conductivity layer can be formed before the third thermal control layer 118c. Once the carrier substrate is formed in the following steps (see Fig.11 ) is bonded to the substrate (see Figure 1 102), the above method results in the second high thermal conductivity layer being located between the interconnect structure 106 and the second thermal control layer 118b. In addition, the third high thermal conductivity layer will be located between the interconnect structure 106 and the third thermal control layer 118c. High thermal conductivity layer (see Figure 5 502) distributes the heat generated in the active components on the thermal control layer 118, thereby increasing the heat transfer rate into the thermal control layer 118.

[0050] like Fig.11 As shown in the cross-sectional view 1100 of , the carrier substrate 110 is bonded to the substrate 102 using the bonding layer 112. That is, the second thermal control layer 118b (or the carrier substrate 110, if the second thermal control layer 118b is omitted) is placed on the bonding layer 112. Then, the bonding layer 112 is hardened. In some embodiments, the bonding layer 112 can be hardened at room temperature. In other embodiments, the bonding layer 112 can be hardened using one or more of ultraviolet rays, applied pressure, or one or more heating cycles. The second thermal control layer 118b can expand and contract when undergoing a phase change. Due to the relatively low hardness of the bonding layer 112, the placement of the bonding layer 112 in contact with the second thermal control layer 118b results in lower stress generated by deformation or expansion of the second thermal control layer 118b within the integrated device.

[0051] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , the TIM 116 is formed on the carrier substrate 110. In the embodiment where the third thermal control layer 118c is not omitted, the TIM 116 is formed on the third thermal control layer 118c. The TIM 116 is or includes the third thermal control layer 118c and the heat dissipation module (see FIG. 1 ) to be formed below. Figure 1 In some embodiments, TIM 116 is or includes a thermal interface material, such as thermal paste, thermal adhesive, etc. The hardness of TIM 116 is lower than the hardness of thermal control layer 118. Third thermal control layer 118c can expand and contract when undergoing a phase change. The placement of TIM 116 in contact with third thermal control layer 118c results in lower stress generated by deformation or expansion of third thermal control layer 118c within the integrated device.

[0052] like Fig.13As shown in the cross-sectional view 1300 of FIG. 1 , the heat dissipation module 114 is thermally coupled to the carrier substrate 110 through the TIM 116. The heat dissipation module 114 is or includes a thermally conductive material, such as metal. In some embodiments, the heat dissipation module 114 is connected to the substrate 102, the second substrate (see FIG. 1 ) using an adhesive, a welding process, etc. Figure 3 301) or multilayer board (see Figure 3 one of 320).

[0053] Figure 14-18 A series of cross-sectional views 1400 - 1800 illustrate some embodiments of a method of forming one or more patterned thermal control layers disposed between an interconnect structure and an outer sidewall of a semiconductor package. Figure 14-15 A first method of forming a patterned thermal control layer is shown and in some embodiments replaces Fig.19 . Figure 16-Figure 18 A second method of forming a patterned thermal control layer is shown and in some embodiments replaces Fig.19 . In forming the second thermal control layer (see Fig.10 118b) and / or a third thermal control layer (see Fig.10 118c) of the process, you can also use Figure 14-15 and Figure 16-18 The method shown, and different methods can be used to pattern different thermal control layers 118.

[0054] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 14, after forming the interconnect structure 106, the uppermost layer of the interlayer dielectric 107 (also the first thermal control layer (see FIG. 14) is Figure 1 The etching process is performed on the interlayer dielectric 107 by first forming and patterning a first mask layer 1404 on the upper surface of the interlayer dielectric. In some embodiments, the first mask layer 1404 is a photoresist and is patterned using photolithography. After the photoresist is patterned, the interlayer dielectric 107 is patterned according to the openings in the first mask layer 1404 using a dry etching process 1402. The dry etching process 1402 forms a plurality of openings 1406 in the interlayer dielectric 107. After the dry etching process 1402, the first mask layer 1404 is removed.

[0055] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 15, the first thermal control layer 118a is formed with a plurality of openings in the lower layer (see FIG. Fig.14 The deposition process used to form the first thermal control layer 118a causes the first thermal control layer 118a to conform to and fill the plurality of openings (see Fig.141406). Filling the plurality of openings results in the first thermal control layer 118a having a plurality of protrusions extending into the underlying layer. Thus, the first thermal control layer 118a can have an increased surface area obtained by patterning without directly etching the first thermal control layer 118a. The second thermal control layer (see Figure 4 118b) and a third thermal control layer (see Figure 4 118c) This technique can also be used to pattern a carrier substrate (see Figure 4 The patterned carrier substrate (see Figure 1 110) makes the second thermal control layer (see Figure 4 118b) and a third thermal control layer (see Figure 4 118c) has a larger surface area on one side when formed (see Fig.10 ), thereby increasing the thermal control layer 118 and the carrier substrate (see Figure 1 110) between the heat transfer rate.

[0056] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 16 , the first thermal control layer 118 a is formed on the interlayer dielectric 107. Fig.19 The steps described.

[0057] like Fig.17 As shown in the cross-sectional view 1700 of , the first thermal control layer 118a is subjected to an etching process. The etching process is performed by first forming and patterning a second mask layer 1704 on the upper surface of the interlayer dielectric. In some embodiments, the second mask layer 1704 is a photoresist and is patterned using photolithography. After patterning the photoresist, the first thermal control layer 118a is patterned according to the openings in the second mask layer 1704 using a dry etching process 1702. The dry etching process 1702 forms a plurality of openings 1706 in the first thermal control layer 118a and leaves a plurality of protrusions extending from the first thermal control layer 118a. After the dry etching process 1702, the second mask layer 1704 is removed.

[0058] like Fig.18 As shown in the cross-sectional view 1800 of FIG. 1 , the bonding layer 112 is formed in a plurality of openings in the first thermal control layer 118a (see FIG. Fig.17 1706). The process used to form the bonding layer 112 causes the bonding layer 112 to conform to and fill the plurality of openings (see Fig.17 1706). Thus, the first thermal control layer 118a can have an increased surface area in contact with the bonding layer 112, which can increase the bonding strength and increase the heat transfer rate between the first thermal control layer 118a and the bonding layer 112. The second thermal control layer (see Figure 1 118b) and a third thermal control layer. Patterned carrier substrate (see Figure 1110) leads to a second thermal control layer (see Figure 1 118b) and the third thermal control layer (see Figure 1 118c) can also use this technique to form a thermal control layer 118 on a carrier substrate (see Figure 1 110) and then patterning it to form a patterned carrier substrate (see Figure 1 110) leads to a second thermal control layer (see Figure 1 118b) and a third thermal control layer (see Figure 1 118c) has a larger surface area on one side when formed (see Fig.10 ), thereby increasing the thermal control layer 118 and the carrier substrate (see Figure 1 110) between the heat transfer rate.

[0059] Fig.19 Flowcharts of some embodiments of methods for forming one or more patterned thermal control layers disposed between an interconnect structure and an outer sidewall of a semiconductor package are shown. Although the method and other methods shown and / or described herein are shown as a series of actions or events, it should be understood that the present disclosure is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in a different order than shown, and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0060] At 1902, one or more active components are formed on a substrate. For example, see Figure 7 .

[0061] At 1904, an interconnect structure is formed over the active components. For example, see Figure 8 .

[0062] At 1906, a first thermal control layer is formed over the interconnect structure. See, for example, FIG. 9 .

[0063] At 1908, a bonding layer is formed over the first thermal control layer. For example, see Fig.10 .

[0064] At 1910, a second thermal control layer and a third thermal control layer are formed on a carrier substrate. For example, see Fig.10 .

[0065] At 1912, the carrier substrate is bonded to the bonding layer. For example, see Fig.11 .

[0066] At 1914, a thermal interface material (TIM) is disposed on a carrier substrate or a third thermal control layer. For example, see Fig.12 .

[0067] At 1916, the heat sink module is thermally coupled to the TIM. For example, see Fig.13 .

[0068] Some embodiments relate to an integrated device, comprising: a substrate, comprising at least one active component; an interconnect structure, disposed on the substrate; a bonding layer, disposed above the interconnect structure; a carrier substrate, disposed above the interconnect structure; a heat dissipation module, disposed above the carrier substrate; and a first thermal control layer, disposed between the carrier substrate and the heat dissipation module, the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer, the first thermal control layer comprising a phase change material (PCM). In some embodiments, the integrated device further comprises a high thermal conductivity layer located on a first side of the first thermal control layer. In some embodiments, the integrated device further comprises a second thermal control layer, disposed between the carrier substrate and the heat dissipation module, the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer, which is different from the first thermal control layer. In some embodiments, the integrated device further comprises a third thermal control layer, disposed between the carrier substrate and the heat dissipation module, the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer, which is different from the first thermal control layer and the second thermal control layer. In some embodiments, the first thermal control layer comprises a solid-solid PCM (SS-PCM). In some embodiments, the SS-PCM comprises a shape memory alloy.

[0069] Other embodiments relate to an integrated device, comprising: a substrate; an active component located on the substrate; an interconnect structure coupled to the active component; a heat dissipation module disposed above the interconnect structure; and a first thermal control layer disposed between the interconnect structure and the heat dissipation module, wherein the first thermal control layer comprises a phase change material (PCM). In some embodiments, the first thermal control layer comprises a solid-solid phase change material (SS-PCM). In some embodiments, the integrated device further comprises a thermal interface material located on a first side of the first thermal control layer, wherein the thermal interface material has a first hardness lower than a second hardness of the first thermal control layer. In some embodiments, the first thermal control layer comprises a first side and a first plurality of protrusions extending from the first side. In some embodiments, the first thermal control layer further comprises a second side opposite to the first side, and wherein the integrated device further comprises a high thermal conductivity layer covering the second side of the first thermal control layer. In some embodiments, the integrated device further comprises: a carrier substrate disposed between the first thermal control layer and the heat dissipation module; and a second thermal control layer disposed between the carrier substrate and the heat dissipation module. In some embodiments, the second thermal control layer comprises a second side and a second plurality of protrusions extending from the second side, wherein the first plurality of protrusions and the second plurality of protrusions extend into the carrier substrate. In some embodiments, the integrated device further includes: a bonding layer located between the interconnect structure and the first thermal control layer; and a third thermal control layer located between the bonding layer and the interconnect structure, wherein the third thermal control layer includes a third side and a third plurality of protrusions extending from the third side, and wherein the third plurality of protrusions extend toward the interconnect structure.

[0070] Still other embodiments relate to methods of forming an integrated device, including: providing a substrate; forming an active component on the substrate; forming an interconnect structure on the substrate; bonding a carrier substrate over the interconnect structure; forming a thermal interface material over the carrier substrate; positioning a heat dissipation module over the carrier substrate, wherein the thermal interface material thermally couples the carrier substrate to the heat dissipation module; and forming a first thermal control layer on the interconnect structure or the carrier substrate after forming the interconnect structure and before positioning the heat dissipation module. In some embodiments, forming the first thermal control layer further includes: forming the first thermal control layer on the carrier substrate before positioning the carrier substrate on the interconnect structure; and forming a bonding layer on the interconnect structure, wherein after positioning the carrier substrate over the interconnect structure, the carrier substrate and the first thermal control layer are mechanically coupled to the substrate through the bonding layer. In some embodiments, forming the first thermal control layer further includes: forming a second thermal control layer on the carrier substrate before positioning the carrier substrate on the interconnect structure, wherein the second thermal control layer is separated from the first thermal control layer by the carrier substrate; and bonding one of the first thermal control layer or the second thermal control layer to the bonding layer. In some embodiments, forming the first thermal control layer further comprises: etching a plurality of grooves in one or more of the carrier substrate or the interconnect structure; and depositing the material of the first thermal control layer in the plurality of grooves, so that the first thermal control layer has a first plurality of protrusions extending into one of the carrier substrate or the interconnect structure. In some embodiments, the method further comprises forming a bonding layer on the interconnect structure; and when the first thermal control layer is to be located between the carrier substrate and the bonding layer, forming a first high thermal conductivity layer after forming the first thermal control layer, so that the first high thermal conductivity layer is located between the first thermal control layer and the bonding layer. In some embodiments, forming the first thermal control layer further comprises: depositing the material of the first thermal control layer onto the carrier substrate or the interconnect structure; and etching a plurality of grooves in the first thermal control layer, exposing the first plurality of protrusions of the first thermal control layer, so that the first thermal control layer has a first plurality of protrusions extending from one of the carrier substrate or the interconnect structure. In some embodiments, when the first thermal control layer is to be formed on the interconnect structure, the first high thermal conductivity layer is formed before forming the first thermal control layer, so that the first high thermal conductivity layer is located between the first thermal control layer and the interconnect structure.

[0071] It should be understood that in this written description and in the claims that follow, the terms "first," "second," and "third," etc., are merely general identifiers used for ease of description to distinguish between different elements of a figure or series of figures. By themselves, these terms do not imply any temporal order or structural proximity of these elements, nor are they intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, a "first dielectric layer" described in conjunction with one figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in an embodiment not shown.

[0072] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. An integrated device comprising: a substrate comprising at least one active component; an interconnect structure, disposed on the substrate; a bonding layer disposed above the interconnect structure; a carrier substrate disposed above the interconnect structure; A heat dissipation module is arranged above the carrier substrate; as well as The first thermal control layer is disposed between the carrier substrate and the heat dissipation module, the bonding layer and the interconnection structure, or the carrier substrate and the bonding layer, and the first thermal control layer includes a phase change material. 2 . The integrated device of claim 1 , further comprising a high thermal conductivity layer on the first side of the first thermal control layer.

3. The integrated device according to claim 1, further comprising a second thermal control layer, disposed between the carrier substrate and the heat dissipation module, the bonding layer and the interconnect structure, or one of the carrier substrate and the bonding layer that is different from the first thermal control layer.

4. The integrated device according to claim 3 further includes a third thermal control layer, which is arranged between the carrier substrate and the heat dissipation module, the bonding layer and the interconnection structure, or the carrier substrate and the bonding layer, which is different from the first thermal control layer and the second thermal control layer.

5. An integrated device comprising: substrate; an active component located on the substrate; an interconnect structure coupled to the active component; A heat dissipation module, arranged above the interconnection structure; as well as A first thermal control layer is disposed between the interconnection structure and the heat dissipation module, wherein the first thermal control layer comprises a phase change material.

6. The integrated device according to claim 5, wherein: The first thermal control layer includes a first side and a first plurality of protrusions extending from the first side.

7. The integrated device according to claim 6, wherein: The first thermal control layer further includes a second side opposite the first side, and wherein the integrated device further includes a high thermal conductivity layer covering the second side of the first thermal control layer.

8. A method of forming an integrated device, comprising: providing a substrate; forming active components on the substrate; forming an interconnect structure on the substrate; bonding a carrier substrate over the interconnect structure; forming a thermal interface material over the carrier substrate; positioning a heat dissipation module over the carrier substrate, wherein the thermal interface material thermally couples the carrier substrate to the heat dissipation module; as well as After forming the interconnect structure and before positioning the heat dissipation module, a first thermal control layer is formed on the interconnect structure or the carrier substrate.

9. The method according to claim 8, wherein: Forming the first thermal control layer further comprises: etching a plurality of recesses in one or more of the carrier substrate or the interconnect structure; and Material of the first thermal control layer is deposited within the plurality of recesses such that the first thermal control layer has a first plurality of protrusions extending into one of the carrier substrate or the interconnect structure.

10. The method according to claim 8, wherein: Forming the first thermal control layer further comprises: depositing material of the first thermal control layer onto the carrier substrate or the interconnect structure; and A plurality of trenches are etched in the first thermal control layer to expose a first plurality of protrusions of the first thermal control layer, such that the first thermal control layer has the first plurality of protrusions extending from one of the carrier substrate or the interconnect structure.

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