Miniaturized ultra-wideband high-pass filter and notch filter integrated chip based on LTCC technology

Abstract

The present invention discloses a miniaturized ultra-wideband high-pass filter and notch integrated chip based on LTCC technology. The chip includes a substrate, external electrodes, a filter circuit module, and a notch filter module. The chip is internally constructed of 21 stacked circuit layers, primarily including the ultra-wideband high-pass filter's capacitor plate metal layer and inductor winding metal layer, the notch filter's stripline metal layer, a bottom ground plate, and a top ground plate. The present invention utilizes the LTCC process for three-dimensional structural construction to achieve a compact chip with high integration, adapting to the new trend of electronic component integration and miniaturization. By adjusting the transmission zero point through a resonator and adjusting the in-band impedance matching and out-of-band suppression through impedance matching, a high-pass filter with an ultra-wideband and strong out-of-band signal suppression is achieved. The chip also provides strong suppression of clutter interference near specific frequencies, and has the advantages of low loss, multiple transmission zero points, a steep notch curve, and high reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of filters, and in particular relates to a miniaturized ultra-wideband high-pass filter and notch integrated chip based on LTCC technology. Background Art

[0002] The rapid development of wireless communication technology is driving a growing demand for high-performance, miniaturized RF components. In the military, aerospace, and civilian communications sectors, the trend toward miniaturization and multifunctionality is placing higher demands on key components such as filters. As a core component in communication systems, filter performance directly impacts the communication quality and reliability of the entire system. Traditional filter designs often suffer from large size, high loss, insufficient selectivity, and limited out-of-band rejection, making them unable to meet the growing demand for high-performance filters in modern communication systems.

[0003] Low-temperature co-fired ceramic (LTCC) technology, as an advanced microelectronics packaging technology, has attracted widespread attention due to its ability to achieve high-density integration and three-dimensional structural design. LTCC technology utilizes low-temperature co-fired ceramic materials as a substrate, integrating passive components (such as capacitors and inductors) with active components through multi-layer circuit board technology. This technology not only significantly reduces the size and weight of electronic components, but also improves component reliability and performance stability. LTCC technology also offers excellent thermal stability and mechanical strength, making it an ideal choice for manufacturing high-performance RF components. Summary of the Invention

[0004] The purpose of the present invention is to provide a miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology with the advantages of miniaturization, low loss, multiple transmission zeros, strong suppression of out-of-band signals, steep notch curve, and high reliability.

[0005] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is:

[0006] The present invention provides a miniaturized ultra-wideband high-pass filter and notch filter integrated chip based on LTCC technology, which uses LTCC process technology to achieve three-dimensional integration of the chip, including substrate, external electrodes, filter circuit module, and notch filter module;

[0007] The external electrode includes an input terminal, an output terminal and a ground terminal;

[0008] The filter circuit module and the wave trap module are arranged inside the base body;

[0009] The filtering circuit module includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a first inductor, a second inductor, a third inductor and a fourth inductor. One end of the first capacitor is connected to the input end through a first via, and the other end of the first capacitor is connected to one end of the third capacitor through a second via. At the same time, the two ends of the third capacitor are respectively connected in parallel with the two ends of the fifth capacitor through a third via and a fourth via to form a first equivalent capacitor. One end of the seventh capacitor is connected to one end of the fifth capacitor through a fifth via, so that the first capacitor, the first equivalent capacitor and the seventh capacitor are connected in series. The input end is simultaneously connected to one end of the second capacitor through the first via, and the other end of the second capacitor is connected to one end of the first inductor through a thirteenth via to form a A series resonant structure forms a first zero point, one end of the fourth capacitor is connected to one end of the third capacitor through a sixth via, and the other end of the fourth capacitor is connected to one end of the second inductor through a fourteenth via to form a series resonant structure to form a second zero point, one end of the sixth capacitor is connected to one end of the fifth capacitor through a seventh via, and the other end of the sixth capacitor is connected to one end of the third inductor through a fifteenth via to form a series resonant structure to form a third zero point, one end of the eighth capacitor is connected to one end of the seventh capacitor through an eighth via, and the other end of the eighth capacitor is connected to one end of the fourth inductor through a sixteenth via to form a series resonant structure to form a fourth zero point, and the other ends of the first to fourth inductors are connected to the first ground layer through twenty-fifth to twenty-eighth vias, respectively, so that the first to fourth inductors are connected in parallel;

[0010] The wave trap module includes a first coupler, a second coupler, and a third coupler, wherein the first coupler, the second coupler, and the third coupler are sequentially connected in series;

[0011] The first ground layer is connected to the ground terminal.

[0012] Furthermore, the filter circuit module and the wave trap module are connected via a ground filtering and decoupling capacitor to weaken the coupling effect between the filter circuit module and the wave trap module and achieve impedance matching.

[0013] Furthermore, the chip includes a multi-layer LTCC ceramic substrate and a circuit layer correspondingly arranged on the LTCC ceramic substrate.

[0014] Furthermore, the filtering circuit module has eleven layers, the first capacitor, the third capacitor, the fifth capacitor, and the seventh capacitor are arranged on the first, second, and third layers of the chip three-dimensional circuit, the second capacitor, the fourth capacitor, the sixth capacitor, and the eighth capacitor are arranged on the fourth, fifth, sixth, and seventh layers of the chip three-dimensional circuit, the first inductor, the second inductor, the third inductor, and the fourth inductor are arranged on the eighth, ninth, and tenth layers of the chip three-dimensional circuit, and the eleventh layer of the chip three-dimensional circuit is the ground layer.

[0015] Furthermore, the first to eighth capacitors all adopt parallel stacking technology to reduce the volume occupied by the capacitors and achieve chip miniaturization.

[0016] Furthermore, the first to fourth inductors all adopt a stacked structure, and the metal coils on different dielectric layers are connected through vias.

[0017] Furthermore, the trap module has ten layers, the first coupler is arranged on the twelfth and thirteenth layers of the chip three-dimensional circuit, the second coupler is arranged on the fifteenth, sixteenth and seventeenth layers of the chip three-dimensional circuit, the first coupler is arranged on the nineteenth and twentieth layers of the chip three-dimensional circuit, and the fourteenth, eighteenth and twenty-first layers of the chip three-dimensional circuit are ground layers.

[0018] Furthermore, the first to third couplers all adopt parallel coupled stripline structures, wherein the first coupler and the third coupler are both two-segment parallel coupled lines, and the second coupler is three-segment parallel coupled lines.

[0019] Furthermore, the dielectric layers where the first to third couplers are located are each provided with an isolation wall, and the isolation wall is connected to the ground end to separate the coupled transmission line stages from each other and from other devices to avoid other coupling effects.

[0020] Furthermore, the circuit layer is made of metal, and its LTCC ceramic substrate is made of a LTCC dielectric substrate with a dielectric constant of 7.5 and a dielectric loss tangent of 0.003.

[0021] The beneficial effects of the present invention are as follows: by adopting LTCC process technology, each circuit layer is connected through vias, thereby realizing a three-dimensional structure of the filter circuit, and making full use of the stacked structure, the size and weight of the electronic component are significantly reduced, and the reliability and performance stability of the component are improved; the chip has the advantages of miniaturization, low loss, multiple transmission zero points, strong suppression of out-of-band signals, steep notch curve and high reliability; by adjusting the transmission zero point through a resonator and adjusting the in-band impedance matching and out-of-band suppression through impedance matching, a high-pass filter with an ultra-wide bandwidth and strong suppression of out-of-band signals is realized, and strong suppression of clutter interference near a specific frequency is satisfied; the overall chip package size is millimeter-level, which adapts to the development trend of integration and miniaturization of modern electronic components. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 2. It is a schematic diagram of the internal three-dimensional structure of the hidden ground plate of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0023] Figure 2 2 is a schematic diagram of the internal structure of a filter and notch integrated chip according to an embodiment of the present invention;

[0024] Figure 3 2. It is a schematic diagram of the internal structure of the hidden ground plate of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0025] Figure 4 2 is a schematic front view of the internal structure of a filter and notch integrated chip according to an embodiment of the present invention;

[0026] Figure 5 2. It is a schematic front view of the internal structure of the hidden ground plate of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0027] Figure 6 2 is a schematic diagram of the top-level structure of a filter and notch integrated chip according to an embodiment of the present invention;

[0028] Figure 7 2 is a schematic diagram of the first internal circuit layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0029] Figure 8 2 is a schematic diagram of the internal second-layer circuit of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0030] Figure 9 2. This is a schematic diagram of the internal third layer circuit of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0031] Figure 10 2 is a schematic diagram of the fourth internal circuit layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0032] Figure 11 2 is a schematic diagram of the internal fifth layer circuit of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0033] Figure 12 2. This is a schematic diagram of the internal sixth layer circuit of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0034] Figure 13 2. This is a schematic diagram of the seventh internal circuit layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0035] Figure 142 is a schematic diagram of the internal eighth layer circuit of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0036] Figure 15 2. This is a schematic diagram of the ninth internal circuit layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0037] Figure 16 2 is a schematic diagram of the internal tenth layer circuit of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0038] Figure 17 11th internal circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0039] Figure 18 12th layer internal circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0040] Figure 19 13th layer internal circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0041] Figure 20 14th layer circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0042] Figure 21 15th internal circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0043] Figure 22 16th internal circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0044] Figure 23 17th layer circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0045] Figure 24 18th layer circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0046] Figure 25 19th internal circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0047] Figure 26 20th layer circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0048] Figure 27 21st layer internal circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0049] Figure 28 2 is a schematic diagram of the bottom structure of a filter and notch integrated chip according to an embodiment of the present invention;

[0050] Figure 29 Schematic diagram of the first and third circuit hole layers inside the integrated filter and notch filter chip according to an embodiment of the present invention;

[0051] Figure 30 2. This is a schematic diagram of the second internal circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0052] Figure 31 Schematic diagram of the fourth, fifth, and sixth circuit hole layers inside the integrated filter and notch filter chip according to an embodiment of the present invention;

[0053] Figure 32 2. This is a schematic diagram of the seventh internal circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0054] Figure 33 2. This is a schematic diagram of the eighth circuit hole layer inside the integrated filter and notch filter chip according to an embodiment of the present invention;

[0055] Figure 34 2. This is a schematic diagram of the ninth internal circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0056] Figure 35 2. This is a schematic diagram of the inner tenth circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0057] Figure 36 2. It is a schematic diagram of the eleventh internal circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0058] Figure 37 2. It is a schematic diagram of the internal circuit hole layer of the twelfth layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0059] Figure 38 3. This is a schematic diagram of the internal circuit hole layer of the thirteenth layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0060] Figure 39 2. This is a schematic diagram of the fourteenth internal circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0061] Figure 40 2. This is a schematic diagram of the fifteenth internal circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0062] Figure 412. This is a schematic diagram of the sixteenth internal circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0063] Figure 42 2. It is a schematic diagram of the seventeenth circuit hole layer inside the integrated filter and notch filter chip according to an embodiment of the present invention;

[0064] Figure 43 2. This is a schematic diagram of the internal eighteenth circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0065] Figure 44 2. This is a schematic diagram of the nineteenth internal circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0066] Figure 45 20th circuit hole layer schematic diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0067] Figure 46 21st internal circuit hole layer schematic diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0068] Figure 47 2 is a top-view schematic diagram of the external structure of a filter and notch integrated chip according to an embodiment of the present invention;

[0069] Figure 48 2. It is a bottom-level perspective diagram of the external structure of a filter and notch integrated chip according to an embodiment of the present invention;

[0070] Figure 49 2 is a schematic diagram of the equivalent circuit principle of a filter and notch integrated chip according to an embodiment of the present invention;

[0071] Figure 50 4 is an S-parameter electrical performance curve of a filter and notch integrated chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0072] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0073] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0074] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0075] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0076] The embodiment of the present invention provides a miniaturized ultra-wideband high-pass filter and notch integrated chip based on LTCC technology.

[0077] like Figure 1-5 、 Figures 47-49 As shown, the miniaturized ultra-wideband high-pass filter and notch filter integrated chip based on LTCC technology includes a substrate 100, an external electrode 200 disposed on the surface of the substrate 100, and a filter circuit module 300 and a notch filter module 400 disposed within the substrate 100. The substrate 100 is a low-temperature co-fired ceramic dielectric, manufactured using the LTCC (Low Temperature Co-fired Ceramic) process. It is manufactured by printing electronic components on the surface of a multi-layer LTCC ceramic substrate and sintering them. It is used to achieve high slope, high suppression, high Q value, and miniaturization of the ultra-wideband filter and notch filter.

[0078] In this embodiment, the chip includes a multi-layer LTCC ceramic substrate, each layer of the LTCC ceramic substrate is provided with a corresponding circuit layer, and the circuit layers are connected through vias, thereby realizing a three-dimensional structure of the filter circuit and making full use of the laminated structure.

[0079] The external electrode 200 includes an input electrode IN, an output electrode OUT, and a ground electrode GND. The input electrode IN is used to receive a radio frequency signal, the output electrode OUT is used to output a filtered radio frequency signal, and the ground electrode GND is used to stabilize the voltage of the filter circuit module 300 and enable the filter circuit module 300 to work normally. The shapes and positions of the input electrode IN, the ground electrode GND, and the output electrode OUT can be set accordingly as required, such as Figures 47-48In one embodiment, the input electrode IN and the output electrode OUT are respectively disposed on the left and right sides of the substrate 100 , and the ground electrode GND is disposed on the front and rear plates and the bottom area of ​​the substrate 100 .

[0080] In this embodiment, the filter circuit module 300 and the trap module 400 are arranged inside the base 100 and are placed in the upper and lower parts respectively. The two circuit modules are connected through the ground filtering decoupling capacitor C9 to weaken the coupling between the filter circuit module and the trap module and achieve impedance matching, thereby improving the trap's suppression of clutter interference.

[0081] The filter circuit module 300 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4. Among them, one end of the first capacitor C1 is connected to the input electrode IN through the first via 501, and the other end of the first capacitor C1 is connected to one end of the third capacitor C3 through the second via 502. At the same time, the two ends of the third capacitor C3 are connected in parallel with the two ends of the fifth capacitor C5 through the third via 503 and the fourth via 504 respectively to form a first equivalent capacitor, and one end of the seventh capacitor C7 is connected to one end of the fifth capacitor C5 through the fifth via, so that the first capacitor C1, the first equivalent capacitor, and the seventh capacitor C7 are connected in series; the input electrode IN is simultaneously connected to one end of the second capacitor C2 through the first via 501, and the other end of the second capacitor C2 is connected to one end of the first inductor L1 through the ninth via 509 to form a series resonant structure to form a first zero point, one end of the fourth capacitor C4 is connected to one end of the third capacitor C3 through the sixth via 506, and the other end of the fourth capacitor C4 is connected to One end of the second inductor L2 is connected to form a series resonant structure to form a second zero point. One end of the sixth capacitor C6 is connected to one end of the fifth capacitor C5 through the seventh via 507. The other end of the sixth capacitor C6 is connected to one end of the third inductor L3 through the eleventh via 511 to form a series resonant structure to form a third zero point. One end of the eighth capacitor C8 is connected to one end of the seventh capacitor C7 through the eighth via 508. The other end of the eighth capacitor C8 is connected to one end of the fourth inductor L4 through the twelfth via 512 to form a series resonant structure to form a fourth zero point. The other ends of the first inductor L1, the second inductor L2, the third inductor L3, and the fourth inductor L4 are connected to the first ground layer 61 through the twenty-first via 521, the twenty-second via 522, the twenty-third via 523, and the twenty-fourth via 524, respectively, so that the first inductor L1, the second inductor L2, the third inductor L3, and the fourth inductor L4 are connected in parallel.

[0082] In this embodiment, the first to eighth capacitors C1, C2, C3, C4, C5, C6, C7, and C8 all utilize parallel stacking technology to reduce the size of the capacitors and achieve chip miniaturization. The first capacitor C1, the third capacitor C3, the fifth capacitor C5, and the seventh capacitor C7 are three-layer parallel plate capacitors, located on the first, second, and third layers of the chip's three-dimensional circuit. The second capacitor C2, the fourth capacitor C4, the sixth capacitor C6, and the eighth capacitor C8 are four-layer parallel plate capacitors, located on the fourth, fifth, sixth, and seventh layers of the chip's three-dimensional circuit. The first inductor L1, the second inductor L2, the third inductor L3, and the fourth inductor L4 all utilize a stacked structure, with metal coils on different dielectric layers connected by vias to form a stack. This reduces the size of the inductor components and increases the integration density. The first inductor L1, the second inductor L2, the third inductor L3, and the fourth inductor L4 are located on the eighth, ninth, and tenth layers of the chip's three-dimensional circuit.

[0083] Combine Figure 1-17 、 Figure 29-36 , the specific structures of the first to eleventh circuit layers are described in detail:

[0084] The first circuit layer includes a first electrode plate 3101 connected to a ninth electrode plate 3109 and an input electrode IN through a first via 501; a second electrode plate 3102 connected to a tenth electrode plate 3110 through a sixth via 506; a third electrode plate 3103 connected to an eleventh electrode plate 3111 through a seventh via 507; and a fourth electrode plate 3104 connected to a twelfth electrode plate 3112 through an eighth via 508.

[0085] The second circuit layer includes a fifth electrode plate 3105, the left portion of which is connected to the first electrode plate 3101 and the ninth electrode plate 3109 respectively through vertical coupling, and the right portion is connected to the tenth electrode plate 3110 through the second via 502; a sixth electrode plate 3106, the left portion of which is connected to the second electrode plate 3102 and the tenth electrode plate 3110 respectively through vertical coupling, and the right portion is connected to the eleventh electrode plate 3111 through the third via 503; a seventh electrode plate 3107, the left portion of which is connected to the tenth electrode plate 3110 through the fourth via 504, and the right portion of which is connected to the third electrode plate 3103 and the eleventh electrode plate 3111 respectively through vertical coupling; and an eighth electrode plate 3108, the left portion of which is connected to the eleventh electrode plate 3111 through the fifth via 505, and the right portion of which is connected to the fourth electrode plate 3104 and the twelfth electrode plate 3112 respectively through vertical coupling.

[0086] The third circuit layer is completely consistent with the first circuit layer in structure;

[0087] The fourth circuit layer includes a thirteenth electrode plate 3113 connected to the seventeenth electrode plate 3117 through vertical coupling, and connected to the twenty-first electrode plate 3121 through the ninth via 509; a fourteenth electrode plate 3114 connected to the eighteenth electrode plate 3118 through vertical coupling, and connected to the twenty-second electrode plate 3122 through the tenth via 510; a fifteenth electrode plate 3115 connected to the nineteenth electrode plate 3119 through vertical coupling, and connected to the twenty-third electrode plate 3123 through the eleventh via 511; a sixteenth electrode plate 3116 connected to the twentieth electrode plate 3120 through vertical coupling, and connected to the twenty-fourth electrode plate 3124 through the twelfth via 512;

[0088] The fifth circuit layer includes a seventeenth electrode plate 3117 connected to the twenty-fifth electrode plate 3125 and the input electrode IN through the first via 501; an eighteenth electrode plate 3118 connected to the tenth electrode plate 3110 and the twenty-sixth electrode plate 3126 through the sixth via 506; a nineteenth electrode plate 3119 connected to the eleventh electrode plate 3111 and the twenty-seventh electrode plate 3127 through the seventh via 507; and a twentieth electrode plate 3120 connected to the twelfth electrode plate 3112 and the twenty-eighth electrode plate 3128 through the eighth via 508.

[0089] The sixth circuit layer includes a twenty-first electrode plate 3121 connected to the twenty-fifth electrode plate 3125 through vertical coupling, and connected to the first metal conductive strip 3201 through the thirteenth via 513; the twenty-second electrode plate 3122 is connected to the twenty-sixth electrode plate 3126 through vertical coupling, and connected to the second metal conductive strip 3202 through the fourteenth via 514; the twenty-third electrode plate 3123 is connected to the twenty-seventh electrode plate 3127 through vertical coupling, and connected to the third metal conductive strip 3203 through the fifteenth via 515; the twenty-fourth electrode plate 3124 is connected to the twenty-eighth electrode plate 3128 through vertical coupling, and connected to the fourth metal conductive strip 3204 through the sixteenth via 516; wherein, the thirteenth via 513 is connected to the ninth via 509, the fourteenth via 514 is connected to the tenth via 510, the fifteenth via 515 is connected to the eleventh via 511, and the sixteenth via 516 is connected to the twelfth via 512.

[0090] The seventh circuit layer is completely identical to the fifth circuit layer in structure, and the twenty-eighth electrode plate 3128 is connected to the twenty-ninth electrode plate 3129 through the eighth via 508;

[0091] The eighth circuit layer includes a first metal conductive strip 3201 connected to a fifth metal conductive strip 3205 through a seventeenth via 517; a second metal conductive strip 3202 connected to a sixth metal conductive strip 3206 through an eighteenth via 518; a third metal conductive strip 3203 connected to a seventh metal conductive strip 3207 through a nineteenth via 519; and a fourth metal conductive strip 3204 connected to an eighth metal conductive strip 3208 through a twentieth via 520.

[0092] The ninth circuit layer includes a fifth metal conductive strip 3205 connected to a ninth metal conductive strip 3209 via a twenty-first via 521; a sixth metal conductive strip 3206 connected to a tenth metal conductive strip 3210 via a twenty-second via 522; a seventh metal conductive strip 3207 connected to an eleventh metal conductive strip 3211 via a twenty-third via 523; an eighth metal conductive strip 3208 connected to a twelfth metal conductive strip 3212 via a twenty-fourth via 524; and a twenty-ninth electrode plate 3129 connected to the second metal stripline 412 via the eighth via 508 and the thirtieth via 530.

[0093] The tenth circuit layer includes a ninth metal conductive strip 3209 , a tenth metal conductive strip 3210 , an eleventh metal conductive strip 3211 , and a twelfth metal conductive strip 3212 , which are connected to the first ground layer 61 through a twenty-fifth via 525 , a twenty-sixth via 526 , a twenty-seventh via 527 , and a twenty-eighth via 528 , respectively.

[0094] The eleventh circuit layer includes the first ground layer 61 with a matrix area of ​​0.35 mm in length and width dug out to pass through the eighth via hole 508 .

[0095] Among them, the first electrode plate 3101, the fifth electrode plate 3105, and the ninth electrode plate 3109 form a capacitor C1; the second electrode plate 3102, the sixth electrode plate 3106, and the tenth electrode plate 3110 form a capacitor C3; the third electrode plate 3103, the seventh electrode plate 3107, and the eleventh electrode plate 3111 form a capacitor C5; the fourth electrode plate 3104, the eighth electrode plate 3108, and the twelfth electrode plate 3112 form a capacitor C7; the thirteenth electrode plate 3113, the seventeenth electrode plate 3117, the twenty-first electrode plate 3121, and the twenty-fifth electrode plate 3125 form a capacitor C2; the fourteenth electrode plate 3114, the eighteenth electrode plate 3118, the twenty-second electrode plate 3122, and the twenty-sixth electrode plate 3126 form a capacitor C4; the fifteenth electrode plate 3115, the nineteenth electrode plate 3117, the twenty-first electrode plate 3121, and the twenty-fifth electrode plate 3125 form a capacitor C2; Plate 3119, the twenty-third electrode plate 3123, and the twenty-seventh electrode plate 3127 form capacitor C6; the sixteenth electrode plate 3116, the twentieth electrode plate 3120, the twenty-fourth electrode plate 3124, and the twenty-eighth electrode plate 3128 form capacitor C8; the twenty-ninth electrode plate 3129 is a ground filtering and decoupling capacitor C9; the first metal conductive strip 3201, the fifth metal conductive strip 3205, and the ninth metal conductive strip 3209 form inductor L1; the second metal conductive strip 3202, the sixth metal conductive strip 3206, and the tenth metal conductive strip 3210 form inductor L2; the third metal conductive strip 3203, the seventh metal conductive strip 3207, and the eleventh metal conductive strip 3211 form inductor L3; the fourth metal conductive strip 3204, the eighth metal conductive strip 3208, and the twelfth metal conductive strip 3212 form inductor L4.

[0096] The trap module 400 includes a first coupler CL1, a second coupler CL2, and a third coupler CL3. The first coupler CL1, the second coupler CL2, and the third coupler CL3 are connected in series, with the other end of the first coupler CL1 connected to one end of the ground filter decoupling capacitor C9 via the 30th via 530, and the other end of the third coupler CL3 connected to the output electrode OUT. The first coupler CL1, the second coupler CL2, and the third coupler CL3 all employ a parallel coupled stripline structure, with the first coupler CL1 and the third coupler CL3 forming two parallel coupled lines, and the second coupler CL2 forming three parallel coupled lines. The first coupler CL1 is located on the 12th and 13th layers of the chip's three-dimensional circuitry, the second coupler CL2 is located on the 15th, 16th, and 17th layers of the chip's three-dimensional circuitry, and the third coupler CL3 is located on the 19th and 20th layers of the chip's three-dimensional circuitry. The 14th, 18th, and 21st layers are ground layers, connected to the ground electrode GND.

[0097] Combine Figure 18-27 、 Figures 37-46 , the specific structures of the twelfth to twenty-first circuit layers are described in detail:

[0098] The twelfth circuit layer includes a first metal stripline 411 connected to a second metal stripline 412 via vertical coupling, and connected to the first ground layer 61 via a twenty-ninth via 529;

[0099] The thirteenth circuit layer includes the second metal stripline 412 connected to the fourth metal stripline through the thirty-first via 531;

[0100] The fourteenth circuit layer includes the second ground layer 62 , which is dug out from a matrix area with a length and width of 0.35 mm passing through the thirty-first via hole 531 ;

[0101] The fifteenth circuit layer includes a third metal stripline 413 connected to a fourth metal stripline 414 via vertical coupling, and connected to the second ground layer 62 via a thirty-second via 532;

[0102] The sixteenth circuit layer includes the fourth metal stripline 414 connected to the seventh metal stripline 417 through the thirty-third via 533;

[0103] The seventeenth circuit layer includes a fifth metal stripline 415 connected to the fourth metal stripline 414 through vertical coupling, and connected to the third ground layer 63 through a thirty-fourth via 534;

[0104] The eighteenth circuit layer includes the third ground layer 63 , where a matrix area having a length and a width of 0.35 mm is dug out and passes through the thirty-third via hole 533 ;

[0105] The nineteenth circuit layer includes the sixth metal stripline 416 connected to the seventh metal stripline 417 through vertical coupling, and connected to the third ground layer 63 through the thirty-fifth via 535;

[0106] The twentieth circuit layer includes a seventh metal stripline 417 connected to the output electrode OUT through a thirty-sixth via 536;

[0107] The twenty-first circuit layer includes a fourth ground layer 64 .

[0108] The first ground layer 61 , the second ground layer 62 , the third ground layer 63 , and the fourth ground layer 64 are all connected to the ground electrode GND.

[0109] The first metal stripline 411 and the second metal stripline 412 form a first coupler CL1 ; the third metal stripline 413 , the fourth metal stripline 414 , and the fifth metal stripline 415 form a second coupler CL2 ; and the sixth metal stripline 416 and the seventh metal stripline 417 form a third coupler CL3 .

[0110] like Figure 18-19 、 Figure 21-23As shown, the twelfth, thirteenth, fifteenth, sixteenth and seventeenth circuit layers where the couplers are located are all provided with isolation walls IW, and the isolation walls IW are all connected to and grounded to the second ground layer 62 and the third ground layer 63, and a ground layer is provided between each level of the coupled transmission line. This design separates the coupled transmission line levels from each other and from other devices, and at the same time plays the role of lateral isolation and vertical isolation to avoid other coupling effects that affect the passband width, and at the same time shields the internal circuit signals and provides strong support.

[0111] In this embodiment, the relative dielectric constant of the LTCC ceramic dielectric substrate used is 7.5, the dielectric loss tangent is 0.003, and the circuit layer is made of metal, preferably silver.

[0112] In this embodiment, a miniaturized ultra-wideband high-pass filter plus notch filter integrated chip is constructed by using a three-dimensional structure of LTCC technology. The overall package size is controlled to 4.5×3.2×2.5mm. The ultra-wideband high-pass filter module and notch filter module are integrated internally. The transmission zero point is adjusted by the resonator, and the impedance matching is adjusted to adjust the in-band impedance matching and out-of-band suppression. Figure 50 , taking fc as the benchmark (fc is a certain frequency in the S band, and the horizontal axis is expressed as multiples of fc as the benchmark), a high-pass filter with an ultra-wide bandwidth of fc to 9*fc and strong out-of-band signal suppression is realized, and it meets the requirements of strong suppression of clutter interference near the 3*fc frequency within the fc to 9*fc frequency band, and the suppression in the nearby frequency range exceeds 25dB. It has the performance characteristics of low loss, multiple transmission zeros, strong out-of-band signal suppression, steep notch curve, high reliability, etc., meeting the requirements of electronic component integration and miniaturization.

[0113] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A miniaturized ultra-wideband high-pass filter and notch filter integrated chip based on LTCC technology, characterized by: Use LTCC process technology to achieve three-dimensional integration of chips, including substrate, external electrodes, filter circuit module, and notch filter module; The external electrode includes an input terminal, an output terminal and a ground terminal; The filter circuit module and the wave trap module are arranged inside the base body; The filtering circuit module includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a first inductor, a second inductor, a third inductor and a fourth inductor. One end of the first capacitor is connected to the input end through a first via, and the other end of the first capacitor is connected to one end of the third capacitor through a second via. At the same time, the two ends of the third capacitor are respectively connected in parallel with the two ends of the fifth capacitor through a third via and a fourth via to form a first equivalent capacitor. One end of the seventh capacitor is connected to one end of the fifth capacitor through a fifth via, so that the first capacitor, the first equivalent capacitor and the seventh capacitor are connected in series. The input end is simultaneously connected to one end of the second capacitor through the first via, and the other end of the second capacitor is connected to one end of the first inductor through a thirteenth via to form a A series resonant structure forms a first zero point, one end of the fourth capacitor is connected to one end of the third capacitor through a sixth via, and the other end of the fourth capacitor is connected to one end of the second inductor through a fourteenth via to form a series resonant structure to form a second zero point, one end of the sixth capacitor is connected to one end of the fifth capacitor through a seventh via, and the other end of the sixth capacitor is connected to one end of the third inductor through a fifteenth via to form a series resonant structure to form a third zero point, one end of the eighth capacitor is connected to one end of the seventh capacitor through an eighth via, and the other end of the eighth capacitor is connected to one end of the fourth inductor through a sixteenth via to form a series resonant structure to form a fourth zero point, and the other ends of the first to fourth inductors are connected to the first ground layer through twenty-fifth to twenty-eighth vias, respectively, so that the first to fourth inductors are connected in parallel; The wave trap module includes a first coupler, a second coupler, and a third coupler, wherein the first coupler, the second coupler, and the third coupler are sequentially connected in series; The first ground layer is connected to the ground terminal.

2. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 1, characterized in that: The filter circuit module and the wave trap module are connected via a ground filtering and decoupling capacitor to weaken the coupling effect between the filter circuit module and the wave trap module and achieve impedance matching.

3. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 2, characterized in that: The chip includes a multi-layer LTCC ceramic substrate and a circuit layer correspondingly arranged on the LTCC ceramic substrate.

4. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 3, characterized in that: The filtering circuit module has eleven layers, the first capacitor, the third capacitor, the fifth capacitor, and the seventh capacitor are arranged on the first, second, and third layers of the chip three-dimensional circuit, the second capacitor, the fourth capacitor, the sixth capacitor, and the eighth capacitor are arranged on the fourth, fifth, sixth, and seventh layers of the chip three-dimensional circuit, the first inductor, the second inductor, the third inductor, and the fourth inductor are arranged on the eighth, ninth, and tenth layers of the chip three-dimensional circuit, and the eleventh layer of the chip three-dimensional circuit is the ground layer.

5. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 4, characterized in that: The first to eighth capacitors all adopt parallel stacking technology to reduce the volume occupied by the capacitors and achieve chip miniaturization.

6. The miniaturized ultra-wideband high-pass filter and notch filter integrated chip based on LTCC technology according to claim 4, characterized in that: The first to fourth inductors all adopt a stacked structure, and the metal coils on different dielectric layers are connected through vias.

7. The miniaturized ultra-wideband high-pass filter and notch filter integrated chip based on LTCC technology according to claim 3, characterized in that: The trap module has ten layers, the first coupler is arranged on the twelfth and thirteenth layers of the chip three-dimensional circuit, the second coupler is arranged on the fifteenth, sixteenth and seventeenth layers of the chip three-dimensional circuit, the first coupler is arranged on the nineteenth and twentieth layers of the chip three-dimensional circuit, and the fourteenth, eighteenth and twenty-first layers of the chip three-dimensional circuit are ground layers.

8. The miniaturized ultra-wideband high-pass filter and notch filter integrated chip based on LTCC technology according to claim 7, characterized in that: The first to third couplers all adopt parallel coupled stripline structures, wherein the first coupler and the third coupler are both two-segment parallel coupled lines, and the second coupler is three-segment parallel coupled lines.

9. The miniaturized ultra-wideband high-pass filter and notch filter integrated chip based on LTCC technology according to claim 8, characterized in that: The dielectric layers where the first to third couplers are located are all provided with isolation walls, which are connected to the ground end and are used to separate the coupling transmission line stages from each other and from other devices to avoid other coupling effects.

10. The miniaturized ultra-wideband high-pass filter and notch filter integrated chip based on LTCC technology according to claim 3, characterized in that: The circuit layers are all made of metal, and the LTCC ceramic substrates thereof are all LTCC dielectric substrates with a dielectric constant of 7.5 and a dielectric loss tangent of 0.003.

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