Small-size delay network based on SIP technology

Abstract

The invention provides a small-size delay network based on an SIP (Session Initiation Protocol) technology. The delay network comprises an amplifier, a delayer, a power divider, a switch and an equalizer, the radio frequency signal transmission sequence is as follows: four radio frequency input ends pass through four high-gain low-noise amplifiers; entering four delayers to complete the delay function of four branches; each path of radio-frequency signal is divided into two paths after passing through a single-pole two-throw switch, the two paths of radio-frequency signals are synthesized through a power divider, and the synthesized four paths of signals are selectively output through a single-pole two-throw switch; a delayer chip is arranged on the trunk; the radio frequency amplitude is compensated through an amplifier and an equalizer, and the whole delay network is arranged in a central symmetry mode. According to the invention, the radio frequency delay line chips are respectively arranged on the upper printed board and the lower printed board in the ceramic tube shell, the delay chips on the upper layer and the lower layer are interconnected through the solder balls, and the serial-to-parallel conversion chip and the delayer chip are directly bonded through the gold wire.

Description

Technical Field

[0001] The present application relates to the field of microwave technology, and in particular to a small-size delay network based on SIP technology. Background Art

[0002] Traditional phased array antennas use microwave phase shifters to control the beam. Due to the limitations of aperture effect and aperture transit time, it is difficult to achieve large instantaneous bandwidth at large scanning angles. The fundamental reason is that microwave phase shifters can only provide a constant signal phase shift value, and the size does not change with the signal frequency. In addition, the signal delay of each phase shifter is basically the same, and it is impossible to compensate for the time difference caused by the spatial position relationship of the signal element. The good amplitude-frequency characteristics and continuity of the delay line can effectively solve this problem, thereby ensuring that instantaneous large signals can be transmitted without distortion. Therefore, the research on high-precision microwave broadband delay line technology under high-frequency characteristics has certain practical significance in improving the performance of phased array systems.

[0003] SIP (system in package) technology refers to a technology that further reduces component size and improves integration through high-density packaging of multifunctional chip units at the device level. The back of the module unit can be flipped on a traditional printed circuit board through the BGA (Ball Grid Array) assembly method. It has the advantages of high system reliability, small size, light weight, low research and development cost and short development time.

[0004] The circuit design of the traditional delay line network is to realize the cascade connection of multiple delay chips on a two-dimensional planar circuit. However, due to the large size and large number of pins of the delay chip, the circuit area occupied is large, and a parallel port is often used to control the working state of the delay chip. Summary of the invention

[0005] The present application provides a small-size delay network based on SIP technology, which can be used to solve the technical problems of large size and high loss of existing delay networks.

[0006] The present application provides a small-size delay network based on SIP technology, the delay network including an amplifier, a delayer, a power divider, a switch, and an equalizer;

[0007] The RF signal transmission sequence is as follows:

[0008] The four radio frequency input ends pass through four high-gain low-noise amplifiers; the four input ends are input end A, input end B, input end C, and input end D;

[0009] Enter four delay devices to complete the delay function of four branches;

[0010] Each RF signal is divided into two paths after passing through a single-pole double-throw switch, and then synthesized through a power divider to form two output port networks of A+B and A+C, or B+D and C+D. The synthesized four-path signal is selected for output through a single-pole double-throw switch; a delay chip is set on the main line; finally, the RF amplitude is compensated through a high-gain amplifier and an equalizer, and the entire delay network is arranged in a central symmetrical manner.

[0011] Further, the delay network includes two layers of printed circuit board areas, a top layer and a bottom layer;

[0012] Four delay chips are arranged on the top printed circuit board area as the delay amounts of the four branches;

[0013] Two delay chips are arranged in the bottom printed circuit board area as the delay of two common outputs;

[0014] The four RF input ports, after being interconnected by gold wire bonding and printed circuit boards, the amplifier transmits four RF signals to the top printed circuit board through a BGA ball, namely BGA ball 1, BGA ball 2, BGA ball 3, and BGA ball 4;

[0015] Each path passes through a 7-bit delay chip and then a single-pole double-throw switch to divide the four RF signals into eight RF signal links named A1, A2, B1, B2, C1, C2, D1 and D2, and then these eight signals are combined through a two-way power divider;

[0016] Then the two combined signals are combined through a single-pole double-throw switch, passed through an amplifier, and then transmitted to the lower substrate through a BGA ball 5. The other RF signal is also combined through a single-pole double-throw switch, passed through an amplifier, and then transmitted to the bottom printed circuit board through a BGA ball 6.

[0017] Furthermore, the amplifier chips with four input ports are arranged in a centrally symmetrical distribution inside the tube shell, wherein each section of the RF transmission line is interconnected by the same number of RF through holes and is symmetrically arranged, with eight branch phase transmissions and two common end output ports also arranged symmetrically.

[0018] Furthermore, the four high-gain low-noise amplifiers at the input end have a gain of more than 21 dB, and the two high-gain amplifiers arranged at the common output port also have a gain of 21 dB.

[0019] Furthermore, the serial-to-parallel conversion chip and the delay chip are bonded with gold wires; six serial-to-parallel conversion chips are connected in series, and 48 parallel control lines are controlled by controlling 4 serial code data.

[0020] Furthermore, the delay chip is a 7-bit chip with a mirror version and a delay accuracy of 6ps.

[0021] Compared with the prior art, the present invention has the following significant advantages:

[0022] (1) The common RF port at the bottom of the ceramic tube shell is used for RF input and output layout, and BGA balls are used to realize the internal and external transmission of RF signals, control signals and power supply. At the same time, a large number of BGA balls are laid out for grounding, which effectively ensures the RF transmission performance and heat dissipation performance;

[0023] (2) In the layout of the upper and lower printed circuit boards inside the ceramic tube shell, a 7-bit delay chip with a delay accuracy of 6ps is selected with a mirror version. Two delay chips are arranged on the lower substrate as the delay of the two common outputs. The circuit is arranged with central symmetry to ensure the amplitude and phase consistency of the link transmission. At the same time, four delay chips are arranged on the upper substrate as the delay of the four branches. The maximum delay that can be achieved for each single output of the combined network is 768ps. After the combination, the final total delay reaches 1.512ns;

[0024] (3) The serial-to-parallel conversion chip is placed near the delay chip, and the two chips are directly interconnected by gold wire bonding, which not only reduces the circuit area but also reduces the number of control ports.

[0025] (4) By adopting a double-layer SIP circuit layout and using BGA balls to achieve electrical connection between RF signals and digital signals between two layers of printed circuit boards, the product size is greatly reduced, and the volume is reduced by more than 85% compared to traditional network size;

[0026] (5) In the RF link, multiple high-gain low-noise amplifiers are deployed to ensure that the entire delay network has a low noise coefficient and small insertion loss, so that it can be cascaded with other functional modules to realize network functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A concise principle block diagram for realizing the present invention;

[0028] Figure 2 A schematic diagram of the distribution of solder joints at the bottom of the BGA tube shell to realize the present invention;

[0029] Figure 3 To realize the underlying circuit schematic diagram of the present invention;

[0030] Figure 4 To implement the top-level circuit schematic diagram of the present invention;

[0031] Figure 5 A schematic diagram of direct gold wire bonding between the delay chip and the serial-to-parallel conversion chip to realize the present invention;

[0032] Figure 6A schematic diagram of the bottom chip layout for implementing the present invention;

[0033] Figure 7 A schematic diagram of top-level radio frequency connections for implementing the present invention. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0035] The present invention adopts 3D stacking technology to layout the radio frequency delay chip on the upper and lower printed circuit boards inside the ceramic tube shell respectively, and interconnects the upper and lower delay chips through BGA solder balls. At the same time, the integrated serial-to-parallel conversion chip and the delay chip are directly interconnected by gold wire bonding to reduce the number of control ports. Since the chip with a large delay has a large loss, a high-gain low-noise amplifier is added in the link design to compensate for the loss of the link, and finally a delay network device with small insertion loss, large delay, small number of control ports and small size is realized.

[0036] Combination Figure 1 A small-size delay network based on SIP technology. The overall link design includes four RF input ends, which first pass through four high-gain low-noise amplifiers to ensure the low-noise performance of the link, and then enter four delay chips to complete the delay function of the four branches. Then each RF signal is divided into two after passing through a single-pole double-throw switch, and then through a power divider to synthesize the two paths. In this embodiment, the A port is respectively synthesized with the B and C ports, and the D port is respectively synthesized with the B and C ports. The synthesized four-way signal is selected for output through a single-pole double-throw switch, and finally a same delay chip is set on the trunk line. Finally, the RF amplitude is compensated by a high-gain amplifier and an equalizer. The high-gain amplifier is selected in the link mainly to compensate for the large insertion loss of the delay chip. The entire link is arranged in a central symmetrical manner, so that the device has the function of combining two equal-amplitude and in-phase output. The size of the entire SIP unit is only 21mm*16mm*3.8mm, which is equivalent to 1 / 5 of the size of traditional components. The application also includes several ceramic sheets with a thickness of 0.127mm for compensating RF transmission. Four high-gain low-noise amplifiers are arranged at the input port, with a gain of more than 21dB. At the same time, two high-gain amplifiers are arranged at the common output port, with a gain of 21dB, for a total gain of 42dB, ensuring that the entire delay network has a low noise figure and small insertion loss, which is convenient for cascading with other functional modules. In this application, 11 RF ports use standard SIP ceramic tube shells.

[0037] Four high-gain low-noise amplifiers are arranged at the input port with a gain of more than 21dB. At the same time, two high-gain amplifiers are arranged at the common output port with a gain of 21dB, with a total gain of 42dB. This ensures that the entire delay network has a low noise figure and a small insertion loss, which is convenient for cascading with other functional modules.

[0038] Combination Figure 2 , the external interface diagram of the device of the present invention, as shown in the figure, wherein A04B04, A16B04, A04B22 and A16B22 correspond to the four RF input ports A, B, C, D of the device of the present invention, and their distribution is centrally symmetrical, A10B04, A10B22 correspond to the RF output port 1 and port 2 of the device of the present invention, which are also symmetrically distributed, A04B08, A04B09, A04B10, A04B11 correspond to the chip select signal, clock signal, data bit and latch signal of port 1 of the four serial control interfaces, A16B08, A16B09, A16B10, A16B11 data bit of port 2, -5V power supply, state switching and +5V power supply, and the remaining interfaces are all grounded.

[0039] Combination Figure 3 and Figure 4 The RF chips are arranged in the top and bottom printed circuit board areas respectively, mainly for the delay device, amplifier, single-pole double-throw switch, one-to-two equal-division power divider, etc. in the link. Four delay device chips are arranged in the top printed circuit board area as the delay of the four branches; two delay device chips are arranged in the bottom printed circuit board area as the delay of the two common outputs; as shown in the figure, A, B, C, and D are four RF input ports, which directly enter the amplifier after gold wire bonding and printed circuit board interconnection, and then pass through a BGA ball, respectively. Named as BGA ball 1, BGA ball 2, BGA ball 3, BGA ball 4, the four RF signals are transmitted to the top printed circuit board, and then each pass through a 7-bit delay chip, and then pass through a single-pole double-throw switch to divide the four RF signals into eight RF signal links named A1, A2, B1, B2, C1, C2, D1 and D2 respectively, and then these eight signals are combined through a two-way power divider, where A1 and C2 are combined into A+C branches. The specific corresponding combining relationship is shown in Table 1 below.

[0040] Table 1. Combined path relationship table

[0041] RF branch A1 A2 B1 B2 C1 C2 D1 D2 A+B √ √ C+D √ √ A+C √ √ B+D √ √

[0042] Then the two combined signals A+B and A+C are combined through a single-pole double-throw switch, passed through an amplifier, and then transmitted to the lower substrate through a BGA ball 5. In addition, the RF signals of B+C and B+D are also combined through a single-pole double-throw switch, passed through an amplifier, and then transmitted to the bottom printed circuit board through a BGA ball 6. In this way, the entire top-level printed layout is completed.

[0043] The RF signals reaching the bottom printed circuit board are processed by the same branch respectively. The RF signals A+B and A+C are output through output port 2 after passing through amplifier 6, equalizer 1, branch delay 1 and attenuator 1. The signals C+D and B+D are also processed by the same chip and finally output through output port 1. In this way, the entire link completes the combination of the four RF input ports A, B, C, and D into two networks A+B / C+D and A+C / B+D for output.

[0044] Among them, six serial-to-parallel conversion chips are connected in series, and only by controlling 4 serial code data, up to 48 parallel control lines of the link can be controlled, which greatly reduces the number of control ports. At the same time, the serial-to-parallel conversion chip and the delay chip are bonded with gold wire, which effectively reduces the circuit area and realizes a compact and small-size circuit layout. Compared with conventional delay network components, the size is reduced by more than 85%.

[0045] Combination Figure 5 There are 6 CNC delay chips in the link, and each CNC delay has 6 control bits, so a total of 36 data lines are required. The total size of the circuit board surface is only 19.2mm*16.2mm, and the chips also need RF links for transmission. Therefore, in order to further reduce the circuit area of ​​chip interconnection and reduce circuit loss, the control circuit of each 7-bit CNC delay is directly interconnected with the parallel data output port of the serial-to-parallel conversion chip through gold wire bonding, and then only 6 serial control bits are directly interconnected to the outside. Among them, the delay chip has a mirror version of 7 bits, and the delay accuracy is 6ps. Finally, the maximum delay of the combined network for each output is 768ps, and the maximum delay of 7 bits reaches 1.512ns.

[0046] Combination Figure 6In order to further realize the amplitude and phase characteristics of the delay network, the entire circuit substrate adopts a centrally symmetrical way to layout the RF circuit. First, the amplifier chips of the four input ports are arranged at the corresponding ports A04B04, A16B04, A04B22 and A16B22 inside the tube shell, and are centrally symmetrically distributed. When designing each section of the RF transmission line as shown in the figure A1-A1, A2-A2, B1-B1, B2-B2, C1-C1, C2-C2, D1-D1 and D2-D2, each section of the transmission line is interconnected by the same number of RF through holes. Each section of the transmission line uses simulation software to optimize its electrical length and the size of the through hole for performance, and finally realizes the characteristics of eight branch transmissions with equal phase transmission. At the same time, the output ports of the two common ends also adopt a symmetrical circuit design method.

[0047] The above-described embodiments of the present application do not constitute a limitation on the protection scope of the present application.

Claims

1. A small-size delay network based on SIP technology, characterized in that: The delay network includes an amplifier, a delay device, a power divider, a switch, and an equalizer; The RF signal transmission sequence is as follows: The four radio frequency input ends pass through four high-gain low-noise amplifiers; the four input ends are input end A, input end B, input end C, and input end D; Enter four delay devices to complete the delay function of four branches; Each RF signal is divided into two paths after passing through a single-pole double-throw switch, and then synthesized through a power divider to form two output port networks of A+B and A+C, or B+D and C+D. The synthesized four-path signal is selected for output through a single-pole double-throw switch; A delay chip is provided on the trunk line; Finally, the RF amplitude is compensated through an amplifier and an equalizer, and the entire delay network is arranged in a central symmetrical manner.

2. The delay network according to claim 1, characterized in that The delay network includes two layers of printed circuit board areas, a top layer and a bottom layer; Four delay chips are arranged on the top printed circuit board area as the delay amounts of the four branches; Two delay chips are arranged in the bottom printed circuit board area as the delay of the two common outputs; The four RF input ports, after being interconnected by gold wire bonding and printed circuit boards, the amplifier transmits four RF signals to the top printed circuit board through a BGA ball, namely BGA ball 1, BGA ball 2, BGA ball 3, and BGA ball 4; Each path passes through a 7-bit delay chip and then a single-pole double-throw switch to divide the four RF signals into eight RF signal links named A1, A2, B1, B2, C1, C2, D1 and D2, and then these eight signals are combined through a two-way power divider; Then the two combined signals are combined through a single-pole double-throw switch, passed through an amplifier, and then transmitted to the lower substrate through a BGA ball 5. The other RF signal is also combined through a single-pole double-throw switch, passed through an amplifier, and then transmitted to the bottom printed circuit board through a BGA ball 6.

3. The delay network according to claim 1, characterized in that The amplifier chip with four input ports is arranged in a centrally symmetrical distribution inside the tube shell, wherein each section of the RF transmission line is interconnected by the same number of RF through holes and is symmetrically arranged, with eight branch phase transmissions and two common-end output ports also arranged symmetrically.

4. The delay network according to claim 1, characterized in that The four high-gain low-noise amplifiers at the input end have a gain of more than 21dB, and the two high-gain amplifiers arranged at the common output port also have a gain of 21dB.

5. The delay network according to claim 1, characterized in that The serial-to-parallel conversion chip and the delay chip are bonded with gold wire; six serial-to-parallel conversion chips are connected in series, and 48 parallel control lines are controlled by controlling 4 serial code data.

6. The delay network according to claim 1, characterized in that The delay chip is a mirrored 7-bit chip with a delay accuracy of 6ps.

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