A small size delay network based on sip technology

Abstract

The application provides a small-size delay network based on SIP technology, which comprises an amplifier, a delay device, a power divider, a switch and an equalizer; and the sequence of radio frequency signal transmission is as follows: four radio frequency input ends, four high-gain low-noise amplifiers, four delay devices for completing four branch delay functions, each radio frequency signal being divided into two paths through a single-pole double-throw switch, then being combined through a power divider, and then being selected and output through a single-pole double-throw switch; a delay device chip is arranged on the main path; the radio frequency amplitude is compensated through an amplifier and an equalizer; and the whole delay network is centrally symmetrically arranged. In the application, the radio frequency delay line chip is arranged on the upper and lower two layers of printed boards in the ceramic tube shell, the upper and lower two layers of delay chips are interconnected through solder balls, and the series-parallel conversion chip is directly gold wire bonded with the delay device chip.

Description

Technical Field

[0001] This application relates to the field of microwave technology, and in particular to a small-size delay network based on SIP technology. Background Technology

[0002] Traditional phased array antennas control the beam using microwave phase shifters. Due to aperture effects and limitations in aperture transit time, achieving large instantaneous bandwidth at large scan angles is difficult. The fundamental reason is that microwave phase shifters can only provide a constant signal phase shift value, the magnitude of which does not change with the signal frequency. Furthermore, the signal delay of each phase shifter is essentially the same, and it cannot compensate for the time difference caused by the spatial relationship of the array elements. The excellent amplitude-frequency characteristics and continuity of delay lines can effectively solve this problem, thus ensuring distortion-free transmission of large instantaneous signals. Therefore, research on high-precision microwave broadband delay line technology under high-frequency characteristics has practical significance in improving the performance of phased array systems.

[0003] SIP (system-in-package) technology refers to a technology that further reduces component size and improves integration by packaging multifunctional chip units at the device level with high density. The back side can be assembled by BGA (Ball Grid Array) to flip-chip onto a traditional printed circuit board, which has the advantages of high system reliability, small size, light weight, low development cost and short development time.

[0004] Traditional delay line network circuit design involves cascading multiple delay chip chips on a two-dimensional planar circuit. However, due to the large size and numerous pins of the delay chip, it occupies a large circuit area. In addition, parallel ports are often used to control the operating state of the delay chip. Summary of the Invention

[0005] This application provides a small-size delay network based on SIP technology, which can be used to solve the technical problems of large size and high loss in existing delay networks.

[0006] This application provides a small-size delay network based on SIP technology. The delay network includes an amplifier, a delay unit, a power divider, a switch, and an equalizer.

[0007] The radio frequency signal transmission sequence is as follows:

[0008] The four radio frequency inputs pass through four high-gain, low-noise amplifiers; the four inputs are input A, input B, input C, and input D.

[0009] The circuit enters four delay units to complete the delay function of the four branches;

[0010] Each RF signal is split into two paths after passing through a single-pole double-throw switch, and then combined with a power divider to form two output port networks, A+B and A+C, or B+D and C+D. The combined four signals are then selected for output by a single-pole double-throw switch. A delay chip is installed on the trunk line. Finally, a high-gain amplifier and an equalizer are used to compensate for the RF amplitude. The entire delay network has a centrally symmetrical layout.

[0011] Furthermore, the delay network comprises two printed circuit board areas: a top layer and a bottom layer.

[0012] Four delay chips are arranged in the top printed circuit board area to provide delay for the four branch circuits;

[0013] Two delay chips are arranged in the bottom printed circuit board area to serve as delays for the outputs of the two common paths;

[0014] After the four RF input ports are interconnected by gold wire bonding and printed circuit board, the amplifier transmits the four RF signals to the top printed circuit board through a BGA ball, namely BGA ball 1, BGA ball 2, BGA ball 3, and BGA ball 4.

[0015] Each path passes through a 7-bit delay chip, and then through a single-pole double-throw switch to divide the four RF signals into eight RF signal links named A1, A2, B1, B2, C1, C2, D1, and D2 respectively. These eight signals are then combined through a two-way power divider.

[0016] Then, the two combined signals are combined through a single-pole double-throw switch, then amplified, and then transmitted to the lower substrate through a BGA ball 5. The other RF signal is also combined through a single-pole double-throw switch, then amplified, and then transmitted to the bottom printed circuit board through a BGA ball 6.

[0017] Furthermore, the amplifier chips with four input ports are arranged in a centrally symmetrical manner inside the housing, with each RF transmission line interconnected by the same number of RF vias and symmetrically arranged, with eight branch phase transmissions, and the two common output ports are also arranged symmetrically.

[0018] Furthermore, the input side features four high-gain, low-noise amplifiers with gains exceeding 21dB, and the two high-gain amplifiers located at the common output port also have a gain of 21dB.

[0019] Furthermore, the serial-to-parallel conversion chip and the delay chip are bonded together using gold wire; the six serial-to-parallel conversion chips are connected in series, and 48 parallel control lines are controlled by controlling 4 serial code data.

[0020] Furthermore, the delay chip is a 7-bit chip with a mirror image and a delay accuracy of 6ps.

[0021] Compared with the prior art, the significant advantages of this invention are:

[0022] (1) The common RF port at the bottom of the ceramic tube shell is used for RF input and output layout. BGA balls are used to realize the internal and external transmission of RF signals, control signals and power supply. At the same time, a large number of BGA balls are laid out for grounding, which effectively ensures RF transmission performance and heat dissipation performance.

[0023] (2) In the layout of the upper and lower printed circuit boards inside the ceramic tube shell, a 7-bit delay chip with a mirrored version and a delay accuracy of 6ps is selected. Two delay chips are arranged on the lower substrate as the delay of the two common outputs. The circuit is arranged with central symmetry to ensure the amplitude and phase consistency of the link transmission. At the same time, four delay chips are arranged on the upper substrate as the delay of the four branch paths. The maximum delay that can be achieved for each single output of the combined network is 768ps. The final total delay after combining is 1.512ns.

[0024] (3) The serial-to-parallel conversion chip is placed near the delay chip, and the two chips are directly interconnected by gold wire bonding, which not only reduces the circuit area, but also reduces the number of control ports.

[0025] (4) By adopting a double-layer SIP circuit layout, BGA balls are used to realize the electrical property connection between the radio frequency signal and the digital signal between the two printed circuit boards, thereby greatly reducing the product size. The size of the product is reduced by more than 85% compared to the traditional network size.

[0026] (5) By deploying multiple high-gain, low-noise amplifiers in the RF link, the entire delay network is guaranteed to have a low noise figure and low insertion loss, so as to facilitate cascading with other functional modules to realize network functions. Attached Figure Description

[0027] Figure 1 A simplified principle block diagram of the present invention;

[0028] Figure 2 A schematic diagram showing the distribution of solder joints at the bottom of the BGA casing according to the present invention;

[0029] Figure 3 The underlying circuit schematic of this invention;

[0030] Figure 4 To implement the top-level circuit schematic of this invention;

[0031] Figure 5 A schematic diagram illustrating the direct gold wire bonding between the delay chip and the serial-to-parallel conversion chip of this invention;

[0032] Figure 6A schematic diagram of the underlying chip layout for implementing the present invention;

[0033] Figure 7 A schematic diagram of the top-level radio frequency interconnection for implementing the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0035] This invention employs 3D stacking technology to lay out RF delay chip on upper and lower printed circuit boards inside a ceramic housing. The upper and lower delay chip layers are interconnected by BGA solder balls. At the same time, the integrated serial-to-parallel conversion chip and the delay chip are directly interconnected by gold wire bonding, reducing the number of control ports. Since chips with large delay have greater losses, a high-gain low-noise amplifier is added in the link design to compensate for the link loss. Ultimately, a delay network device with low insertion loss, large delay, few control ports, and small size is achieved.

[0036] Combination Figure 1 This invention discloses a small-size delay network based on SiP technology. The overall link design includes four RF input terminals. These inputs first pass through four high-gain, low-noise amplifiers to ensure low-noise performance. Then, they enter four delay chips to perform four-way delay functions. Each RF signal is then split into two paths by a single-pole double-throw switch, and then combined by a power divider. In this embodiment, port A is combined with ports B and C, and port D is combined with ports B and C in pairs. The combined four signals are then selected for output by a single-pole double-throw switch. Finally, another delay chip is placed on the trunk line, and a high-gain amplifier and an equalizer compensate for the RF amplitude. The high-gain amplifier is chosen to compensate for the large insertion loss of the delay chip. The entire link uses a centrally symmetrical layout, enabling the device to have two equal-amplitude, in-phase combined outputs. The entire SiP unit measures only 21mm*16mm*3.8mm, equivalent to 1 / 5 the size of traditional components. This application also includes several ceramic sheets with a thickness of 0.127mm to compensate for RF transmission. The input ports are equipped with four high-gain, low-noise amplifiers, each with a gain of over 21dB. Two more high-gain amplifiers, also with a gain of 21dB, are located at the common output port, resulting in a total gain of 42dB. This ensures the entire delay network has a low noise figure and minimal insertion loss, facilitating cascading with other functional modules. In this application, the 11 RF ports utilize standard SIP ceramic housings.

[0037] The input port is equipped with four high-gain, low-noise amplifiers with a gain of over 21dB, while the common output port is equipped with two high-gain amplifiers with a gain of 21dB, for a total gain of 42dB. This ensures that the entire delay network has a low noise figure and low insertion loss, making it easy to cascade with other functional modules.

[0038] Combination Figure 2 The external interface diagram of the device of the present invention is shown in the figure. Among them, A04B04, A16B04, A04B22 and A16B22 correspond to the four radio frequency input ports A, B, C and D of the device of the present invention, and their distribution is centrally symmetrical. A10B04 and A10B22 correspond to the radio frequency output ports 1 and 2 of the device of the present invention, which are also symmetrically distributed. A04B08, A04B09, A04B10 and A04B11 correspond to the chip select signal, clock signal, data bit and latch signal of port 1 of the four serial control interfaces. A16B08, A16B09, A16B10 and A16B11 correspond to the data bit of port 2, -5V power supply, state switching and +5V power supply. All other interfaces are grounded.

[0039] Combination Figure 3 and Figure 4 The RF chips are placed on two separate printed circuit board (PCB) layers, one on the top layer and one on the bottom layer. This primarily involves the placement of delay units, amplifiers, single-pole double-throw (SPDT) switches, and power dividers (1-to-2 splitters) within the circuit. Four delay unit chips are placed on the top PCB layer to provide delay for the four branch circuits; two delay unit chips are placed on the bottom PCB layer to provide delay for the two common output circuits. As shown in the diagram, A, B, C, and D are four RF input ports. After being wire-bonded and interconnected on the PCB, they directly enter the amplifier, and then pass through a BGA ball. Named BGA ball 1, BGA ball 2, BGA ball 3, and BGA ball 4, these four RF signals are transmitted to the top printed circuit board. Each signal then passes through a 7-bit delay chip and a single-pole double-throw switch, dividing the four RF signals into eight RF signal links named A1, A2, B1, B2, C1, C2, D1, and D2. These eight signals are then combined using a two-way power divider, where A1 and C2 are combined into the A+C branch. The specific combining relationships are shown in Table 1 below.

[0040] Table 1. Combining Relationships

[0041] RF branch A1 A2 B1 B2 C1 C2 D1 D2 A+B √ √ C+D √ √ A+C √ √ B+D √ √

[0042] Then, the two combined signals A+B and A+C are combined again through a single-pole double-throw switch, then amplified, and then transmitted to the lower substrate through a BGA ball 5. In addition, the radio frequency signals B+C and B+D are also combined through a single-pole double-throw switch, then amplified, and then transmitted to the bottom printed circuit board through a BGA ball 6. This completes the layout of the entire top layer printed circuit.

[0043] The RF signals arriving at the bottom printed circuit board are processed through the same branch. The RF signals of A+B and A+C are output through output port 2 after passing through amplifier 6, equalizer 1, branch delay 1 and attenuator 1. The signals of C+D and B+D are also processed through the same chip and finally output through output port 1. In this way, the entire link completes the combination of the four RF input ports A, B, C and D into two networks, A+B / C+D and A+C / B+D, for output.

[0044] The six serial-to-parallel conversion chips are connected in series. By controlling only four serial code data, up to 48 parallel control lines can be controlled, greatly reducing the number of control ports. At the same time, the serial-to-parallel conversion chips and delay chips are bonded with gold wire, which effectively reduces the circuit area and achieves a compact small-size circuit layout. Compared with conventional delay network components, the size is reduced by more than 85%.

[0045] Combination Figure 5 The link contains six numerically controlled delay chips, each with six control bits, requiring a total of 36 data lines. The total surface area of ​​the circuit board is only 19.2mm*16.2mm. Furthermore, radio frequency links are needed between the chips for transmission. Therefore, to further reduce the circuit area for chip interconnection and lower circuit losses, the control circuit of each 7-bit numerically controlled delay chip is directly interconnected with the parallel data output port of the serial-to-parallel converter chip via gold wire bonding. Only six serial control bits are directly interconnected externally. The delay chip has a mirrored 7-bit version with a delay accuracy of 6ps. Ultimately, the combined network can achieve a maximum delay of 768ps for each output, resulting in a maximum delay network delay of 1.512ns for the 7-bit chips.

[0046] Combination Figure 6To further realize the amplitude and phase characteristics of the delay network, the entire circuit board adopts a centrally symmetrical layout for the RF circuit. First, the amplifier chips with four input ports are arranged in a centrally symmetrical manner inside the casing, corresponding to ports A04B04, A16B04, A04B22, and A16B22. Each RF transmission line segment, as shown in the figure (A1-A1, A2-A2, B1-B1, B2-B2, C1-C1, C2-C2, D1-D1, and D2-D2), uses the same number of RF vias for interconnection. The electrical length and via size of each transmission line are optimized using simulation software to achieve the characteristic of equal-phase transmission in the eight branch transmissions. At the same time, the output ports of the two common terminals also adopt a symmetrical circuit design.

[0047] The embodiments described above do not constitute a limitation on the scope of protection of this application.

Claims

1. A small-size latency network based on SIP technology, characterized in that, The delay network includes amplifiers, delay units, power dividers, switches, and equalizers; The radio frequency signal transmission sequence is as follows: The four radio frequency inputs pass through four high-gain, low-noise amplifiers; the four inputs are input A, input B, input C, and input D. The circuit enters four delay units to complete the delay function of the four branches; Each RF signal is split into two paths after passing through a single-pole double-throw switch, and then combined with a power divider to form two output port networks, A+B and A+C, or B+D and C+D. The combined four signals are then selected for output by a single-pole double-throw switch. A delay chip is installed on the main circuit; Finally, the RF amplitude is compensated by an amplifier and an equalizer, and the entire delay network is centrally symmetrically laid out. RF chips are placed on the top and bottom printed circuit board (PCB) areas respectively. Delays, amplifiers, single-pole double-throw (SPD) switches, and power dividers are arranged in the links. Four delay chips are placed on the top PCB area to provide delay for the four branches. Two delay chips are placed on the bottom PCB area to provide delay for the two common outputs. A, B, C, and D are four RF input ports. After being wire bonded and interconnected on the PCB, they go directly to the amplifier, and then through a BGA ball, named BGA ball 1, BGA ball 2, BGA ball 3, and BGA ball 4, respectively, to transmit the four RF signals to the top PCB. Each of the four RF signals then goes through a 7-bit delay chip and a SPD switch to divide the four RF signals into eight RF signal links, named A1, A2, B1, B2, C1, C2, D1, and D2. The eight signals are then combined through a power divider. Then, the two combined signals A+B and A+C are combined again through a single-pole double-throw switch, then amplified, and then transmitted to the lower substrate through a BGA ball 5. In addition, the radio frequency signals B+C and B+D are also combined through a single-pole double-throw switch, then amplified, and then transmitted to the bottom printed circuit board through a BGA ball 6, completing the layout of the entire top layer printed circuit. The RF signals arriving at the bottom printed circuit board are processed through the same branch. The RF signals of A+B and A+C are output through output port 2 after passing through amplifier 6, equalizer 1, branch delay 1 and attenuator 1. The signals of C+D and B+D are processed by the same chip and finally output through output port 1. The entire link combines the four RF input ports A, B, C, and D into two networks, A+B / C+D and A+C / B+D, for output. Among them, six serial-to-parallel conversion chips are connected in series, and only four serial code data are controlled; The RF input terminals are evenly distributed at the four corners of the delay network, and the four circuits from the RF input terminals, the delay unit, the single-pole double-throw switch, and the power divider converge towards the center with the same layout. The two trunk lines after convergence are also symmetrically distributed.

2. The delay network according to claim 1, characterized in that, The amplifier chip with four input ports is arranged symmetrically inside the housing. Each RF transmission line is interconnected with the same number of RF vias and is symmetrically arranged. There are eight branch phase transmissions, and the two common output ports are also arranged symmetrically.

3. The delay network according to claim 1, characterized in that, The input has four high-gain, low-noise amplifiers with gains above 21dB, and the two high-gain amplifiers at the common output port also have a gain of 21dB.

4. The delay network according to claim 1, characterized in that, The serial-to-parallel conversion chip and the delay chip are bonded together using gold wire; the six serial-to-parallel conversion chips are connected in series, and 48 parallel control lines are controlled by controlling 4 serial code data.

5. The delay network according to claim 1, characterized in that, The delay chip is a 7-bit chip with a mirror image and a delay accuracy of 6ps.

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