Phase frequency detector, phase-locked loop and chip

Abstract

The invention discloses a phase frequency detector, a phase-locked loop and a chip, the phase frequency detector comprises a first trigger, a second trigger, a first AND gate and a second AND gate, the CK end of the first trigger is connected with a reference signal, the D end of the first trigger is connected with a high potential, the first input end of the first AND gate is connected with the Q end of the first trigger, and the second input end of the first AND gate is connected with the Q end of the second trigger; the output end of the second AND gate is connected with the RST end of the first trigger, the CK end of the second trigger is connected with a feedback signal, the D end of the second trigger is connected with a high potential, the first input end of the second AND gate is connected with the Q end of the first trigger, the second input end of the second AND gate is connected with the Q end of the second trigger, and the output end of the second AND gate is connected with the RST end of the second trigger; the first trigger and the first AND gate are powered by a first power supply, the second trigger and the second AND gate are powered by a second power supply, and the first power supply and the second power supply are the same or different power supplies. According to the invention, the linearity of the phase frequency detector is improved, the low-frequency noise of the phase-locked loop is reduced, and the area and the power consumption are reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a frequency detector, a phase-locked loop and a chip. Background Art

[0002] In the field of analog integrated circuit technology, especially in wireless and wired communications, phase-locked loops are widely used because they can generate high-quality clocks. Figure 1 As shown, in wireless communication, a phase-locked loop is used to provide a local oscillator (LO) signal to the mixer (Mixer) of the transmitter (Tx) and the receiver (Rx); wherein the phase-locked loop uses a low-frequency reference signal with high stability and low phase noise to control the voltage-controlled oscillator (VCO) through a negative feedback loop to obtain a high-frequency output clock with high stability.

[0003] In the field of phase-locked loops, especially fractional phase-locked loops of analog charge pump type, the limitation of the minimum step of integer phase-locked loops has been broken, so that the loop bandwidth of the phase-locked loop can be much larger than the minimum frequency step. A wide bandwidth of the phase-locked loop has great advantages in frequency hopping time, suppression of in-band phase noise of voltage-controlled oscillator VCO, etc. However, in the process of using multiple integers to equal decimals, the fractional phase-locked loop will introduce quantization noise. The quantization noise is not only related to the type and operating frequency of the SDM (Sigma-Delta Modulator) unit, but also to the linearity of the phase-locked loop's frequency detector. When the linearity of the phase-locked loop's frequency detector is not good, the quantization noise of the SDM unit will undergo noise folding, that is, the noise in the high-frequency band will be folded into the low-frequency band, deteriorating the in-band phase noise of the phase-locked loop.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a frequency detector, a phase-locked loop and a chip. Summary of the invention

[0005] The object of the present invention is to provide a phase-locked loop, which can solve the technical problems of noise folding, large chip area and high power consumption in the prior art when the phase-locked loop is nonlinear.

[0006] In order to achieve the above-mentioned object, a specific embodiment of the present invention provides a frequency detector, which is used to compare the phases of a reference signal and a feedback signal and output a first phase difference signal and a second phase difference signal, and is characterized in that the frequency detector includes: a first trigger, a second trigger, a first AND gate and a second AND gate, wherein:

[0007] The CK terminal of the first trigger is connected to the reference signal, the D terminal is connected to a high potential, the first input terminal of the first AND gate is connected to the Q terminal of the first trigger, the second input terminal is connected to the Q terminal of the second trigger, and the output terminal is connected to the RST terminal of the first trigger;

[0008] The CK terminal of the second trigger is connected to the feedback signal, the D terminal is connected to a high potential, the first input terminal of the second AND gate is connected to the Q terminal of the first trigger, the second input terminal is connected to the Q terminal of the second trigger, and the output terminal is connected to the RST terminal of the second trigger;

[0009] The first trigger and the first AND gate are powered by a first power supply, and the second trigger and the second AND gate are powered by a second power supply; or the first trigger, the first AND gate, the second trigger and the second AND gate are all powered by a third power supply.

[0010] In one or more embodiments of the present invention, the power supply terminal of the first trigger and the power supply terminal of the first AND gate are respectively connected to a first power supply, and the first power supply is a first LDO power supply;

[0011] The power supply terminal of the second trigger and the power supply terminal of the second AND gate are respectively connected to a second power supply, and the second power supply is a second LDO power supply.

[0012] In one or more embodiments of the present invention, the power supply terminal of the first trigger and the power supply terminal of the first AND gate are respectively connected to the third power supply through the first filtering unit, the power supply terminal of the second trigger and the power supply terminal of the second AND gate are respectively connected to the third power supply through the second filtering unit, and the third power supply is a third LDO power supply.

[0013] In one or more embodiments of the present invention, the first filtering unit includes a first resistor and a first capacitor, wherein:

[0014] The first end of the first resistor is connected to the third LDO power supply, and the second end of the first resistor is connected to the first trigger and the first AND gate respectively;

[0015] The first end of the first capacitor is connected to the second end of the first resistor, and the second end of the first capacitor is connected to the reference potential;

[0016] The second filtering unit includes a second resistor and a second capacitor, wherein:

[0017] The first end of the second resistor is connected to the third LDO power supply, and the second end of the second resistor is connected to the second trigger and the second AND gate respectively;

[0018] The first end of the second capacitor is connected to the second end of the second resistor, and the second end of the second capacitor is connected to a reference potential.

[0019] In another aspect of the present invention, a phase-locked loop is provided, the phase-locked loop further comprising an input driver, a charge pump, a multi-mode frequency divider, a low-pass filter, an SDM unit, a voltage-controlled oscillator and a local oscillator frequency divider, wherein:

[0020] The input end of the input driver is connected to the input reference signal, and the output end is connected to the CK end of the first trigger;

[0021] The first input terminal of the charge pump is connected to the Q terminal of the first trigger, and the second input terminal is connected to the Q terminal of the second trigger;

[0022] The input end of the low-pass filter is connected to the output end of the charge pump;

[0023] The input end of the voltage controlled oscillator is connected to the output end of the low pass filter;

[0024] The input end of the local oscillator frequency divider is connected to the output end of the voltage-controlled oscillator, and the output end of the local oscillator frequency divider outputs a local oscillator signal;

[0025] The first input end of the multi-mode divider is connected to the output end of the voltage-controlled oscillator, the second input end is connected to the output end of the SDM unit, and the output end of the multi-mode divider is respectively connected to the CK end of the second trigger and the input end of the SDM unit.

[0026] In one or more embodiments of the present invention, the power supply terminal of the input driver, the power supply terminal of the first trigger and the power supply terminal of the first AND gate are respectively connected to the first power supply, and the power supply terminal of the multi-mode divider, the power supply terminal of the second trigger and the power supply terminal of the second AND gate are respectively connected to the second power supply, wherein the first power supply is a first LDO power supply and the second power supply is a second LDO power supply.

[0027] In one or more embodiments of the present invention, the power supply end of the charge pump is respectively connected to the first power supply or the fourth power supply, the first power supply is the first LDO power supply, and the fourth power supply is the fourth LDO power supply; the power supply end of the voltage-controlled oscillator is connected to the fifth power supply, and the fifth power supply is the fifth LDO power supply; the power supply end of the SDM unit is connected to the second power supply or the sixth power supply, the second power supply is the second LDO power supply, and the sixth power supply is the sixth LDO power supply.

[0028] In one or more embodiments of the present invention, the power supply terminal of the input driver, the power supply terminal of the first trigger, the power supply terminal of the first AND gate, the power supply terminal of the multi-mode divider, the power supply terminal of the second trigger and the power supply terminal of the second AND gate are respectively connected to a third power supply, and the third power supply is a third LDO power supply.

[0029] In one or more embodiments of the present invention, the power supply terminal of the charge pump is connected to the third power supply or the fourth power supply, the third power supply is the third LDO power supply, and the fourth power supply is the fourth LDO power supply; the power supply terminal of the SDM unit is connected to the third power supply or the sixth power supply, and the sixth power supply is the sixth LDO power supply; the power supply terminal of the voltage-controlled oscillator is connected to the fifth power supply, and the fifth power supply is the fifth LDO power supply.

[0030] In another aspect of the present invention, a chip is provided, comprising the above-mentioned phase-locked loop.

[0031] Compared with the prior art, the frequency detector, phase-locked loop and chip of the present invention separate the voltage domains of the reference signal and the feedback signal to solve the problem of power supply crosstalk between the two signals at different power-on times, thereby greatly improving the linearity of the frequency detector, reducing the low-frequency noise of the phase-locked loop, and adaptively adding an AND gate to the first trigger and the second trigger, so that the two triggers provide reset signals in the corresponding voltage domains respectively;

[0032] The present invention uses an LDO power supply as a power supply and divides the power supply for different components according to the working frequency domain. Different numbers of power supplies can be used to power the low-frequency circuit part of the phase-locked loop according to actual conditions, thereby reducing the area and power consumption of the phase-locked loop and the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 is a schematic diagram of a wireless transceiver in the prior art;

[0035] Figure 2 It is a schematic diagram of a charge pump type integer phase-locked loop in the prior art;

[0036] Figure 3 It is a schematic diagram of a charge pump type fractional phase-locked loop in the prior art;

[0037] Figure 4 S is the folded noise of the SDM unit q (f) - graph of f;

[0038] Figure 5 A circuit diagram of a frequency detector and a charge pump in the prior art;

[0039] Figure 6 It is a transient waveform diagram of a frequency and phase detector in the prior art;

[0040] Figure 7 is a curve diagram of the PFD / CP transfer function under ideal conditions in the prior art;

[0041] Figure 8 It is a waveform diagram of a frequency and phase detector under non-ideal conditions in the prior art;

[0042] Fig. 9 is a curve diagram of the PFD / CP transfer function under non-ideal conditions in the prior art;

[0043] Fig.10 A circuit diagram of a frequency and phase detector in one embodiment of the present invention;

[0044] Fig.11 is a circuit diagram of a filter unit in one embodiment of the present invention;

[0045] Fig.12 A circuit diagram of a low-frequency circuit portion of a phase-locked loop in the prior art;

[0046] Fig.13 1 is a circuit diagram of a low-frequency circuit portion of a phase-locked loop in Embodiment 1 of the present invention;

[0047] Fig.14 This is a circuit diagram of the low-frequency circuit portion of the phase-locked loop in the second embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0049] like Figure 2 As shown in FIG. 1 , a circuit diagram of a charge pump type integer phase-locked loop in the prior art is shown. The charge pump type integer phase-locked loop includes a phase frequency detector PFD, a charge pump CP, a loop filter LPF, a voltage-controlled oscillator VCO, a local oscillator frequency divider LODiv, and a multi-mode frequency divider MMD. The input control voltage of the voltage-controlled oscillator VCO is V tune , the output frequency is f vco , output frequency f vco After the multi-mode divider MMD divides the frequency, the feedback signal f is obtained. DIV ; The phase frequency detector PFD compares the reference signal f REF and the feedback signal f DIV The phase difference is used to control the charge pump CP, and the charge pump outputs a signal that is different from the reference signal f REF and the feedback signal f DIV The phase difference is proportional to the current i CP ,i CP After filtering by the loop filter LPF, the control voltage V tune, thus forming a negative feedback closed loop; the phase frequency detector PFD compares the reference signal f REF and the feedback signal f DIV The phase difference outputs the first phase difference signal Q A and the second phase difference signal Q B ; The output frequency f of the voltage controlled oscillator VCO output vco After passing through the local oscillator frequency divider LODiv, the local oscillator signal f LO ; The division ratio N of the multi-mode divider MMD is controlled by a register, where the reference signal f REF With the output frequency f vco Between satisfies satisfies f vco＝ N*f REF , for an integer phase-locked loop, N is an integer.

[0050] like Figure 3 As shown, it is a schematic diagram of a charge pump type fractional phase-locked loop in the prior art. A SDM (Sigma-Delta Modulator) unit is added to the charge pump type integer phase-locked loop. The SDM unit can equivalently output a fractional division ratio of Nf, wherein N is the integer part and f is the fractional part. Although the introduction of the SDM unit improves the limitation of the minimum step of the integer phase-locked loop, it also brings quantization noise.

[0051] like Figure 4 As shown in the figure, the quantization noise of the SDM unit will experience noise folding, that is, the noise in the high frequency band will be folded into the low frequency band, where S q (f) represents the spectrum of quantization noise, with the highest value at f CK / 2, f CK is the operating frequency of the SDM unit. When the phase-locked loop has nonlinearity, S q (f) Mixing occurs, that is, frequency f 1 and frequency f 2 The phase noise at the position will generate a new frequency component f through nonlinearity. 2 -f 1 , because f 2 -f 1 It is located at a low frequency, therefore, it raises the low frequency noise of the SDM unit, and this noise cannot be filtered out by the loop filter LPF.

[0052] Therefore, to avoid the noise folding phenomenon of the SDM unit, the nonlinearity of the phase-locked loop must be solved, and the nonlinearity in the phase-locked loop usually comes from the phase frequency detector (PFD).

[0053] like Figures 4-5 As shown in the figure, it is a circuit diagram of a phase frequency detector PFD and a charge pump CP of a phase-locked loop in the prior art. The phase frequency detector PFD includes a first trigger DFF 1and the second flip-flop DFF 2 And the first AND gate AND 1 , the first trigger DFF 1 The CK terminal is connected to the reference signal f REF , D terminal is connected to high potential H; the second trigger DFF 2 The CK terminal is connected to the feedback signal f DIV , D terminal is connected to high potential H. The first trigger DFF 1 The output is the first phase difference signal Q A (ie UP), the second trigger DFF 2 Output the second phase difference signal Q B (ie, DN). The first phase difference signal Q A and the second phase difference signal Q B After the first AND gate 1 After that, a reset signal RST is output. The charge pump CP includes a first current source I UP , the second current source I DN , a first switch S1 and a second switch S2. The first switch S1 is controlled by the first phase difference signal Q A Control, when the first phase difference signal Q A When it is 1, the first switch S1 is turned on, and the first current source I UP The load capacitance C of the loop filter LPF P The second switch S2 is charged by the second phase difference signal Q B Control, when the second phase difference signal Q B When it is 1, the second switch S2 is turned on, and the second current source I DN Give the load capacitance C P Discharge. The total output current of the charge pump CP is i CP , output current i CP The corresponding output voltage is Vout. Ideally, the current of the current source satisfies: I UP =I DN =I CP , I CP Represents the charge pump current.

[0054] The working principle of the phase frequency detector (PFD) is as follows: REF When the rising edge comes, the first phase difference signal Q A Pull high; when the feedback signal f DIV When the rising edge comes, the second phase difference signal Q B Pull high; when the first phase difference signal Q A and the second phase difference signal Q B When both are high, the reset signal RST is pulled high, and the first trigger DFF 1 and the second flip-flop DFF 2Reset and set the first phase difference signal Q A and the second phase difference signal Q B To avoid the dead zone, the first AND gate is usually 1 Add a delay unit to avoid the reference signal f REF With the feedback signal f DIV When the rising edge approaches, the first phase difference signal Q A and the second phase difference signal Q B The waveform is distorted.

[0055] like Figure 6 As shown, when the reference signal f REF Lead feedback signal f DIV When the phase difference is ΔФ, the charge pump current I CP Keep charging the load capacitor CP, the output voltage Vout rises in a step-like manner, scan the phase difference ΔФ, and observe the output response of the voltage Vout, and you can get the transfer function of the phase frequency detector PFD / charge pump CP: Among them, I P is the peak current, and s is the complex frequency variable in the Laplace transform.

[0056] like Figure 7 As shown in the figure, it is the curve of the transfer function of the phase frequency detector PFD / charge pump CP under ideal conditions. Under ideal conditions, the curve is a straight line. When the transfer function curve deviates from the curve, it is the nonlinearity of the phase frequency detector PFD and the charge pump CP. Among them, the nonlinearity of the phase frequency detector PFD mainly comes from the jitter of the power supply. The power supply of the phase frequency detector PFD comes from the on-chip LDO (low-dropout linear regulator). The output of the LDO generally places a large enough capacitor to play a filtering and voltage stabilization role. However, the loop bandwidth of the LDO is limited, and the filter capacitor cannot be infinite. Therefore, the LDO output voltage will change with the change of the pumping current of the phase frequency detector.

[0057] like Figure 8 As shown, the reference signal f REF Phase advance feedback signal f DIV The phase difference is ΔФ, each time the reference signal f REF When the rising edge comes, the first trigger DFF of the phase frequency detector PFD 1 Extracting a part of the transient current causes the LDO voltage AVDD_PFD to drop rapidly and then recover slowly. Then wait for the feedback signal f DIV When the rising edge comes, the voltage recovery process is interrupted and the voltage continues to pull down. Because the transient power supply voltage at different times is different, the lower the voltage, the greater the delay. Therefore, the reference signal f REFThe time interval from the rising edge to the UP rising edge must be smaller than the feedback signal f DIV The time interval from the rising edge to the rising edge of DN, such a process will result in the reference signal f REF Lead feedback signal f DIV The phase is smaller than the first phase difference signal Q A Leading the second phase difference signal Q B When ΔФ approaches 0, this phenomenon will be even worse.

[0058] like Fig. 9 As shown in the figure, under the above non-ideal conditions, the curve of the transfer function of the phase frequency detector PFD / charge pump CP has a bump at the origin, which is equivalent to the gain expansion at this time. Therefore, this effect worsens the nonlinearity of the phase frequency detector PFD and the charge pump CP. Especially when the phase-locked loop is locked, the reference signal f REF With the feedback signal f DIV Close alignment causes the folding of the SDM unit noise, thereby deteriorating the in-band phase noise of the phase-locked loop. From the above analysis, it can be concluded that the nonlinearity of the phase frequency detector (PFD) mainly comes from the reference signal f REF With the feedback signal f DIV Power crosstalk at different power withdrawal times.

[0059] As attached Fig.10 As shown, in view of the above problems, the present invention provides a phase frequency detector PFD, which is used to convert the reference signal f REF With the feedback signal f DIV Perform phase comparison and output the first phase difference signal Q A and the second phase difference signal Q B The phase frequency detector PFD includes: the first trigger DFF 1 , the second trigger DFF 2 , the first AND gate AND 1 And the second AND gate 2 ,in,

[0060] First trigger DFF 1 The CK terminal and the reference signal f REF connected, the D terminal is connected to the high potential H, the first AND gate AND 1 The first input terminal of the first flip-flop DFF 1 The second input terminal is connected to the Q terminal of the second flip-flop DFF 2 The Q end is connected to the output end of the first trigger DFF 1 The RST end is connected;

[0061] The second trigger DFF 1 The CK terminal and the feedback signal f DIVconnected, the D terminal is connected to the high potential H, and the second AND gate AND 2 The first input terminal of the first flip-flop DFF 1 The second input terminal is connected to the Q terminal of the second flip-flop DFF 2 The Q end is connected to the output end of the second flip-flop DFF 2 The RST end is connected;

[0062] Among them, the first trigger DFF 1 AND the first AND gate 1 The first power supply is used for power supply, and the second trigger DFF 2 And the second AND gate 2 A second power supply is used for power supply; or, a first trigger DFF 1 , the first AND gate AND 1 , the second trigger DFF 2 And the second AND gate 2 A third power source is used for power supply.

[0063] Based on the existing frequency detector and phase detector, the reference signal f REF and the feedback signal f DIV The working voltage domain is distinguished to solve the reference signal f REF and the feedback signal f DIV The power crosstalk problem at different power-drawing moments corresponds to the first trigger DFF 1 The first power supply is used for power supply, and the second trigger DFF 2 A second power supply is used to supply power. To ensure that the reset signals of the two triggers can also work in different voltage domains, a second AND gate is further added. 2 , so the first flip-flop DFF 1 AND the first AND gate 1 The first power supply is used to supply power, and the first trigger DFF 1 AND the first AND gate 1 The supply voltage is the first voltage AVDD_f REF , the second flip-flop DFF 2 And the second AND gate 2 The second power supply is used to supply power, and the second trigger DFF 2 And the second AND gate 2 The supply voltage is the second voltage AVDD_f DIV .

[0064] In a further embodiment, the first flip-flop DFF 1 The power supply terminal and the first AND gate AND 1The power supply ends of the second trigger DFF are respectively connected to the first power supply, the first power supply is the first LDO power supply; 2 The power supply terminal and the second AND gate AND 2 The power supply ends are respectively connected to the second power supply, and the second power supply is a second LDO power supply.

[0065] The first voltage AVDD_f REF and the second voltage AVDD_f DIV Supplied by different LDO power supplies, the power supply crosstalk between different signals at different power-drawing times of the same power supply is solved from the source, thereby greatly improving the linearity of the phase frequency detector (PFD).

[0066] In a further embodiment, the first flip-flop DFF 1 , the first AND gate AND 1 , the second trigger DFF 2 And the second AND gate 2 Both are powered by a third power supply; the first trigger DFF 1 The power supply terminal and the first AND gate AND 1 The power supply ends are connected to the third power supply through the first filtering unit, and the second trigger DFF 2 The power supply terminal and the second AND gate AND 2 The power supply ends are respectively connected to the third power supply through the second filtering unit, and the third power supply is a third LDO power supply.

[0067] Compared with setting the first power supply and the second power supply, setting the third power supply has a greater impact on the first trigger DFF. 1 , the first AND gate AND 1 , the second trigger DFF 2 And the second AND gate 2 For power supply, only one LDO power supply can be used to distinguish the corresponding power supply voltage of the phase frequency detector (PFD).

[0068] As attached Fig.11 As shown, in a further embodiment, the first filtering unit includes a first resistor R1 and a first capacitor C1, wherein:

[0069] The first end of the first resistor R1 is connected to the third LDO power supply, and the second end of the first resistor R1 is connected to the first trigger DFF 1 and the first AND gate ADD 1 The first end of the first capacitor C1 is connected to the second end of the first resistor R1, and the second end of the first capacitor C1 is connected to the reference potential;

[0070] The second filtering unit includes a second resistor R2 and a second capacitor C2, wherein the first end of the second resistor R2 is connected to the third LDO power supply, and the second end of the second resistor R2 is connected to the second trigger DFF 2 and the second AND gate ADD 2 connected; a first end of the second capacitor C2 is connected to the second end of the second resistor R2, and a second end of the second capacitor C2 is connected to the reference potential.

[0071] The first voltage AVDD_f is generated by the first filtering unit REF , a second voltage AVDD_f is generated by a second filtering unit DIV , which not only solves the reference signal f REF and the feedback signal f DIV It solves the problem of power crosstalk caused by different power withdrawal times and reduces the number of LDO power supplies used.

[0072] The present invention also provides a phase-locked loop, comprising the phase frequency detector PFD mentioned above, the phase-locked loop also includes an input driver REF Driver, a charge pump CP, a multi-mode divider MMD, a low-pass filter LPF, an SDM unit, a voltage-controlled oscillator VCO and a local oscillator divider LODiv, wherein:

[0073] The input terminal of the input driver REF Driver is connected to the input reference signal f REF_in , the output end is connected to the CK end of the first trigger; the first input end of the charge pump CP is connected to the Q end of the first trigger, and the second input end is connected to the Q end of the second trigger; the input end of the low-pass filter LPF is connected to the output end of the charge pump CP; the input end of the voltage-controlled oscillator VCO is connected to the output end of the low-pass filter LPF; the input end of the local oscillator frequency divider LODiv is connected to the output end of the voltage-controlled oscillator VCO, and the output end of the local oscillator frequency divider LODiv outputs the local oscillator signal f LO The first input terminal of the multi-mode divider MMD is connected to the output terminal of the voltage-controlled oscillator VCO, the second input terminal is connected to the output terminal of the SDM unit, and the output terminals of the multi-mode divider MMD are respectively connected to the second trigger DFF 2 The CK terminal of the SDM unit is connected to the input terminal of the SDM unit.

[0074] Input driver REF Driver connects to the input reference signal f REF_in And output reference signal f REF ; Phase frequency detector PFD compares the reference signal f REF and the feedback signal f DIV The phase difference outputs the first phase difference signal Q A and the second phase difference signal Q B The charge pump CP outputs a signal that is the same as the reference signal f REFand the feedback signal f DIV The phase difference is proportional to the current i CP ,i CP After filtering by the loop filter LPF, the control voltage V tune , voltage controlled oscillator VCO input control voltage V tune , the output frequency is f vco , output frequency f vco After the multi-mode divider MMD divides the frequency, the feedback signal f is obtained. DIV , thus forming a negative feedback closed loop; the output frequency f of the voltage controlled oscillator VCO output vco After passing through the local oscillator frequency divider LODiv, the local oscillator signal f LO The frequency division ratio N of the multi-mode divider MMD is controlled by a register, and the SDM unit can output n Nf fractional frequency division ratios equivalently, where N is the integer part and f is the fractional part. In this embodiment, the SDM unit can output 8 integer values ​​equivalently. For example, for a typical third-order SDM unit, the output is N-3, N-2, N-1, N, N+1, N+2, N+3, and N+4. By combining these eight numbers in different proportions, a fractional frequency division ratio of Nf can be output equivalently. Where N is the integer part and f is the fractional part, for example, Nf=50.2, then N=50, and f=0.2.

[0075] The voltage-controlled oscillator (VCO) operates at high frequency and is sensitive to power supply noise, so it usually requires a separate LDO power supply. The loop filter (LPF) is usually composed of passive resistors and capacitors and does not require an LDO power supply. Fig.12 As shown, the power supply method of the low-frequency circuit part of the traditional phase-locked loop includes: the input driver REF Driver is connected to the input reference signal f REF_in And output reference signal f REF The power supply voltage is AVDD_Buffer, the power supply voltage of the phase frequency detector PFD is AVDD_PFD, the power supply voltage of the charge pump CP is AVDD_CP, the power supply voltage of the multi-mode divider MMD is AVDD_MMD, and the power supply voltage of the SDM unit is AVDD_SDM. The 5 different power supply voltages require a total of 5 LDO power supplies and corresponding filter capacitors for the LDO power supplies. A large number of power supplies and filter capacitors increase the power consumption and area of ​​the phase-locked loop.

[0076] If the high linearity phase frequency detector PFD of the present invention is adopted on the basis of the existing phase-locked loop low-frequency circuit power supply scheme, at least one more LDO power supply needs to be added, a total of 6 LDO power supplies and their filter capacitors, which further increases the power consumption and area of ​​the phase-locked loop.

[0077] Embodiment 1

[0078] As attached Fig.13 As shown, in order to solve the above problem, this embodiment divides the supply voltage according to the working frequency domain of the corresponding signal, including dividing the power supply end of the input driver REF Driver, the first trigger DFF 1 The power supply terminal and the first AND gate ADD 1 The power supply end of the multi-mode frequency divider MMD and the second trigger DFF are respectively connected to the first power supply. 2 The power supply terminal and the second AND gate ADD 2 The power supply ends are respectively connected to the second power supply, wherein the first power supply is a first LDO power supply, and the supply voltage of the first LDO power supply is a first voltage AVDD 1 , the second power supply is a second LDO power supply, and the supply voltage of the second LDO power supply is a second voltage AVDD 2 .

[0079] In a further embodiment, the power supply terminal of the charge pump CP is connected to the first power supply or the fourth power supply, the first power supply is the first LDO power supply, and the supply voltage of the first LDO power supply is the first voltage AVDD 1 , the fourth power supply is a fourth LDO power supply, and the supply voltage of the fourth power supply is a fourth voltage AVDD 4， The power supply end of the voltage-controlled oscillator is connected to the fifth power supply, which is the fifth LDO power supply. The SDM is a pure digital circuit, so the power supply end of the SDM unit is connected to the second power supply or the sixth power supply, which is the second LDO power supply, and the supply voltage of the second LDO power supply is the second voltage AVDD. 2 , the sixth power supply is a sixth LDO power supply, and the supply voltage of the sixth LDO power supply is a sixth voltage AVDD 6 .

[0080] Among them, the SDM unit is a pure digital circuit. According to the location of the SDM unit in the chip layout, it can be shared with the second power supply or have a separate power supply. The charge pump CP uses a separate power supply. According to the specific circuit implementation structure of the charge pump, for some circuit structures, because only the i of the charge pump CP UP The current source is connected to the power supply, and the charge pump CP's i DN The current source is grounded, so the charge pump CP can share the first power supply.

[0081] Through the above division, in this embodiment, only the first LDO power supply (or the first LDO power supply and the fourth LDO power supply), the second LDO power supply (or the second LDO power supply and the sixth LDO power supply), the fourth LDO power supply and the fifth LDO power supply are used, which not only ensures the high linearity of the phase frequency detector PFD, but also reduces the number of LDO power supplies used, further limiting the number of LDOs used.

[0082] Embodiment 2

[0083] As attached Fig.14 As shown, if the phase frequency detector PFD adopts the power supply mode of the third LDO power supply, the power supply end of the input driver REFDriver and the first trigger DFF 1 The power supply terminal, the first AND gate ADD 1 The power supply end of the multi-mode divider MMD, the second trigger DFF 2 The power supply terminal and the second AND gate ADD 2 The power supply ends are respectively connected to a third power supply, and the third power supply is a third LDO power supply.

[0084] In a further embodiment, the power supply terminal of the charge pump CP is connected to a third power supply or a fourth power supply, the third power supply is a third LDO power supply, and the supply voltage of the third LDO power supply is a third voltage AVDD. 3 The fourth power supply is a fourth LDO power supply, the power supply end of the SDM unit is connected to the third power supply or the sixth power supply, the sixth power supply is the sixth LDO power supply, the power supply end of the voltage-controlled oscillator VCO is connected to the fifth power supply, and the fifth power supply is the fifth LDO power supply.

[0085] In the corresponding circuit structure, the third LDO power supply can be used to power the input driver REF Driver, the phase and frequency detector PFD, the multi-mode divider MMD, the charge pump CP and the SDM unit, and the fifth LDO power supply can be used to power the voltage-controlled oscillator VCO. Only two LDO power supplies are used to power the low-frequency circuit part of the phase-locked loop, which not only solves the nonlinear problem of the phase and frequency detector, but also greatly reduces the chip area and power consumption.

[0086] The present invention also provides a chip, comprising the above-mentioned phase-locked loop.

[0087] The frequency detector, phase-locked loop and chip in this embodiment are configured to generate a reference signal f REF and the feedback signal f DIV The working voltage domain is separated to solve the power supply crosstalk of the two signals at different power-on times, thereby greatly improving the linearity of the phase frequency detector PFD, reducing the low-frequency noise of the phase-locked loop, and adaptively providing the first trigger DFF 1 and the second flip-flop DFF 2 An AND gate is added, and the two triggers provide reset signals in the corresponding voltage domain respectively; the present invention uses an LDO power supply as the power supply, and divides the power supply for different components according to the working frequency domain. Different numbers of power supplies can be used to power the phase-locked loop according to actual conditions, thereby reducing the area and power consumption of the phase-locked loop and the chip.

[0088] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and range of equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0089] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A phase frequency detector, which is used to compare the phases of a reference signal and a feedback signal and output a first phase difference signal and a second phase difference signal, characterized in that: The frequency and phase detector comprises: a first trigger, a second trigger, a first AND gate and a second AND gate, wherein: The CK terminal of the first trigger is connected to the reference signal, the D terminal is connected to a high potential, the first input terminal of the first AND gate is connected to the Q terminal of the first trigger, the second input terminal is connected to the Q terminal of the second trigger, and the output terminal is connected to the RST terminal of the first trigger; The CK terminal of the second trigger is connected to the feedback signal, the D terminal is connected to a high potential, the first input terminal of the second AND gate is connected to the Q terminal of the first trigger, the second input terminal is connected to the Q terminal of the second trigger, and the output terminal is connected to the RST terminal of the second trigger; The first trigger and the first AND gate are powered by a first power supply, and the second trigger and the second AND gate are powered by a second power supply; or the first trigger, the first AND gate, the second trigger and the second AND gate are all powered by a third power supply.

2. The phase frequency detector according to claim 1, characterized in that: The power supply terminal of the first trigger and the power supply terminal of the first AND gate are respectively connected to a first power supply, and the first power supply is a first LDO power supply; The power supply terminal of the second trigger and the power supply terminal of the second AND gate are respectively connected to a second power supply, and the second power supply is a second LDO power supply.

3. The phase frequency detector according to claim 1, characterized in that: The power supply terminal of the first trigger and the power supply terminal of the first AND gate are respectively connected to the third power supply through the first filtering unit, the power supply terminal of the second trigger and the power supply terminal of the second AND gate are respectively connected to the third power supply through the second filtering unit, and the third power supply is a third LDO power supply.

4. The phase frequency detector according to claim 3, characterized in that: The first filtering unit includes a first resistor and a first capacitor, wherein: The first end of the first resistor is connected to the third LDO power supply, and the second end of the first resistor is connected to the first trigger and the first AND gate respectively; The first end of the first capacitor is connected to the second end of the first resistor, and the second end of the first capacitor is connected to the reference potential; The second filtering unit includes a second resistor and a second capacitor, wherein: The first end of the second resistor is connected to the third LDO power supply, and the second end of the second resistor is connected to the second trigger and the second AND gate respectively; The first end of the second capacitor is connected to the second end of the second resistor, and the second end of the second capacitor is connected to a reference potential.

5. A phase-locked loop, characterized in that: The phase-frequency detector comprises the phase detector as claimed in any one of claims 1 to 4, wherein the phase-locked loop further comprises an input driver, a charge pump, a multi-mode frequency divider, a low-pass filter, an SDM unit, a voltage-controlled oscillator and a local oscillator frequency divider, wherein: The input end of the input driver is connected to the input reference signal, and the output end is connected to the CK end of the first trigger; The first input terminal of the charge pump is connected to the Q terminal of the first trigger, and the second input terminal is connected to the Q terminal of the second trigger; The input end of the low-pass filter is connected to the output end of the charge pump; The input end of the voltage controlled oscillator is connected to the output end of the low pass filter; The input end of the local oscillator frequency divider is connected to the output end of the voltage-controlled oscillator, and the output end of the local oscillator frequency divider outputs a local oscillator signal; The first input end of the multi-mode divider is connected to the output end of the voltage-controlled oscillator, the second input end is connected to the output end of the SDM unit, and the output end of the multi-mode divider is respectively connected to the CK end of the second trigger and the input end of the SDM unit.

6. The phase-locked loop according to claim 5, characterized in that: The power supply end of the input driver, the power supply end of the first trigger and the power supply end of the first AND gate are respectively connected to the first power supply, which is a first LDO power supply; the power supply end of the multi-mode divider, the power supply end of the second trigger and the power supply end of the second AND gate are respectively connected to the second power supply, which is a second LDO power supply.

7. The phase-locked loop according to claim 6, characterized in that: The power supply end of the charge pump is connected to the first power supply or the fourth power supply respectively, the first power supply is the first LDO power supply, and the fourth power supply is the fourth LDO power supply; the power supply end of the SDM unit is connected to the second power supply or the sixth power supply, the second power supply is the second LDO power supply, and the sixth power supply is the sixth LDO power supply; the power supply end of the voltage-controlled oscillator is connected to the fifth power supply, and the fifth power supply is the fifth LDO power supply.

8. The phase-locked loop according to claim 5, characterized in that: The power supply end of the input driver, the power supply end of the first trigger, the power supply end of the first AND gate, the power supply end of the multi-mode divider, the power supply end of the second trigger and the power supply end of the second AND gate are respectively connected to a third power supply, and the third power supply is a third LDO power supply.

9. The phase-locked loop according to claim 8, characterized in that: The power supply end of the charge pump is connected to the third power supply or the fourth power supply, the third power supply is the third LDO power supply, and the fourth power supply is the fourth LDO power supply; the power supply end of the SDM unit is connected to the third power supply or the sixth power supply, the third power supply is the third LDO power supply, and the sixth power supply is the sixth LDO power supply; the power supply end of the voltage-controlled oscillator is connected to the fifth power supply, and the fifth power supply is the fifth LDO power supply.

10. A chip, characterized in that: Comprising a phase locked loop as claimed in any one of claims 5 to 9.

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