Electronic device

Abstract

The invention relates to an electronic device. The present specification relates to a device adapted to transmit and receive signals with the same antenna, the device comprising a first winding, a second winding and a third winding, the first winding and the second winding being coupled to transmit signals to be transmitted by the antenna, the first winding and the third winding being coupled to transmit signals received by the antenna, the device includes a first chip and a second chip, the first chip including an antenna and a first winding, and the second chip including a winding of a second winding and a third winding, the first chip and the second chip being bonded to each other by molecular bonding.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to French patent application No. FR2309456, filed on September 8, 2023, entitled “Dispositifélectronique”, which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic devices and, in particular embodiments, to transceiver devices. Background Art

[0004] In the field of wireless communications, there are various modes of operation to allow two-way communication between two elements capable of transmitting and receiving signals.

[0005] Duplex or "full-duplex" mode is a mode of operation in which both circuits can transmit signals simultaneously. Thus, signals can be sent and received at the same time.

[0006] Time division duplex mode is an operating mode in which data transmission and reception occur on the same frequency band, where the signals are transmitted continuously.

[0007] Frequency division duplex mode is an operation mode in which data transmission and reception are performed simultaneously on two different frequency bands. In other words, the frequency of the signal carrier differs depending on the transmission direction.

[0008] Different operation modes face various problems. One problem is the isolation between the receiving part and the transmitting part. Summary of the invention

[0009] Embodiments overcome all or part of the disadvantages of known electronic transceiver devices.

[0010] One embodiment provides a device suitable for transmitting and receiving signals using the same antenna, the device including a first winding, a second winding and a third winding, the first winding and the second winding being coupled to transmit the signal to be transmitted by the antenna, the first winding and the third winding being coupled to transmit the signal received by the antenna, the device including a first chip and a second chip, the first chip including the antenna and the first winding, and the second chip including one of the second winding and the third winding, the first chip and the second chip being bonded to each other by molecular bonding.

[0011] According to one embodiment, a first winding is coupled between an antenna and a node for applying a reference voltage, a second winding is coupled between two terminals of a first circuit configured to generate a signal to be transmitted, and a third winding is coupled between two terminals of a second circuit configured to process a received signal.

[0012] According to one embodiment, each first chip or the second chip includes a semiconductor substrate and an interconnection network, the interconnection network includes an insulating layer stack, the insulating layer stack includes conductive tracks and conductive vias, each interconnection network includes a first layer, the first layer of each interconnection network is farthest from the substrate of the chip, and the first chip and the second chip are bonded to each other through the first layer of each interconnection network.

[0013] According to an embodiment, the first winding comprises a first conductive track in a second layer of an interconnect network of the first chip, the first track being separated from the second chip only by insulating material.

[0014] According to an embodiment, the second winding comprises a second conductive track in a third layer of the interconnection network of the second chip, the second track being separated from the first chip only by insulating material.

[0015] According to an embodiment, the third winding comprises a third conductive track in a fourth layer of the interconnect network of the first chip, the third track being separated from the first track by an insulating material, the third track being located between the first track and a substrate of the first chip.

[0016] According to an embodiment, the third winding comprises a third conductive track in a fifth layer of the interconnection network of the second chip, the third track being separated from the first chip by an insulating material.

[0017] According to an embodiment, the third winding comprises a second conductive track in a third layer of the interconnection network of the second chip, the second track being separated from the first chip only by insulating material.

[0018] According to an embodiment, the second winding comprises a third conductive track in a fourth layer of the interconnect network of the first chip, the third track being separated from the first track by an insulating material, the third track being located between the first track and a substrate of the first chip.

[0019] According to an embodiment, the second winding comprises a third conductive track in a fifth layer of the interconnection network of the second chip, the third track being separated from the first chip by an insulating material.

[0020] According to one embodiment, the second track and the third track are located in a same third layer of the interconnection network of the second chip.

[0021] According to one embodiment, the device is configured to operate in a time division duplex mode or a frequency division duplex mode.

[0022] According to one embodiment, the molecular bonding is metal-to-metal bonding or oxide-to-oxide bonding.

[0023] Another embodiment provides a method for manufacturing a device suitable for transmitting and receiving signals using the same antenna, the device including a first winding, a second winding and a third winding, the first winding and the second winding being coupled to transmit the signal to be transmitted by the antenna, the first winding and the third winding being coupled to transmit the signal received by the antenna, the method including forming a first chip and a second chip, the first chip including an antenna and the first winding, and the second chip including a winding of the second winding and the third winding, the method also including bonding the first chip and the second chip to each other by molecular bonding.

[0024] According to one embodiment, the previously described manufacturing method is applied to manufacture a device such as previously described. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above features and advantages and other features and advantages will become apparent upon examination of the detailed description of exemplary embodiments given by way of illustration and not limitation with reference to the accompanying drawings in which:

[0026] Figure 1 An example of a transceiver device is illustrated;

[0027] Figure 2 An embodiment of a transceiver device is schematically illustrated;

[0028] Figure 3 Schematically illustrates Figure 2 Implementation of the embodiments;

[0029] Figure 4 Another embodiment of a transceiver device is schematically illustrated; and

[0030] Figure 5 Schematically illustrates Figure 4 Implementation of an embodiment. DETAILED DESCRIPTION

[0031] In the various figures, the same features are represented by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals, and may be provided with the same structure, size, and material properties.

[0032] For the sake of clarity, only the steps and elements that are useful for understanding the described embodiments are shown and described in detail. Specifically, unless otherwise specified, when referring to two elements connected together, this means a direct connection without any intermediate elements other than conductors, and when referring to two elements being coupled together, this means that the two elements can be connected or coupled via one or more other elements.

[0033] In the following description, unless otherwise stated, when referring to terms defining absolute positions (such as terms "edge", "back", "top", "bottom", "left side", "right side", etc.), or relative positions (such as terms "above", "below", "upper", "lower", etc.) or terms defining directions (such as terms "horizontal", "vertical", etc.) are referred to, they refer to the orientation of the figure.

[0034] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "in the order of" mean plus or minus 10% or plus or minus 5%.

[0035] Figure 1 Illustrated is an example of a transceiver device 10. The device 10 is, for example, configured to operate in a frequency division duplex mode or a time division duplex mode.

[0036] For example, device 10 forms part of a transceiver system. The system includes device 10 and another transceiver device (not shown). The other device is configured to transmit and receive signals. The other device is configured to operate in the same operating mode as device 10. Device 10 and the other device are configured to be able to communicate with each other wirelessly.

[0037] The device 10 includes an antenna 12, for example a single antenna 12. The antenna 12 is configured to transmit and receive signals.

[0038] The device 10 comprises, for example, a switching circuit 14. The circuit 14 comprises, for example, a main terminal 16 and two auxiliary terminals 18, 20. The circuit 14 is configured to connect the terminal 16 to one or the other of the terminals 18, 20. The circuit 14 is controlled by a control signal CTRL (e.g., a binary signal). The signal CTRL determines whether the terminal 16 is coupled to the terminal 18 or to the terminal 14. The signal CTRL determines whether the device 10 is in a transmission mode, i.e., a mode in which a signal is supplied to an antenna for transmission, or in a reception mode, i.e., a mode in which a signal is received by an antenna and supplied by the antenna to the rest of the device 10. Thus, the signal CTRL can take a first value, indicating that the device is in a transmission mode and that the circuit 14 couples the terminals 16 and 18; or a second value, indicating that the device is in a reception mode and that the circuit 14 couples the terminals 16 and 20.

[0039] The switch circuit 14, more specifically the terminal 16, is coupled or connected to the antenna 12. The switch circuit 14, more specifically the terminal 18, is coupled or connected to a node 22, to which a signal TX to be transmitted is supplied, through a balun 24. The switch circuit 14, more specifically the terminal 20, is coupled or connected to a node 26, to which a signal RX received by the antenna 12 is acquired, through a balun 28.

[0040] Balun 24 includes two windings or coils, namely a first winding 24a and a second winding 24b. One end of winding 24a is coupled or connected to terminal 18. One end of winding 24b is coupled or connected to node 22. Windings 24a and 24b are magnetically coupled to allow transmission between antenna 12 and the rest of device 10. Similarly, balun 28 includes two windings, namely a first winding 28a and a second winding 28b. One end of winding 28a is coupled or connected to terminal 20. One end of winding 28b is coupled or connected to node 26. Windings 28a and 28b are magnetically coupled to allow transmission between antenna 12 and the rest of device 10.

[0041] Separation between the transmission branch comprising terminal 18, circuit or balun 24 and node 22 and the reception branch comprising terminal 20, circuit or balun 28 and node 26 needs to be ensured to avoid power leakage that could increase power consumption and interfere with transmission.

[0042] Figure 2 An embodiment of a transceiver device 30 is schematically shown. The device 30 is configured to operate in a frequency division duplex mode or a time division duplex mode. The device 30 comprises Figure 1 Elements of device 10.

[0043] Device 30 includes a first chip 32 and a second chip 34. Chip 32 includes and may completely include a transmission branch of device 30. Chip 34 includes at least a portion of a reception branch of device 30.

[0044] The chip 32 includes the antenna 12. The chip 32 also includes a winding 36. The winding 36 is coupled or connected to the antenna 12 at one end and to a reference node 38, such as ground, at the other end.

[0045] Chip 32 includes transmission circuitry 40 . Circuitry 40 is configured to generate a signal for transmission by antenna 12 .

[0046] The chip 32 further comprises a winding 42. The winding is coupled between two terminals 40a, 40b of the circuit 40. Thus, the winding 40 comprises a first end coupled or connected to the terminal 40a of the circuit 40 and a second end coupled or connected to the other terminal 40b of the circuit 40.

[0047] Windings 36 and 42 are magnetically coupled to form balun 24. Then, winding 36 corresponds to winding 24a, and winding 42 corresponds to winding 24b. Windings 36 and 42 are configured to be coupled to each other so as to allow signal transmission in a first frequency range corresponding to the transmission frequency.

[0048] Terminals 40a and 40b of circuit 40 are coupled to node 38, for example, both through switches (e.g., transistors). Thus, terminal 40a is coupled or connected, for example, to a conduction terminal of transistor 44, the other conduction terminal of which is coupled or connected to node 38. Terminal 40a is coupled or connected, for example, to a conduction terminal of transistor 46, the other conduction terminal of which is coupled or connected to node 38. Transistors 44 and 46 are controlled, for example, by control circuitry of device 30, for example, located in chip 32.

[0049] Chip 34 includes receiving circuitry 46 . Circuitry 40 is configured to process signals received by antenna 12 .

[0050] The chip 34 also includes a winding 48. The winding 48 is coupled between two terminals 46a, 46b of the circuit 46. Thus, the winding 48 includes a first end coupled or connected to the terminal 46a of the circuit 46 and a second end coupled or connected to the other terminal 46b of the circuit 46.

[0051] Windings 36 and 48 are magnetically coupled to form balun 28. Then, winding 36 corresponds to winding 28a, and winding 48 corresponds to winding 28b. Windings 36 and 48 are configured to be coupled to each other so as to allow signal transmission in a second frequency range corresponding to the reception frequency.

[0052] Terminals 46a and 46b of circuit 40 are coupled to node 38, for example, both through switches (e.g., transistors). Thus, terminal 46a is coupled or connected, for example, to a conduction terminal of transistor 50, the other conduction terminal of which is coupled or connected to node 38. Terminal 46a is coupled or connected, for example, to a conduction terminal of transistor 52, the other conduction terminal of which is coupled or connected to node 38. Transistors 50 and 52 are controlled, for example, by control circuitry of device 30, for example, located in chip 34.

[0053] The switches 44, 46, 50, 52 are configured, for example, to enable the device 30 to operate in a time division duplex mode.

[0054] Figure 3 Schematically shows Figure 2 Implementation of an embodiment.

[0055] exist Figure 3 , device 30 includes chip 32 and chip 34. Each chip 32, 34 includes a substrate, such as a semiconductor substrate, in which electronic components may be formed, such as forming circuits 40 and 46. Chip 32 includes substrate 54, and chip 34 includes substrate 56. In other words, substrate 54 may include electronic components of circuit 40, such as all electronic components of circuit 40. Substrate 56 may include electronic components of circuit 46, such as all electronic components of circuit 46.

[0056] Furthermore, each chip 32 , 34 includes an interconnect network covering its substrate 54 or 56 .

[0057] Thus, chip 32 includes an interconnect network 58. Network 58 includes a stack of multiple insulating layers 60. More specifically, network 58 includes alternating layers 60 including metal tracks or metallizations 68 and layers 60 including conductive vias coupling the metal tracks together. Network 58 is located on surface 54a of substrate 54, for example over the entire surface 54a of substrate 54.

[0058] Similarly, chip 34 includes an interconnect network 62. Network 62 includes a stack of multiple insulating layers 60. More specifically, network 62 includes alternating layers 60 including metal tracks or metallization 78 and layers 60 including conductive vias that couple the metal tracks together. Network 62 is located on surface 56a of substrate 56, for example, over the entire surface 56a of substrate 56.

[0059] The network 58 comprises a layer 66. The layer 66 is an insulating layer corresponding to the layer 60 of the network 58 and comprises a metallization 68. The layer 66 is separated from the substrate 54 by at least one layer 60.

[0060] Metal tracks 68 are located in layer 66. Tracks 68 extend from the upper surface of layer 66 (i.e., the surface that contacts top layer 60 in network 58) to the lower surface of layer 66 (i.e., the surface that contacts bottom layer 60 in network 58). Metal tracks 68 form Figure 2 Thus, the length of the track 68 and its layout enable the formation of the winding 42. For example, the track 68 forms a spiral in the layer 66, wherein a first end of the track 68 is located outside the spiral and the other end of the track 68 is located inside the spiral.

[0061] The network 58 comprises a layer 70. The layer 70 is an insulating layer corresponding to the layer 60 of the network 58, which comprises a metallization 78.

[0062] Metal tracks 72 are located in layer 70. Tracks 72 extend from the upper surface of layer 70 (i.e., the surface that contacts the top layer 60 in network 58) to the lower surface of layer 70 (i.e., the surface that contacts the bottom layer 60 in network 58). Metal tracks 72 form Figure 2 The length of the track 72 and its arrangement thus enable the formation of the winding 36. For example, the track 72 forms a spiral in the layer 70, with a first end of the track 72 being located outside the spiral and the other end of the track 72 being located inside the spiral.

[0063] Track 72 is at least partially located in front of track 68. Layers 66 and 70, and more specifically tracks 68 and 72, are separated from each other by at least one layer 60. In some embodiments, at least one layer 60 separating layers 66 and 70 does not include metal tracks or conductive vias between tracks 68 and 72 or between portions of layer 66 and 70 located between portions of tracks 68 and 72.

[0064] The number and height of layers 60 separating layers 66 and 70 are selected to ensure that tracks 68 and 72 forming windings 36 and 42 are magnetically coupled and form a balun having a desired operating frequency range. For example, layers 66 and 70 are separated by a single layer 74 and a single layer 80. For example, the thickness of layer 74 is in the range of 1 nm to 1 mm, and the thickness of layer 80 is in the range of 1 nm to 1 mm.

[0065] Network 58 includes layer 74. Layer 74 is an insulating layer covering layer 70. Layer 74 corresponds to layer 60 of network 58 that is farthest from substrate 54. Layer 74 covers at least tracks 72, and in some embodiments completely covers layer 70. For example, layer 74 corresponds to a single layer of the interconnected network or a single layer made of an insulating material different from the material of layer 60. As a variant, layer 74 includes multiple insulating layers, for example including one or more layers 60 and / or one or more insulating layers made of one or more insulating materials different from the material of layer 60.

[0066] Layer 74 is separated from layer 66 by layer 70. Layer 66 is located between layer 70 and substrate 54. Thus, network 58 in some embodiments includes, in order from surface 54a of substrate 54, one or more layers 60 separating layer 66 from substrate 54, layer 66, one or more layers 60 separating layers 66 and 70, layer 70, and layer 74.

[0067] The layer(s) 60 separating the layer 66 from the substrate 54 include, for example, conductive tracks and conductive vias (not shown) to electrically couple the tracks 68 and the substrate 54. More specifically, the layer(s) 60 separating the layer 66 from the substrate 54 include, for example, conductive tracks and conductive vias (not shown) to electrically couple the tracks 68 and the circuit 40.

[0068] Network 62 of chip 34 includes layer 76. Layer 76 is an insulating layer corresponding to layer 60 in network 62. Layer 76 is separated from substrate 56 by at least one layer 60 in some embodiments.

[0069] Metal tracks 78 are located in layer 76. Tracks 78 extend from the upper surface of layer 76 (i.e., the surface that contacts the top layer 60 in network 62) to the lower surface of layer 76 (i.e., the surface that contacts the bottom layer 60 in network 62). Metal tracks 78 form Figure 2Thus, the length of the track 78 and its layout enable the formation of the winding 48. For example, the track 78 forms a spiral in the layer 76, wherein a first end of the track 78 is located outside the spiral and the other end of the track 78 is located inside the spiral.

[0070] Network 62 includes layer 80. Layer 80 is an insulating layer covering layer 76. Layer 80 corresponds to the layer 60 in network 62 that is farthest from substrate 56. Layer 80 covers at least track 78, and in some embodiments completely covers layer 76. For example, layer 80 corresponds to a single layer of the interconnect network or a single layer made of an insulating material different from the material of layer 60. Alternatively, layer 80 includes multiple insulating layers, for example including one or more layers 60 and / or one or more insulating layers made of one or more insulating materials different from the material of layer 60.

[0071] Tracks 78 are separated from substrate 56, for example, by at least one layer 60. Layer 80 is separated from substrate 56 by layer 76. Thus, network 62 in some embodiments includes, in order from surface 56a of substrate 56, one or more layers 60, layer 76, and layer 80 separating layer 76 from substrate 56.

[0072] Track 78 is at least partially located in front of track 72. Layers 74 and 80 do not include conductive elements between tracks 72 and 78 and between portions of layers 70 and 76 that are located in the spiral formed by tracks 72 or 78 in some embodiments.

[0073] Tracks 78 and 72 are arranged to be magnetically coupled and form a balun having a desired operating frequency range. Therefore, layers 74 and 80, and more specifically the thickness of layers 74 and 80, are selected to ensure that tracks 72 and 78 are magnetically coupled and form a balun. For example, the thickness of layer 74 is in the range of 1 nm to 1 mm, and the thickness of layer 80 is in the range of 1 nm to 1 mm.

[0074] The layer(s) 60 separating the layer 78 from the substrate 56 include, for example, conductive tracks and conductive vias (not shown) to electrically couple the tracks 78 and the substrate 56. More specifically, the layer(s) 60 separating the layer 78 from the substrate 56 include, for example, conductive tracks and conductive vias (not shown) to electrically couple the tracks 78 and the circuit 46.

[0075] Chips 32 and 34 are bonded to each other by molecular bonding, which in some embodiments is a hybrid molecular bonding, such as metal-to-metal bonding, oxide-to-oxide bonding, or a combination thereof. More specifically, layers 74 and 80 are bonded to each other by molecular bonding. Thus, the surface of layer 74 farthest from substrate 54 contacts the surface of layer 80 farthest from substrate 56.

[0076] For example, layers 74 and 80 include conductive tracks (not shown) that contact each other to allow electrical coupling of chips 32 and 34. Such tracks (not shown) are not located between tracks 72 and 78.

[0077] Figure 4 A further embodiment of a transceiver device 100 is schematically shown.

[0078] Device 100 includes the elements, and in some embodiments all of the elements, of device 30 in a different arrangement.

[0079] Therefore, with Figure 2 Like the chip 32 of FIG. 1 , the chip 320 includes the antenna 12 and the winding 36. Figure 2 As shown, one end of winding 36 is coupled or connected to antenna 12 , and the other end of winding 36 is coupled or connected to node 38 .

[0080] and Figure 2 Like the chip 34 of FIG. 1 , the chip 340 includes a winding 48, a circuit 46, and transistors 50, 52. Figure 2 As shown, winding 48 is coupled or connected between terminals 46a and 46b of circuit 46, and transistors 50, 52 are connected as shown. Figure 2 Coupling is performed in .

[0081] and Figure 2 In contrast to the embodiment of FIG. 3 , the chip 340 further includes a circuit 40, a winding 42 and transistors 44, 46. Figure 2 As shown, winding 42 is coupled or connected between terminals 40a and 40b of circuit 40, and transistors 44, 46 are connected as shown in FIG. Figure 2 Coupling is performed in .

[0082] The windings 36, 42, 48 are arranged in such a way that the windings 36 and 42 are coupled, the windings 36 and 48 are coupled, and the windings 42 and 48 are neither coupled nor touching. The windings 36 and 42 are coupled so as to transmit only the transmit operating frequency range. The windings 36 and 48 are coupled so as to transmit only the receive operating frequency range.

[0083] Figure 5 Schematically shows Figure 4 Implementation of an embodiment.

[0084] exist Figure 5 In the embodiment, the device 100 includes a chip 320 and a chip 340. Each chip 320, 340 includes a substrate, such as a semiconductor substrate, in which electronic components may be formed. More specifically, Figure 3 Like chip 32 of FIG. 3 , chip 320 includes substrate 54 , and chip 340 includes substrate 36 . Figure 3In contrast to the embodiments of FIG. 4 , substrate 56 includes the electronic components of circuits 40 and 46 , and in some embodiments includes all components of circuits 40 and 46 . Substrate 54 does not include the electronic components of circuits 40 and 46 in some embodiments.

[0085] Furthermore, each chip 320 , 340 includes an interconnect network covering its substrate 54 or 56 .

[0086] Therefore, with Figure 3 Like the chip 32 of the present invention, the chip 320 includes an interconnect network 58. The network 58 includes a stack of multiple insulating layers 60. More specifically, the network 58 includes alternating layers 60 including metal tracks or metallizations and layers 60 including conductive vias that couple the metal tracks together. The network 58 is located on the surface 54a of the substrate 54, for example, over the entire surface 54a of the substrate 54.

[0087] Similarly, chip 340 includes an interconnect network 62. Network 62 includes a stack of multiple insulating layers 60. More specifically, network 62 includes alternating layers 60 including metal tracks or metallizations and layers 60 including conductive vias coupling the metal tracks together. Network 62 is located on surface 56a of substrate 56, for example, over the entire surface 56a of substrate 56.

[0088] Network 58 includes layer 70. Figure 3 As shown, layer 70 is an insulating layer corresponding to layer 60 of network 58 .

[0089] Metal tracks 72 are located in layer 70. Figure 3 As shown, tracks 72 extend from the upper surface of layer 70 (i.e., the surface that contacts the top layer 60 in network 58) to the lower surface of layer 70 (i.e., the surface that contacts the bottom layer 60 in network 58). Metal tracks 72 form Figure 4 The length of the track 72 and its layout thus enable the formation of the winding 36. For example, the track 72 forms a spiral in the layer 70, with a first end of the track 72 being outside the spiral and the other end of the track 72 being inside the spiral.

[0090] and Figure 3 In contrast to device 30 , chip 320 does not include layer 66 nor track 68 .

[0091] like Figure 3 As shown, network 58 includes layer 74 corresponding to layer 60. Layer 74 is an insulating layer covering layer 70. Layer 74 corresponds to layer 60 of network 58 that is farthest from substrate 54. Layer 74 covers at least tracks 72, and in some embodiments completely covers layer 70.

[0092] Network 58 , in some embodiments, includes, in order from surface 54 a of substrate 54 , one or more layers 60 , layer 70 , and layer 74 separating layer 70 from substrate 54 .

[0093] The layer(s) 60 separating the layer 70 from the substrate 54 include, for example, conductive tracks and conductive vias (not shown) in order to electrically couple the tracks 72 and the substrate 54 .

[0094] and Figure 3 In contrast to the embodiment of FIG. 3 , network 62 of chip 340 does not include layer 76. Network 62 of chip 340 includes layer 102. Layer 102 is an insulating layer corresponding to layer 60 in network 62. Layer 102 is separated from substrate 56 by at least one layer 60 in some embodiments.

[0095] Metal tracks 104 are located in layer 102. Tracks 104 extend from the upper surface of layer 100 (i.e., the surface that contacts the top layer 60 in network 62) to the lower surface of layer 102 (i.e., the surface that contacts the bottom layer 60 in network 62). Metal tracks 104 form Figure 4 Thus, the length of the track 104 and its layout enable the formation of the winding 42. For example, the track 104 forms a spiral in the layer 102, the first end of the track 104 is located outside the spiral, and the second end of the track 104 is located inside the spiral.

[0096] Another metal track 106 is located in layer 102. Track 106 extends from the upper surface of layer 100 (i.e., the surface that contacts the top layer 60 in network 62) to the lower surface of layer 102 (i.e., the surface that contacts the bottom layer 60 in network 62). Metal track 106 forms Figure 4 Thus, the length of the track 106 and its layout enable the formation of the winding 48. For example, the track 106 forms a spiral in the layer 102, wherein a first end of the track 106 is located outside the spiral and a second end of the track 106 is located inside the spiral.

[0097] Tracks 102 and 104 do not touch. Therefore, tracks 102 and 104 are separated by a portion 108 of layer 102.

[0098] Alternatively, tracks 104 and 106 may be located in separate layers in network 62. Tracks 104 and 106 are arranged not facing each other, even partially not facing each other. Each track 104, 106 is separated from chip 320, more specifically from track 72, only by electrically insulating material (e.g., by layers 60, 80, 74).

[0099] Network 62 includes layer 80 corresponding to layer 60. Layer 80 is an insulating layer covering layer 102. Layer 80 corresponds to layer 60 in network 62 that is farthest from substrate 56. Layer 80 covers at least tracks 104 and 106, and in some embodiments completely covers layer 102.

[0100] Tracks 104 and 106 are separated from substrate 56, for example, by at least one layer 60. Layer 80 is separated from substrate 56 by layer 102. Thus, in some embodiments, network 62 includes, in order from surface 56a of substrate 56, one or more layers 60, layer 102, and layer 80 separating layer 102 from substrate 56.

[0101] Tracks 104 and 106 are at least partially located in front of track 72. More specifically, track 104 is at least partially located in front of track 72, and track 106 is at least partially located behind track 72. Layers 74 and 80, in some embodiments, do not include conductive elements between tracks 104 and 72, between tracks 106 and 72, and between portions of layers 70 and 102 that are located in the spiral formed by tracks 72, 104, or 106.

[0102] Tracks 104 and 72 are arranged to magnetically couple and form a balun having a desired operating frequency range to allow transmission via antenna 12. Therefore, layers 74 and 80, and more particularly the thickness of layers 74 and 80, are selected to ensure that tracks 72 and 104 are magnetically coupled and form a balun.

[0103] Tracks 106 and 72 are arranged to magnetically couple and form a balun having a desired operating frequency range to allow reception by antenna 12. Therefore, layers 74 and 80, and more particularly the thickness of layers 74 and 80, are selected to ensure that tracks 72 and 106 are magnetically coupled and form a balun.

[0104] Layer 60, which separates layer 102 from substrate 56, includes, for example, conductive tracks and conductive vias (not shown) to electrically couple tracks 104 and substrate 56, and includes, for example, conductive tracks and conductive vias (not shown) to electrically couple tracks 103 and substrate 56. Tracks 104 and 106 are not electrically connected by conductive vias or tracks located in layer 60 of network 62 in some embodiments.

[0105] like Figure 3 As shown, chips 320 and 340 are bonded to each other by molecular bonding (in some embodiments, hybrid bonding). More specifically, layers 74 and 80 are bonded to each other by molecular bonding. Thus, the surface of layer 74 farthest from substrate 54 is in contact with the surface of layer 80 farthest from substrate 56.

[0106] For example, layers 74 and 80 include conductive tracks (not shown) that contact each other to allow electrical coupling of chips 320 and 340. Such tracks (not shown) are not located between tracks 72 and 104 or between tracks 72 and 106.

[0107] An advantage of the above embodiment is that power leakage between the transmission path and the reception path is reduced. In fact, in the above embodiment, the windings 42 and 48 are not electrically coupled by a conductive element (eg, a via).

[0108] Another advantage of the above described embodiment is that there is no physical connection between the circuits 40 and 46 so that protection against electrostatic discharge can be provided.

[0109] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these different embodiments and variations may be combined, and those skilled in the art will be able to conceive of other variations. In particular, Figure 2 and Figure 3 In the embodiment of the present invention, the components including the circuit 40, the winding 42 and the transistors 44, 46, and the components including the circuit 46, the winding 48 and the transistors 50, 52 may be interchanged.

[0110] Finally, based on the functional indications given above, the actual implementation of the above-described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A device for transmitting and receiving a signal, the device being configured to transmit and receive the signal using the same antenna, the device comprising: a first winding, a second winding, and a third winding, the first winding and the second winding being coupled to transmit a signal to be transmitted by the antenna, the first winding and the third winding being coupled to transmit a signal received by the antenna; and a first chip and a second chip, the first chip including the antenna and the first winding, and the second chip including a winding of the second winding and the third winding, the first chip and the second chip being joined to each other by molecular bonding.

2. The device according to claim 1, wherein the first winding is coupled between the antenna and the application node of the reference voltage, the second winding is coupled between two terminals of a first circuit, the first circuit is configured to generate a signal to be transmitted, and the third winding is coupled between two terminals of a second circuit, the second circuit is configured to process a received signal.

3. The device according to claim 1, wherein each first chip or the second chip comprises a semiconductor substrate and an interconnection network, the interconnection network comprising an insulating layer stack, the insulating layer stack comprising conductive tracks and conductive vias, each corresponding interconnection network comprising a first layer, the corresponding first layer of each corresponding interconnection network being farthest from the substrate of each chip, and wherein the first chip and the second chip are bonded to each other through the first layer of each interconnection network. 4 . The device of claim 3 , wherein the first winding comprises a first conductive track in a second layer of the interconnect network of the first chip, the first conductive track being separated from the second chip only by insulating material.

5. The device of claim 4, wherein the second winding comprises a second conductive track in a third layer of the interconnect network of the second chip, the second conductive track being separated from the first chip only by insulating material.

6. The apparatus of claim 5 , wherein the third winding comprises a third conductive track in a fourth layer of the interconnect network of the first chip, the third conductive track being separated from the first conductive track by an insulating material, the third conductive track being located between the first conductive track and the substrate of the first chip.

7. The apparatus of claim 5, wherein the third winding comprises a third conductive track in a fifth layer of the interconnect network of the second chip, the third conductive track being separated from the first chip by an insulating material.

8. The device of claim 7, wherein the second conductive track and the third conductive track are located in the same third layer of the interconnect network of the second chip.

9. The device of claim 4, wherein the third winding comprises a second conductive track in a third layer of the interconnect network of the second chip, the second conductive track being separated from the first chip only by insulating material.

10. The device of claim 9, wherein the second winding comprises a third conductive track in a fourth layer of the interconnect network of the first chip, the third conductive track being separated from the first conductive track by an insulating material, the third conductive track being located between the first conductive track and the substrate of the first chip.

11. The device of claim 9, wherein the second winding comprises a third conductive track in a fifth layer of the interconnect network of the second chip, the third conductive track being separated from the first chip by an insulating material.

12. The device of claim 11, wherein the second conductive track and the third conductive track are located in a same third layer of the interconnection network of the second chip.

13. The device of claim 1, wherein the device is configured to operate in a time division duplex mode or by frequency division duplexing.

14. The apparatus of claim 1, wherein the molecular bonding is metal-to-metal bonding or oxide-to-oxide bonding.

15. A device for transmitting and receiving signals, the device comprising: antenna; a first interconnect network coupled to the antenna, the first interconnect network comprising a first insulating layer, the first insulating layer covering a first metallization, the first metallization comprising a first winding and a second winding, the second winding coupled to the first winding to transmit a signal to be transmitted by the antenna; as well as A second interconnect network coupled to the antenna, the second interconnect network comprising a second insulating layer bonded to the first insulating layer, the second insulating layer covering a second metallization, the second metallization comprising a third winding coupled to the first winding to transmit a signal received by the antenna.

16. The device of claim 15, wherein the second insulating layer is bonded to the first insulating layer by molecular bonding.

17. The device of claim 16, wherein the molecular bonding is metal-to-metal bonding or oxide-to-oxide bonding.

18. A method for manufacturing a device, the device being configured to transmit and receive signals using the same antenna, the method comprising: forming a first chip, a second chip, a first winding, a second winding, and a third winding, wherein the first chip includes an antenna and the first winding, the second chip includes a winding of the second winding and the third winding, the first winding and the second winding are coupled to transmit a signal to be transmitted by the antenna, and the first winding and the third winding are coupled to transmit a signal received by the antenna; as well as The first chip and the second chip are joined to each other by molecular bonding.

19. The method of claim 18, wherein the second winding is part of the first chip and the third winding is part of the second chip.

20. The method of claim 18, wherein the second winding and the third winding are part of the second chip.

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