Structure with capacitor and fin-shaped transistor and manufacturing method thereof

Abstract

The invention discloses a structure with a capacitor and a fin-shaped transistor and a manufacturing method thereof, the structure with the capacitor and the fin-shaped transistor comprises a substrate, the substrate comprises a capacitor region and a fin-shaped transistor region, a platform is arranged in the capacitor region of the substrate, the platform protrudes out of one surface of the substrate, and the fin-shaped transistor region is arranged on the platform. The platform comprises an upper surface and two inclined surfaces, each inclined surface is respectively connected with the upper surface and the surface of the substrate, a doped region is arranged in the platform, a capacitor electrode is only arranged on the upper surface, and a capacitor dielectric layer is arranged between the capacitor electrode and the doped region.

Description

Technical Field

[0001] The present invention relates to a structure with a capacitor and a fin-shaped transistor and a manufacturing method thereof, and in particular to a manufacturing process combining the fin-shaped transistor and the capacitor to manufacture a capacitor with low capacitance value variation in a predetermined voltage range. Background Art

[0002] Capacitors are energy storage components that are essential in analog and digital electronic circuits. These components can be used for timing, waveform generation, blocking DC and coupling AC signals, performing filtering and smoothing, and of course storing energy. Due to their wide range of uses, there are quite a few capacitors on the market. As analog circuits are integrated into digital circuits based on metal oxide semiconductors, capacitors have begun to dominate analog circuit design. Integrated circuits typically contain a variety of capacitors, one type of which is a metal oxide semiconductor capacitor. This metal oxide semiconductor capacitor is usually formed using only the manufacturing steps required to form other semiconductor components. In this way, the number of steps required to form an integrated circuit can be minimized.

[0003] Since the capacitance value represents the storage capacity of the capacitor for charge, the capacitance value will be affected by the change of the applied voltage, resulting in inconsistent capacitance values ​​at different voltages. In practical applications, a metal oxide semiconductor capacitor that can maintain low capacitance variation in a specific voltage range is required. Summary of the invention

[0004] In view of this, the present invention provides a manufacturing process combining a fin-shaped transistor and a capacitor to manufacture a capacitor with low capacitance variation within a predetermined voltage range.

[0005] According to a preferred embodiment of the present invention, a structure having a capacitor and a fin-shaped transistor includes a substrate, the substrate includes a capacitor region and a fin-shaped transistor region, a platform is arranged in the capacitor region of the substrate, wherein the platform protrudes from a surface of the substrate, the platform includes an upper surface and two inclined surfaces, each inclined surface is connected to the upper surface and the surface of the substrate, a doped region is arranged in the platform, a capacitor electrode is only arranged on the upper surface, and a capacitor dielectric layer is arranged between the capacitor electrode and the doped region.

[0006] According to another preferred embodiment of the present invention, a method for manufacturing a structure having a capacitor and a fin-shaped transistor includes providing a substrate, wherein the substrate includes a capacitor region and a fin-shaped transistor region, then forming a platform disposed in the capacitor region of the substrate, wherein the platform protrudes from a surface of the substrate, the platform includes an upper surface and two inclined surfaces, each inclined surface is connected to the upper surface and the surface of the substrate, then forming a doped region disposed in the platform, then forming a capacitor dielectric layer to cover the doped region, and finally forming a capacitor electrode disposed only on the upper surface of the platform, and the capacitor electrode covers the capacitor dielectric layer.

[0007] According to another preferred embodiment of the present invention, a method for manufacturing a structure having a capacitor and a fin-shaped transistor includes providing a substrate, wherein the substrate includes a capacitor region and a fin-shaped transistor region, then forming a platform located in the capacitor region and forming a fin-shaped structure in the fin-shaped transistor region, wherein the platform protrudes from a surface of the substrate, the platform includes an upper surface and two inclined surfaces, each inclined surface connects the upper surface of the platform and the surface of the substrate, and then a shallow trench insulation is formed to cover the substrate, wherein the upper surface of the shallow trench insulation is aligned with the upper surface of the platform and the upper surface of the fin-shaped structure, and then a dopant implantation process is performed to form a doped region in the platform, and then the shallow trench insulation is etched back, and then a capacitor dielectric layer is formed to cover the platform, and finally a capacitor electrode is formed and only arranged on the upper surface of the platform.

[0008] In order to make the above-mentioned objectives, features and advantages of the present invention more clearly understood, the following is a detailed description of the preferred embodiments and the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and explanation, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 6 A schematic diagram of a method for manufacturing a structure having a capacitor and a fin-shaped transistor according to a preferred embodiment of the present invention;

[0010] Figure 7 for Figure 6 Top view of the mid-capacitor region;

[0011] Figure 8 For along Figure 7 A side view depicted along the median tangent line CC';

[0012] Fig. 9 A schematic diagram of a capacitance variation type depicted in another preferred embodiment of the present invention;

[0013] Fig.10 For along Fig. 9 Side view shown along the midline DD'.

[0014] Explanation of symbols

[0015] 10: Base

[0016] 10a: Surface

[0017] 12: Platform

[0018] 12a: Incline

[0019] 12b: Bevel

[0020] 12c: Bevel

[0021] 12d: Incline

[0022] 12t: Upper surface

[0023] 14: Fin structure

[0024] 16: Shallow Trench Insulation

[0025] 18: Silicon oxide pad

[0026] 20: Mask layer

[0027] 24: Doping area

[0028] 26: Silicon oxide layer

[0029] 28: Polysilicon layer

[0030] 30: Virtual capacitor electrode

[0031] 32: Virtual gate

[0032] 34: Gap wall

[0033] 36: Gap wall

[0034] 38: Etch stop layer

[0035] 40: Dielectric layer

[0036] 42: Groove

[0037] 44: Groove

[0038] 46: High dielectric constant layer

[0039] 48: Capacitor electrode

[0040] 50: Conductive gate

[0041] 52: Upper cover

[0042] 54: Upper cover

[0043] 56a: Contact plug

[0044] 56b: contact plug

[0045] 56c: contact plug

[0046] 58: Capacitor dielectric layer

[0047] 60a: Lower metal buffer layer

[0048] 60b: work function layer

[0049] 60c: upper metal buffer layer

[0050] 60d: Metal layer

[0051] 100: Structure with capacitor and fin transistor

[0052] 200: Capacitor

[0053] 300: Fin transistor

[0054] 400: Capacitor

[0055] A: Capacitor area

[0056] B: Fin transistor area DETAILED DESCRIPTION

[0057] Figures 1 to 6 A method for manufacturing a structure having a capacitor and a fin-shaped transistor is shown in accordance with a preferred embodiment of the present invention.

[0058] like Figure 1 As shown, a substrate 10 is first provided, and the substrate 10 is divided into a capacitor area A and a fin transistor area B. Then, a platform 12 is formed and arranged in the capacitor area A of the substrate 10, wherein the platform 12 protrudes from the surface 10a of the substrate 10. When the platform 12 is formed, a plurality of fin structures 14 are simultaneously formed and arranged in the fin transistor area B, wherein each fin structure 14 protrudes from the surface 10a of the substrate 10. The platform 12 and the fin structure 14 can be formed by etching the substrate 10, and then a shallow trench insulation 16 is formed and arranged on both sides of the platform 12 and both sides of each fin structure 14. At this time, the upper surface of the platform 12, the upper surface of the shallow trench insulation 16 and the upper surface of the fin structure 14 are aligned with each other, and then a pad silicon oxide 18 is formed to cover the upper surface of the platform 12, the upper surface of the shallow trench insulation 16 and the upper surface of the fin structure 14. Next, a mask layer 20 is formed to cover the fin transistor region B and expose the capacitor region A. Then, an ion implantation process is performed to implant ions into the platform 12 in the capacitor region A to form a doped region 24. According to a preferred embodiment of the present invention, the dopant implanted into the capacitor region A may include phosphorus, arsenic, boron, gallium or other N-type or P-type dopants. For example, at a power of 15000 electron volts (eV), arsenic dopant with a concentration of 500E15 atoms / cm2 is implanted into the capacitor region A to form the doped region 24.

[0059] like Figure 2As shown, the mask layer 20 is removed, and then another mask layer (not shown) may be formed to cover the capacitor region A, and then doping is implanted in the fin transistor region B to adjust the threshold voltage value of the subsequently formed fin transistor, and then the mask layer is removed. The pad silicon oxide 18 and the shallow trench insulation 16 are then etched back so that part of the platform 12 protrudes from the shallow trench insulation 16 and part of the fin structure 14 protrudes from the shallow trench insulation 16, and then an oxidation process is performed, such as an in-situ steam generation process, to form a silicon oxide layer 26 covering the platform 12 and the fin structure 14. Specifically, the oxidation process oxidizes the shallow surface of the platform 12 protruding from the shallow trench insulation 16 and the shallow surface of the fin structure 14 protruding from the shallow trench insulation 16. Then a polysilicon layer 28 is formed to fully cover the capacitor region A and the fin transistor region B. The polysilicon layer 28 is preferably formed using a deposition process.

[0060] like Figure 3 As shown, the polysilicon layer 28 is patterned to form a virtual capacitor electrode 30 in the capacitor region A and a virtual gate 32 in the fin transistor region B. Please also refer to Figure 4 , Figure 4 for Figure 3 The top view of the middle capacitor region is to clearly show the relative position between the virtual capacitor electrode 30 and the platform 12. Figure 4 The silicon oxide layer 26 is omitted. Figure 4 As shown, the platform 12 includes an upper surface 12t and four inclined surfaces 12a / 12b / 12c / 12d, the inclined surfaces 12a / 12b / 12c / 12d and the upper surface 12t are separated by dotted lines, the dummy capacitor electrode 30 is only arranged on the upper surface 12t of the platform 12, and the entire dummy capacitor electrode 30 does not cover any inclined surface 12a / 12b / 12c / 12d, nor does it contact the shallow trench isolation 16.

[0061] Figure 5 To continue Figure 3 Steps such as Figure 5As shown, two spacers 34 are formed on both sides of the dummy capacitor electrode 30, wherein the spacers 34 are only arranged on the upper surface 12t of the platform 12, and at the same time, two other spacers 36 are also formed on both sides of the dummy gate 32. Then a mask layer (not shown) is formed to cover the capacitor region A, and then an epitaxial layer (not shown) is formed in the fin structure 14 on both sides of the dummy gate 32 to bury the fin structure 14. Since the mask layer covers the capacitor region A, no epitaxial layer is formed in the capacitor region A. Then the mask layer is removed, and then an etching stop layer 38 is formed to conformably cover the spacers 34, the dummy capacitor electrode 30, the spacers 36, the dummy gate 32 and the epitaxial layer, and then a dielectric layer 40 is formed to cover the capacitor region A and the fin transistor region B, and then the dielectric layer 40 and the etching stop layer 38 are etched back until the upper surface of the dummy capacitor electrode 30 and the upper surface of the dummy gate 32 are exposed by the dielectric layer 40.

[0062] like Figure 6 As shown, the dummy capacitor electrode 30 and the dummy gate 32 are removed, and at this time, grooves 42 and grooves 44 are formed between the spacers 34 and between the spacers 36, and the bottoms of the grooves 42 and 44 are covered with silicon oxide layers 26, respectively. Then, a high dielectric constant layer 46 is formed to fill the grooves 42 and 44 in accordance with the grooves 42 and 44, and then a conductive layer is formed to fill the grooves 42 and 44. The conductive layer in the groove 42 is used as a capacitor electrode 48, and the conductive layer in the groove 44 is used as a conductive gate 50. The capacitor electrode 48 and the conductive gate 50 are formed simultaneously using the same step, and then a cap layer 52 / 54 is formed on the capacitor electrode 48 and the conductive gate 50, respectively. At this point, the structure 100 with a capacitor and a fin-shaped transistor of the present invention has been completed. The high dielectric constant layer 46 and the silicon oxide layer 26 in the capacitor region A are used as the capacitor dielectric layer of the capacitor 200, and the high dielectric constant layer 46 and the silicon oxide layer 26 in the fin-shaped transistor 300 are used as the gate dielectric layer of the fin-shaped transistor 300.

[0063] Figure 7 The picture shown is Figure 6 Top view of the mid-capacitor region, where Figure 7 The oxide layer, dielectric layer and etch stop layer are omitted.

[0064] Subsequently, contact plugs 56a / 56b may be formed on the terraces 12 on both sides of the capacitor electrode 48 and contact plugs 56c may be formed on the capacitor electrode 48. The contact plugs 56a / 56b contact the doped regions 24, and the contact plugs 56c pass through the upper cover layer 52 to contact the capacitor electrode 48. While forming the contact plugs 56a / 56b / 56c, contact plugs (not shown) are also formed in the fin transistor 300 to contact the epitaxial layer and the gate electrode 50, respectively.

[0065] Figure 8 For along Figure 7The side view drawn by the median line CC', please also refer to Figures 6 to 8 A structure 100 having a capacitor and a fin-shaped transistor of the present invention includes a substrate 10, wherein the substrate 10 includes a capacitor region A and a fin-shaped transistor region B. The substrate 10 can be a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate, or a silicon-coated insulating substrate. A platform 12 is disposed in a capacitor region A of a substrate 10, wherein the platform 12 protrudes from a surface 10a of the substrate 10, the platform 12 includes an upper surface 12t and four inclined surfaces 12a / 12b / 12c / 12d, each inclined surface 12a / 12b / 12c / 12d respectively connecting the upper surface 12t and the surface 10a of the substrate 10, a shallow trench insulation 16 is disposed on the surface 10a of the substrate 10 and contacts the inclined surfaces 12a / 12b / 12c / 12d, the shallow trench insulation 16 is preferably silicon oxide, a doped region 24 is disposed in the platform 12, a capacitor electrode 48 is only disposed on the upper surface 12t of the platform 12, that is, the capacitor electrode 48 does not cover any inclined surface 12a / 12b / 12c / 12d of the platform 12, and a capacitor dielectric layer is disposed between the capacitor electrode 48 and the doped region 24. The capacitor dielectric layer 58 is composed of a silicon oxide layer 26 and a high dielectric constant layer 46. The silicon oxide layer 26 contacts and covers the upper surface 12t and the inclined surfaces 12a / 12b / 12c / 12d. The high dielectric constant layer 46 is located between the capacitor electrode 48 and the silicon oxide layer 26. The spacers 34 are arranged on both sides of the capacitor electrode 48, wherein the spacers 34 are only arranged on the upper surface 12t of the platform 12. In addition, the doped region 24 preferably contains phosphorus or arsenic. The capacitor 200 of the present invention is composed of the capacitor electrode 48, the capacitor dielectric layer 58 and the doped region 24. The doped region 24 serves as the lower electrode of the capacitor 200, and the capacitor electrode 48 serves as the upper electrode of the capacitor 200. Furthermore, no epitaxial layer is arranged in the capacitor region A.

[0066] In addition, at least one fin structure 14 is disposed in the fin transistor A region. In the present embodiment, two fin structures 14 are taken as an example, wherein the fin structure 14 protrudes from the surface 10a of the substrate 10, a conductive gate 50 crosses the fin structure 14, a gate dielectric layer is disposed between the gate electrode 50 and the fin structure 14, the gate dielectric layer is composed of a silicon oxide layer 26 and a high dielectric constant layer 46, and a spacer 36 is disposed on both sides of the conductive gate 50, wherein the conductive gate 50 and the capacitor electrode 48 have the same stacked material layer. For example, the stacked material layer includes a lower metal buffer layer 60a, a work function layer 60b, an upper metal buffer layer 60c and a metal layer 60d, and the lower metal buffer layer 60a, the work function layer 60b, the upper metal buffer layer 60c and the metal layer 60d are arranged in order from close to the spacer 34 / 38 to far away from the spacer 34 / 38. The lower metal buffer layer 60a includes titanium nitride and tantalum nitride, the titanium nitride is closer to the spacer 34 / 38, and the tantalum nitride is farther away from the spacer 34 / 38. The work function layer 60b includes a P-type work function layer and an N-type work function layer, the P-type work function layer is closer to the spacer 34 / 38, and the N-type work function layer is farther away from the spacer 34 / 38. Alternatively, the work function layer 60b includes only the N-type work function layer or only the P-type work function layer. The upper metal buffer layer 60c is titanium nitride, and the metal layer 60d is tungsten.

[0067] Fig. 9 The capacitance variation type is shown according to another preferred embodiment of the present invention, wherein the elements having the same function will be used and Figure 7 and Figure 8 The same component numbers are used in the drawings. Fig.10 For along Fig. 9 Side view shown along the midline DD'.

[0068] like Fig. 9 and Fig.10 As shown, capacitor 400 and Figure 8 The difference between the capacitor 200 in FIG. 1 is the position covered by the spacer 34. Fig.10 The spacers 34 on both sides of the capacitor 400 cover the upper surface 12t of the platform 12 and the inclined surfaces 12c / 12d of the platform 12, and Figure 8 The spacer 34 is only located on the upper surface 12t of the platform 12, and does not cover the inclined surface 12c / 12d. Figure 8 The same is not repeated here.

[0069] Since the depth of the doped region is only close to the upper surface of the platform, there will be no doped region inside the inclined surface of the platform close to the shallow trench insulation. If the capacitor electrode covers the inclined surface, there will be no doped region under part of the capacitor electrode, so the capacitance value will become unstable. Therefore, the present invention deliberately sets the capacitor electrode only on the upper surface of the platform to ensure that there is a doped region under all the capacitor electrodes, thereby reducing the variation of the capacitance value.

[0070] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A structure having a capacitor and a fin-shaped transistor, comprising: a substrate including a capacitor region and a fin transistor region; A platform is disposed in the capacitor region of the substrate, wherein the platform protrudes from the surface of the substrate, and the platform comprises an upper surface and two inclined surfaces, each of the inclined surfaces respectively connecting the upper surface and the surface of the substrate; a doped region disposed in the platform; The capacitor electrode is disposed only on the upper surface; as well as The capacitor dielectric layer is arranged between the capacitor electrode and the doped region. 2 . The structure having a capacitor and a fin-shaped transistor as claimed in claim 1 , further comprising a spacer disposed on one side of the capacitor electrode, wherein the spacer is disposed only on the upper surface. 3 . The structure having a capacitor and a fin-shaped transistor as claimed in claim 1 , further comprising a spacer disposed on one side of the capacitor electrode, wherein the spacer covers the upper surface and one of the two inclined surfaces. 4 . The structure with a capacitor and a fin-shaped transistor as claimed in claim 1 , wherein the capacitor dielectric layer comprises a silicon oxide layer, and the silicon oxide layer contacts and covers the upper surface and the two inclined surfaces. 5 . The structure with capacitor and fin transistor as claimed in claim 1 , further comprising a shallow trench insulation disposed on the surface of the substrate and contacting one of the two inclined surfaces.

6. The structure having a capacitor and a fin transistor according to claim 1, further comprising: A fin structure is disposed in the fin transistor region, wherein the fin structure protrudes from the surface of the substrate; a conductive gate across the fin structure; as well as The gate dielectric layer is disposed between the gate electrode and the fin structure; wherein the conductive gate and the capacitor electrode have the same stacked material layer. 7 . The structure with a capacitor and a fin transistor as claimed in claim 1 , wherein the doped region comprises phosphorus or arsenic.

8. A method for manufacturing a structure having a capacitor and a fin-shaped transistor, comprising: Providing a substrate, wherein the substrate comprises a capacitor region and a fin transistor region; Forming a platform disposed in the capacitor region of the substrate, wherein the platform protrudes from the surface of the substrate, the platform comprises an upper surface and two inclined surfaces, each of the inclined surfaces respectively connecting the upper surface and the surface of the substrate; forming a doped region disposed in the platform; The capacitor electrode is formed to be disposed only on the upper surface; as well as A capacitor dielectric layer is formed and arranged between the capacitor electrode and the doped region. 9 . The method for manufacturing a structure having a capacitor and a fin-shaped transistor as claimed in claim 8 , further comprising forming a spacer disposed on one side of the capacitor electrode, wherein the spacer is disposed only on the upper surface. 10 . The method for manufacturing a structure having a capacitor and a fin-shaped transistor as claimed in claim 8 , further comprising forming a spacer disposed on one side of the capacitor electrode, wherein the spacer covers the upper surface and one of the two inclined surfaces. 11 . The method for manufacturing a structure having a capacitor and a fin-shaped transistor as claimed in claim 8 , wherein the capacitor dielectric layer comprises a silicon oxide layer, and the silicon oxide layer contacts and covers the upper surface and the two inclined surfaces. 12 . The method for manufacturing a structure having a capacitor and a fin-shaped transistor as claimed in claim 8 , further comprising forming a shallow trench insulation disposed on the surface of the substrate and contacting one of the two inclined surfaces.

13. The method for manufacturing a structure having a capacitor and a fin-shaped transistor according to claim 8, further comprising: When forming the platform, a fin-shaped structure is formed and disposed in the fin-shaped transistor region, wherein the fin-shaped structure protrudes from the surface of the substrate; forming a gate dielectric layer to cover the fin structure; and When forming the capacitor electrode, a conductive gate is formed across the fin structure. 14 . The method for manufacturing a structure having a capacitor and a fin-shaped transistor as claimed in claim 8 , wherein the doped region comprises phosphorus or arsenic.

15. A method for manufacturing a structure having a capacitor and a fin-shaped transistor, comprising: Providing a substrate, wherein the substrate comprises a capacitor region and a fin transistor region; Forming a platform located in the capacitor region and forming a fin-shaped structure located in the fin-shaped transistor region, wherein the platform protrudes from the surface of the substrate, the platform comprises an upper surface and two inclined surfaces, each of the inclined surfaces respectively connects the upper surface and the surface of the substrate; Forming a shallow trench insulation to cover the substrate, wherein the upper surface of the shallow trench insulation is aligned with the upper surface of the platform and the upper surface of the fin structure; Performing a dopant implantation process to form a doped region in the platform; etching back the shallow trench insulation; forming a capacitor dielectric layer to cover the platform; as well as The capacitor electrode is formed only on the upper surface. 16 . The method for manufacturing a structure having a capacitor and a fin-shaped transistor as claimed in claim 15 , further comprising forming a spacer disposed on one side of the capacitor electrode, wherein the spacer is disposed only on the upper surface. 17 . The method for manufacturing a structure having a capacitor and a fin-shaped transistor as claimed in claim 15 , further comprising forming a spacer disposed on one side of the capacitor electrode, wherein the spacer covers the upper surface and one of the two inclined surfaces. 18 . The method for manufacturing a structure having a capacitor and a fin-shaped transistor as claimed in claim 15 , wherein the capacitor dielectric layer comprises a silicon oxide layer, and the silicon oxide layer contacts and covers the upper surface and the two inclined surfaces.

19. The method for manufacturing a structure having a capacitor and a fin-shaped transistor according to claim 15, further comprising: When forming the capacitor dielectric layer, forming a gate dielectric layer to cover the fin structure; and When forming the capacitor electrode, a conductive gate is formed across the fin structure. 20 . The method for manufacturing a structure having a capacitor and a fin-shaped transistor as claimed in claim 15 , wherein the doped region comprises phosphorus or arsenic.

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