Memory device and forming method thereof

Abstract

A method of forming a memory device includes forming a capacitance in a first dielectric layer, forming a bottom electrode on the capacitance, forming a word line and a second dielectric layer on the bottom electrode and the first dielectric layer, where the word line is embedded in the second dielectric layer, forming a bit line contact on the second dielectric layer, and forming a memory device on the second dielectric layer. Wherein a vertical projection of the bit line contact on the first dielectric layer is spaced apart from a vertical projection of the bottom electrode on the first dielectric layer, after forming the bit line contact, forming a channel contacting the bottom electrode, and forming a top electrode on the channel, and the top electrode contacting the bit line contact. According to the invention, the influence of hydrogen diffusion on the oxide semiconductor device caused by formation of the bit line contact can be reduced.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to memory devices and methods of forming the same. Background Art

[0002] Common dynamic random-access memory (DRAM) combines capacitors and transistors, and the capacitors temporarily access data according to the charge state of the capacitors. The bit line is electrically connected to the source region of the transistor, and the word line is electrically connected to the gate region of the transistor. The channel region of the transistor can be made of oxide semiconductors, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) and indium tin oxide (ITO). The channel region made of oxide semiconductors is easily affected by specific substances produced by the memory process, such as hydrogen. Therefore, the hydrogen concentration in the channel should be reduced to avoid hydrogen affecting the channel characteristics. Summary of the invention

[0003] Some embodiments of the present disclosure provide a method of forming a memory device, comprising forming a capacitor in a first dielectric layer, forming a bottom electrode on the capacitor, forming a word line and a second dielectric layer on the bottom electrode and the first dielectric layer, wherein the word line is embedded in the second dielectric layer, forming a bit line contact on the second dielectric layer, wherein a vertical projection of the bit line contact on the first dielectric layer is separated from a vertical projection of the bottom electrode on the first dielectric layer, after forming the bit line contact, forming a channel contacting the bottom electrode, and forming a top electrode on the channel, and the top electrode contacts the bit line contact.

[0004] In some embodiments, forming a bit line contact includes forming a sacrificial layer on a second dielectric layer, forming a third dielectric layer on the sacrificial layer, forming a first trench by patterning the sacrificial layer and the third dielectric layer to expose the second dielectric layer, forming a barrier material layer in the first trench, and forming a bit line contact material covering the barrier material layer in the first trench.

[0005] In some embodiments, a vertical projection of the first trench on the first dielectric layer is spaced apart from a vertical projection of the bottom electrode on the first dielectric layer.

[0006] In some embodiments, forming the channel includes forming a second trench penetrating the third dielectric layer, the sacrificial layer, the second dielectric layer, the word line and exposing the bottom electrode, and filling the second trench with a channel material, and the method further includes forming a gate dielectric layer along the sidewall of the word line before forming the channel.

[0007] In some embodiments, the method further includes etching the channel material until an upper surface of the channel material is below the sacrificial layer.

[0008] In some embodiments, forming a top electrode includes forming a third trench by etching a portion of a sacrificial layer, wherein the third trench exposes a sidewall of the barrier material layer, filling the third trench with a top electrode material, forming a fourth trench by etching back the top electrode material, and filling the fourth trench on the top electrode material with a dielectric material.

[0009] In some embodiments, the channel does not contain hydrogen.

[0010] In some embodiments, the temperature at which the capacitor is formed is higher than the temperature at which the channel is formed.

[0011] In some embodiments, the channel is made of an oxide semiconductor.

[0012] In some embodiments, the method further includes forming a bit line contacting the bit line contact.

[0013] Some embodiments of the present disclosure provide a memory device, including a first dielectric layer, a capacitor, a bottom electrode, a channel, a top electrode, a gate dielectric layer, a word line, a second dielectric layer, a bit line contact, and a barrier layer. The capacitor is in the first dielectric layer. The bottom electrode is on the capacitor. The channel is on the bottom electrode. The top electrode is on the channel. The gate dielectric layer surrounds the channel. The word line surrounds the gate dielectric layer. The second dielectric layer surrounds the word line, the gate dielectric layer, and the channel. The bit line contact is on the second dielectric layer, and a vertical projection of the bit line contact on the first dielectric layer is separated from a vertical projection of the channel on the first dielectric layer. The barrier layer is between the bit line contact and the top electrode.

[0014] In some embodiments, a vertical projection of the top electrode on the first dielectric layer completely covers a vertical projection of the channel on the first dielectric layer.

[0015] In some embodiments, the top electrode includes a first portion and a second portion, the second portion of the top electrode is on the first portion of the top electrode, a sidewall of the second portion of the top electrode protrudes from a sidewall of the first portion of the top electrode, and a sidewall of the second portion of the top electrode contacts a sidewall of the barrier layer.

[0016] In some embodiments, a sidewall of the first portion of the top electrode is aligned with a sidewall of the gate dielectric layer.

[0017] In some embodiments, a bottom portion of the second portion of the top electrode is aligned with a bottom portion of the barrier layer.

[0018] In some embodiments, the second portion of the top electrode contacts the second dielectric layer.

[0019] In some embodiments, the memory device further includes a third dielectric layer and a fourth dielectric layer, the third dielectric layer is on the top electrode, the fourth dielectric layer contacts the sidewall of the top electrode, wherein the third dielectric layer contacts the upper surface of the top electrode and the upper surface of the fourth dielectric layer, and the fourth dielectric layer and the third dielectric layer are made of different materials.

[0020] In some embodiments, the third dielectric layer also contacts a sidewall of the barrier layer.

[0021] In some embodiments, the channel is made of an oxide semiconductor.

[0022] In some implementations, the memory device further includes a bit line contacting the bit line contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A top view of a memory array in some embodiments of the present disclosure is shown.

[0024] Figure 2 To illustrate the Figure 1 Cross-sectional view of line AA.

[0025] Figures 3 to 22 A cross-sectional view illustrating a process of manufacturing a memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] The following will disclose multiple embodiments of the present disclosure with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be depicted in a simple schematic manner in the drawings.

[0027] Some embodiments of the present disclosure are related to oxide semiconductors in memory arrays. Oxide semiconductor devices are made of oxide semiconductors, and oxide semiconductors are sensitive to hydrogen diffusion caused by the process of other components, such as bit line contacts. Therefore, the process sequence and location of the bit line contacts can be adjusted to reduce the impact of hydrogen diffusion on the oxide semiconductor device. In some embodiments, the memory array can be a vertical dynamic random access memory.

[0028] Figure 1 A top view of a memory array in some embodiments of the present disclosure is shown. Figure 2 To illustrate the Figure 1 A cross-sectional view of line AA. Figure 1 , Figure 1The memory array may include a plurality of memory cells. A common DRAM cell combines a capacitor 110 with a transistor (in Figure 2 Reference), wherein the capacitor 110 temporarily accesses data according to the charge state of the capacitor 110. The bit line 195 is electrically connected to the drain region of the transistor, and the word line 140 is electrically connected to the gate region of the transistor. The bit line 195 has a length direction along a first direction X, and the word line 140 has a length direction along a second direction Y, and the second direction Y is perpendicular to the first direction X. Assuming that the spacing between adjacent word lines 140 and bit lines 195 is 2F, the horizontal size of a DRAM unit can be 4F 2 , that is, a DRAM cell can have 4F 2 or less area, where F is the minimum lithographic feature size.

[0029] Figure 2 To illustrate the Figure 1 A cross-sectional view of line AA. Figure 1 , it should be noted that in order to simplify the drawings, Figure 2 Some components are not shown in Figure 1 In. Figure 2 , a semiconductor substrate 100 is shown. A metal layer 102 is disposed on the semiconductor substrate 100. As described above, each memory cell of the memory device includes a capacitor 110 and a transistor. The capacitor 110 is in a dielectric layer 104, and the dielectric layer 104 is on the metal layer 102. The transistor of each memory cell may include a bottom electrode 122 (i.e., a source of the transistor), a channel 124, a top electrode 126 (i.e., a drain of the transistor), and a gate dielectric layer 180. The word line 140 may serve as a gate of the transistor.

[0030] Specifically, bottom electrode 122 is on capacitor 110. Channel 124 is on bottom electrode 122. Top electrode 126 is on channel 124. That is, capacitor 110, bottom electrode 122, channel 124 and top electrode 126 are vertically stacked. Gate dielectric layer 180 surrounds channel 124. Word line 140 surrounds gate dielectric layer 180. It should be noted that although Figure 1 to Figure 2 The word line 140 is shown as a wraparound gate structure, that is, the word line 140 wraps around the gate dielectric layer 180 and all sides of the channel 124, but the word line 140 in the memory device can also be a single gate structure, a double gate structure, or a triple gate structure.

[0031] The memory device also includes a bit line contact 170, a barrier layer 172, and a bit line 195. The bit line contact 170 is on the channel 124. The barrier layer 172 is between the bit line contact 170 and the top electrode 126. The bit line 195 contacts the bit line contact 170 and is electrically connected to the top electrode 126. The vertical projection of the bit line contact 170 (including the barrier layer 172) on the dielectric layer 104 is separated from the vertical projection of the channel 124 on the dielectric layer 104. That is, the bit line contact 170 (including the barrier layer 172) is laterally translated from the channel 124. In other words, the bit line contact 170 (including the barrier layer 172) and the channel 124 are in contact with each other. Figure 2 The cross-sectional views of FIG. 1 and FIG. 2 do not overlap in the vertical direction. The relative position between the bit line contact 170 and the channel 124 is to avoid hydrogen diffusion from the barrier layer 172 during the process of the bit line contact 170 and the barrier layer 172. The description of hydrogen diffusion will be discussed later.

[0032] The memory device further includes dielectric layer 132, dielectric layer 134, dielectric layer 150, dielectric layer 160, and dielectric layer 190. Dielectric layers 132 and 134 may be collectively referred to as dielectric layer 130. Dielectric layer 130 surrounds bottom electrode 122, channel 124, gate dielectric layer 180, and word line 140. Dielectric layer 160 and dielectric layer 190 cover top electrode 126 and are between top electrode 126 and bit line 195. Dielectric layer 150 is between dielectric layer 160 and dielectric layer 130 and contacts the sidewall of top electrode 126.

[0033] Figures 3 to 22 A cross-sectional view illustrating a process of manufacturing a memory device according to some embodiments of the present disclosure. Figure 3 , a metal layer 102 and a dielectric layer 104 are sequentially formed on a semiconductor substrate 100. In some embodiments, the semiconductor substrate 100 may be made of polysilicon, but the disclosure is not limited thereto, the metal layer 102 may be made of tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN), and the dielectric layer 104 may be made of silicon oxide or silicon nitride, but the disclosure is not limited thereto.

[0034] refer to Figure 4 , a capacitor 110 is formed in the dielectric layer 104. It should be noted that in order to simplify the drawings, Figure 4 The capacitor 110 is depicted as a column. In some embodiments, the capacitor 110 includes an insulating layer surrounded by two electrode layers. In some embodiments, the temperature for forming the capacitor 110 is at least higher than 400 degrees Celsius, such as 450 degrees Celsius to 600 degrees Celsius.

[0035] refer to Figure 5, forming a bottom electrode 122 on the capacitor 110. Specifically, a bottom electrode material layer covering the capacitor 110 may be formed on the dielectric layer 104. Next, the bottom electrode 122 is formed by patterning the bottom electrode material layer. The bottom electrode 122 may completely cover the capacitor 110. In some embodiments, the bottom electrode 122 may be made of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and indium tin oxide (ITO). In some embodiments, the thickness of the bottom electrode 122 is between 10 nanometers and 50 nanometers.

[0036] refer to Figure 6 , a dielectric layer 132 covering the bottom electrode 122 is formed on the dielectric layer 104. In some embodiments, the dielectric layer 132 may be made of silicon oxide or silicon nitride, but the present disclosure is not limited thereto. In some embodiments, the thickness of the dielectric layer 132 is between 20 nanometers and 100 nanometers.

[0037] refer to Figure 7 , forming a word line material layer 140' on the dielectric layer 132, and referring to Figure 8 , patterning the word line material layer 140' to form a word line 140, and the word line 140 has a length along a direction (for example, along Figure 1 The word line material layer 140' is formed in a second direction Y) and overlaps the bottom electrode 122. In some embodiments, the word line material layer 140' can be made of metal such as tungsten (W), copper (Cu) or molybdenum (Mo), but the disclosure is not limited thereto. In some embodiments, the word line material layer 140' has a thickness between 10 nanometers and 500 nanometers.

[0038] refer to Fig. 9 , a dielectric layer 134 covering the word line 140 is formed on the dielectric layer 132. In some embodiments, the dielectric layer 134 may be made of silicon oxide or silicon nitride, but the present disclosure is not limited thereto. In some embodiments, the thickness of the dielectric layer 134 is between 20 nanometers and 550 nanometers. Figures 7 to 9 In the embodiment, the word line 140 and the dielectric layer 130 are formed on the bottom electrode 122 and the dielectric layer 104 , and the word line 140 is embedded in the dielectric layer 130 .

[0039] refer to Fig.10 , a sacrificial layer 150 is formed on the dielectric layer 130, and a dielectric layer 160 is formed on the sacrificial layer 150. In some embodiments, the sacrificial layer 150 is made of a dielectric material, so the sacrificial layer 150 may also be referred to as a dielectric layer 150. The material of the sacrificial layer 150 is different from the materials of the dielectric layer 160 and the dielectric layer 130. In some embodiments, the dielectric layer 160 may be made of silicon oxide or silicon nitride, but the present disclosure is not limited thereto, and the sacrificial layer 150 may be made of silicon oxide or silicon nitride, but the present disclosure is not limited thereto.

[0040] refer to Fig.11 , a photoresist layer PR1 is formed on the dielectric layer 160 . The photoresist layer PR1 includes an opening O1 exposing the dielectric layer 160 , and a vertical projection of the opening O1 of the photoresist layer PR1 on the dielectric layer 104 does not overlap with a vertical projection of the bottom electrode 122 on the dielectric layer 104 .

[0041] refer to Fig.12 , the dielectric layer 160 and the sacrificial layer 150 are patterned to form a first trench T1 exposing the dielectric layer 130. Specifically, a two-stage etching process may be performed to form the first trench T1 penetrating the dielectric layer 160 and the sacrificial layer 150 and exposing the dielectric layer 130. For example, the photoresist layer PR1 (see Fig.11 ) is used as an etching mask to etch the dielectric layer 160, and then the sacrificial layer 150 is etched using the etched dielectric layer 160 as an etching mask. Fig.11 ) on the dielectric layer 104 does not overlap with the vertical projection of the bottom electrode 122 on the dielectric layer 104, and the vertical projection of the first trench T1 on the dielectric layer 104 is separated from the vertical projection of the bottom electrode 122 on the dielectric layer 104. Because the sacrificial layer 150 and the dielectric layer 130 are made of different materials, the dielectric layer 134 can serve as an etching stop layer in the etching process of the sacrificial layer 150. After the first trench T1 is formed, the photoresist layer PR1 can be removed.

[0042] refer to Fig.13 , in the first trench T1 (see Fig.12 ), and then a bit line contact material is filled in the first trench T1 and covers the barrier material layer. After the bit line contact material is filled, a planarization process is performed to remove the excess portions of the bit line contact material and the barrier material layer, so that a barrier layer 172 and a bit line contact 170 are formed in the first trench T1 and on the dielectric layer 130. The barrier layer 172 and the bit line contact 170 have the same profile as the first trench T1, so that the vertical projection of the bit line contact 170 in the first trench T1 on the dielectric layer 104 is also separated from the vertical projection of the bottom electrode 122 on the dielectric layer 104.

[0043] In some embodiments, the barrier layer 172 is made of a conductive material, such as a metal nitride, such as tantalum nitride or titanium nitride, but the disclosure is not limited thereto, and the bit line contact 170 is made of a metal, such as tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), a doped semiconductor material (such as p-type or n-type silicon) and / or other complementary metal-oxide-semiconductor (CMOS) contact materials. In some embodiments, the thickness of the bit line contact 170 is between 10 nanometers and 300 nanometers.

[0044] During the formation of the barrier layer 172 made of metal nitride, ammonia (NH3) is used as a precursor for forming the barrier layer 172, and thus the barrier layer 172 (or the barrier material layer) may contain hydrogen. During the formation of the bit line contact 170, hydrogen may diffuse from the barrier material layer due to a thermal effect of the deposition of the bit line contact 170. Therefore, in order to prevent it from affecting the channel made of an oxide semiconductor formed subsequently, the bit line contact 170 is formed before forming the channel made of an oxide semiconductor.

[0045] refer to Fig.14 A photoresist layer PR2 is formed on the bit line contact 170 and the dielectric layer 160 . The photoresist layer PR2 includes an opening O2 exposing the dielectric layer 160 , and the opening O2 is on the word line 140 . The opening O2 may vertically overlap the dielectric layer 130 and the bottom electrode 122 .

[0046] Next, refer to Fig.15 , forming a second trench T2 penetrating the dielectric layer 160, the sacrificial layer 150, the dielectric layer 130 and the word line 140 and exposing the bottom electrode 122. Specifically, one or more etching processes can be performed to remove portions of the dielectric layer 160, the sacrificial layer 150, the dielectric layer 130 and the word line 140 using the opening O2 of the photoresist layer PR2 as a mask. Therefore, the word line 140 surrounds the second trench T2. The second trench T2 is separated from the bit line contact 170. That is, the second trench T2 does not penetrate the bit line contact 170.

[0047] refer to Fig.16 , forming a gate dielectric layer 180 along the sidewalls of the word line 140. Specifically, a gate dielectric material layer is first formed conformally to the sidewalls, bottom, bit line contact 170 and top of the dielectric layer 160 of the second trench T2. Next, an anisotropic etching is performed to remove the horizontal portion of the gate dielectric material layer, and the remaining portion of the gate dielectric material layer forms the gate dielectric layer 180.

[0048] refer to Fig.17 , in the second trench T2 (see Fig.16 ) is filled with channel material 124'. Next, refer to Fig.18, the channel material 124' and the gate dielectric layer 180 are etched back to reduce the upper surface height of the channel material 124' and the gate dielectric layer 180. More specifically, the channel material 124' may be etched until the upper surfaces of the channel material 124' and the gate dielectric layer 180 are lower than the sacrificial layer 150, and the remaining channel material 124' forms the channel 124. That is, the channel 124 is formed after the bit line contact 170 is formed, and the vertical projection of the bit line contact 170 on the dielectric layer 104 is separated from the vertical projection of the channel 124 on the dielectric layer 104. The channel 124 is made of an oxide semiconductor, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and indium tin oxide (ITO).

[0049] In some embodiments, the oxide semiconductor is sensitive to hydrogen. For example, hydrogen diffused into the oxide semiconductor (e.g., channel 124) may cause an undesirable threshold voltage shift of the oxide semiconductor. As described above, the barrier layer 172 is formed in a hydrogen environment, so the present disclosure provides a process that first forms the bit line contact 170 and the barrier layer 172, and then forms the channel 124, so that hydrogen diffusion does not affect the channel 124 formed in the subsequent process. In this way, the channel 124 does not contain hydrogen, and the device performance can be improved.

[0050] In addition, because the capacitor 110 is formed before the channel 124 , the thermal effect during the formation of the capacitor 110 will not affect the channel 124 .

[0051] refer to Fig.19 , a third trench T3 is formed by etching a portion of the sacrificial layer 150, so that the third trench T3 exposes the sidewall of the barrier layer 172. Specifically, a wet etching process is performed to laterally etch a portion of the sacrificial layer 150. Because the material of the sacrificial layer 150 is different from that of the dielectric layer 130 and the dielectric layer 160, the wet etching process only removes a portion of the sacrificial layer 150, and the dielectric layer 130 and the dielectric layer 160 remain substantially intact. In some embodiments, the wet etching process is performed until the third trench T3 exposes the sidewall of the barrier layer 172.

[0052] refer to Fig. 20, a top electrode material is filled in the third trench T3, and a fourth trench T4 is formed by etching back the top electrode material. The remaining portion of the top electrode material forms a top electrode 126. That is, the top electrode 126 is formed on the channel 124 and contacts the barrier layer 172. The vertical projection of the top electrode 126 on the dielectric layer 104 completely covers the vertical projection of the channel 124 on the dielectric layer 104. More specifically, because the top electrode 126 is formed in the third trench T3, and the third trench T3 protrudes laterally from the sidewall of the gate dielectric layer 180, the top electrode 126 includes a first portion 126A and a second portion 126B, and the second portion 126B is on the first portion 126A. The sidewall of the second portion 126B of the top electrode 126 protrudes from the sidewall of the first portion 126A of the top electrode 126, and the sidewall of the second portion 126B of the top electrode 126 contacts the sidewall of the barrier layer 172. The bottom of the second portion 126B of the top electrode 126 contacts the dielectric layer 130. The sidewalls of the first portion 126A of the top electrode 126 are vertically aligned with the sidewalls of the gate dielectric layer 180. In addition, because the dielectric layer 130 is used as a substrate in forming the first trench T1 (see FIG. Fig.12 ) and the third trench T3 (see Fig.19 ), after forming the top electrode 126, the bottom of the second portion 126B of the top electrode 126 is aligned with the bottom of the barrier layer 172. In some embodiments, the top electrode 126 can be made of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) and indium tin oxide (ITO). In some embodiments, the thickness of the top electrode 126 can be between 10 nanometers and 50 nanometers.

[0053] After forming the top electrode 126, the dielectric layer 160 contacts the upper surface of the top electrode 126 and the sacrificial layer 150 (ie, Figure 1 The upper surface of the dielectric layer 150 mentioned above, and the sidewalls of the barrier layer 172 contact the dielectric layer 160 and the top electrode 126 at the same time.

[0054] refer to Fig.21 , a dielectric layer 190 is formed in the fourth trench T4 on the top electrode 126. Therefore, the dielectric layer 190 and the dielectric layer 160 cover the upper surface of the top electrode 126, and the dielectric layer 190 is surrounded by the dielectric layer 160. In some embodiments, the dielectric layer 190 may be made of silicon oxide or silicon nitride, but the present disclosure is not limited thereto.

[0055] Next, refer to Fig. 22 , a bit line 195 is formed on the bit line contact 170, the dielectric layer 190, and the dielectric layer 160. In some embodiments, the bit line 195 is made of tungsten (W), copper (Cu), or molybdenum (Mo), but the present disclosure is not limited thereto. In some embodiments, the thickness of the bit line 195 can be between 20 nanometers and 100 nanometers.

[0056] In summary, the process sequence and position of the bit line contact can be adjusted to reduce the impact of hydrogen diffusion on the oxide semiconductor device. More specifically, because the bit line contact and the barrier layer are formed before the channel is formed, the hydrogen in the barrier layer covering the bit line contact will diffuse into the dielectric layer but not into the channel. Therefore, hydrogen will not affect the channel characteristics. For example, the threshold voltage shift caused by hydrogen diffusion can be avoided.

[0057] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the definition of the attached claims.

[0058]

Explanation of symbols

[0059] 100: Semiconductor substrate

[0060] 102: Metal layer

[0061] 104, 130, 132, 134, 160, 190: Dielectric layer

[0062] 110: Capacitor

[0063] 122: Bottom electrode

[0064] 124: Channel

[0065] 124': Channel material

[0066] 126: Top electrode

[0067] 126A: Part 1

[0068] 126B: Part 2

[0069] 140: Character line

[0070] 140': Character line material layer

[0071] 150: Dielectric layer / sacrificial layer

[0072] 170: Bit line contacts

[0073] 172: Barrier layer

[0074] 180: Gate dielectric layer

[0075] 195: Bit Line

[0076] A: Line

[0077] O1, O2: Open

[0078] PR1, PR2: Photoresist layer

[0079] T1: First groove

[0080] T2: Second groove

[0081] T3: Third Groove

[0082] T4: The fourth groove

[0083] X: First direction

[0084] Y: Second direction.

Claims

1. A method for forming a memory device, characterized in that: Include: forming a capacitor in the first dielectric layer; forming a bottom electrode on the capacitor; forming a word line and a second dielectric layer on the bottom electrode and the first dielectric layer, wherein the word line is embedded in the second dielectric layer; forming a bit line contact on the second dielectric layer, wherein a vertical projection of the bit line contact on the first dielectric layer is spaced apart from a vertical projection of the bottom electrode on the first dielectric layer; After forming the bit line contact, forming a via contacting the bottom electrode; as well as A top electrode is formed on the channel and contacts the bit line contact.

2. The method according to claim 1, characterized in that Wherein forming the bit line contact comprises: forming a sacrificial layer on the second dielectric layer; forming a third dielectric layer on the sacrificial layer; forming a first trench by patterning the sacrificial layer and the third dielectric layer to expose the second dielectric layer; forming a barrier material layer in the first trench; as well as A bit line contact material is formed in the first trench covering the barrier material layer.

3. The method according to claim 2, characterized in that A vertical projection of the first trench on the first dielectric layer is separated from a vertical projection of the bottom electrode on the first dielectric layer.

4. The method according to claim 2, characterized in that: The formation of the channel comprises: forming a second trench penetrating the third dielectric layer, the sacrificial layer, the second dielectric layer, the word line and exposing the bottom electrode; and The second trench is filled with a channel material, and the method further includes forming a gate dielectric layer along the sidewalls of the word line before forming the channel.

5. The method according to claim 4, characterized in that Also includes: The channel material is etched until an upper surface of the channel material is below the sacrificial layer.

6. The method according to claim 4, characterized in that Wherein forming the top electrode comprises: Forming a third trench by etching a portion of the sacrificial layer, wherein the third trench exposes a sidewall of the barrier material layer; filling the third trench with a top electrode material; forming a fourth trench by etching back the top electrode material; as well as A dielectric material is filled in the fourth trench on the top electrode material.

7. The method according to claim 1, characterized in that The channel contains no hydrogen.

8. The method according to claim 1, characterized in that The temperature at which the capacitor is formed is higher than the temperature at which the channel is formed.

9. The method according to claim 1, characterized in that: The channel is made of an oxide semiconductor.

10. The method according to claim 1, characterized in that Also included is a bit line formed to contact the bit line contact.

11. A memory device, characterized in that: Include: a first dielectric layer; a capacitor in the first dielectric layer; a bottom electrode, on the capacitor; a channel, on the bottom electrode; the top electrode, on the channel; a gate dielectric layer surrounding the channel; A word line surrounding the gate dielectric layer; A second dielectric layer surrounding the word line, the gate dielectric layer and the channel; a bit line contact on the second dielectric layer, wherein a vertical projection of the bit line contact on the first dielectric layer is spaced apart from a vertical projection of the via on the first dielectric layer; as well as A barrier layer is between the bit line contact and the top electrode.

12. The memory device according to claim 11, wherein: The vertical projection of the top electrode on the first dielectric layer completely covers the vertical projection of the channel on the first dielectric layer.

13. The memory device according to claim 11, wherein: The top electrode includes a first portion and a second portion, the second portion of the top electrode is on the first portion of the top electrode, the sidewall of the second portion of the top electrode protrudes from the sidewall of the first portion of the top electrode, and the sidewall of the second portion of the top electrode contacts the sidewall of the barrier layer.

14. The memory device according to claim 13, wherein: The sidewall of the first portion of the top electrode is aligned with the sidewall of the gate dielectric layer.

15. The memory device according to claim 13, wherein: The bottom of the second portion of the top electrode is aligned with the bottom of the barrier layer.

16. The memory device according to claim 13, wherein: The second portion of the top electrode contacts the second dielectric layer.

17. The memory device according to claim 11, wherein: Also includes: a third dielectric layer on the top electrode; and The fourth dielectric layer contacts the sidewall of the top electrode, wherein the third dielectric layer contacts the upper surface of the top electrode and the upper surface of the fourth dielectric layer, and the fourth dielectric layer and the third dielectric layer are made of different materials.

18. The memory device according to claim 17, wherein: The third dielectric layer also contacts the sidewall of the barrier layer.

19. The memory device according to claim 11, wherein: The channel is made of an oxide semiconductor.

20. The memory device according to claim 11, wherein: Also included is a bit line contacting the bit line contact.

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