Crystalline spinel indium gallium zinc oxide channel

Abstract

The present disclosure relates to a crystalline spinel indium gallium zinc oxide (IGZO) channel. Systems, methods, and apparatus are provided for a transistor having a channel region comprising a crystalline spinel IGZO material.

Description

Technical Field

[0001] The present disclosure relates to a transistor including a channel region including a crystalline spinel indium-gallium-zinc-oxide (IGZO) material. Background Art

[0002] Memory is a type of integrated circuit system and can be used in computer systems for storing data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Sense lines can interconnect memory cells in a conductive manner along the columns of the array, and access lines can interconnect memory cells in a conductive manner along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long period of time without power. Non-volatile memory is generally designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to retain or store memory in at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store information at more than two levels or states.

[0004] A transistor is a type of electronic component that can be used in a memory cell. These transistors may include a pair of conductive source / drain regions with a semiconducting channel region therebetween. A conductive gate may be adjacent to the channel region and separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region.

[0005] Transistors may be used in circuitry other than memory circuitry. Summary of the invention

[0006] One aspect of the present disclosure is directed to a transistor comprising: a gate material; a channel region comprising a crystalline spinel indium gallium zinc oxide (IGZO) material adjacent to the gate material; and a buffer material between the channel region and the gate material.

[0007] Another aspect of the present disclosure is directed to a method for making a transistor, the method comprising: forming a first gate oxide material; forming a channel region comprising a crystalline spinel indium gallium zinc oxide (IGZO) material between the first gate oxide material and a second gate oxide material, wherein the channel region comprises from 50 atomic % to 76 atomic % of gallium, from 20 atomic % to 50 atomic % of zinc, and from 0.01 atomic % to 20 atomic % of indium; forming a first buffer region between the first gate oxide material and the channel region; and forming a second buffer region between the second gate oxide material and the channel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 4 is a view of a portion of an example of a transistor according to an embodiment of the present disclosure.

[0009] Figure 5 is an example graph of atomic percentages of IGZO material for a transistor according to an embodiment of the present disclosure.

[0010] Figure 6 is a block diagram illustration of an example device, such as an electronic memory system, according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] The present disclosure includes apparatus, methods, and systems for a transistor having a first source / drain region, a second source drain / region, and a channel region, the channel region comprising a crystalline spinel indium gallium zinc oxide (IGZO) material.

[0012] Some of the aforementioned transistors incorporate indium into gallium zinc oxide to provide a channel material, such as IGZO. However, these previous IGZO transistors may suffer from reliability issues related to bias temperature instability (BTI). For example, under BTI stress, devices utilizing these previous IGZO transistors may exhibit undesirable DVT (ΔV T ) turnover, i.e., a reversal in the direction of the DVT shift. However, embodiments of the present disclosure address this problem by utilizing pure crystalline spinel IGZO. Using pure crystalline spinel IGZO thin films for application in TFT devices and providing a passivation annealing process to reduce defects in the gate material provides better stability for IGZO transistors.

[0013] Both the gate oxide and the channel region may be formed of pure crystalline material, which may provide an improved structure for the transistor and reduce degradation. A passivation annealing process may produce one or more buffer layers surrounding the channel region, which may, for example, reduce conductivity interference. The crystalline structure may include continuous grains / lattice materials for the gate material and the channel. Also, band structure analysis and density of states, which may involve the number of states per unit energy and per unit volume, may specify that the buffer region has a relatively wider band gap than the crystalline channel. The buffer region may also have a relatively larger work function (eV) than the crystalline channel.

[0014] Embodiments of the present disclosure provide that the IGZO material may have a specific atomic percentage to form a crystalline spinel IGZO material. For example, the embodiment provides that, based on 100 atomic % of the metal elements in the crystalline spinel IGZO material, the atomic percentage may be from 50 atomic % to 76 atomic % of gallium, from 20 atomic % to 50 atomic % of zinc, and from 0.01 atomic % to 20 atomic % of indium. One or more embodiments provide that, based on 100 atomic % of the metal elements in the crystalline spinel IGZO material, the atomic percentage may be from 60 atomic % to 70 atomic % of gallium, from 20 atomic % to 40 atomic % of zinc, and from 0.01 atomic % to 15 atomic % of indium. The buffer material may also include a gallium zinc oxide (GZO) material. However, the buffer material need not be crystalline, and one or more embodiments provide that indium is not utilized, for example, the buffer material does not include indium. In other embodiments, the buffer material may be crystalline and contain less indium than the channel material.

[0015] As mentioned, crystalline spinel indium gallium zinc oxide (IGZO) materials can be used to make transistors, such as thin film transistors. These transistors can be incorporated into memory structures, and memory cells, arrays including such memory cells, memory devices, switching devices and other semiconductor devices including such arrays, systems including such arrays, and methods for making and using such memory structures are also disclosed. Embodiments of the present disclosure include a variety of different memory cells, such as volatile memory, non-volatile memory, and / or transistor configurations. Non-limiting examples include random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, resistive random access memory (ReRAM), conductive bridging random access memory (conductive bridging RAM), magnetoresistive random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin torque transfer random access memory (STTRAM), oxygen vacancy based memory, programmable conductor memory, ferroelectric random access memory (FE-RAM), reference field effect transistor (RE-FET), etc.

[0016] The transistors disclosed herein may be used in volatile memory cells, such as dynamic random access memory (DRAM) cells, and may be coupled to storage elements. The storage element may, for example, include a storage node, which may be a capacitor, for example, configured to store a logic state defined by a stored charge in the capacitor. The capacitor may be a capacitor of a single transistor single capacitor memory cell. In another example, the capacitor may be a capacitor of a two transistor memory cell. Embodiments provide that other types of storage nodes may be utilized.

[0017] Some memory devices include a memory array that exhibits memory cells arranged in a cross-point architecture that includes conductive lines, e.g., access lines, such as word lines, that extend perpendicular, e.g., orthogonal, to additional conductive lines, e.g., data lines, such as digit lines. The memory array may be three-dimensional (3D) so as to exhibit multiple stacks, e.g., multiple levels, multiple layers, of memory cells. A selection device, such as a transistor as discussed herein, may be used to select a particular memory cell of the 3D memory array.

[0018] Embodiments of the present disclosure may include different configurations of transistors, such as thin film transistors, including vertically oriented transistors, horizontally oriented transistors, such as planar transistors, etc. Embodiments may also include transistors with different gate configurations, including: single gate, double gate, and gate all around.

[0019] As used herein, "a", "an" or "a number" may refer to one or more of something, and "a plurality" may refer to two or more of such things. For example, a memory device may refer to one or more memory devices, and a plurality of memory devices may refer to two or more memory devices.

[0020] Figure 1 1 is a diagram of a portion of an example of a transistor 102 according to an embodiment of the present disclosure. Figure 1 As shown in , the xyz coordinate system includes a horizontal x-direction 116 , a horizontal y-direction 118 , and a vertical z-direction 120 .

[0021] The transistor 102 may include a channel region 112. The channel region may be formed of a pure crystalline material, which may provide an improved structure for the transistor and reduce degradation. As used herein, "pure crystalline material" refers to a material comprising a crystalline component, for example, a pure crystalline IGZO material comprising indium gallium zinc oxide. In other words, the pure crystalline IGZO material is substantially free of impurities. The crystalline structure may include a continuous grain / lattice material for the channel. As mentioned, an embodiment provides that the channel region 112 includes a crystalline spinel IGZO material, as discussed herein. The crystalline spinel IGZO material may be a pure crystalline material. In one embodiment, the channel region may have a thickness in the range of 150-250 angstroms (A). However, the embodiments are not limited thereto. One or more embodiments provide that the channel region has a thickness of 200A.

[0022] One or more embodiments provide that transistor 102 may include a gate material. The gate material may be adjacent to channel region 112. Figure 1 As shown in FIG. 1 , the gate material may include a first gate material 110 and a second gate material 114 . A channel region 112 may be between the first gate material 110 and the second gate material 114 .

[0023] The first gate material 110 and the second gate material 114 may be aluminum oxide material (AlOx), hafnium dioxide material, or silicon oxide material, as well as other materials.

[0024] The gate material may be formed of pure crystalline material and may include continuous grains / lattice materials. In one embodiment, the gate materials may each have a respective thickness in the range of 30-70 Å. For example, the first gate material 110 may have a thickness in the range of 30-70 Å, and the second gate material 114 may also have a thickness in the range of 30-70 Å. However, the embodiments are not limited thereto. One or more embodiments provide that the first gate material 110 and the second gate material 114 each have a respective thickness of 50 Å.

[0025] Although in Figure 11 , transistor 102 may include a first source / drain region and a second source / drain region. One or more embodiments provide that at least one of the first source / drain region and the second source / drain region includes an IGZO material. One or more embodiments provide that both the first source / drain region and the second source / drain region include an IGZO material. Although reference to first and second source / drain regions is used herein to designate two separate and distinct source / drain regions, it is not intended that source / drain regions referred to as “first” and / or “second” source / drain regions have a unique meaning. The first source / drain region and the second source / drain region may be formed of doped semiconductor materials, such as Si, SiGe, Ge, SiCo, transition metal dichalcogenides (TMDs), metals, and / or metal composites containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), doped conductive oxides, such as indium tin oxide (ITO), indium oxide, or semiconductive oxides, such as IGZO, IZO, SnZnO, and other materials. The first source / drain region and the second source / drain region may be formed adjacent to the channel region 112.

[0026] Figure 2 is a diagram of a portion of an example of a transistor 232 according to an embodiment of the present disclosure. Figure 2 An xyz coordinate system is included that includes a horizontal x-direction 216 , a horizontal y-direction 218 , and a vertical z-direction 220 .

[0027] Figure 2 The channel region 212 may be similar or similar to Figure 1 The channel region 102 is formed in the vicinity of the substrate. Figure 2 The first gate material 210 may be similar to or similar to Figure 1 A first gate material 110 is provided. Figure 2 The second gate material 214 may be similar to or similar to Figure 1 The second gate material 114 is formed by a plurality of electrodes.

[0028] The passivation annealing process 204 may be applied to one or more portions of the transistor 232 to provide a buffer zone (at Figure 3 ). Embodiments provide that the passivation annealing process 204 disclosed herein and / or devices including the transistors may be made using various processing techniques, such as rapid thermal processing, atomic material deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), supercritical fluid deposition (SFD), patterning, etching, filling, chemical mechanical planarization (CMP), combinations thereof, and / or other suitable processes. According to various embodiments of the present disclosure, the material may be grown in situ. The passivation annealing process does not reduce the thickness of the channel region 212, the first gate material 110, or the second gate material 114.

[0029] A passivation annealing process 204 may be applied adjacent to the channel region 212 and the second gate material 214. One or more embodiments provide that the buffer region may be formed by rapid thermal processing. The rapid thermal processing may occur at a temperature ranging from 750 to 1,000° C. for a time period ranging from 5 to 60 seconds (among other values).

[0030] Figure 3 is a diagram of a portion of an example of a transistor 342 according to an embodiment of the present disclosure. Figure 3 An xyz coordinate system is included that includes a horizontal x-direction 316 , a horizontal y-direction 318 , and a vertical z-direction 320 .

[0031] Figure 3 The channel regions 312 may be similar to or similar to Figure 1 and 2 The channel regions 112 and 212 are also shown. Figure 3 The first gate material 310 may be similar to or similar to Figure 1 and 2 The first gate materials 110 and 210 are provided. Figure 3 The second gate material 314 may be similar to or similar to Figure 1 and 2 The second gate material 114 and 214 is formed.

[0032] The transistor 342 may include a buffer material. The buffer material may be adjacent to the channel region 312. Figure 3 As shown in FIG. 3 , the buffer material may include a first buffer region 306 and a second buffer region 308. A channel region 312 may be between the first buffer region 306 and the second buffer region 308. For example, the first buffer region 306 may be adjacent to the first gate material 310, and the second buffer region 308 may be adjacent to the second gate material 314.

[0033] The first buffer region 306 and the second buffer region 308 may respectively passivate defects within the first gate material 310 and the second gate material 314. For example, the formation of the first buffer region 306 and the second buffer region 308 may reduce the conductivity between the channel region 312 and the gate materials 310 and 314. The first buffer region 306 and the second buffer region 308 may also improve the positive bias temperature instability (PBTI) of the transistor 342.

[0034] The buffer material for the first buffer region 306 and the second buffer region 308 may be formed of a gallium zinc oxide (GZO) material. In some embodiments, the buffer material for the first buffer region 306 and the second buffer region 308 may be formed of a material that is relatively less conductive than the gate material and / or the channel material. One or more embodiments provide that the buffer material may not be formed of a crystalline material.

[0035] In one embodiment, the buffer regions may each have a thickness in the range of 30-70A, respectively. For example, the first buffer region 306 may have a thickness in the range of 30-70A, and the second buffer region 308 may also include a thickness in the range of 30-70A. However, embodiments are not limited thereto. In some embodiments, the first buffer region 306 may have a thickness similar to (e.g., the same as) the first gate material 310, and the second buffer region 308 may have a thickness similar to (e.g., the same as) the second gate material 314. One or more embodiments provide that the first buffer region 306 and the second buffer region 308 each have a respective thickness in the range of 30-70A.

[0036] Figure 4 is a view of a portion of an example of a transistor 472 according to an embodiment of the present disclosure. Figure 4 An xyz coordinate system is included that includes a horizontal x-direction 416 , a horizontal y-direction 418 , and a vertical z-direction 420 . Figure 4 Can Figure 3 Different views of the transistor shown in .

[0037] Figure 3 The channel regions 312 may be similar to or similar to Figure 1 and 2 The channel regions 112 and 212 are also shown. Figure 3 The first gate material 310 may be similar to or similar to Figure 1 and 2 The first gate materials 110 and 210 are provided. Figure 3 The second gate material 314 may be similar to or similar to Figure 1 and 2 The second gate material 114 and 214 is formed.

[0038] The transistor 472 may include a first gate material 410 and a second gate material 414. The gate material may be made of Figure 1 The transistor 472 may include a channel region 412. The channel region 412 may be formed of materials such as Figure 1 The transistor 472 may include a first buffer 406 and a second buffer 408. The buffer may be formed of materials such as Figure 3 Although Figure 4 Although not shown in the figure, transistor 472 may include a first source / drain region and a second source / drain region. The first source / drain region and the second source / drain region may be formed adjacent to channel region 412.

[0039] The embodiments of the present disclosure are not limited to Figures 1 to 4The physical structure of the transistor shown in . For example, in several embodiments, the structure of the transistor may include one or more additional components and / or may have a different arrangement of materials.

[0040] As an example, the transistors disclosed herein and / or devices including the transistors may be made by, for example, forming a material stack on a substrate, the material stack including a plurality of channel regions, a first source / drain material, a second source / drain material, and a gate material. The material stack may include one or more additional materials for transistor and / or device including transistor fabrication. Processing steps may include patterning and etching the material stack, selectively removing a portion of one or more materials, depositing materials, and planarizing, etc. to fabricate the transistors disclosed herein and / or devices including the transistors.

[0041] Figure 5 is an example graph 574 of atomic percentages of IGZO material for a transistor according to an embodiment of the present disclosure. As mentioned, embodiments provide that the channel region includes a crystalline spinel IGZO material. The channel region may be, for example, according to graph 574, composed of Figures 1 to 4 The materials discussed in the formation.

[0042] As mentioned earlier, Figure 5 As shown in , based on 100 atomic % of the metal elements in the crystalline spinel IGZO material, the channel region can be formed of a material including 50 atomic % to 76 atomic % of gallium, 20 atomic % to 50 atomic % of zinc, and 0.01 atomic % to 20 atomic % of indium. One or more embodiments provide that based on 100 atomic % of the metal elements in the crystalline spinel IGZO material, the atomic percentages can be from 60 atomic % to 70 atomic % of gallium, from 20 atomic % to 40 atomic % of zinc, and from 0.01 atomic % to 15 atomic % of indium. The crystalline structure of the channel can provide better stability and structure for the channel region and prevent degradation. As discussed herein, the crystalline structure formed using atomic percentages according to this graph can be a continuous grain / lattice material.

[0043] The transistor formed may cause the work function of the first gate material and the second gate material to be relatively greater than the work function of the channel region. The first gate material and the second gate material may have a work function in the range of 6.0 eV to 7 eV, and the channel region may have a work function in the range of 3.0 eV to 3.8 eV.

[0044] Figure 66 is a block diagram illustration of an example device, such as an electronic memory system 690, according to an embodiment of the present disclosure. The memory system 690 may include a device, such as a memory device 692 and a controller 650, such as a memory controller, such as a host controller. For example, the controller 650 may include a processor. The controller 650 may be coupled to, for example, a host, and may receive command signals (or commands), address signals (or addresses), and data signals (or data) from the host, and may output data to the host.

[0045] Memory device 692 includes a memory array 652 of memory cells. For example, memory array 652 may include one or more of memory arrays, such as cross-point arrays, as well as other types of arrays. Memory array 652 may include a number of transistors, such as access devices where the channel region includes a crystalline spinel IGZO material as disclosed herein. Memory device 692 may include address circuitry 654 to latch address signals provided on I / O connections 694 by I / O circuitry 656. Row decoder 658 and column decoder 616 may receive and decode address signals to access memory array 652.

[0046] The memory device 692 can sense (e.g., read) data in the memory array 652 by sensing voltage and / or current changes in the memory array columns using sensing / buffer circuitry, which in some examples can be read / latch circuitry 696. The read / latch circuitry 696 can read and latch data from the memory array 652. The sensing circuitry 660 can include a number of sense amplifiers coupled to the memory cells of the memory array 652, which can operate in conjunction with the read / latch circuitry 696 to sense (e.g., read) memory states from the target memory cells. An I / O circuitry 656 can be included for bidirectional data communication with the controller 650 on the I / O connection 694. A write circuitry 622 can be included to write data to the memory array 652.

[0047] Control circuitry 624 may decode signals provided from controller 650 over control connections 626. These signals may include chip signals, write enable signals, and address latch signals used to control operations on memory array 652, including data read and data write operations.

[0048] Control circuitry 624 may be included, for example, in a controller 650. Controller 650 may include other circuitry, firmware, software, etc., alone or in combination. Controller 650 may be an external controller, such as in a die separate in whole or in part from memory array 652, or an internal controller, such as included in the same die as memory array 652. For example, the internal controller may be a state machine or a memory sequencer.

[0049] Although specific embodiments have been shown and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of several embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative and not restrictive manner. Upon reviewing the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of several embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of several embodiments of the present disclosure should be determined with reference to the attached claims and the full scope of equivalents to which such claims are assigned.

[0050] In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than are expressly recited in each claim. In fact, as reflected in the appended claims, the subject matter of the present invention lies in less than all of the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A transistor (102), comprising: Gate material (110, 114); a channel region (112) comprising a crystalline spinel indium gallium zinc oxide (IGZO) material adjacent to the gate material; as well as A buffer material is located between the channel region and the gate material.

2. The transistor of claim 1, wherein the channel region comprises from 50 atomic % to 76 atomic % gallium.

3. The transistor of claim 2, wherein the channel region comprises from 20 atomic % to 50 atomic % zinc.

4. The transistor of claim 1, wherein the transistor comprises one of a single gate, a double gate, and a gate-all-around.

5. The transistor of claim 1, wherein the transistor is coupled to one of a capacitor of a single-transistor single-capacitor memory cell (1t1c) and a two-transistor memory cell.

6. The transistor of claim 1, wherein the channel region has a thickness in the range of 150-250 angstroms A. 7 . The transistor according to claim 1 , wherein the buffer material comprises gallium zinc oxide (GZO) material.

8. The transistor of claim 7, wherein the buffer material has a thickness of 30-70 angstroms. 9 . The transistor of claim 1 , wherein first and second source / drain regions are adjacent to the channel region.

10. The transistor according to claim 1, comprising: The channel region comprises the indium gallium zinc oxide (IGZO) material adjacent to the gate material, wherein the channel region comprises gallium in a range from 50 atomic % to 76 atomic %.

11. The transistor of claim 10, wherein the gate material is a crystalline aluminum oxide (AlOx) material.

12. The transistor of claim 10, wherein the channel region is between the gate material and a second gate material.

13. The transistor of claim 12, wherein a second buffer zone is formed adjacent to the second gate material.

14. The transistor of claim 10, wherein the gate material has a thickness in the range of 30-70 angstroms.

15. A method of making a transistor (342), the method comprising: forming a first gate oxide material (310); forming a channel region (312) comprising a crystalline spinel indium gallium zinc oxide (IGZO) material between the first gate oxide material and the second gate oxide material (314), wherein the channel region comprises from 50 atomic % to 76 atomic % gallium, from 20 atomic % to 50 atomic % zinc, and from 0.01 atomic % to 20 atomic % indium; forming a first buffer region (306) between the first gate oxide material and the channel region; and A second buffer region (308) is formed between the second gate oxide material and the channel region. The method of claim 15 , wherein forming the first buffer region comprises using a passivation annealing process. The method of claim 15 , wherein forming the first buffer region comprises using rapid thermal processing.

18. The method of claim 15, wherein forming the first buffer region comprises using a rapid thermal process at 750-1000°C for 5 to 60 seconds.

19. The method of claim 15, wherein forming the first buffer region comprises using one of atomic layer deposition, physical vapor deposition, and chemical vapor deposition.

20. The method of claim 15, wherein forming the transistor comprises an effective work function of the first gate oxide material and the second gate oxide material in a range between 6.0 eV and 7 eV, and the channel region comprises an effective work function in a range between 3.0 eV and 3.8 eV.

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