LDMOS device and method of manufacturing the same

Abstract

The application relates to an LDMOS device and a preparation method thereof. The LDMOS device comprises a semiconductor substrate, a first drift region, a first well region, a first source-drain region, a second source-drain region and a buried field plate unit. The first drift region and the first well region are formed in the semiconductor substrate and adjacent to each other. The first source-drain region is arranged in the first drift region. The second source-drain region is arranged in the first well region. The buried field plate unit comprises a first shallow trench isolation structure and a conductive layer. The first shallow trench isolation structure is arranged in the first drift region and located between the first source-drain region and the second source-drain region. The conductive layer is embedded in the first shallow trench isolation structure.

Description

LDMOS devices and their fabrication methods Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an LDMOS device and its fabrication method. Background Technology

[0002] In the field of semiconductor devices, such as power devices, laterally-diffused metal-oxide semiconductor (LDMOS) devices have been widely used.

[0003] Power devices often need to withstand high voltage and high current conditions, which requires LDMOS devices to have good voltage withstand performance. In related technologies, to improve the voltage withstand performance of LDMOS devices, the channel length and other parameters are usually adjusted. However, such methods are difficult to meet the requirements of device miniaturization.

[0004] Therefore, how to design an optimized LDMOS device to improve its breakdown voltage characteristics has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application provides an LDMOS device and a method for fabricating the same, which enhances the breakdown voltage performance of the LDMOS device without increasing its size.

[0006] To achieve the above-mentioned technical objectives, this application provides an LDMOS device in its first aspect. The LDMOS device includes: a semiconductor substrate, a first drift region, a first well region, a first source-drain region, a second source-drain region, and a buried field plate unit. The first drift region and the first well region are formed in the semiconductor substrate and are adjacent to each other. The first source-drain region is disposed in the first drift region. The second source-drain region is disposed in the first well region. The buried field plate unit includes a first shallow trench isolation structure and a conductive layer. The first shallow trench isolation structure is disposed in the first drift region and located between the first source-drain region and the second source-drain region. The conductive layer is buried within the first shallow trench isolation structure.

[0007] To achieve the above-mentioned technical objectives, a second aspect of this application provides a method for fabricating an LDMOS device. The method includes: fabricating a buried field plate unit in a semiconductor substrate, wherein the buried field plate unit includes: a first shallow trench isolation structure and a conductive layer buried within the first shallow trench isolation structure; forming a first drift region and a first well region adjacent to each other in the semiconductor substrate by doping, wherein the first drift region is configured as a continuous region surrounding and adjacent to the buried field plate unit; and forming a first source-drain region by doping in the first drift region and forming a second source-drain region by doping in the first well region, wherein the first source-drain region is located on the side of the buried field plate unit away from the first well region.

[0008] This application provides an LDMOS device and a method for fabricating the same. The LDMOS device includes a semiconductor substrate, a first drift region, a first well region, a first source-drain region, a second source-drain region, and a buried field plate unit. The first drift region and the first well region are formed in the semiconductor substrate and are adjacent to each other. The first source-drain region is disposed in the first drift region. The second source-drain region is disposed in the first well region. The buried field plate unit includes a first shallow trench isolation structure and a conductive layer. The first shallow trench isolation structure is disposed in the first drift region and located between the first source-drain region and the second source-drain region. The conductive layer is buried within the first shallow trench isolation structure. By burying the conductive layer within the first shallow trench isolation structure, the conductive layer can form a large-area field plate near the bottom and sides of the drift region of the first shallow trench isolation structure. By applying a reverse voltage to the conductive layer, the electric field distribution of the drift region of the LDMOS device can be better adjusted, thereby increasing the breakdown voltage of the LDMOS transistor without increasing its on-resistance, thus improving its breakdown voltage performance. Attached Figure Description

[0009] This application will describe the embodiments in conjunction with the accompanying drawings. The drawings are for illustrative purposes only and are used to describe the embodiments. Without departing from the principles of this application, those skilled in the art can easily make other embodiments based on the steps described below.

[0010] Figure 1 is a top view of an LDMOS device according to some embodiments of this application;

[0011] Figure 2 is a cross-sectional view of an LDMOS device according to some embodiments of the present application along section A-A' in Figure 1;

[0012] Figure 3 is a flowchart of a preparation method according to some embodiments of this application;

[0013] Figure 4 is a flowchart illustrating operation S31 in Figure 3 according to some embodiments of this application;

[0014] Figure 5 is a first structural schematic diagram of the fabrication process of an embedded field plate unit according to some embodiments of this application;

[0015] Figure 6 is a schematic diagram of the second structure during the fabrication process of an embedded field plate unit according to some embodiments of this application;

[0016] Figure 7 is a schematic diagram of the third structure during the fabrication process of an embedded field plate unit according to some embodiments of this application;

[0017] Figure 8 is a fourth structural schematic diagram of the fabrication process of an embedded field plate unit according to some embodiments of this application;

[0018] Figure 9 is a fifth structural schematic diagram of the fabrication process of an embedded field plate unit according to some embodiments of this application;

[0019] Figure 10 is a sixth structural schematic diagram of the fabrication process of an embedded field plate unit according to some embodiments of this application;

[0020] Figure 11 shows the TCAD simulation results of an LDMOS device according to some embodiments of this application;

[0021] Figure 12 shows the simulation results of the impact ionization intensity of the LDMOS device without embedded field plate units;

[0022] Figure 13 shows the simulation results of the impact ionization intensity of the LDMOS device when a reverse voltage of 10V is applied to the embedded field plate unit according to some embodiments of this application.

[0023] Figure 14 shows the simulation results of the current density of the LDMOS device without embedded field plate units;

[0024] Figure 15 shows the simulation results of the current density of the LDMOS device when a reverse voltage of 10V is applied to the embedded field plate unit according to some embodiments of this application. Detailed Implementation

[0025] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0026] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0027] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "more" in this article means two or more objects.

[0028] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified in some embodiments. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0029] Referring to Figures 1 and 2, Figure 1 is a top view of an LDMOS device 1 according to some embodiments of the present application, and Figure 2 is a cross-sectional view of an LDMOS device 1 according to some embodiments of the present application along section A-A' in Figure 1.

[0030] Figures 1 and 2 illustrate an example using a transistor with two shared drain regions. Specifically, the LDMOS device 1 comprises two adjacent transistors. The two transistors share a common drain region. The two source regions of the two adjacent transistors are respectively located on the side furthest from the common drain region, serving as the source regions of their respective transistors. In some embodiments, the LDMOS device 1 may also include only a single transistor structure; this application does not impose specific limitations on this.

[0031] As shown in Figures 1 and 2, the LDMOS device 1 includes a semiconductor substrate 10, a first drift region 12, a first well region 14, a first source-drain region 22, a second source-drain region 24, and a buried field plate unit 30.

[0032] In some embodiments, the semiconductor substrate 10 may be made of semiconductor materials such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III / V or II / VI compound semiconductors, or may include layered substrates such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI) or silicon-germanium-on-insulator. This application does not limit the scope of the invention.

[0033] In some embodiments, the first drift region 12 and the first well region 14 may be formed in the semiconductor substrate 10 and are adjacent to each other. As shown in Figures 1 and 2, in the case of a transistor with two shared drain regions, the LDMOS device 1 may include a first drift region 12 formed between the two first well regions 14.

[0034] In some embodiments, the doping types of the first drift region 12 and the first well region 14 are opposite. For example, the first drift region 12 shown in FIG. 2 can be doped with P-type, while the first well region 14 can be doped with N-type; this application does not impose specific limitations. In P-type doping, a P-type dopant element (also called an acceptor impurity) is introduced into the semiconductor material, so that holes are the majority carriers in the doped semiconductor material, and the semiconductor material exhibits P-type conductivity. Acceptor impurities include, for example, boron (B) and gallium (Ga). In N-type doping, an N-type dopant element (also called a donor impurity) is introduced into the semiconductor material, so that electrons are the majority carriers in the doped semiconductor material, and the semiconductor material exhibits N-type conductivity. Donor impurities include, for example, phosphorus (P) and arsenic (As).

[0035] In some embodiments, the first source-drain region 22 is disposed in the first drift region 12, and the second source-drain region 24 is disposed in the first well region 14. In the two transistor structures with a shared drain region shown in Figures 1 and 2, the first source-drain region 22 is the drain region, and the second source-drain region 24 is the source region. The first source-drain region 22 and the second source-drain region 24 can be formed by doping the material at corresponding positions on the semiconductor substrate 10, and the doping concentration of the first source-drain region 22 and the second source-drain region 24 can be higher than the doping concentration of the first drift region 12 and the first well region 14. In the embodiment of Figure 2, both the first source-drain region 22 and the second source-drain region 24 can be formed by N-type doping, and this application does not impose specific limitations.

[0036] In some embodiments, the embedded field plate unit 30 may include a first shallow trench isolation structure 32 and a conductive layer 34. The first shallow trench isolation structure 32 is disposed in the first drift region 12 and located between the first source-drain region 22 and the second source-drain region 24. The conductive layer 34 is embedded within the first shallow trench isolation structure 32. In the technical solution of this application, a voltage can be applied to the conductive layer 34, which can generate an electric field in the first drift region 12, thereby adjusting the electric field distribution of the first drift region 12 of the LDMOS device 1.

[0037] In the technical solution of this application, a conductive layer 34 is embedded within a first shallow trench isolation structure 32. The conductive layer 34 can form a large-area field plate near the bottom and sides of the first drift region 12 of the first shallow trench isolation structure 32. By applying a voltage, especially a reverse voltage, to the conductive layer 34, the electric field distribution of the first drift region 12 of the LDMOS device 1 can be better adjusted, thereby improving the impact ionization intensity of the first drift region 12. With this configuration, the breakdown voltage of the LDMOS device 1 can be increased without increasing the on-resistance of the LDMOS device 1, thereby improving its withstand voltage performance.

[0038] In some embodiments, the embedded field plate unit 30 further includes a contact hole 36. In Figures 1 and 2, the contact hole 36 is shown in black filled portions. The contact hole 36 is configured to be electrically connected to the conductive layer 34. The contact hole 36, also called a contact plug, is a conductive structure connecting different layers of a semiconductor device. The contact hole 36 may include a hole defined in the semiconductor material and a conductive material filling the hole. The conductive material may be, for example, a metal or polysilicon, etc., and this application does not impose specific limitations. The contact hole 36 can be configured to provide a voltage to the conductive layer 34. The contact hole 36 itself can also generate a corresponding electric field, which can cooperate with the electric field generated by the conductive layer 34 to better adjust the electric field distribution of the first drift region 12 of the LDMOS device 1, thereby enhancing the breakdown voltage performance of the LDMOS device 1.

[0039] In some embodiments, the conductive layer 34 can be in the shape of a thin film. The conductive layer 34 includes a conductive material. In this embodiment, the conductive layer 34 includes TiN material as the conductive material. TiN material has good conductivity, excellent stability and corrosion resistance, and high mechanical hardness, which can ensure the integrity of the conductive layer 34 during the manufacturing process and increase the yield of the LDMOS device 1 of this application. Furthermore, TiN material has excellent diffusion barrier properties and can be used as a stop layer in the fabrication process of vias or plugs. In addition, TiN has good adhesion to the conductive material, which can improve the connection reliability between the conductive layer 34 and the contact hole 36.

[0040] As shown in Figure 2, the first shallow trench isolation structure 32 may include a trench 322 and an insulating material 324 filled in the trench 322. The insulating material 324 may be, for example, SiO2, etc., and this application does not impose specific limitations. Specifically, the first shallow trench isolation structure 32 may be formed based on shallow trench isolation (STI) technology. The trench 322 shown in Figure 2 is a trapezoidal trench 322 that is wide at the top and narrow at the bottom. The trench 322 may also be a rectangular trench 322, an inverted trapezoidal trench 322 that is narrow at the top and wide at the bottom, a U-shaped trench 322 with an arc-shaped bottom, etc., and this application does not impose specific limitations in this regard.

[0041] In some embodiments, the conductive layer 34 is located close to the trench wall of the trench 322 and embedded in the insulating material 324. As shown in FIG2, the conductive layer 34 may extend substantially along the bottom and side walls of the trench 322. Preferably, the conductive layer 34 may completely cover the trench wall of the trench 322, thereby maximizing the extension area of ​​the conductive layer 34 and improving the electric field adjustment efficiency of the first drift region 12 outside the first shallow trench isolation structure 32.

[0042] In some embodiments, as shown in FIG2, the conductive layer 34 may divide the insulating material 324 into a first insulating material portion 3241 adjacent to the trench wall and a second insulating material portion 3242 away from the trench wall. A contact hole 36 may be configured to pass through the second insulating material portion 3242 and connect to the conductive layer 34. The first insulating material portion 3241 may isolate the conductive layer 34 from the first drift region 12, thereby preventing leakage current from the conductive layer 34. Through this arrangement, the first insulating material portion 3241 and the second insulating material portion 3242 may together securely fix the conductive layer 34 within the first shallow trench isolation structure 32.

[0043] In some embodiments, the LDMOS device 1 may further include a gate structure 26. The gate structure 26 may be located between the first source-drain region 22 and the second source-drain region 24, and is located on the surface of a portion of the first drift region 12, a portion of the first well region 14, and a portion of the buried field plate unit 30.

[0044] The gate structure 26 includes a gate insulating layer 262 and a gate electrode layer 264. The gate insulating layer 262 is located between the gate electrode layer 264 and the semiconductor substrate 10. That is, the gate insulating layer 262 may be located on the surface of a portion of the first drift region 12, a portion of the first well region 14, and a portion of the buried field plate unit 30. The gate insulating layer 262 is used to isolate the gate electrode layer 264 and the semiconductor substrate 10. In other words, the gate electrode layer 264 may be located on the surface of a portion of the first drift region 12, a portion of the first well region 14, and a portion of the buried field plate unit 30, and is spaced apart from these portions by the gate insulating layer 262. The gate insulating layer 262 may be formed, for example, of silicon oxide, silicon oxynitride, high-k dielectric, or other insulating materials, and the gate electrode layer 264 may be formed, for example, of polysilicon, metal, or other materials; this application does not impose specific limitations.

[0045] The gate structure 26 also includes a spacer. The spacer may include one or more layers of walls. The spacer includes one or more dielectric layers, such as SiO2, SiN, and SiO2, disposed on both sides of the gate electrode layer 264. The spacer serves to isolate and protect the gate electrode layer 264, which will not be described in detail in this application.

[0046] In some embodiments, the LDMOS device 1 may further include a second shallow trench isolation structure 16. The second shallow trench isolation structure 16 is disposed in the first well region 14 and located on the side of the second source-drain region 24 away from the first source-drain region 22. As shown in FIG2, the second shallow trench isolation structure 16 is disposed on both sides of the transistor in the common drain region to separate the transistor in the common drain region from other parts. The second shallow trench isolation structure 16 can be a conventional shallow trench isolation structure, which will not be described in detail here.

[0047] Referring to FIG3, FIG3 is a flowchart of a fabrication method according to some embodiments of the present application. As shown in FIG3, and in conjunction with FIG2 and FIGS5 to 10, a fabrication method of an LDMOS device 1 according to the present application includes the following steps.

[0048] S31: Fabricate an embedded field plate unit 30 in a semiconductor substrate 10.

[0049] In some embodiments, as described above, the embedded field plate unit 30 includes a first shallow trench isolation structure 32 and a conductive layer 34. The conductive layer 34 is configured to be embedded within the first shallow trench isolation structure 32.

[0050] In the case where the LDMOS device 1 is a transistor with a common drain region, two spaced-apart embedded field plate units 30 can be fabricated in the semiconductor substrate 10.

[0051] In some embodiments, two second shallow trench isolation structures 16 distributed on both sides of the LDMOS device 1 may also be fabricated in the semiconductor substrate 10. The second shallow trench isolation structures 16 can be used to separate the transistors of the LDMOS device 1 from other parts. The second shallow trench isolation structures 16 can be ordinary shallow trench isolation structures, which will not be described in detail here.

[0052] As described above, the semiconductor substrate 10 may be made of semiconductor materials such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III / V or II / VI compound semiconductors, or may include layered substrates such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI) or silicon-germanium-on-insulator. This application does not limit the material used.

[0053] Referring to Figure 4, which is a flowchart illustrating operation S31 in Figure 3 according to some embodiments of this application, the structural schematic diagram of the LDMOS device 1 during the fabrication process of the embedded field plate unit 30 according to an embodiment of this application can be specifically referred to Figures 5-10.

[0054] Referring to Figure 4, the operation of fabricating an embedded field plate unit 30 in a semiconductor substrate 10 includes the following steps.

[0055] S311: Define trench 322 in semiconductor substrate 10.

[0056] In some embodiments, trenches 322 of a predetermined depth are defined in the semiconductor substrate 10 by methods such as photolithography or etching. The depth of the trenches 322 can be set according to specific application scenarios, which will not be elaborated here. The shape of the trenches 322 can be a trapezoidal trench 322 that is wide at the top and narrow at the bottom, or a rectangular trench 322, an inverted trapezoidal trench 322 that is narrow at the top and wide at the bottom, a U-shaped trench 322 with an arc-shaped bottom, etc., and this application does not impose specific limitations on them.

[0057] The following uses a hard mask as an example to introduce the definition method of trench 322. Hard masks have the characteristics of high hardness, strong chemical inertness, high melting point, and high etching selectivity. They can be used to etch deep target depths with very thin thickness, which can improve etching resolution, etching process stability, and product yield.

[0058] First, a hard mask can be formed on the semiconductor substrate 10. Before forming the hard mask, an oxide layer (e.g., SiO2) can be deposited on the semiconductor substrate 10 as a buffer layer. The hard mask may include, for example, silicon nitride (Si3N4), and this application does not limit the specific material of the hard mask.

[0059] Next, the hard mask and / or oxide layer can be patterned to expose the exposure area corresponding to the trench 322. In some embodiments, the exposure location above the trench 322 can be defined on the hard mask using a photolithography process, and then the hard mask and / or oxide layer of the exposure area can be removed by etching.

[0060] Next, the semiconductor substrate 10 beneath the exposed area is etched away to form a trench 322 of a predetermined depth.

[0061] In some embodiments, after etching to form the trench 322, the trench walls, including the sidewalls and bottom wall, of the trench 322 may be oxidized to form a silicon oxide layer. This operation can reduce the defect density at the interface between the trench 322 and the semiconductor substrate 10, thereby reducing the risk of leakage current.

[0062] S312: Fill the trench 322 with the first insulating material portion 3241.

[0063] Referring to Figure 5, which is a first structural schematic diagram of the fabrication process of an embedded field plate unit according to some embodiments of this application, the retained hard mask 3222 is also shown in bold black lines in Figure 5. A layer of silicon oxide or other insulating material can be deposited on the bottom and sidewalls of the trench 322 as a first insulating material portion 3241 by processes such as chemical vapor deposition (CVD).

[0064] The first insulating material portion 3241 can isolate the conductive layer 34 from the first drift region 12, thereby preventing leakage current from the conductive layer 34.

[0065] S313: A conductive layer 34 is formed on the surface of the first insulating material portion 3241.

[0066] In some embodiments, the conductive layer 34 may include TiN material as the conductive material. That is, a TiN material layer is formed on the surface of the first insulating material portion 3241. TiN material has good conductivity, excellent stability and corrosion resistance, and high mechanical hardness, which can ensure the integrity of the conductive layer 34 during the manufacturing process and increase the yield of the LDMOS device 1 of this application. Furthermore, TiN material has excellent diffusion barrier properties and can be used as a barrier layer in the fabrication process of the contact hole 36. In addition, TiN has good adhesion to the conductive material, which can improve the connection reliability between the conductive layer 34 and the hole. This application does not limit the specific type of conductive material of the conductive layer.

[0067] Referring to Figure 6, which is a second structural schematic diagram of the fabrication process of an embedded field plate unit according to some embodiments of this application, a conductive material film 342 can first be deposited on the surface of the LDMOS device 1. The conductive material film 342 can be, for example, a TiN layer. Specifically, a TiN layer can be deposited on the surface of the LDMOS device 1 by methods such as physical vapor deposition or chemical vapor deposition.

[0068] Referring to Figure 7, which is a third structural schematic diagram of the fabrication process of an embedded field plate unit according to some embodiments of this application. As shown in Figure 7, next, photoresist 344 is filled into the trench 322.

[0069] Referring to FIG8, FIG8 is a fourth structural schematic diagram of the fabrication process of an embedded field plate unit according to some embodiments of the present application. As shown in FIG8, next, the conductive material film layer 342 of other parts is etched away, and only the conductive material film layer 342 in the trench 322 is retained as the conductive layer 34 in the embedded field plate unit 30, and then the remaining photoresist 344 is removed.

[0070] S314: Fill the trench 322 with a second insulating material portion 3242.

[0071] Referring to Figure 9, which is a fifth structural schematic diagram of the fabrication process of an embedded field plate unit according to some embodiments of this application, as shown in Figure 9, silicon oxide or other insulating material types can be filled in the trench 322 by processes such as chemical vapor deposition (CVD) to serve as the second insulating material portion 3242. The first insulating material portion 3241 and the second insulating material portion 3242 sandwich the conductive layer 34 in between. The first insulating material portion 3241 and the second insulating material portion 3242 together constitute the insulating material 324 of the first shallow trench isolation structure 32.

[0072] After filling the trench 322 with an insulating material, an insulating material layer covering at least a portion of the surface of the LDMOS device 1 can be further filled. This excess insulating material layer ensures that the surface of the LDMOS device 1 is sufficiently flat, thereby facilitating the subsequent mechanical chemical polishing (CMP) process.

[0073] S315: Remove the insulating material layer and hard mask 3222 on the surface of the semiconductor substrate 10 to expose the embedded field plate unit 30.

[0074] In some embodiments, an excess insulating material layer on the surface of the semiconductor substrate 10 is removed by a chemical mechanical polishing (CMP) process. The CMP process may utilize the aforementioned hard mask 3222 as a stop layer. Embodiments of this application may further remove the hard mask 3222 and / or oxide layer on the surface of the semiconductor substrate 10 by etching or other methods.

[0075] Referring to Figure 10, which is a sixth structural schematic diagram of the fabrication process of an embedded field plate unit according to some embodiments of this application, as shown in Figure 10, the fabrication of the first shallow trench isolation structure 32 is completed, and the excess insulating material layer, hard mask 3222 and / or oxide layer on the surface of the semiconductor substrate 10 has been completely removed.

[0076] S32: By doping, a first drift region 12 and a first well region 14 adjacent to each other are formed in the semiconductor substrate 10.

[0077] The position of the first drift region 12 can correspond to the position of the embedded field plate unit 30. Specifically, the first drift region 12 can be configured as a continuous region surrounding and adjacent to the embedded field plate unit 30. In other words, the embedded field plate unit 30 is disposed in the first drift region 12.

[0078] Referring to Figure 2, in the case where the LDMOS device 1 is a transistor with two shared drain regions and there are two spaced-apart buried field plate units 30, the first drift region 12 can be configured as a continuous region surrounding and adjacent to the two spaced-apart buried field plate units 30.

[0079] In some embodiments, the first drift region 12 and the first well region 14 have opposite doping types. For example, the first drift region 12 shown in FIG2 may be P-type and the first well region 14 may be N-type; this application does not impose any specific limitations.

[0080] In the case where the LDMOS device 1 is a transistor with two shared drain regions, the LDMOS device 1 may include a first drift region 12 formed between the two first well regions 14.

[0081] In some embodiments, where two second shallow trench isolation structures 16 are present, the first well region 14 and the first drift region 12 may be formed between the two second shallow trench isolation structures 16.

[0082] S33: A first source-drain region 22 is formed by doping in the first drift region 12, and a second source-drain region 24 is formed by doping in the first well region 14. The first source-drain region 22 is located on the side of the buried field plate unit 30 away from the first well region 14.

[0083] In some embodiments, the fabrication method of this application may further include fabricating a gate structure 26. The gate structure 26 is located between the first source-drain region 22 and the second source-drain region 24, and is located on the surface of a portion of the first drift region 12, a portion of the first well region 14, and a portion of the buried field plate unit 30. The gate structure 26 can be fabricated by a gate-before process or a gate-after process, which is not specifically limited in this application and will not be elaborated here.

[0084] S34: Create a contact hole 36 that connects to the conductive layer 34.

[0085] In some embodiments, a contact window may be formed through the second insulating material portion 3242 to expose the conductive layer 34, and the contact window may be filled with conductive material to form a contact hole 36. The conductive material may be, for example, a metal or other conductive material, and this application does not impose any specific limitations.

[0086] In some embodiments, an interlayer dielectric layer (not shown) may be formed covering the gate structure 26. A contact window may be formed through the interlayer dielectric layer and the second insulating material portion 3242, and the contact window may be filled with a conductive material to form a contact hole 36.

[0087] When forming the contact window, the conductive layer 34 of the embedded field plate unit 30 can be used as a stop layer or a barrier layer. TiN material has excellent diffusion barrier properties and is suitable as a stop layer.

[0088] The contact hole 36 can be configured to connect the conductive layer 34 to a control terminal. The control terminal can be configured to apply a predetermined voltage to the conductive layer 34 to adjust the electric field distribution around the first drift region 12 of the embedded field plate unit 30, thereby enhancing the durability of the LDMOS device 1.

[0089] Embodiments of this application provide a method for fabricating an LDMOS device 1. The LDMOS device 1 includes an embedded field plate unit 30 disposed in a first drift region 12. The embedded field plate unit 30 includes a conductive layer 34 embedded within a first shallow trench isolation structure 32. The conductive layer 34 can form a large-area field plate near the bottom and sidewalls of the first drift region 12 of the first drift region 12. By applying a voltage, especially a reverse voltage, to the conductive layer 34, the electric field distribution of the first drift region 12 of the LDMOS device 1 can be better adjusted, thereby increasing the impact ionization intensity of the first drift region 12. With this configuration, the breakdown voltage of the LDMOS device 1 can be increased without increasing its on-resistance, thereby improving its breakdown voltage performance.

[0090] Referring to Figure 11, Figure 11 shows the TCAD simulation results of an LDMOS device 1 according to some embodiments of this application. Those skilled in the art should know that TCAD (Technology Computer-Aided Design) is a computer-aided design tool for the design and analysis of semiconductor devices, which will not be described in detail here.

[0091] Specifically, Figure 11 shows the IdVd curve of LDMOS device 1. The IdVd curve is also called the drain current-voltage curve. The horizontal axis of the curve is Vd (Drain-Source Voltage), in volts (V). The vertical axis of the curve is Id (Drain Current), in amperes (A). Figure 11 shows three IdVd curves, corresponding to the IdVd curves under three conditions: reference voltage (i.e., no reverse voltage applied to the buried field plate cell 30), a 5V reverse voltage applied to the buried field plate cell 30, and a 10V reverse voltage applied to the buried field plate cell 30. The reverse voltage is the voltage with the opposite polarity to the voltage at the drain terminal of the transistor, also called the reverse bias voltage. For example, when the voltage at the drain terminal is positive, the reverse voltage is negative, and vice versa.

[0092] As shown in Figure 11, when the drain voltage Vd is the same, the larger the reverse voltage, the smaller the drain current Id.

[0093] The breakdown voltage of LDMOS device 1 is characterized by the voltage threshold at which the drain current rapidly increases when a certain voltage is applied between the drain and source of LDMOS device 1. In Figure 11, without applying a reverse voltage (reference voltage curve) to the buried field plate cell 30, the breakdown voltage corresponding to the rapid increase in drain current is 30.6V. When a reverse voltage of 10V is applied to the buried field plate cell 30, the breakdown voltage corresponding to the rapid increase in drain current is 33.1V. It can be seen that the latter breakdown voltage is 8.2% higher than the former. Therefore, applying a reverse voltage to the buried field plate cell 30 can effectively increase the breakdown voltage of LDMOS device 1.

[0094] Referring to Figures 12 to 15, Figure 12 shows the simulation results of the impact ionization intensity of the LDMOS device 1 without the embedded field plate unit 30. Figure 13 shows the simulation results of the impact ionization intensity of the LDMOS device 1 when a reverse voltage of 10V is applied to the embedded field plate unit 30 according to some embodiments of this application. Figure 14 shows the simulation results of the current density of the LDMOS device 1 without the embedded field plate unit 30. Figure 15 shows the simulation results of the current density of the LDMOS device 1 when a reverse voltage of 10V is applied to the embedded field plate unit 30 according to some embodiments of this application.

[0095] In Figures 12-15, the drain voltage Vd (or reference drain voltage, shown as Ref@Vd in the figure) is 25V, at which point LDMOS device 1 is not broken down.

[0096] As shown in Figure 12, when the embedded field plate unit 30 is not provided, there is a region with high collisional ionization intensity in the first drift region 12 adjacent to the first shallow trench isolation structure 32, especially at the corner of the first shallow trench isolation structure 32. As shown in Figure 13, when the embedded field plate unit 30 is provided and a reverse voltage of 10V is applied, the high collisional ionization region near the first shallow trench isolation structure 32 is significantly eliminated.

[0097] As shown in Figure 14, when the embedded field plate unit 30 is not provided, there is a region with high current density in the first drift region 12 adjacent to the first shallow trench isolation structure 32, especially at the corner of the first shallow trench isolation structure 32. As shown in Figure 15, when the embedded field plate unit 30 is provided and a reverse voltage of 10V is applied, the high current density region near the first shallow trench isolation structure 32 is significantly eliminated.

[0098] In summary, as can be seen from Figures 12-15, when an embedded field plate unit 30 is provided in the LDMOS device 1 and a reverse voltage is applied, the electric field formed by the conductive layer 34 and the contact hole 36 can effectively reduce the collision ionization intensity and current density in the surrounding first drift region 12, thereby enhancing the breakdown voltage of the first drift region 12 and improving the durability of the LDMOS device 1. The technical effect of the technical solution of this application is significant.

[0099] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

Claims

1. An LDMOS device, characterized in that, include: Semiconductor substrate; A first drift region and a first well region are formed in the semiconductor substrate and are adjacent to each other; The first source-drain region is set in the first drift region; The second source-drain region is set in the first well region; An embedded field plate unit includes: a first shallow trench isolation structure disposed in a first drift region and located between a first source-drain region and a second source-drain region; a conductive layer comprising TiN material embedded within the first shallow trench isolation structure; and a contact hole configured to connect to the conductive layer, wherein the first shallow trench isolation structure includes a trench and an insulating material filling the trench; the conductive layer includes a first portion extending opposite to the bottom wall of the trench and a second portion extending opposite to the side wall of the trench, the conductive layer being embedded in the insulating material, the first portion and the second portion of the conductive layer dividing the insulating material into a first insulating material portion adjacent to the trench wall and a second insulating material portion away from the trench wall; the contact hole being configured to connect to the conductive layer through the second insulating material portion; and the conductive layer being configured as a barrier layer for the contact hole.

2. The LDMOS device according to claim 1, characterized in that, A gate structure is located between the first source-drain region and the second source-drain region, and on a portion of the first drift region, a portion of the first well region, and a portion of the buried field plate unit surface.

3. The LDMOS device according to claim 1, characterized in that, The first drift region and the first well region have opposite doping types.

4. The LDMOS device according to claim 1, characterized in that, Also includes: The second shallow trench isolation structure is disposed in the first well region and located on the side of the second source-drain region away from the first source-drain region.

5. A method for fabricating an LDMOS device, characterized in that, include: An embedded field plate unit is fabricated in a semiconductor substrate, wherein the embedded field plate unit includes: a first shallow trench isolation structure, and a conductive layer embedded within the first shallow trench isolation structure; by doping, a first drift region and a first well region are formed adjacent to each other in the semiconductor substrate, wherein the first drift region is configured as a continuous region surrounding and adjacent to the embedded field plate unit; a first source-drain region is formed by doping in the first drift region, and a second source-drain region is formed by doping in the first well region, wherein the first source-drain region is located on the side of the embedded field plate unit away from the first well region; and a contact hole connected to the conductive layer is fabricated; wherein fabricating the embedded field plate unit in the semiconductor substrate includes: in the semiconductor substrate... The method includes defining a trench in a conductor substrate; filling the trench with a first insulating material portion; forming the conductive layer on the surface of the first insulating material portion; and filling the trench with a second insulating material portion; wherein forming the conductive layer on the surface of the first insulating material portion includes forming a TiN material layer on the surface of the first insulating material portion; the method further includes forming a contact window that exposes the conductive layer through the second insulating material portion; and filling the contact window with conductive material to form a contact hole; wherein the conductive layer is configured as a barrier layer for the contact hole, and wherein the conductive layer includes a first portion extending opposite to the bottom wall of the trench and a second portion extending opposite to the side wall of the trench.

6. The method according to claim 5, characterized in that, Also includes: A gate structure is fabricated, wherein the gate structure is located between the first source-drain region and the second source-drain region, and is located on the surface of a portion of the first drift region, a portion of the first well region, and a portion of the buried field plate unit.

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