Semiconductor device

Abstract

A semiconductor device includes: a substrate having a main surface and a back surface facing the main surface; a first transistor (35a) provided on the main surface in the active region and including a first source electrode, a first drain electrode, and a first gate electrode disposed between the first source electrode and the first drain electrode in the first direction; a second transistor (35c) provided on the main surface, the second transistor (35c) including a second source electrode provided within the first source electrode when viewed from the second direction and electrically connected to the first source electrode, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode disposed between the second source electrode and the second drain electrode in the first direction; a first gate wiring (24) which is provided on the main surface, has the second source electrode disposed between the first gate wiring (24) and the second gate electrode, is provided inside the first source electrode when viewed from the second direction, and is electrically connected to the first gate electrode; and a back surface metal layer provided on the back surface and electrically connected to the first source electrode via a via hole (20a) penetrating the substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] It is known that in a field effect transistor (FET) having finger-shaped source electrodes, gate electrodes, and drain electrodes, a plurality of unit FETs having source electrodes, gate electrodes, and drain electrodes are arranged along the extending direction of the electrodes (for example, Patent Documents 1 and 2).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2002-299351

[0006] Patent Document 2: U.S. Patent Application Publication No. 2017 / 0271329

[0007] In Patent Document 1, by configuring a plurality of unit FETs along the extension direction of the electrode, the width of the gate electrode in the unit FET can be shortened. Thus, the gate resistance can be suppressed. However, the source electrode and the gate wiring overlap when viewed from above, so the gate / source parasitic capacitance increases and the performance deteriorates. Summary of the invention

[0008] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to suppress performance degradation.

[0009] One embodiment of the present disclosure is a semiconductor device, comprising: a substrate having a main surface and a back surface opposite to the main surface; a first transistor provided on the main surface at an active region of the substrate, comprising a first source electrode, a first drain electrode, and a first gate electrode arranged between the first source electrode and the first drain electrode in a first direction; a second transistor provided on the main surface, comprising a second source electrode provided in the first source electrode and electrically connected to the first source electrode when viewed from a second direction intersecting the first direction, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode arranged between the second source electrode and the second drain electrode in the first direction; a first gate wiring provided on the main surface, so that the second source electrode is arranged between the first gate wiring and the second gate electrode, provided in the first source electrode when viewed from the second direction, and electrically connected to the first gate electrode; and a back metal layer provided on the back surface, electrically connected to the first source electrode via a via hole penetrating the substrate, wherein a first end of the via hole away from the second transistor is farther from the second transistor than a second end of the active region in a region where the first gate electrode is provided, away from the second transistor, when viewed from the first direction.

[0010] Effects of the Invention

[0011] According to the present disclosure, performance degradation can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 1 is a top view of the semiconductor device of Example 1.

[0013] Figure 2 yes Figure 1 A-A section view.

[0014] Figure 3 yes Figure 1 B-B section view.

[0015] Figure 4 yes Figure 1 C-C section view.

[0016] Figure 5 yes Figure 1 D-D section view.

[0017] Figure 6 3 is a top view of the semiconductor device of Comparative Example 1.

[0018] Figure 7 This is an enlarged top view of the semiconductor device of Example 1.

[0019] Figure 8 It is a top view of a semiconductor device according to Modification 1 of Embodiment 1.

[0020] Fig. 9 It is a top view of the semiconductor device of Example 2.

[0021] Fig.10 This is an enlarged top view of the semiconductor device of Example 2.

[0022] Fig.11 It is a top view of a semiconductor device according to a first variation of the second embodiment.

[0023] Description of Reference Numerals

[0024] 10, 10a: substrate; 10b: semiconductor layer; 11a, 11c, 11d: active region; 12, 12a, 12c, 12d: source electrode; 13: inactive region; 14, 14a, 14b, 14c, 14d: gate electrode; 16, 16a, 16b, 16c, 16d: drain electrode; 24b: wiring layer; 20a: via hole; 22, 22a, 22b, 22c: source wiring; 24, 25a, 2 5b: gate wiring; 24a: gate metal layer; 26a, 26b: drain wiring; 28, 28a: metal layer; 30: insulating layer; 34: gate bus; 35, 35a, 35b, 35c, 35d: transistor; 36: drain bus; 38, 38a, 38b: transistor group; 50: main surface; 52: back surface; 54: part; 55: end edge; 100, 102, 104, 106, 110: semiconductor device. DETAILED DESCRIPTION

[0025] [Description of Embodiments of the Present Disclosure]

[0026] First, the contents of the embodiments of the present disclosure will be listed and described.

[0027] (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate having a main surface and a back surface opposite to the main surface; a first transistor provided on the main surface at an active region of the substrate, comprising a first source electrode, a first drain electrode, and a first gate electrode arranged between the first source electrode and the first drain electrode in a first direction; a second transistor provided on the main surface, comprising a second source electrode provided in the first source electrode and electrically connected to the first source electrode when viewed from a second direction intersecting the first direction, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode arranged between the second source electrode and the second drain electrode in the first direction; a first gate wiring provided on the main surface, such that the second source electrode is arranged between the first gate wiring and the second gate electrode, provided in the first source electrode and electrically connected to the first gate electrode when viewed from the second direction; and a back metal layer provided on the back surface, electrically connected to the first source electrode via a via hole penetrating the substrate, wherein a first end of the via hole, which is away from the second transistor, is farther from the second transistor than a second end of the active region in a region where the first gate electrode is provided, which is away from the second transistor, when viewed from the first direction. This can suppress source inductance and thus suppress performance degradation.

[0028] (2) In the above (1), the via hole may be provided in the first source electrode when viewed from the thickness direction of the substrate. This increases the contact area between the via hole and the first source electrode, and can reduce source inductance and source resistance.

[0029] (3) In the above (2), the semiconductor device may include: a drain bus provided on the main surface so that the first transistor is arranged between the drain bus and the second transistor; and a drain wiring connecting the first drain electrode and the second drain electrode to the drain bus, wherein when viewed from the first direction, the distance between the first source electrode at the third end away from the second transistor and the drain wiring is greater than the distance between the first source electrode and the drain wiring at the second end. Thus, drain / source parasitic capacitance can be suppressed.

[0030] (4) In the above (3), the third end of the first source electrode may be provided on an inactive region of the substrate. This can suppress drain / source parasitic capacitance.

[0031] (5) In the above (3) or (4), the distance between the first source electrode and the drain wiring may increase from the second end to the third end. This can suppress drain / source parasitic capacitance.

[0032] (6) In any of the above (1) to (5), the gate width of the first transistor may be greater than or equal to 0.9 times and less than or equal to 1.1 times the gate width of the second transistor. This makes it possible to make transistor performance uniform.

[0033] (7) In any one of the above (1) to (6), the first gate electrode and the second gate electrode may be separated from each other between the first transistor and the second transistor. This can suppress performance degradation.

[0034] (8) In any one of the above (1) to (6), the first gate electrode and the second gate electrode may be connected between the first transistor and the second transistor. This can reduce gate resistance.

[0035] (9) In any one of the above (1) to (8), the semiconductor device may include: a third transistor provided on the main surface, including: the first source electrode; a third drain electrode, such that the first source electrode is arranged between the third drain electrode and the first gate electrode; and a third gate electrode, such that the first source electrode is arranged between the first source electrode and the third drain electrode in the first direction and is electrically connected to the first gate wiring; and a fourth transistor provided on the main surface, including: a third source electrode, such that the first gate wiring is arranged between the third source electrode and the second source electrode, provided inside the first source electrode when viewed from the second direction and is electrically connected to the first source electrode; a fourth drain electrode, such that the third source electrode is arranged between the fourth drain electrode and the first gate wiring; and a fourth gate electrode, such that the third source electrode is arranged between the fourth drain electrode and the first gate wiring, in the first direction. Thus, transistors can be arranged in the first direction and the second direction.

[0036] (10) In any one of the above (1) to (9), the semiconductor device may include: a source wiring provided on the main surface and electrically connecting the first source electrode and the second source electrode; and a second gate wiring provided on the main surface and electrically connecting the first gate wiring and the first gate electrode. Thus, the first gate electrode and the gate wiring can be electrically connected.

[0037] (11) In any one of the above (1) to (10), the semiconductor device may include: a gate bus provided on the main surface, connected to the second gate electrode and the first gate wiring; and a drain bus provided on the main surface, so that the first transistor and the second transistor are arranged between the drain bus and the gate bus in the second direction, and electrically connected to the first drain electrode and the second drain electrode. Thus, a gate potential can be provided from the gate bus to the gate electrode, and a drain potential can be provided from the drain bus to the drain electrode.

[0038] [Details of the embodiments of the present disclosure]

[0039] Hereinafter, specific examples of semiconductor devices according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0040] [Example 1]

[0041] The following description will take as an example a semiconductor device of an amplifier for amplifying a high-frequency signal of, for example, 0.5 GHz to 10 GHz in a mobile communication base station. Figure 1 1 is a top view of the semiconductor device of Example 1. Figure 2 to Figure 5 They are Figure 1 A-A cross-sectional view, B-B cross-sectional view, C-C cross-sectional view and D-D cross-sectional view. The thickness direction of the substrate 10 is set to the Z direction, the extension direction of the finger-shaped source electrode 12, the gate electrode 14 and the drain electrode 16 is set to the Y direction (a second direction intersecting the first direction), and the arrangement direction of the source electrode 12, the gate electrode 14 and the drain electrode 16 is set to the X direction (the first direction).

[0042] exist Figure 1 In the top view, when the source electrode 12 and the drain electrode 16 overlap with the source wiring 22 and the drain wiring 26, it is difficult to observe. Therefore, the thick dotted line diagram that sees through the source wiring 22 and the drain wiring 26 and only shows the outer periphery of the source wiring 22 and the drain wiring 26 is shown inside the source electrode 12 and the drain electrode 16.

[0043] In each figure, the active region 11, the source electrode 12, the gate electrode 14, the drain electrode 16, the source wiring 22, the drain wiring 26, and the transistor 35 (unit FET) represent general elements, and the active regions 11a, 11c, 11d, the source electrodes 12a, 12c, 12d, the gate electrodes 14a to 14d, the drain electrodes 16a to 16d, the source wirings 22a to 22c, the drain wirings 26a and 26b, and the transistors 35a to 35d represent specific elements included in the general elements. Hereinafter, the transistors 35a to 35d will be described mainly using the active regions 11a, 11c, 11d, the source electrodes 12a, 12c, 12d, the gate electrodes 14a to 14d, the drain electrodes 16a to 16d, the source wirings 22a to 22c, and the drain wirings 26a and 26b.

[0044] like Figure 1 to Figure 5 As shown, in the semiconductor device 100 of the first embodiment, the substrate 10 has a main surface 50 and a back surface 52 opposite to the main surface 50. A plurality of transistors 35a to 35d are provided on the main surface of the substrate 10. The transistors 35, 35a to 35d arranged in the Y direction form transistor groups 38, 38a and 38b. In the Y direction, the drain bus 36 and the gate bus 34 are provided on the main surface 50, with the transistor groups 38, 38a and 38b interposed therebetween.

[0045] The transistors 35 closest to the drain bus 36 are transistors 35a and 35b. The transistors 35 closer to the gate bus 34 than the transistors 35a and 35b are transistors 35c and 35d. The transistor group 38a includes one transistor 35a and three transistors 35c. The transistor group 38b includes one transistor 35b and three transistors 35d. The number of transistors 35c is one or more, and the number of transistors 35d is one or more.

[0046] The substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In the XY plane parallel to the X direction and the Y direction, the region of the semiconductor layer 10b deactivated by ion implantation or the like is the inactive region 13, and the region not deactivated (the region where current flows when the transistor is in the on state) is the active region 11a, 11c and 11d. The active region 11a extends in the X direction. The active regions 11c and 11d are arranged in the X direction. Three active regions 11c are arranged in the Y direction, and three active regions 11d are arranged in the Y direction. Transistors 35a and 35b are provided in the active region 11a. Transistors 35c and 35d are provided in the active regions 11c and 11d, respectively.

[0047] The transistor 35a (first transistor) includes a source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode). The gate electrode 14a is arranged between the source electrode 12a and the drain electrode 16a in the X direction. The source electrode 12a, the gate electrode 14a, and the drain electrode 16a are arranged in sequence along the + direction of the X direction.

[0048] The transistor 35b (third transistor) includes a source electrode 12a, a gate electrode 14b (third gate electrode), and a drain electrode 16b (third drain electrode). The source electrode 12a is disposed between the drain electrode 16b and the gate electrode 14a. The gate electrode 14b is disposed between the source electrode 12a and the drain electrode 16b in the X direction. The source electrode 12a, the gate electrode 14b, and the drain electrode 16b are arranged in sequence along the - direction of the X direction. The transistors 35a and 35b share the source electrode 12a.

[0049] The transistor 35c (second transistor) includes a source electrode 12c (second source electrode), a gate electrode 14c (second gate electrode), and a drain electrode 16c (second drain electrode). The gate electrode 14c is arranged between the source electrode 12c and the drain electrode 16c in the X direction. The source electrode 12c is arranged inside the source electrode 12a when viewed from the Y direction. That is, when viewed from the Y direction, the source electrode 12c is not arranged outside the source electrode 12a. A plurality of source electrodes 12c overlap each other when viewed from the Y direction. A plurality of drain electrodes 16c overlap each other when viewed from the Y direction. The source electrode 12c, the gate electrode 14c, and the drain electrode 16c are arranged in sequence along the + direction of the X direction.

[0050] The transistor 35d (fourth transistor) includes a source electrode 12d (third source electrode), a gate electrode 14d (fourth gate electrode), and a drain electrode 16d (fourth drain electrode). A gate wiring 24 is arranged between the source electrode 12d and the source electrode 12c, and the source electrode 12d is arranged inside the source electrode 12a when viewed from the Y direction. That is, when viewed from the Y direction, the source electrode 12d is not arranged outside the source electrode 12a. A plurality of source electrodes 12d overlap each other when viewed from the Y direction. A plurality of drain electrodes 16d overlap each other when viewed from the Y direction. A gate electrode 14d is arranged between the source electrode 12d and the drain electrode 16d in the X direction. The source electrode 12d, the gate electrode 14d, and the drain electrode 16d are arranged in sequence along the - direction of the X direction.

[0051] A source wiring 22c is provided in contact with the source electrode 12a. When viewed from the X direction, the + end of the source electrode 12a in the Y direction is located farther from the transistors 35c and 35d than the + ends of the gate electrodes 14a and 14b in the Y direction. When viewed from the X direction, a portion 54 of the source electrode 12a that is farther from the transistors 35c and 35d than the gate electrodes 14a and 14b is provided on the inactive region 13.

[0052] A source wiring 22a (first source wiring) is provided in contact with the source electrode 12c. The source wiring 22a extends in the Y direction, electrically connects the plurality of source electrodes 12c to each other, and electrically connects the plurality of source electrodes 12c to the source wiring 22c. A source wiring 22b (second source wiring) is provided in contact with the source electrode 12d. The source wiring 22b extends in the Y direction, electrically connects the plurality of source electrodes 12d to each other, and electrically connects the plurality of source electrodes 12d to the source wiring 22c.

[0053] A drain wiring 26a is provided in contact with the drain electrodes 16a and 16c. The drain wiring 26a extends in the Y direction, electrically connects the plurality of drain electrodes 16a and 16c to each other, and electrically connects the plurality of drain electrodes 16a and 16c to the drain bus 36. A drain wiring 26b is provided in contact with the drain electrodes 16b and 16d. The drain wiring 26b extends in the Y direction, electrically connects the plurality of drain electrodes 16b and 16d to each other, and electrically connects the plurality of drain electrodes 16b and 16d to the drain bus 36.

[0054] A gate wiring 24 (first gate wiring) extending in the Y direction is provided on the inactive region 13 between the transistor 35c and the transistor 35d. The gate wiring 24 is provided inside the source electrode 12a when viewed from the Y direction. That is, the gate wiring 24 is not provided outside the source electrode 12a when viewed from the Y direction. The gate wiring 24 is electrically connected to the gate bus 34. The gate wiring 24 includes a gate metal layer 24a provided on the substrate 10 and a wiring layer 24b provided in contact with the gate metal layer 24a.

[0055] A gate wiring 25a (second gate wiring) extending in the X direction is provided on the inactive region 13 between the transistor 35a and the transistor 35c and between the transistors 35c. The gate wiring 25a crosses the source wiring 22a without contact, and electrically connects the gate wiring 24 to the gate electrodes 14a and 14c. A gate wiring 25b (third gate wiring) extending in the X direction is provided on the inactive region 13 between the transistor 35b and the transistor 35d and between the transistors 35d. The gate wiring 25b crosses the source wiring 22b without contact, and electrically connects the gate wiring 24 to the gate electrodes 14b and 14d. Thus, the gate electrodes 14a to 14d are electrically connected to the gate bus 34 via the gate wirings 24, 25a, and 25b. The gate electrodes 14c and 14d of the transistors 35c and 35d closest to the gate bus 34 are directly electrically connected to the gate bus 34 without the gate wirings 24, 25a, and 25b.

[0056] The via hole 20a penetrates the substrate 10, and the via hole 20a is arranged in a manner that it spans from the source electrode 12a on the active area 11a to the source electrode 12a on the inactive area 13. A metal layer 28 is provided on the back surface 52 of the substrate 10. A metal layer 28a is provided on the inner surface of the via hole 20a. Thus, the metal layer 28 (back metal layer) is electrically connected to the source electrode 12a via the via hole 20a. The planar shape of the via hole 20a can be an ellipse, an oblong, a rounded quadrilateral or a circle. The source electrodes 12c and 12d are not connected to the via hole 20a.

[0057] The source potential (for example, a reference potential such as a ground potential) is provided from the metal layer 28 to the source electrode 12a via the metal layer 28a in the via 20a. Furthermore, the source potential is provided from the source wiring 22c to the source electrodes 12c and 12d via the source wirings 22a and 22b, respectively. The gate potential (for example, a high-frequency signal and a gate bias voltage) is provided from the gate bus 34 to the gate electrodes 14a to 14d via the gate wirings 24, 25a, and 25b. The drain bias voltage is provided from the drain bus 36 to the drain electrodes 16a to 16d via the drain wirings 26a and 26b. The high-frequency signal amplified in each transistor 35a to 35d is output from the drain wirings 26a and 26b to the drain bus 36.

[0058] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the transistors 35a to 35d are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs)-based semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer. The semiconductor device 100 may be a silicon semiconductor device such as LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0059] The source electrodes 12a, 12c and 12d and the drain electrodes 16a to 16d are metal films, for example, titanium films and aluminum films from the substrate 10 side. The gate electrodes 14a to 14d and the gate metal layer 24a are metal films, for example, nickel films and gold films from the substrate 10 side. The source wirings 22a to 22c, the drain wirings 26a and 26b, the wiring layer 24b, the metal layers 28 and 28a, and the drain bus 36 are, for example, gold layers, copper layers, or aluminum layers. The insulating layer 30 provided on the substrate 10 so as to cover the transistors 35a to 35d is, for example, an organic insulating layer such as a polyimide layer or a BCB (Benzocyclobutene) layer.

[0060] The width of the source electrode 12a in the X direction is, for example, 50 μm to 150 μm. The width of the source electrodes 12c and 12d in the X direction is, for example, 5 μm to 20 μm. The gate length of the gate electrodes 14a to 14d in the X direction is, for example, 0.25 μm to 2 μm. The width of the drain electrodes 16a to 16d in the X direction is, for example, 5 μm to 150 μm. The width of the gate wiring 24 in the X direction is, for example, 5 μm to 20 μm. The width of the gate wiring 25a and 25b in the Y direction is, for example, 3 μm to 20 μm. The gate width of the transistors 35a to 35d in the Y direction is, for example, 100 μm to 400 μm. The width of the via 20a in the X direction is, for example, 10 μm to 60 μm.

[0061] The width of the source wirings 22a to 22c and the drain wirings 26a and 26b in the X direction is the same as, slightly smaller than, or slightly larger than the width of the source electrodes 12a, 12c, 12d and the drain electrodes 16a to 16d in the X direction. The thickness of the source wirings 22a to 22c and the drain wirings 26a and 26b is, for example, 1 μm to 20 μm.

[0062] [Comparative Example 1]

[0063] Figure 6 is a top view of the semiconductor device of Comparative Example 1. Figure 6 As shown, in the semiconductor device 110 of Comparative Example 1, the + end of the source electrode 12a in the Y direction is located at substantially the same position as the + end of the active region 11a in the Y direction when viewed from the X direction.

[0064] In Comparative Example 1, the gate potential is provided to the gate electrodes 14a to 14d via the gate wirings 24, 25a, and 25b, so that the gate resistance can be reduced. The gate wiring 24 does not overlap the source electrodes 12c and 12d in a plan view, so that the gate / source parasitic capacitance can be reduced compared to Patent Documents 1 and 2.

[0065] In the plurality of transistors 35a to 35d, the widths of the active regions 11a, 11c, and 11d in the Y direction correspond to the gate widths Wg1 to Wg4. If the gate widths Wg1 to Wg4 are different from each other, the operation of the plurality of transistors 35a to 35d becomes uneven, which deteriorates the high frequency performance of the semiconductor device 110. Therefore, the gate widths Wg1 to Wg4 are made substantially equal.

[0066] By reducing the gate width Wg1 to Wg4, the gate resistance becomes lower, and high-frequency performance such as gain can be improved. However, if the gate width Wg1 to Wg4 is evenly reduced, the width of the source electrode 12a in the Y direction will become smaller. As a result, the width of the via 20a in the Y direction also becomes smaller. Therefore, the source inductance and source resistance between the metal layer 28 and the source electrode 12a through the via 20a become larger. As a result, the gain decreases. In this way, even if you want to reduce the gate resistance to increase the gain, the source inductance becomes larger, making it difficult to increase the gain.

[0067] [Description of Example 1]

[0068] Figure 7 1 is an enlarged top view of the semiconductor device of Example 1, in which the vicinity of the source electrode 12a is enlarged. The source electrode 12a, source wiring 22c and via 20a (solid line) in Example 1 are overlapped with the source electrode 12a, source wiring 22c and via 20a (dashed line) in Comparative Example 1.

[0069] like Figure 7As shown, in Comparative Example 1, the width of the source electrode 12a and the source wiring 22a in the Y direction is approximately the gate width Wg1. In contrast, in Example 1, the width W1 of the source electrode 12a and the source wiring 22a in the Y direction is larger than the gate width Wg1 by a width W2. The width W2 corresponds to the distance between the positive end of the active region 11a in the Y direction and the positive end of the source electrode 12a in the Y direction.

[0070] Thus, the width W3 of the via 20a in the Y direction of Example 1 can be larger than the width W5 of the via 20a in the Y direction of Comparative Example 1 by about the width W2. Thus, in Example 1, when viewed from the X direction, the end Y1 (first end) of the via 20a away from the transistor 35c is farther from the transistor 35c than the end Y2 (second end) of the active area 11a in the area where the gate electrode 14a is provided away from the transistor 35c. In other words, the via 20a spans both the active area 11a (first active area) and the inactive area 13 of the substrate 10 that is not activated. Thus, the area of ​​the via 20a can be made larger than that of Comparative Example 1. Thus, by reducing the gate widths Wg1 to Wg4, the gate resistance can be suppressed and the source inductance can be suppressed. Thus, the high-frequency performance such as the gain of the semiconductor device can be suppressed from being deteriorated.

[0071] From the perspective of increasing the area of ​​the via 20a, the width W4 of the ends Y1 and Y2 can be set to be 0.1 times or more of the width W3 of the via 20a in the Y direction, and can be set to be 0.2 times or more of the width W3. From the perspective of miniaturization, the width W4 can be set to be 0.5 times or less of the width W2.

[0072] From the perspective of increasing the area of ​​the via hole 20a, the end of the source electrode 12a in the Y direction and the width W6 of the end of the via hole 20a can be set to be less than 0.3 times the width W1 of the source electrode 12a in the Y direction, and can be set to be less than 0.2 times the width W1. The end and width of the via hole 20a are determined by the portion where the via hole 20a is in contact with the main surface 50 of the substrate 10.

[0073] From the viewpoint of making the high frequency performance of transistors 35a to 35d uniform, the gate width Wg1 of transistor 35a can be set to be 0.9 times or more and 1.1 times or less of the gate width Wg2 of transistor 35c, and can be set to be 0.95 times or more and 1.05 times or less of the gate width Wg2. Gate widths Wg1 to Wg4 can be equal to each other in terms of manufacturing error.

[0074] like Figure 1 to Figure 5 As shown, by providing the transistors 35b and 35d, the transistors 35 can be arranged in the X direction and the Y direction.

[0075] The source wiring 22a electrically connects the source electrodes 12a and 12c. The gate wiring 25a electrically connects the gate wiring 24 and the gate electrode 14a. Thus, the gate electrode 14a and the gate wiring 24 can be electrically connected.

[0076] A gate bus bar 34 electrically connected to the gate wiring 24 and a drain bus bar 36 electrically connected to the drain wirings 26a and 26b are provided. Thus, a gate potential can be supplied from the gate bus bar 34 to the gate electrodes 14a to 14d, and a drain potential can be supplied from the drain bus bar 36 to the drain electrodes 16a to 16d.

[0077] [Variation 1 of Example 1]

[0078] Figure 8 FIG. 1 is a top view of a semiconductor device according to a first variation of the first embodiment. Figure 8 As shown, in the semiconductor device 102 of the first modification of the first embodiment, the gate electrodes 14 in the transistors 35 of the same transistor group 38 are connected as a whole. The gate electrodes 14a and 14c of the transistor group 38a are connected as a whole. The gate electrodes 14b and 14d of the transistor group 38b are connected as a whole. The other structures are the same as those of the first embodiment, and the description is omitted.

[0079] [Example 2]

[0080] Fig. 9 FIG. 2 is a top view of the semiconductor device of Example 2. Fig. 9 As shown, in the semiconductor device 104 of the second embodiment, the corners of the source electrode 12a and the source wiring 22c at the + end in the Y direction are chamfered. The other structures are the same as those of the first embodiment, and the description thereof is omitted.

[0081] Fig.10 1 is an enlarged plan view of the semiconductor device of Example 2, in which the vicinity of the source electrode 12a is enlarged. The source electrode 12a and source wiring 22c (dashed line) in Example 1 are shown superimposed on the source electrode 12a and source wiring 22c (solid line) in Example 2.

[0082] like Fig.10 As shown, in both embodiments 1 and 2, when viewed from the Z direction, the via 20a is provided in the source electrode 12a. As a result, the contact area between the metal layer 28a and the source electrode 12a becomes larger, which can reduce the source inductance and source resistance. The positive end Y3 of the source electrode 12a and the source wiring 22c in the Y direction is closer to the drain bus 36 than the positive end Y2 of the active region 11a in the Y direction.

[0083] In the first embodiment, in the portion 54 closer to the drain bus bar 36 than the active region 11a, the edge 55 of the planar shape of the source electrode 12a and the source wiring 22c in the X direction is substantially parallel to the edge of the drain wiring 26a and 26b in the X direction. Therefore, a parasitic capacitance C0 is generated between the source electrode 12a and the source wiring 22c and the drain wiring 26a. The parasitic capacitance C0 is a drain / source parasitic capacitance, and the high-frequency performance of the semiconductor device is deteriorated.

[0084] In the second embodiment, the distance between the source electrode 12a and the drain wiring 26a at the end Y3 (third end) of the source electrode 12a far from the transistor 35c when viewed from the X direction is set to D1. The distance between the source electrode 12a and the drain wiring 26a at the end Y2 of the active region 11a far from the transistor 35c when viewed from the X direction is set to D2. In this case, the distance D1 is greater than the distance D2. Thus, the parasitic capacitance C1 generated between the source electrode 12a and the source wiring 22c and the drain wiring 26a can be made smaller than the parasitic capacitance C0 of the first embodiment. Thus, the drain / source parasitic capacitance can be suppressed, and thus the high-frequency performance of the semiconductor device can be suppressed from being deteriorated.

[0085] In addition, the end Y3 of the source electrode 12a is provided on the inactive region 13. Thus, the parasitic capacitance C1 can be reduced. Thus, the drain-source parasitic capacitance can be suppressed, and thus the high-frequency performance of the semiconductor device can be suppressed from being deteriorated.

[0086] The width W7 (i.e., the difference between the distances D1 and D2) between the position of the end side 55 in the X direction at the end Y2 and the position of the end side 55 in the X direction at the end Y3 can be set to be 0.2 times or more of the width W2 in the Y direction of the ends Y2 and Y3, can be set to be 0.5 times or more of the width W2, and can be set to be 1.0 times or more of the width W2. Thus, the parasitic capacitance C1 can be further suppressed.

[0087] If the distance between the source electrode 12a and the drain wiring 26a is reduced at the end Y2, the margin between the via 20a and the source electrode 12a increases. Therefore, the distance between the source electrode 12a and the drain wiring 26a increases as it moves from the end Y2 to the end Y3. That is, the end edge 55 moves toward the inner side of the source electrode 12a and the source wiring 22c as it moves from the end Y2 to the end Y3. As a result, the parasitic capacitance C1 generated between the source electrode 12a and the source wiring 22c and the drain wiring 26a can be reduced. As a result, the drain / source parasitic capacitance can be suppressed, and thus the high-frequency performance of the semiconductor device can be suppressed from being deteriorated.

[0088] The planar shape of the edge 55 may be a straight line or a curve. The edge 55 may be a straight line or a curve that bulges outward from the source electrode 12a and the source wiring 22c. This ensures a margin between the via 20a and the source electrode 12a.

[0089] [Variation 1 of Example 2]

[0090] Fig.11 FIG. 1 is a top view of a semiconductor device according to a first variation of the second embodiment. Fig.11 As shown, in the semiconductor device 106 of the modification 1 of the second embodiment, the gate electrodes 14 in the transistors 35 of the same transistor group 38 are connected as a whole, as in the modification 1 of the first embodiment. The gate electrodes 14a and 14c of the transistor group 38a are connected as a whole. The gate electrodes 14b and 14d of the transistor group 38b are connected as a whole. The other structures are the same as those of the second embodiment, and the description is omitted.

[0091] In the modification 1 of the embodiment 1 and the modification 1 of the embodiment 2, the gate electrode 14a is connected to the gate electrode 14c between the transistor 35a and the transistor 35c, and the gate electrode 14b is connected to the gate electrode 14d between the transistor 35b and the transistor 35d. Thus, the gate potential is provided to the gate electrodes 14c and 14d from the + end and the - end in the Y direction. Thus, the gate resistance of the transistors 35c and 35d can be further suppressed. In addition, the gate widths Wg2 to Wg4 of the transistors 35c and 35d can be increased.

[0092] However, in transistors 35c and 35d, high-frequency signals are input from the - ends of gate electrodes 14c and 14d in the Y direction. If high-frequency signals are input from both ends of the + and - ends of gate electrodes 14c and 14d in the Y direction to gate electrodes 14c and 14d, the high-frequency performance of transistors 35c and 35d will deteriorate due to phase differences, etc.

[0093] Therefore, in Embodiments 1 and 2, gate electrodes 14a and 14c are separated between transistors 35a and 35c, and gate electrodes 14b and 14d are separated between transistors 35b and 35d. This can suppress degradation of high frequency performance of transistors 35c and 35d.

[0094] In the first and second embodiments and their modified examples, an example in which four transistor groups 38a and 38b are arranged in the X direction is described, but three or more transistor groups 38a and 38b may be arranged in the X direction. One or more transistors 35c and 35d may be arranged in the Y direction, respectively. A source wiring across the drain wiring 26 in the X direction may also be connected between the drain wiring and the gate bus 34.

[0095] In the first and second embodiments and their variations, the plurality of drain electrodes 16 (e.g., drain electrodes 16a and 16c) electrically connected to the same drain wiring 26 (e.g., drain wiring 26a) are separated from each other in the inactive region 13. The plurality of drain electrodes 16 (e.g., drain electrodes 16a and 16c) electrically connected to the drain wiring 26 (e.g., drain wiring 26a) may also be connected to each other in the inactive region 13. In the transistor 35 (e.g., transistor 35a), the source electrode 12 and the source wiring 22 (e.g., source electrode 12a and source wiring 22c) may also be collectively referred to as source electrodes, and the drain electrode 16 and the drain wiring 26 (e.g., drain electrode 16a and drain wiring 26a) may also be collectively referred to as drain electrodes.

[0096] The embodiments disclosed herein are illustrative in all aspects and should not be considered restrictive. The scope of the present disclosure is indicated by the claims rather than the above meanings, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: A substrate having a main surface and a back surface opposite to the main surface; A first transistor is provided on the main surface provided in the active region of the substrate, and includes a first source electrode, a first drain electrode, and a first gate electrode, wherein the first gate electrode is arranged between the first source electrode and the first drain electrode in a first direction; a second transistor, provided on the main surface, comprising: a second source electrode, provided inside the first source electrode and electrically connected to the first source electrode when viewed from a second direction intersecting the first direction; a second drain electrode, electrically connected to the first drain electrode; and a second gate electrode, arranged between the second source electrode and the second drain electrode in the first direction; a first gate wiring provided on the main surface so that the second source electrode is arranged between the first gate wiring and the second gate electrode, provided inside the first source electrode when viewed from the second direction, and electrically connected to the first gate electrode; as well as a back metal layer, disposed on the back surface and electrically connected to the first source electrode via a via hole penetrating the substrate, When viewed from the first direction, a first end of the via hole away from the second transistor is farther from the second transistor than a second end of the active region in a region where the first gate electrode is provided away from the second transistor.

2. The semiconductor device according to claim 1, wherein When viewed from a thickness direction of the substrate, the via hole is provided in the first source electrode.

3. The semiconductor device according to claim 2, wherein: The semiconductor device comprises: a drain bus bar provided on the main surface, so that the first transistor is arranged between the drain bus bar and the second transistor; and a drain wiring connecting the first drain electrode and the second drain electrode to the drain bus bar, When viewed from the first direction, a distance between the first source electrode and the drain wiring at a third end of the first source electrode far from the second transistor is greater than a distance between the first source electrode and the drain wiring at the second end.

4. The semiconductor device according to claim 3, wherein: The third end of the first source electrode is disposed on an inactive region of the substrate.

5. The semiconductor device according to claim 3 or 4, wherein: The distance between the first source electrode and the drain wiring increases from the second end toward the third end.

6. The semiconductor device according to any one of claims 1 to 4, wherein: A gate width of the first transistor is greater than or equal to 0.9 times and less than or equal to 1.1 times a gate width of the second transistor.

7. The semiconductor device according to any one of claims 1 to 4, wherein: The first gate electrode is separated from the second gate electrode between the first transistor and the second transistor.

8. The semiconductor device according to any one of claims 1 to 4, wherein: The first gate electrode and the second gate electrode are connected between the first transistor and the second transistor.

9. The semiconductor device according to any one of claims 1 to 4, comprising: A third transistor is provided on the main surface, and comprises: the first source electrode; a third drain electrode, the first source electrode is arranged between the third drain electrode and the first gate electrode; and a third gate electrode is arranged between the first source electrode and the third drain electrode in the first direction and is electrically connected to the first gate wiring; as well as a fourth transistor provided on the main surface, comprising: a third source electrode, the first gate wiring being arranged between the third source electrode and the second source electrode, being provided inside the first source electrode when viewed from the second direction and being electrically connected to the first source electrode; a fourth drain electrode, wherein the third source electrode is disposed between the fourth drain electrode and the first gate wiring; and a fourth gate electrode disposed between the third source electrode and the fourth drain electrode in the first direction.

10. The semiconductor device according to any one of claims 1 to 4, comprising: a source wiring provided on the main surface and electrically connecting the first source electrode and the second source electrode; and The second gate wiring is provided on the main surface and electrically connects the first gate wiring and the first gate electrode.

11. The semiconductor device according to any one of claims 1 to 4, comprising: a gate bus bar, provided on the main surface, connected to the second gate electrode and the first gate wiring; and A drain bus bar is provided on the main surface, and arranges the first transistor and the second transistor between the drain bus bar and the gate bus bar in the second direction, and is electrically connected to the first drain electrode and the second drain electrode.

Images