Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device includes: a substrate; a compound semiconductor layer disposed on the substrate; and a plurality of unit FETs each provided with: a source electrode, a drain electrode, and a gate electrode, each provided on the compound semiconductor layer and extending in the first direction, the gate electrode being disposed between the source electrode and the drain electrode; and a field plate electrode provided above the compound semiconductor layer between the gate electrode and the drain electrode via an insulating film, the plurality of unit FETs being arranged in a second direction intersecting the first direction, the plurality of unit FETs including: a first unit FET; and a second unit FET closer to the ends of the plurality of unit FETs in the second direction than the first unit FET, a first distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the first unit FET, and a second distance between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the second direction. A second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the second unit FET is shorter than a second distance in the second direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] A technique is known in which a field plate is used in a FET (Field Effect Transistor) such as a HEMT (High Electron Mobility Transistor) having a compound semiconductor layer (for example, Patent Documents 1 and 2).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-102756

[0006] Patent Document 2: Japanese Patent Application Publication No. 2008-277604

[0007] The use of a field plate can suppress the electric field concentration in the semiconductor layer between the gate electrode and the drain electrode. In addition, it can suppress the drift phenomenon of the drain current such as current collapse. However, when a field plate is set, the electrostatic capacitance between the source and the drain increases, and the high-frequency characteristics deteriorate. Summary of the invention

[0008] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to suppress degradation of high-frequency characteristics.

[0009] One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a compound semiconductor layer provided on the substrate; and a plurality of unit FETs, each of the plurality of unit FETs comprising: a source electrode provided on the compound semiconductor layer and extending in a first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction; a gate electrode provided on the compound semiconductor layer and extending in the first direction and arranged between the source electrode and the drain electrode; and a field plate electrode provided above the compound semiconductor layer between the gate electrode and the drain electrode via an insulating film, the plurality of unit FETs being arranged in a second direction intersecting the first direction, the plurality of unit FETs comprising: a first unit FET; and a second unit FET being closer to ends of the plurality of unit FETs in the second direction than the first unit FET, a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the first unit FET being shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the second unit FET.

[0010] One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a compound semiconductor layer provided on the substrate; and a plurality of unit FETs, each of the plurality of unit FETs comprising: a source electrode provided on the compound semiconductor layer and extending in a first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction; a gate electrode provided on the compound semiconductor layer and extending in the first direction and arranged between the source electrode and the drain electrode; and a field plate electrode provided above the compound semiconductor layer between the gate electrode and the drain electrode via an insulating film, the plurality of unit FETs being arranged in a second direction intersecting the first direction, and in at least one of the plurality of unit FETs, a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at a center of the at least one unit FET in the first direction is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at an end of the at least one unit FET in the first direction.

[0011] Effects of the Invention

[0012] According to the present disclosure, degradation of high frequency characteristics can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a top view of the semiconductor device in Example 1.

[0014] Figure 2 yes Figure 1 A-A section view.

[0015] Figure 3 30 is a top view of the unit FET 30 a , the unit FET 30 d , and the unit FET 30 h in the first embodiment.

[0016] Figure 4A It is a cross-sectional view taken along the line AA of the unit FET 30 a .

[0017] Figure 4B It is a cross-sectional view taken along the line AA of the unit FET 30 d.

[0018] Figure 4C It is a cross-sectional view taken along the line AA of the unit FET 30h.

[0019] Figure 5 This is a diagram showing the length L1 and the distance L2 in each unit FET in Example 1.

[0020] Figure 6This is a diagram showing the length L1 and the distance L2 in each unit FET in Comparative Example 1.

[0021] Figure 7 This is a diagram showing the length L1 and the distance L2 in each unit FET in Modification 1 of Example 1.

[0022] Figure 8 It is a top view of the unit FET 30 a , the unit FET 30 d , and the unit FET 30 h in the second embodiment.

[0023] Fig. 9 This is a diagram showing the length L1 and the distance L2 in each unit FET in Example 2.

[0024] Fig.10 30 is a top view of the unit FET 30 a , the unit FET 30 d , and the unit FET 30 h in the third embodiment.

[0025] Fig.11 This is a diagram showing the length L1 and the distance L2 in each unit FET in Example 3.

[0026] Description of Reference Numerals

[0027] 10, 10a: substrate;

[0028] 10b: semiconductor layer;

[0029] 10c: channel layer;

[0030] 10d: barrier layer;

[0031] 11: active area;

[0032] 12: source electrode;

[0033] 13: inactive area;

[0034] 14: gate electrode;

[0035] 15: Wiring;

[0036] 16: drain electrode;

[0037] 18: Field plate electrode;

[0038] 18a: Central part;

[0039] 18b: end;

[0040] 22: vias;

[0041] 24: Gate busbar;

[0042] 25, 25a, 25b: insulating film;

[0043] 26: drain busbar;

[0044] 28, 28a: metal layer;

[0045] 30a to 30h: unit FET;

[0046] 40, 44: center;

[0047] 42, 46: end;

[0048] 50, 52: dotted lines;

[0049] 54, 56: Group;

[0050] 100: Semiconductor device. DETAILED DESCRIPTION

[0051] [Details of the embodiments of the present disclosure]

[0052] First, the contents of the embodiments of the present disclosure will be listed and described.

[0053] (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a compound semiconductor layer provided on the substrate; and a plurality of unit FETs, each of the plurality of unit FETs comprising: a source electrode provided on the compound semiconductor layer and extending in a first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction; a gate electrode provided on the compound semiconductor layer and extending in the first direction and arranged between the source electrode and the drain electrode; and a field plate electrode provided above the compound semiconductor layer between the gate electrode and the drain electrode via an insulating film, the plurality of unit FETs being arranged in a second direction intersecting the first direction, the plurality of unit FETs comprising: a first unit FET; and a second unit FET being closer to ends of the plurality of unit FETs in the second direction than the first unit FET, a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the first unit FET being shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the second unit FET. This can suppress degradation of high frequency characteristics.

[0054] (2) In the above (1), the distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the unit FET closest to the center of the unit FETs in the second direction among the plurality of unit FETs may be the shortest among the distances in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode among the plurality of unit FETs. Thus, high frequency characteristics can be improved.

[0055] (3) In the above (1) or (2), the distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the unit FET closest to the ends of the unit FETs in the second direction among the multiple unit FETs may be the longest distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode among the multiple unit FETs. Thus, high-frequency characteristics can be improved.

[0056] (4) In any of the above (1) to (3), the first distance at the center of the first unit FET in the first direction may be shorter than the first distance at the end of the first unit FET in the first direction. This can improve high frequency characteristics.

[0057] (5) In any one of the above (1) to (4), the plurality of unit FETs may include a third unit FET, the third unit FET being provided between the first unit FET and the second unit FET in the second direction, and a third distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the third unit FET being longer than the first distance and shorter than the second distance. Thus, high frequency characteristics can be improved.

[0058] (6) In any of the above (1) to (5), a first length of the field plate electrode in the first unit FET in the second direction may be shorter than a second length of the field plate electrode in the second unit FET in the second direction. This can improve high frequency characteristics.

[0059] (7) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a compound semiconductor layer provided on the substrate; and a plurality of unit FETs, each of the plurality of unit FETs comprising: a source electrode provided on the compound semiconductor layer and extending in a first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction; a gate electrode provided on the compound semiconductor layer and extending in the first direction and arranged between the source electrode and the drain electrode; and a field plate electrode provided above the compound semiconductor layer between the gate electrode and the drain electrode via an insulating film, the plurality of unit FETs being arranged in a second direction intersecting the first direction, and in at least one of the plurality of unit FETs, a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at a center of the at least one unit FET in the first direction is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at an end of the at least one unit FET in the first direction. Thus, high frequency characteristics can be improved.

[0060] (8) In the above (7), it is also possible that, in a central portion included in the at least one unit FET and including the center in the first direction and having a certain width in the first direction, the distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode is constant, and the distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode gradually increases as it moves from the central portion toward the end in the first direction. In this way, high-frequency characteristics can be improved.

[0061] (9) In any one of the above (1) to (8), in the plurality of unit FETs, the field plate electrode and the source electrode may be electrically short-circuited. This can suppress drift of the drain current.

[0062] (10) In any one of the above (1) to (9), the compound semiconductor layer may be a nitride semiconductor layer. This can further suppress the drift of the drain current.

[0063] Hereinafter, specific examples of semiconductor devices according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0064] [Example 1]

[0065] Embodiment 1 is an example of a FET used for a high-frequency power amplifier. Figure 1 This is a top view of the semiconductor device in Example 1. Figure 2 yes Figure 1 The arrangement direction of the source electrode 12, the gate electrode 14, and the drain electrode 16 is set to the X direction (a second direction intersecting the first direction), the extension direction of the source electrode 12, the gate electrode 14, and the drain electrode 16 is set to the Y direction (the first direction), and the normal direction of the substrate 10 (i.e., the direction perpendicular to the upper surface of the substrate 10) is set to the Z direction. Figure 1 and Figure 2 In the figure, the field plate is omitted.

[0066] like Figure 1 and Figure 2 As shown, in the semiconductor device 100, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. The semiconductor layer 10b includes, for example, a channel layer 10c and a barrier layer 10d provided on the channel layer 10c. An active region 11 is provided on the substrate 10. The region other than the active region 11 is an inactive region 13 after the semiconductor layer 10b is deactivated by ion implantation or the like. That is, the active region 11 is a region after the semiconductor layer 10b in the substrate 10 is activated, and the inactive region 13 is a region after the semiconductor layer 10b is deactivated.

[0067] On the active region 11, a source electrode 12 (source finger), a gate electrode 14 (gate finger), and a drain electrode 16 (drain finger) are provided so as to extend in the Y direction. The planar shape of the source electrode 12, the gate electrode 14, and the drain electrode 16 is substantially rectangular, and the long side of the rectangle extends in the Y direction. The source electrode 12, the gate electrode 14, and the drain electrode 16 are arranged in the X direction.

[0068] The source electrode 12 and the drain electrode 16 are alternately arranged in the X direction. The gate electrode 14 is arranged between one source electrode 12 and one drain electrode 16. The gate electrode 14, and the source electrode 12 and the drain electrode 16 between which the gate electrode 14 is arranged form a unit FET 30a to 30h. Adjacent unit FETs 30a to 30h share the source electrode 12 or the drain electrode 16. A plurality of unit FETs 30a to 30h are arranged in the X direction. Unit FETs 30a to unit FETs 30h are arranged in sequence from the end 42 in the X direction to the center 40. The number of unit FETs can be appropriately set. It should be noted that the end 42 is the end in the X direction of the source electrode 12 of the outermost unit FET 30a in the X direction. The center 40 is the center of the two ends 42 in the X direction.

[0069] A gate bus 24 and a drain bus 26 are provided on the inactive region 13 of the substrate 10. The gate bus 24 and the drain bus 26 extend in the X direction. The +Y ends of the plurality of gate electrodes 14 in the Y direction are connected to the gate bus 24. The −Y ends of the plurality of drain electrodes 16 in the Y direction are connected to the drain bus 26.

[0070] A via hole 22 penetrating the substrate 10 is provided below the source electrode 12. A metal layer 28 is provided on the lower surface of the substrate 10. A reference potential such as a ground potential is supplied to the metal layer 28. A metal layer 28a is provided on the side and upper surface (i.e., bottom surface) of the via hole 22. The metal layer 28a is the same metal layer as the metal layer 28 and is formed at the same time as the metal layer 28. The source electrode 12 is electrically connected to the metal layer 28 via the via hole 22, thereby being short-circuited. Thus, a reference potential is supplied to the source electrode 12. Alternatively, the source electrode 12 may not be provided with the via hole 22, a source pad to which the source electrode 12 is connected is provided on the inactive region 13, and a via hole is provided on the source pad.

[0071] Figure 3 30 is a top view of the unit FET 30 a , the unit FET 30 d , and the unit FET 30 h in the first embodiment. FIG. 4A to FIG. 4C The unit FET 30 a , the unit FET 30 d , and the unit FET 30 h are cross-sectional views taken along line AA, respectively.

[0072] like Figures 3 to 4C In this way, the field plate electrode 18 extends from above the gate electrode 14 to the middle position between the gate electrode 14 and the drain electrode 16 along the X direction, and is provided above the semiconductor layer 10b between the gate electrode 14 and the drain electrode 16 via the insulating film 25a. The field plate electrode 18 is electrically connected to the source electrode 12 through the wiring 15 outside the active region 11, so as to be short-circuited. The wiring 15 is formed of, for example, the same metal layer as the field plate electrode 18, and the wiring 15 and the source electrode 12 are electrically contacted via the opening of the insulating film 25a. Thus, a reference potential is supplied to the field plate electrode 18. The field plate electrode 18 can also be electrically connected to the source electrode 12 through the insulating film 25a above the gate electrode 14 in the active region 11. An insulating film 25b is provided on the source electrode 12, the drain electrode 16, and the field plate electrode 18. The insulating film 25a and the insulating film 25b form an insulating film 25.

[0073] Figure 5 This is a diagram showing the length L1 and the distance L2 in each unit FET in Example 1. Figure 5The horizontal axis represents the unit FETs 30a to 30h arranged in the X direction, and the vertical axis represents the length L1 and the distance L2 in the unit FETs 30a to 30h. The length L1 is the length in the X direction of the field plate electrode 18. The distance L2 is the distance between the end of the gate electrode 14 closer to the drain electrode 16 in the X direction and the end of the field plate electrode 18 closer to the drain electrode 16 in the X direction.

[0074] like Figures 3 to 4C In this way, the distance Lgd between the unit FET 30a and the unit FET 30h is substantially the same in terms of the degree of manufacturing error. The lengths L1 of the unit FET 30a, the unit FET 30d, and the unit FET 30h are L1A, L1D, and L1H, respectively. The distances L2 of the unit FET 30a, the unit FET 30d, and the unit FET 30h are L2A, L2D, and L2H, respectively. Figures 3 to 4C In this way, L1A>L1D>L1H, and L2A>L2D>L2H. Figure 5 Thus, the length L1 and the distance L2 become shorter from the end 42 toward the center 40. In each of the unit FETs 30a to 30h, the length L1 is substantially constant in the Y direction within the degree of manufacturing error, and the distance L2 is substantially constant in the Y direction within the degree of manufacturing error.

[0075] The semiconductor layer 10b is a compound semiconductor layer, such as a nitride semiconductor layer or an arsenide semiconductor layer. When the semiconductor layer 10b is a nitride semiconductor layer, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, or a diamond substrate. The semiconductor layer 10b includes, for example, one or more layers of nitride semiconductor layers such as gallium nitride, aluminum gallium nitride (AlGaN), or indium gallium nitride (InGaN). When the semiconductor device is a GaN HEMT, the channel layer 10c is, for example, a gallium nitride layer, and the barrier layer 10d is, for example, an aluminum gallium nitride layer.

[0076] When the semiconductor layer 10b is an arsenide semiconductor layer, the substrate 10a is, for example, a gallium arsenide (GaAs) substrate. The semiconductor layer 10b includes, for example, one or more layers of arsenide semiconductor layers such as gallium arsenide, aluminum gallium arsenide (AlGaAs), or indium gallium arsenide (InGaAs).

[0077] The source electrode 12 and the drain electrode 16 are, for example, a metal film such as a sealing film (for example, a titanium film) provided on the substrate 10 and an aluminum film provided on the sealing film. A low resistance film such as gold may also be provided on the aluminum film. The gate electrode 14 is, for example, a metal film such as a sealing film (for example, a nickel film) provided on the substrate 10 and a gold film provided on the sealing film. The field plate electrode 18 is, for example, a metal film such as a sealing film (for example, a nickel film or a titanium film) provided on the insulating film 25a and a low resistance film (aluminum film or a gold film) provided on the sealing film. The metal layer 28 and the metal layer 28a are, for example, gold layers.

[0078] The insulating film 25a is an inorganic insulating film such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer, and is a silicon nitride layer as an example. The insulating film 25b is an inorganic insulating film such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer, or an organic insulating film such as a polyimide layer.

[0079] [Comparative Example 1]

[0080] Figure 6 is a diagram showing the length L1 and the distance L2 in each unit FET in Comparative Example 1. Figure 6 As shown, in Comparative Example 1, the length L1 of the unit FET 30a to the unit FET 30h is the length L10 and is substantially constant in the degree of manufacturing error. The distance L2 of the unit FET 30a to the unit FET 30h is the distance L20 and is substantially constant in the degree of manufacturing error.

[0081] By providing a field plate electrode 18 in the semiconductor layer 10b between the gate electrode 14 and the drain electrode 16 via an insulating film 25a, the electric field concentration in the semiconductor layer 10b can be suppressed. When the electric field in the semiconductor layer 10b between the gate electrode 14 and the drain electrode 16 becomes high, a drift of the drain reactive current (Idq) or a drift of the drain current known as a current collapse phenomenon is likely to occur. The principle of the occurrence of the drift of the drain current is explained. Electrons become high energy due to the high electric field and are captured by traps in the semiconductor layer 10b. As a result, the drain current decreases. The electrons captured by the traps are released over time. Therefore, when the electric field between the gate electrode 14 and the drain electrode 16 becomes low, the drain current recovers over time. In this way, a drift of the drain current occurs.

[0082] For example, when a semiconductor device is used for an amplifier circuit, if a drift in the drain current occurs, the output characteristics of the amplifier circuit will change due to the influence of the immediately preceding output. Therefore, the processing of the distortion compensation circuit of the amplifier circuit will be complicated, making it difficult to perform distortion compensation. Such a drift in the drain current is a problem that occurs in a FET using a compound semiconductor layer as the semiconductor layer 10b, and is particularly prone to occur when a nitride semiconductor layer is used as the semiconductor layer 10b.

[0083] When the length of the field plate electrode 18 between the gate electrode 14 and the drain electrode 16 is lengthened (i.e., the distance L2), the electric field in the semiconductor layer 10b is relaxed, and the number of electrons trapped by the trap is reduced. As a result, the drift of the drain current is reduced. However, when the distance L2 is increased, the distance between the field plate electrode 18 and the drain electrode 16 is shortened, and the source-drain capacitance Cds is increased. As a result, the high-frequency characteristics of the semiconductor device are degraded.

[0084] Thus, in Comparative Example 1, when the length L1 and the distance L2 are lengthened, the drift of the drain current is suppressed, but Cds increases and the high-frequency characteristics deteriorate. When the length L1 and the distance L2 are shortened, Cds decreases and the high-frequency characteristics improve, but the drift of the drain current increases.

[0085] In order to reduce Cds, it is also possible to consider lengthening the distance Lgd between the gate electrode 14 and the drain electrode 16. However, when the distance Lgd is lengthened, the drain resistance increases.

[0086] [Operation of Example 1]

[0087] Figure 1 The dotted line 50 and the dotted line 52 in FIG. 1 are isothermal lines showing the temperature distribution when the semiconductor device 100 is operated. The temperature of the dotted line 52 is higher than the temperature of the dotted line 50. Among the unit FETs 30a to 30h, the temperature of the unit FET 30h closest to the center 40 is the highest, and the temperature of the unit FET 30a closest to the end 42 in the X direction of the unit FETs 30a to 30h is the lowest. The temperatures of the unit FETs 30b to 30g decrease as they go from the center 40 toward the end 42.

[0088] In the drift of the drain current, the higher the temperature, the faster the time constant of electrons being released from the trap. Therefore, when the temperature becomes higher, the drift of the drain current is mitigated. As a result, in the unit FET 30h close to the center 40, the drift of the drain current is small, and in the unit FET 30a close to the end 42, the drift of the drain current is large.

[0089] In the unit FET30h (first unit FET) with a high temperature, even if the distance L2H (first distance) is shortened, the drift of the drain current is small, and it can be made within the allowable range of the drift of the drain current. On the other hand, in the unit FET30a (second unit FET) with a low temperature, when the distance L2A (second distance) is shortened, the drift of the drain current becomes larger and exceeds the allowable range of the drift of the drain current. Therefore, the distance L2H is made shorter than the distance L2A. As a result, in the unit FET30h, the drift of the drain current can be made within the allowable range, and Cds can be reduced. On the other hand, in the unit FET30a, although Cds is large, the drift of the drain current can be made within the allowable range. As a result, both Example 1 and Comparative Example 1 can make the drift of the drain current within the allowable range. In Example 1, compared with Comparative Example 1, Cds can be suppressed in the entire semiconductor device and high-frequency characteristics can be improved.

[0090] In addition, in the X direction, a unit FET 30d (third unit FET) is provided between the unit FET 30h and the unit FET 30a. The distance L2D (third distance) in the unit FET 30d is longer than the distance L2H and shorter than the distance L2A. Thus, in the unit FET 30d, the drift of the drain current can be within the allowable range, and Cds can be reduced. Therefore, the drift of the drain current can be within the allowable range in the entire semiconductor device, and Cds can be suppressed, thereby improving high-frequency characteristics.

[0091] Not only the distance between the field plate electrode 18 and the drain electrode 16 affects Cds, but also the length L1 of the field plate electrode 18 in the X direction affects Cds. That is, when the length L1 becomes longer, Cds becomes larger. On the other hand, when the length L1 becomes longer, the distance L2 becomes longer, and the drift of the drain current is suppressed.

[0092] Therefore, the length L1H (first length) of the field plate electrode 18 in the X direction of the unit FET 30h is shorter than the length L1A (second length) of the field plate electrode 18 in the X direction of the unit FET 30a. This makes it possible to keep the drift of the drain current within the allowable range, suppress Cds in the entire semiconductor device, and improve high-frequency characteristics.

[0093] The length L1D (third length) of the field plate electrode 18 in the unit FET 30d in the X direction is shorter than the length L1A and longer than the length L1H. This allows the drift of the drain current to be within the allowable range, suppresses Cds in the entire semiconductor device, and improves high-frequency characteristics.

[0094] In order to suppress Cds, the distance L2H of the unit FET 30h closest to the center 40 can be set to less than 0.9 times the distance L2A of the unit FET 30a closest to the end 42, can be set to less than 0.8 times the distance L2A, can be set to less than 0.7 times the distance L2A. The length L1H of the unit FET 30h closest to the center 40 can be set to less than 0.9 times the length L1A of the unit FET 30a closest to the end 42, can be set to less than 0.8 times the length L1A, can be set to less than 0.7 times the length L1A. The distance L2H and length L1H of the unit FET 30h can also be 0. That is, the unit FET 30h can also be provided with no field plate electrode 18.

[0095] [Variation 1 of Example 1]

[0096] Figure 7 1 is a diagram showing the length L1 and the distance L2 of each unit FET in the first modification of the first embodiment. Figure 7 As shown, for example, the length L1H of the unit FET 30e to the unit FET 30h in the group 54 including the center 40 is substantially the same in terms of the degree of manufacturing error, and the distance L2H from the unit FET 30e to the unit FET 30h is substantially the same in terms of the degree of manufacturing error. The length L1A of the unit FET 30a to the unit FET 30d in the group 56 including the end 42 is substantially the same in terms of the degree of manufacturing error, and the distance L2A from the unit FET 30a to the unit FET 30d is substantially the same in terms of the degree of manufacturing error. As in the first variation of the first embodiment, the unit FET 30a to the unit FET 30h may be divided into a plurality of groups 54 and 56, and in each group 54 and group 56, the length L1 is substantially the same and the distance L2 is substantially the same. The number of groups 54 and 56 may also be three or more.

[0097] The unit FET with the highest temperature among the unit FETs 30a to 30h is the unit FET 30h closest to the center 40. Therefore, as in the first embodiment and its modified example 1, the distance L2H among the unit FETs 30a to 30h closest to the center 40 can be made the shortest among the distances L2 among the unit FETs 30a to 30h. Thus, the high frequency characteristics can be improved.

[0098] The unit FET with the lowest temperature among the unit FETs 30a to 30h is the unit FET 30a closest to the end 42. Therefore, as in the first embodiment and its modified example 1, the distance L2A among the unit FETs 30a to 30h closest to the end 42 can be made the longest among the distances L2 among the unit FETs 30a to 30h. Thus, the high frequency characteristics can be improved.

[0099] As in the first embodiment, the length L1 gradually decreases and the distance L2 gradually decreases as the distance from the end 42 to the center 40 is approached. Figure 5 In this way, the length L1 and the distance L2 change in a linear manner relative to the horizontal axis where the unit FETs are arranged. The length L1 and the distance L2 may also change in a curved manner relative to the horizontal axis where the unit FETs are arranged. As in the first variation of the first embodiment, the length L1 may be shortened in a step-like manner and the distance L2 may be shortened in a step-like manner as it moves from the end 42 toward the center 40. In addition, the length L1 and the distance L2 may be symmetrical in the X direction relative to the center 40, or may be asymmetrical in the X direction relative to the center 40.

[0100] [Example 2]

[0101] Figure 8 It is a top view of the unit FET 30 a , the unit FET 30 d , and the unit FET 30 h in the second embodiment. Fig. 9 This is a diagram showing the length L1 and the distance L2 in each unit FET in Example 2.

[0102] like Figure 8 As shown, the center and the end in the Y direction of the unit FET 30a to the unit FET 30h are respectively set to 44 and 46. The end 46 on the positive side in the Y direction is the end of the drain electrode 16, and the end 46 on the negative side in the Y direction is the end of the source electrode 12 or the active region 11. The center 44 is the center of the two ends 46 in the Y direction.

[0103] The region including the center 44 in the Y direction of the field plate electrode 18 is referred to as the central portion 18a. The region including the end 46 in the Y direction of the field plate electrode 18 is referred to as the end portion 18b. Fig. 9 In this way, in the unit FET 30a to the unit FET 30h, the length L10b at the end 46 is longer than the length L10a at the center 44. In the unit FET 30a to the unit FET 30h, the distance L20b at the end 46 is longer than the distance L20a at the center 44. The lengths L10a in the unit FET 30a to the unit FET 30h are substantially the same in terms of the degree of manufacturing error, the lengths L10b in the unit FET 30a to the unit FET 30h are substantially the same in terms of the degree of manufacturing error, the distances L20a in the unit FET 30a to the unit FET 30h are substantially the same in terms of the degree of manufacturing error, and the distances L20b in the unit FET 30a to the unit FET 30h are substantially the same in terms of the degree of manufacturing error.

[0104] like Figure 8Thus, within the range of the central portion 18a, the length L10a is substantially the same in terms of manufacturing error, and the distance L20a is substantially the same in terms of manufacturing error. In the end portion 18b between the central portion 18a and the end 46, the length L10 gradually increases as it goes from the central portion 18a toward the end 46, and the distance L20 gradually increases as it goes from the central portion 18a toward the end 46. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

[0105] [Operation of Example 2]

[0106] like Figure 1 Thus, when the semiconductor device 100 is operated, the temperature at the center 44 in the Y direction is the highest, and the temperature at the end 46 in the Y direction is the lowest in each of the unit FETs 30a to 30h. The temperature decreases as it moves from the center 44 toward the end 46.

[0107] Therefore, in at least one of the unit FETs 30a to 30h, the distance L20a (first distance) at the center 44 in the Y direction is made shorter than the distance L20b (second distance) at the end 46 in the Y direction. In addition, the length L10a at the center 44 is made shorter than the length L10b at the end 46. Thus, at the center 44 where the temperature is high, the distance L20a is short, so the drift of the drain current is within the allowable range, and Cds can be reduced. At the end 46, the distance L20b is long, so the drift of the drain current can be within the allowable range even at a low temperature. Thus, the drift of the drain current can be within the allowable range, and Cds can be suppressed in the entire semiconductor device, thereby improving high-frequency characteristics.

[0108] The temperature distribution in the Y direction of the unit FETs closer to the center 40 in the unit FETs 30a to 30h tends to be larger. Therefore, the distance L20a at the center 44 of at least the unit FET 30h in the unit FETs 30a to 30h can be made shorter than the distance L20b at the end 46 of the unit FET 30h.

[0109] In the unit FET 30h, L20b-L20a can be set to be 0.05 times or more of the distance L20b, can be set to be 0.1 times or more of the distance L20b, can be set to be 0.2 times or more of the distance L20b. L10b-L10a can be set to be 0.05 times or more of the length L10b, can be set to be 0.1 times or more of the length L10b, can be set to be 0.2 times or more of the length L10b.

[0110] [Example 3]

[0111] Fig.10 30 is a top view of the unit FET 30 a , the unit FET 30 d , and the unit FET 30 h in the third embodiment. Fig.11 This is a diagram showing the length L1 and the distance L2 in each unit FET in Example 3.

[0112] like Fig.10 As shown, the length L1 at the center 44 in the Y direction of the unit FET 30a, the unit FET 30d, and the unit FET 30h are L1Aa, L1Da, and L1Ha, respectively. The distance L2 at the center 44 in the Y direction of the unit FET 30a, the unit FET 30d, and the unit FET 30h are L2Aa, L2Da, and L2Ha, respectively. The length L1 at the end 46 in the Y direction of the unit FET 30a, the unit FET 30d, and the unit FET 30h are L1Ab, L1Db, and L1Hb, respectively. The distance L2 at the end 46 in the Y direction of the unit FET 30a, the unit FET 30d, and the unit FET 30h are L2Ab, L2Db, and L2Hb, respectively.

[0113] L1Aa<L1Ab, L2Aa<L2Ab, L1Da<L1Db, L2Da<L2Db, L1Ha<L1Hb and L2Ha<L2Hb, and L1Aa>L1Da>L1Ha, L1Ab>L1Db>L1Hb, L2Aa>L2Da>L2Ha and L2Ab>L2Db>L2Hb.

[0114] like Fig.11 As shown, in the unit FET30a to the unit FET30h, the terminal 46 (refer to Fig.10 ) is longer than the center 44 (refer to Fig.10 ) is longer. In the unit FET 30a to the unit FET 30h, the distance L2 at the end 46 is longer than the distance L2 at the center 44. The length L1 and the distance L2 at the center 44 become shorter as they go from the end 42 toward the center 40. The length L1 and the distance L2 at the end 46 become shorter as they go from the end 42 toward the center 40. The other configurations are the same as those in the embodiment 2, and the description thereof is omitted.

[0115] [Operation of Embodiment 3]

[0116] like Figure 1 Thus, when the semiconductor device 100 is operated, the temperature at the center 40 and the center 44 of the unit FETs 30 a to 30 h is the highest, and the temperature decreases from the center 40 toward the end 42 and from the center 44 toward the end 46 .

[0117] Therefore, the distance L2Ha and the distance L2Hb in the unit FET30h are respectively shorter than the distance L2Aa and the distance L2Ab in the unit FET30a, and in the unit FET30h, the distance L2Ha is shorter than the distance L2Hb. Thus, at the center 40 and the center 44 where the temperature is high, the distance L2Ha is short, so the drift of the drain current is within the allowable range and Cds can be reduced. At the ends 42 and 46, the distance L2Aa is long, so even if the temperature is low, the drift of the drain current can be within the allowable range. Thus, the drift of the drain current can be within the allowable range, and Cds can be suppressed in the entire semiconductor device to improve high-frequency characteristics. Alternatively, in the unit FET30a, the distance L2Aa can also be shorter than the distance L2Ab.

[0118] The temperature distribution in the Y direction of the unit FETs closer to the center 40 is likely to be larger among the unit FETs 30a to 30h. Therefore, the distance L1Ha at the center 44 of at least the unit FET 30h among the unit FETs 30a to 30h can be made shorter than the distance L1Hb at the end 46 of the unit FET 30h.

[0119] The length L1Ha and the length L1Hb of the unit FET 30h may be shorter than the length L1Aa and the length L1Ab of the unit FET 30a, respectively, and the length L1Ha may be shorter than the length L1Hb in the unit FET 30h. The length L1Aa may also be shorter than the length L1Ab in the unit FET 30a.

[0120] exist Figure 1 In the embodiment, the temperature of the unit FET 30a to the unit FET 30h is relatively constant near the center in the Y direction, and the temperature drops sharply as it approaches the end 46. Therefore, the length L1 and the distance L2 at the center portion 18a including the center 40 and having a certain width in the Y direction can be made constant, and the length L1 and the distance L2 at the end portion 18b can be made gradually longer as they go from the center portion 18a toward the end 46. The width of the center portion 18a in the Y direction is, for example, 0.1 times or more and 0.9 times or less of the gate width of the unit FET 30a to the unit FET 30h, or 0.3 times or more and 0.6 times or less of the gate width.

[0121] In Example 2 and Example 3, the length L1 and the distance L2 at the end 18b are linearly increased as they go from the central portion 18a toward the end 46, but they may also be curvedly increased. In addition, the length L1 at the end 18b may be a constant length at any position in the Y direction, and the distance L2 at the end 18b may be a constant distance at any position in the Y direction. It is also possible not to provide the central portion 18a where the length L1 and the distance L2 in the Y direction are constant, and the length L1 and the distance L2 may gradually increase as they go from the center 44 toward the end 46. In addition, the length L1 and the distance L2 may be symmetrical in the Y direction relative to the center 44, or they may be asymmetrical in the Y direction relative to the center 44.

[0122] In Examples 1 to 3, in the unit FETs 30a to 30h, the field plate electrode 18 and the source electrode 12 are electrically short-circuited. This can further suppress the electric field concentration in the semiconductor layer 10b between the gate electrode 14 and the drain electrode 16.

[0123] In the unit FETs 30a to 30h, the field plate electrode 18 may not be provided above the gate electrode 14. By providing the field plate electrode 18 above the gate electrode 14 via the insulating film 25a, the parasitic capacitance between the gate electrode 14 and the drain electrode 16 can be suppressed.

[0124] Drain current drift is likely to occur when the semiconductor layer 10b is a nitride semiconductor layer. Therefore, when the semiconductor layer 10b is a nitride semiconductor layer, the length L1 and the distance L2 may be different as in the first to third embodiments.

[0125] Drain current drift easily occurs when the semiconductor layer 10b has a GaN channel layer and an AlGaN barrier layer. Therefore, when the semiconductor layer 10b has a GaN channel layer and an AlGaN barrier layer, the length L1 and the distance L2 may be different as in the first to third embodiments.

[0126] The embodiments disclosed herein are illustrative in all aspects and are not restrictive. The scope of the present disclosure is indicated by the claims rather than the above meanings, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: substrate; a compound semiconductor layer disposed on the substrate; and A plurality of unit FETs, each of the plurality of unit FETs comprises: a source electrode disposed on the compound semiconductor layer and extending in a first direction; a drain electrode, disposed on the compound semiconductor layer and extending in the first direction; a gate electrode, provided on the compound semiconductor layer, extending in the first direction, and arranged between the source electrode and the drain electrode; and a field plate electrode disposed above the compound semiconductor layer between the gate electrode and the drain electrode via an insulating film, wherein the plurality of unit FETs are arranged in a second direction intersecting the first direction, The plurality of unit FETs have: First unit FET; as well as The second unit FET is closer to the ends of the plurality of unit FETs in the second direction than the first unit FET is, A first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the first unit FET is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the second unit FET.

2. The semiconductor device according to claim 1, wherein The distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the unit FET closest to the center of the multiple unit FETs in the second direction is the shortest among the distances in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the multiple unit FETs.

3. The semiconductor device according to claim 1 or 2, wherein: The distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the unit FET closest to the ends of the multiple unit FETs in the second direction is the longest among the distances in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the multiple unit FETs.

4. The semiconductor device according to claim 1 or 2, wherein: The first distance at the center of the first unit FET in the first direction is shorter than the first distance at the end of the first unit FET in the first direction.

5. The semiconductor device according to claim 1 or 2, wherein: The plurality of unit FETs include a third unit FET, the third unit FET being provided between the first unit FET and the second unit FET in the second direction, A third distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the third unit FET is longer than the first distance and shorter than the second distance.

6. The semiconductor device according to claim 1 or 2, wherein: A first length of the field plate electrode in the first unit FET in the second direction is shorter than a second length of the field plate electrode in the second unit FET in the second direction.

7. A semiconductor device comprising: substrate; a compound semiconductor layer disposed on the substrate; and A plurality of unit FETs, each of the plurality of unit FETs comprises: a source electrode disposed on the compound semiconductor layer and extending in a first direction; a drain electrode, disposed on the compound semiconductor layer and extending in the first direction; a gate electrode, provided on the compound semiconductor layer, extending in the first direction, and arranged between the source electrode and the drain electrode; and a field plate electrode disposed above the compound semiconductor layer between the gate electrode and the drain electrode via an insulating film, wherein the plurality of unit FETs are arranged in a second direction intersecting the first direction, In at least one unit FET among the plurality of unit FETs, a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at the center of the at least one unit FET in the first direction is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at an end of the at least one unit FET in the first direction.

8. The semiconductor device according to claim 7, wherein: In a central portion included in the at least one unit FET and in a central portion including the center in the first direction and having a certain width in the first direction, the distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode is constant, and the distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode gradually increases as it moves from the central portion toward the end in the first direction.

9. The semiconductor device according to claim 1, wherein: In the plurality of unit FETs, the field plate electrode is electrically short-circuited with the source electrode.

10. The semiconductor device according to claim 7, wherein: In the plurality of unit FETs, the field plate electrode is electrically short-circuited with the source electrode.

11. The semiconductor device according to claim 1, wherein The compound semiconductor layer is a nitride semiconductor layer.

12. The semiconductor device according to claim 7, wherein: The compound semiconductor layer is a nitride semiconductor layer.

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