Transistor and semiconductor memory device including same

Abstract

The invention discloses a transistor and a semiconductor memory device including the same. The transistor comprises a substrate which comprises an active region; an element isolation film in the substrate, the element isolation film defining the active region; a first impurity region on a lower surface of the element isolation film; the second impurity region is positioned in the substrate; a gate electrode on the substrate and extending in a first direction; a source / drain region on at least one side of the gate electrode; a first source / drain contact group on the source / drain region; and a second source / drain contact group on the source / drain region and spaced apart from the first source / drain contact group in the first direction, wherein the second impurity region is between the first source / drain contact group and the second source / drain contact group.

Description

Technical Field

[0001] The present disclosure relates to a transistor and a semiconductor memory device including the same. More particularly, the present disclosure relates to a transistor and a three-dimensional semiconductor memory device including the same and a memory cell arranged three-dimensionally. Background Art

[0002] In order to meet consumers' demand for high performance and low price of semiconductor memory devices, the integration of semiconductor memory devices can be improved. The integration of semiconductor memory devices is an important factor in determining their price. Therefore, semiconductor memory devices with higher integration may be particularly needed.

[0003] The integration of two-dimensional (2D) or planar semiconductor memory devices depends largely on the occupied area of ​​the unit memory cell, and therefore may be greatly affected by the level of fine pattern formation technology. However, forming fine patterns usually requires very expensive equipment. Therefore, although the integration of 2D semiconductor memory devices is increasing, its increase may be limited. Therefore, a three-dimensional semiconductor memory device including a three-dimensionally arranged memory cell is proposed. Summary of the invention

[0004] The present disclosure describes a transistor that may have improved durability and reliability.

[0005] The present disclosure describes a semiconductor memory device including a transistor that may have improved durability and reliability.

[0006] The purpose according to the present disclosure is not limited to the above-mentioned purpose. Other purposes and advantages not mentioned according to the present disclosure can be understood based on the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the purposes and advantages according to the present disclosure can be achieved using the means shown in the claims and their combinations.

[0007] According to one aspect of the present disclosure, a transistor is provided, the transistor comprising: a substrate, the substrate comprising an active area; an element isolation film in the substrate, the element isolation film defining the active area; a first impurity region, the first impurity region being located on a lower surface of the element isolation film; a second impurity region, the second impurity region being located in the substrate; a gate electrode, the gate electrode being located on the substrate and extending in a second direction; a source / drain region, the source / drain region being located on at least one side of the gate electrode; a first source / drain contact group, the first source / drain contact group being located on the source / drain region; and a second source / drain contact group, the second source / drain contact group being located on the source / drain region and being spaced apart from the first source / drain contact group in the second direction, wherein the second impurity region is located between the first source / drain contact group and the second source / drain contact group.

[0008] According to another aspect of the present disclosure, a transistor is provided, the transistor comprising: a substrate, the substrate comprising an active region; a gate electrode, the gate electrode being located on the substrate and extending in a second direction; an element isolation film in the substrate, the element isolation film defining the active region; a first impurity region, the first impurity region being located on a lower surface of the element isolation film; a second impurity region, the second impurity region being located in the substrate and extending in a first direction intersecting with the second direction; a source / drain region, the source / drain region being located on at least one side of the gate electrode; a first source / drain contact group, the first source / drain contact group located on the source / drain region; and a second source / drain contact group, the second source / drain contact group is located on the source / drain region and is spaced apart from the first source / drain contact group in the second direction, wherein the source / drain region includes: a third impurity region in contact with the first source / drain contact group; and a fourth impurity region located between the third impurity region and the gate electrode, wherein the concentration of N-type impurities in the third impurity region is greater than the concentration of N-type impurities in the fourth impurity region, wherein the second impurity region does not overlap with the first source / drain contact group in a third direction perpendicular to the upper surface of the substrate.

[0009] According to another aspect of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a peripheral circuit structure, the peripheral circuit structure comprising a transistor; and a unit structure, the unit structure being located on the peripheral circuit structure, wherein the unit structure comprises: a unit substrate; a mold structure comprising a plurality of unit gate electrodes sequentially stacked on the unit substrate; and a channel structure extending through the plurality of unit gate electrodes, wherein the transistor comprises: a substrate including an active region; an element isolation film in the substrate defining the active region; a first impurity region located on a lower surface of the element isolation film; a second impurity region located in the substrate; a gate electrode located on the substrate and extending in a second direction; a source / drain region located on at least one side of the gate electrode; a first source / drain contact group located on the source / drain region; and a second source / drain contact group located on the source / drain region and spaced apart from the first source / drain contact group in the second direction, wherein the second impurity region is located between the first source / drain contact group and the second source / drain contact group. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0011] Figure 1 is a top view layout diagram showing a transistor according to some embodiments;

[0012] Figure 2 It is along Figure 1 A cross-sectional view taken along line AA in FIG.

[0013] Figure 3 It is along Figure 1 A cross-sectional view taken along line BB in FIG.

[0014] Figure 4 is a top view layout diagram showing a transistor according to some embodiments;

[0015] Figure 5 is a cross-sectional view showing a transistor according to some embodiments;

[0016] Figure 6 is a cross-sectional view showing a transistor according to some embodiments;

[0017] Figure 7 and Figure 8 is a diagram showing a transistor according to some embodiments;

[0018] Fig. 9 is a top view layout diagram showing a transistor according to some embodiments;

[0019] Fig.10 is a block diagram illustrating a semiconductor memory device according to some embodiments;

[0020] Fig.11 is a circuit diagram illustrating a semiconductor memory device according to some embodiments;

[0021] Fig.12 is a schematic diagram illustrating a semiconductor memory device according to some embodiments;

[0022] Fig.13 It is shown Fig.12 An enlarged view of region R1 in FIG.

[0023] Fig.14 is a schematic diagram illustrating a semiconductor memory device according to some embodiments;

[0024] Fig.15 is a schematic diagram illustrating a semiconductor memory device according to some embodiments;

[0025] Fig.16 is a block diagram illustrating an electronic system according to some embodiments;

[0026] Fig.17 is a perspective view showing an electronic system according to some embodiments;

[0027] Fig.18 It is along Fig.17 Schematic cross-sectional view taken along line II. DETAILED DESCRIPTION

[0028] For simplicity and clarity of explanation, the elements in the drawings are not necessarily drawn to scale. The same reference numerals in different drawings represent the same or similar elements, and thus perform similar functionality. In addition, in order to simplify the description, the description and details of the known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a comprehensive understanding of the present disclosure. However, it will be understood that the present disclosure can be practiced without these specific details. In other cases, known methods, procedures, components and circuits are not described in detail to avoid unnecessary obscurity of various aspects of the present disclosure. Examples of various embodiments are further shown and described below. It should be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover alternatives, modifications and equivalents that may be included in the spirit and scope of the present disclosure defined by the appended claims.

[0029] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the accompanying drawings for illustrating the embodiments of the present disclosure are illustrative, and the present disclosure is not limited thereto. The same reference numerals refer to the same elements herein. In addition, in order to simplify the description, the description and details of the known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a comprehensive understanding of the present disclosure. However, it will be understood that the present disclosure can be practiced without these specific details. In other cases, known methods, procedures, components and circuits are not described in detail to avoid unnecessary obscurity of various aspects of the present disclosure.

[0030] The terms used herein are only for the purpose of describing specific embodiments, rather than being intended to limit the present disclosure. As used herein, the singular forms "one" and "an" are also intended to include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include", "contain", "comprise" and "cover" used in this specification specify the presence of the features, integers, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, operations, elements, parts and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listing. Expressions such as "at least one" can modify the entire element list when located in front of the element list, and cannot modify the individual elements of the list. When referring to "C to D", this means C (including endpoints) to D (including endpoints), unless otherwise stated.

[0031] It will be understood that, although the terms "first", "second", "third", etc., may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0032] In addition, it should be understood that when a first element or layer is referred to as being present "on" or "below" a second element or layer, the first element may be directly disposed on or below the second element, or may be indirectly disposed on or below the second element, with a third element or layer disposed between the first element or layer and the second element or layer and connected to the first element or layer and the second element or layer. It should be understood that when an element or layer is referred to as being "connected to another element or layer" or "coupled to another element or layer," it may be directly on, directly connected to or coupled to another element or layer, or one or more intermediate elements or layers may be present. In addition, it should be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0033] In addition, as used herein, when a layer, film, area, plate, etc. may be disposed "on" or "on top of" another layer, film, area, plate, etc., the former may directly contact the latter, or another layer, film, area, plate, etc. may be disposed between and connected to the former and the latter. As used herein, when a layer, film, area, plate, etc. is disposed "on" or "on top of" another layer, film, area, plate, etc., the former may directly contact the latter, and another layer, film, area, plate, etc. is not disposed between and connected to the former and the latter. In addition, as used herein, when a layer, film, area, plate, etc. may be disposed "below" or "below" another layer, film, area, plate, etc., the former may directly contact the latter, or another layer, film, area, plate, etc. may be disposed between and connected to the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed “under” or “beneath” another layer, film, region, plate, etc., the former directly contacts the latter, and another layer, film, region, plate, etc. is not disposed between and connected to the former and the latter.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0035] In one example, when a certain embodiment can be implemented differently, the function or operation specified in a particular block can occur in an order different from that specified in the flow chart. For example, two consecutive blocks can actually be run simultaneously. Depending on the relevant functions or operations, these blocks can be run in reverse order. All embodiments disclosed herein can be intended to be implemented separately or in any manner and / or combination. The various aspects described about an embodiment can be incorporated into different embodiments, although not specifically described with respect to it. That is to say, the features of all embodiments and / or any embodiment can be combined in any manner and / or combination.

[0036] In the description of a temporal relationship, for example, a temporal precedence relationship between two events, such as "after", "subsequently", "before", etc., another event may occur between the two events unless "immediately after", "immediately after", or "immediately before" is not specified. The features of various embodiments of the present disclosure may be combined with each other in part or in whole, and may be technically associated with each other or operate with each other. These embodiments may be implemented independently of each other, and may be implemented together in an associated relationship.

[0037] For ease of explanation, spatially relative terms such as "below," "beneath," "lower," "lower," "above," "upper," and the like may be used herein to illustrate the relationship of one element or feature shown in a figure to another element or feature. It should be understood that, in addition to the orientation depicted in the accompanying drawings, spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the figure is flipped, then an element described as being "below" or "below" or "lower" other elements or features will be oriented as being "above" the other elements or features. Thus, the example terms "below" and "below" may encompass both above and below orientations. The device may be oriented in other ways, such as rotated 90 degrees or in other orientations, and the spatially relative descriptors used herein may be interpreted accordingly.

[0038] The terms "first direction Y", "second direction X", and "third direction Z" as used herein should not be interpreted as having only a geometric relationship in which the first direction, the second direction, and the third direction are perpendicular to each other. "First direction Y", "second direction X", and "third direction Z" can be interpreted as having a wider range of directions within which the components in this article can functionally work.

[0039] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and their repeated descriptions are omitted.

[0040] In the drawings related to transistors according to some embodiments, examples of transistors including a channel region in a planar shape are shown. However, the present disclosure is not limited thereto. The transistors according to some embodiments may include a fin transistor (FinFET) including a channel region in a fin pattern shape, a transistor including a nanowire or a nanosheet, and an MBCFET. TM (Multi-bridge channel field effect transistor). In addition, the semiconductor device according to some embodiments may include a tunnel transistor (tunnel FET) or a three-dimensional (3D) transistor. In addition, the technical concept of the present disclosure can be applied to transistors based on 2D materials (FETs based on 2D materials) and their heterostructures.

[0041] In the following, reference Figures 1 to 9 , a transistor according to some embodiments is described.

[0042] Figure 1 is a top view layout diagram showing a transistor according to some embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA in FIG. Figure 3 It is along Figure 1 A cross-sectional view taken along line BB in FIG. Figure 4 is a layout diagram showing a transistor according to some embodiments.

[0043] refer to Figures 1 to 4 According to some embodiments, the transistor may include a substrate 200 , a first impurity region 210 , a second impurity region 215 , a gate electrode 220 , a gate insulating film 225 , source / drain regions 230 , and source / drain contacts 250 , among others.

[0044] The substrate 200 may be made of or may include a semiconductor material. The substrate 200 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. In other embodiments, the substrate 200 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, and / or gallium antimonide.

[0045] The active region AR may be disposed on the substrate. The active region AR may be defined by the element isolation film 235. In one example, the active region AR may be a region in which an N-type channel metal oxide semiconductor is formed. In another example, the active region AR may be a region in which a P-type channel metal oxide semiconductor is formed.

[0046] The element isolation film 235 may be disposed in the substrate 200. In other embodiments, the element isolation film 235 may be formed on the substrate 200 to define the active area AP. The element isolation film 235 may be located in the element isolation trench and at least partially fill the element isolation trench. The element isolation film 235 may have a shallow trench isolation (STI) structure, which has excellent element isolation capability and a small footprint, and is therefore advantageous in terms of high integration. However, the embodiments of the present disclosure are not limited thereto. For example, the element isolation film 235 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof.

[0047] The first impurity region 210 may be provided in the substrate 200. The first impurity region 210 may be formed on the lower surface 235_BS of the element isolation film 235. The boundary surface between the first impurity region 210 and the element isolation film 235 may be the bottom surface of the element isolation trench. Figure 1 In a top view of FIG. 1 , the first impurity region 210 may surround the active region AR.

[0048] The second impurity region 215 may be disposed in the substrate 200. The second impurity region 215 may extend in the first direction. The second impurity region 215 may be at least partially surrounded by the substrate 200. In other words, the second impurity region 215 may be disposed in the substrate 200.

[0049] In a top view, the second impurity region 215 may be disposed between the first source / drain contact group 250_G1 and the second source / drain contact group 250_G2 (which will be described below), and between the second source / drain contact group 250_G2 and the third source / drain contact group 250_G3 (which will be described below). The second impurity region 215 may not overlap with the first to third source / drain contact groups 250_G1, 250_G2, and 250_G3 in the third direction Z.

[0050] The first impurity region 210 may have a first vertical (ie, third direction Z) dimension H1 up to the upper surface 200_US of the substrate 200. In this regard, the first vertical dimension H1 may be a distance from a top surface of the first impurity region 210 to the upper surface 200_US of the substrate 200.

[0051] The second impurity region 215 may be spaced apart from the upper surface 200_US of the substrate 200 by a second vertical dimension H2. In this regard, the second vertical dimension H2 may be a distance from a top surface of the second impurity region 215 to the upper surface 200_US of the substrate 200. The first vertical dimension H1 and the second vertical dimension H2 may be equal to each other.

[0052] The first impurity region 210 and the second impurity region 215 may contain dopants of the same conductivity type. In one example, the dopant may include a P-type impurity. The P-type impurity may be, for example, one of boron (B) or gallium (Ga). However, the embodiments of the present disclosure are not limited thereto. In another example, the dopant may include an N-type impurity. For example, the N-type impurity may include phosphorus (P), arsenic (As), antimony (Sb) and / or bismuth (Bi). In the following description, an example in which the dopant includes a P-type impurity is described.

[0053] The gate electrode 220 may be disposed on the substrate 200 and the active region AR. The gate electrode 220 may extend in the second direction Y. The gate electrode 220 may overlap in the third direction Z with the second impurity region 215 disposed in the substrate 200 .

[0054] The gate electrode 220 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and / or a conductive metal oxynitride. The gate electrode 220 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride ( The conductive metal oxides and conductive metal oxynitrides may include oxidized products of the above-mentioned materials. The conductive metal oxides and conductive metal oxynitrides may include oxidized products of the above-mentioned materials. The conductive metal oxides and conductive metal oxynitrides may include oxidized products of the above-mentioned materials.

[0055] The gate electrode 220 is shown as a single-layer film. However, the embodiments of the present disclosure are not limited thereto. For example, the gate electrode 220 may have a stacked structure of multiple layers of films each made of the above-mentioned conductive metal materials or a combination thereof.

[0056] The gate insulating film 225 may be disposed on the upper surface 200 of the substrate 200. The gate insulating film 225 may be disposed between the substrate 200 and the gate electrode 220.

[0057] The gate insulating film 225 is shown as a single film. However, the embodiments of the present disclosure are not limited thereto. The gate insulating film 225 may include an interface insulating film and a high dielectric constant insulating film.

[0058] The gate insulating film 225 may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant (high-k) material may include, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, and / or lead zinc niobate.

[0059] The gate spacer 260 may be disposed on the substrate 200. The gate spacer 260 may be disposed on the sidewalls of the gate insulating film 225 and the sidewalls of the gate electrode 220. The gate spacer 260 is shown as having a strip shape. However, the embodiments of the present disclosure are not limited thereto. For example, the shape of the gate spacer 260 may be L-shaped.

[0060] The gate spacer 160 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. However, the embodiments of the present disclosure are not limited thereto. Although the gate spacer 160 is shown to be implemented as a single-layer film, this is only intended for ease of description, and the embodiments of the present disclosure are not limited thereto.

[0061] The source / drain region 230 may be disposed on the substrate 200. The source / drain region 230 may be disposed on at least one side of the gate electrode 220. The source / drain region 230 may be disposed on each of two opposite sides of the gate electrode 220.

[0062] The source / drain region 230 may include a third impurity region 232 and a fourth impurity region 234 .

[0063] The third impurity regions 232 may be arranged to be spaced apart from each other in the second direction Y. The third impurity regions 232 may be disposed in a manner corresponding to the source / drain contacts 250, which will be described below. That is, the third impurity regions 232 may be disposed to overlap with the source / drain contacts 250 in the third direction Z. The third impurity regions 232 may not overlap with the second impurity regions 215 in the third direction Z.

[0064] The third impurity region 232 may be in contact with the source / drain contact 250, which will be described below. The depth of the third impurity region 232 may be greater than the depth of the fourth impurity region 234 from the upper surface 200 of the substrate 200 into the substrate 200. The third impurity region 232 and the fourth impurity region 234 may be aligned with each other in the first direction X. The fourth impurity region 234 may be formed on each side of two opposite sides of the gate electrode 220. The fourth impurity region 234 is shown as overlapping with the gate spacer 260 in the third direction Z. However, the embodiments of the present disclosure are not limited thereto. For example, the fourth impurity region 234 may not overlap with the gate spacer 260 in the third direction Z.

[0065] The third impurity region 232 and the fourth impurity region 234 may include impurities of the same conductivity type. The concentration of the impurities in the third impurity region 232 is greater than the concentration of the impurities in the fourth impurity region 234.

[0066] The source / drain contact 250 may be disposed on the source / drain region 230. The source / drain contact 250 may contact the third impurity region 232. The source / drain contact 250 may be disposed on each of two opposite sides of the gate electrode 220. The source / drain contacts 250 may be arranged along the second direction Y.

[0067] The source / drain contacts 250 may be divided into a first source / drain contact group 250_G1 , a second source / drain contact group 250_G2 , and a third source / drain contact group 250_G3 .

[0068] The first source / drain contact group 250_G1, the second source / drain contact group 250_G2, and the third source / drain contact group 250_G3 may include the same number of source / drain contacts 250. For example, the number of source / drain contacts 250 in the first source / drain contact group 250_G1, the second source / drain contact group 250_G2, and the third source / drain contact group 250_G3 may be four.

[0069] The first source / drain contact group 250_G1, the second source / drain contact group 250_G2, and the third source / drain contact group 250_G3 may be aligned with each other in the second direction Y. Specifically, the first source / drain contact group 250_G1 and the second source / drain contact group 250_G2 may be spaced apart from each other in the second direction Y. The second source / drain contact group 250_G2 and the third source / drain contact group 250_G3 may be spaced apart from each other in the second direction Y. The distance between the first source / drain contact group 250_G1 and the second source / drain contact group 250_G2 is equal to the distance between the second source / drain contact group 250_G2 and the third source / drain contact group 250_G3.

[0070] The first to third source / drain contact groups 250_G1, 250_G2, and 250_G3 are shown to each include four source / drain contacts. However, the embodiments of the present disclosure are not limited thereto. For example, Figure 4 As shown, the number of source / drain contacts 250 may be two. In another example, the number of source / drain contacts may be three, five, or more.

[0071] The source / drain contacts 250 may include a conductive material, such as a metal, a metal nitride, a metal carbonitride, a two-dimensional (2D) material, and / or a conductive semiconductor material.

[0072] The first inter-wiring insulating film 240 may be formed on the upper surface 200 of the substrate 200. The first inter-wiring insulating film 240 may include an insulating material. The first inter-wiring insulating film 240 may be located on the element isolation film 235, the gate electrode 220, and the source / drain contact 250 and at least partially cover the element isolation film 235, the gate electrode 220, and the source / drain contact 250.

[0073] Figure 5 is a cross-sectional view illustrating a transistor according to some embodiments. Figure 6 is a cross-sectional view showing a transistor according to some embodiments. For ease of description, the following description is based on its Figures 1 to 4 The differences described in .

[0074] refer to Figure 5 and Figure 6 , the first impurity region 210 may have a first vertical dimension H1 up to the upper surface 200_US of the substrate 200. In this regard, the first vertical dimension H1 may be a distance from a top surface of the first impurity region 210 to the upper surface 200_US of the substrate 200.

[0075] The second impurity region 215 may be spaced apart from the upper surface 200_US of the substrate 200 by a second vertical dimension H2. In this regard, the second vertical dimension H2 may be a distance from a top surface of the second impurity region 215 to the upper surface 200_US of the substrate 200.

[0076] In one example, if Figure 5 As shown, the first vertical dimension H1 may be greater than the second vertical dimension H2. Figure 6 As shown, the first vertical dimension H1 may be smaller than the second vertical dimension H2.

[0077] Figure 7 and Figure 8 is a diagram showing a transistor according to some embodiments. For ease of description, the following description is based on its Figures 1 to 4 The differences described in .

[0078] refer to Figure 7 and Figure 8 , the third impurity region 232 may include a sub-impurity region 232S.

[0079] Figure 2 The third impurity region 232 in FIG. 1 may be divided into separate sub-impurity regions 232S in a manner corresponding to the source / drain contacts 250. Except for this difference, the description of the sub-impurity region 232 may be the same as that of FIG. Figure 2 The description of the third impurity region 232 in is basically the same.

[0080] Specifically, the sub-impurity region 232S may contact the source / drain contact 250. The sub-impurity region 232S may overlap the source / drain contact 250 in the third direction Z. The sub-impurity region 232S may be arranged along the second direction Y. The sub-impurity regions 232S may be spaced apart from each other in the second direction Y.

[0081] Fig. 9 is a top view layout diagram showing a transistor according to some embodiments. For ease of description, the following description is based on the Figures 1 to 4 as well as Figure 8 The differences described in .

[0082] refer to Fig. 9 , the second impurity region 215 may be disposed in the substrate 200. The second impurity region 215 may be at least partially surrounded by the substrate 200. The second impurity region 215 may not overlap with the source / drain contact groups 250_G1, 250_G2, and 250_G3 in the second direction Y and the third direction Z.

[0083] In the following, reference Figures 10 to 15 , a semiconductor memory device including a transistor according to some embodiments is described.

[0084] Fig.10 is a block diagram illustrating a semiconductor memory device according to some embodiments.

[0085] refer to Fig.10 , a semiconductor memory device 10 according to some embodiments includes a memory cell array 20 and a peripheral circuit 30 .

[0086] The memory cell array 20 may include a plurality of memory cell blocks (BLK1 to BLKn). Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 via a bit line BL, a word line WL, at least one string selection line SSL, and at least one ground selection line GSL. Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 via the word line WL, the string selection line SSL, and the ground selection line GSL. In addition, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 via the bit line BL.

[0087] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from an external device and the semiconductor memory device 10, and may transmit and receive data to and from the external device and the semiconductor memory device 10. The peripheral circuit 30 may include a control logic 37, a row decoder 33, and a page buffer 35. Although not shown, the peripheral circuit 30 may further include various sub-circuits such as an input / output circuit, a voltage generating circuit for generating various voltages required for the operation of the semiconductor memory device 10, and an error correction circuit for correcting errors of the data DATA read from the memory cell array 20.

[0088] The control logic 37 may be connected to the row decoder 33, the input / output circuit, and the voltage generating circuit. The control logic 37 may control the overall operation of the semiconductor memory device 10. The control logic 37 may generate various internal control signals used in the semiconductor memory device 10 in response to the control signal CTRL. For example, when performing a storage operation such as a program operation or an erase operation, the control logic 37 may adjust the voltage levels supplied to the word lines WL and the bit lines BL.

[0089] The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and may select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL in the selected at least one memory cell block BLK1 to BLKn. In addition, the row decoder 33 may transmit a voltage for performing a storage operation to the word line WL of the selected at least one memory cell block BLK1 to BLKn.

[0090] The page buffer 35 may be connected to the memory cell array 20 via the bit line BL. The page buffer 35 may operate as a write driver or a sense amplifier. Specifically, when a program operation is performed, the page buffer 35 operates as a write driver to apply a voltage to the bit line BL based on the data DATA to be stored in the memory cell array 20. On the other hand, when a read operation is performed, the page buffer 35 may operate as a sense amplifier to detect the data DATA stored in the memory cell array 20.

[0091] Fig.11 is a circuit diagram illustrating a semiconductor memory device according to some embodiments.

[0092] refer to Fig.11 , a memory cell array (eg, Fig.10 20) includes a common source line CSL, a plurality of bit lines BL and a plurality of cell strings CSTR.

[0093] The common source line CSL may extend in the first direction X. In some embodiments, a plurality of common source lines CSL may be arranged in a two-dimensional manner. For example, a plurality of common source lines CSL may be spaced apart from each other and extend in the first direction X. The same voltage may be applied to the common source lines CSL. In other embodiments, different voltages may be applied to the common source lines CSL individually.

[0094] A plurality of bit lines BL may be arranged in a two-dimensional manner. For example, the bit lines BL may be spaced apart from each other and extend in a second direction Y intersecting the first direction X. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell string CSTR may be connected to a common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL.

[0095] Each cell string CSTR may include a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. Each memory cell transistor MCT may include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistor MCT may be connected in series to each other.

[0096] The common source line CSL may be commonly connected to the source of the ground selection transistor GST. In addition, the ground selection line GSL, a plurality of word lines WL11 to WL1n and WL21 to WL2n, and a string selection line SSL may be provided between the common source line CSL and the bit line BL. The ground selection line GSL may serve as a gate electrode of the ground selection transistor GST. The word lines WL11 to WL1n and WL21 to WL2n may serve as gate electrodes of the memory cell transistors MCT, respectively. The string selection line SSL may serve as a cell gate electrode of the string selection transistor SST.

[0097] In some embodiments, the erase control transistor ECT may be disposed between a common source line CSL and a ground selection transistor GST. The common source line CSL may be commonly connected to the source of the erase control transistor ECT. In addition, the erase control line ECL may be disposed between the common source line CSL and the ground selection line GSL. The erase control line ECL may serve as a cell gate electrode of the erase control transistor ECT. The erase control transistor ECT may generate a gate induced drain leakage current (GIDL) to perform an erase operation of the memory cell array.

[0098] Fig.12 is a schematic diagram illustrating a semiconductor memory device according to some embodiments. Fig.13 It is used to show Fig.12 Magnified view of region R1 in FIG.

[0099] refer to Figure 12 to Figure 13 According to some embodiments, a semiconductor memory device includes a memory cell region CELL and a peripheral circuit region PERI. The memory cell region CELL may be stacked on the peripheral circuit region PERI.

[0100] The memory cell region CELL may include a cell substrate 100 , an insulating substrate 101 , mold structures MS1 and MS2 , interlayer insulating films 140 a and 140 b , a channel structure CH, a channel pad 136 , a bit line BL, a cell contact 162 , a source contact 164 , a through via 166 , and a first wiring structure 180 .

[0101] The unit substrate 100 may include, for example, a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. In other embodiments, the unit substrate 100 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some embodiments, the unit substrate 100 may include impurities. For example, the unit substrate 100 may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0102] The unit substrate 100 may include a cell array region CAR and an extension region EXT.

[0103] A memory cell array including a plurality of memory cells (eg, Fig.10 20) may be formed in the cell array region CAR. For example, the channel structure CH, the bit line BL and the cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2, etc., which will be described below, may be disposed in the cell array region CAR. In the following description, the surface of the unit substrate 100 on which the memory cell array is disposed may be referred to as the front side of the unit substrate 100. The surface of the unit substrate 100 opposite to the front side of the unit substrate 100 may be referred to as the back side of the unit substrate 100.

[0104] The extension region EXT may be disposed around the cell array region CAR. Gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 to be described below may be disposed in the extension region EXT and may be stacked in a stepped manner.

[0105] In some embodiments, the unit substrate 100 may further include a through region THR. The through region THR may be disposed in the cell array region CAR and the extension region EXT, or may be disposed outside the cell array region CAR and the extension region EXT. A through via 166 to be described later may be disposed in the through region THR.

[0106] The insulating substrate 101 may be formed in the unit substrate 100 and the extension region EXT. The insulating substrate 101 may constitute an insulating region in the unit substrate 100 and the extension region EXT. The insulating substrate 101 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or silicon carbide. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the insulating substrate 101 may be formed in the unit substrate 100 and the through region THR.

[0107] The lower surface of the insulating substrate 101 is only shown as being coplanar with the lower surface of the unit substrate 100. However, this is only an example. In another example, the vertical height of the lower surface of the insulating substrate 101 (i.e., the height in the third direction Z) may be lower than the vertical height of the lower surface of the unit substrate 100.

[0108] The mold structures MS1 and MS2 may be formed on the front side of the unit substrate 100. The mold structures MS1 and MS2 may include a plurality of unit gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 stacked on the unit substrate 100, and a plurality of mold insulating films 110 and 115. Each of the unit gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 and each of the mold insulating films 110 and 115 may have a layered structure extending to the front side of the unit substrate 100 in a parallel manner. The unit gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 may be sequentially stacked on the unit substrate 100 while being spaced apart from each other via each of the mold insulating films 110 and 115.

[0109] In some embodiments, the mold structures MS1 and MS2 may include a first mold structure MS1 and a second mold structure MS2 sequentially stacked on the unit substrate 100 .

[0110] The first mold structure MS1 may include first cell gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n alternately stacked on the cell substrate 100 and a first mold insulating film 110. In some embodiments, the first cell gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n may include an erase control line ECL, ground selection lines GSL1 and GSL2, and a plurality of first word lines WL11 to WL1n sequentially stacked on the cell substrate 100. The ground selection lines GSL1 and GSL2 may include a first ground selection line GSL1 and a second ground selection line GSL2 sequentially stacked. It is shown that the first cell gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n include two ground selection lines GSL1 and GSL2. This is just an example, and the first cell gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n may include three or more ground selection lines. In some other embodiments, the erase control line ECL may be omitted.

[0111] The second mold structure MS2 may include second cell gate electrodes WL21 to WL2n, SSL1, and SSL2 alternately stacked on top of each other and disposed on the first mold structure MS1, and a second mold insulating film 115. In some embodiments, the second cell gate electrodes WL21 to WL2n, SSL1, and SSL2 may include a plurality of second word lines WL21 to WL2n and string selection lines SSL1 and SSL2 sequentially stacked on the first mold structure MS1. The string selection lines SSL1 and SSL2 may include first string selection lines SSL1 and second string selection lines SSL2 sequentially stacked. It is shown that the second cell gate electrodes WL21 to WL2n, SSL1, and SSL2 include only two string selection lines SSL1 and SSL2. This is merely an example, and the second cell gate electrodes WL21 to WL2n, SSL1, and SSL2 may include three or more string selection lines.

[0112] Each of the cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 may be made of a conductive material, for example, a metal such as tungsten (W), cobalt (Co), and / or nickel (Ni), or a semiconductor material such as silicon. However, the embodiments of the present disclosure are not limited thereto.

[0113] The mold insulating films 110 and 115 may each include an insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments of the present disclosure are not limited thereto.

[0114] In some embodiments, the mold structures MS1 and MS2 in the through region THR may include a plurality of mold sacrificial films 112 and 117 and a plurality of mold insulating films 110 and 115 alternately stacked on the unit substrate 100 and / or the insulating substrate 101. Each of the mold sacrificial films 112 and 117 and each of the mold insulating films 110 and 115 may have a layered structure extending in a parallel manner to the upper surface of the unit substrate 100. The mold sacrificial films 112 and 117 may be sequentially stacked on the unit substrate 100 while being spaced apart from each other via each of the mold insulating films 110 and 115.

[0115] In some embodiments, the first mold structure MS1 in the through region THR may include first mold sacrificial films 112 and first mold insulating films 110 alternately stacked on the unit substrate 100. The second mold structure MS2 in the through region THR may include second mold sacrificial films 117 and second mold insulating films 115 alternately stacked on the first mold structure MS1.

[0116] The molded sacrificial films 112 and 117 may each include an insulating material, such as silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the molded sacrificial films 112 and 117 may each include a material having an etching selectivity relative to the material of the molded insulating films 110 and 115. In one example, the molded insulating films 110 and 115 may each include silicon oxide, and the molded sacrificial films 112 and 117 may each include silicon nitride.

[0117] Interlayer insulating films 140a and 140b may be formed on the unit substrate 100 to be located on the mold structures MS1 and MS2 and to at least partially cover the mold structures MS1 and MS2. In some embodiments, the interlayer insulating films 140a and 140b may include a first interlayer insulating film 140a and a second interlayer insulating film 140b sequentially stacked on the unit substrate 100. The first interlayer insulating film 140a may be located on the first mold structure MS1 and at least partially cover the first mold structure MS1, and the second interlayer insulating film 140b may be located on the second mold structure MS2 and at least partially cover the second mold structure MS1. The interlayer insulating films 140a and 140b may include, for example, at least one of silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. However, embodiments of the present disclosure are not limited thereto.

[0118] The channel structure CH may be formed in the cell array region CAR and the mold structures MS1 and MS2. The channel structure CH may extend in a vertical direction (hereinafter referred to as a third direction Z) intersecting the upper surface of the cell substrate 100, and may extend through the mold structures MS1 and MS2. For example, the channel structure CH may have a columnar shape (e.g., a cylindrical shape) extending in the third direction Z. Therefore, the channel structure CH may intersect each of the cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. In some embodiments, the channel structure CH may have a step portion between the first mold structure MS1 and the second mold structure MS2.

[0119] The channel structure CH may include a semiconductor pattern 130 and an information storage film 132 .

[0120] The semiconductor pattern 130 may extend in the third direction Z and may extend through the mold structures MS1 and MS2. Although the semiconductor pattern 130 is shown only in a cup shape, this is only an example. In another example, the semiconductor pattern 130 may have various shapes, such as a cylindrical shape, a rectangular shape, and a solid column shape. The semiconductor pattern 130 may include, for example, a semiconductor material such as single crystal silicon, polycrystalline silicon, an organic semiconductor material, and a carbon nanostructure. However, the embodiments of the present disclosure are not limited thereto.

[0121] The information storage film 132 may be interposed between the semiconductor pattern 130 and each of the cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. For example, the information storage film 132 may extend along and on the outer surface of the semiconductor pattern 130. The information storage film 132 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0122] In some embodiments, the information storage film 132 may be composed of multiple layers. For example, the information storage film 132 may include a tunnel insulating film 132 a , a charge storage film 132 b , and a blocking insulating film 132 c sequentially stacked on the outer surface of the semiconductor pattern 130 .

[0123] The tunnel insulating film 132a may include, for example, silicon oxide or a high dielectric constant material having a dielectric constant higher than that of silicon oxide (eg, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 )). The charge storage film 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high dielectric constant material having a dielectric constant higher than that of silicon oxide (eg, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 )).

[0124] In some embodiments, the channel structure CH may further include a filling pattern 134. The filling pattern 134 may be formed to at least partially fill the inside of the cup-shaped semiconductor pattern 130. The filling pattern 134 may include an insulating material such as silicon oxide. However, the embodiments of the present disclosure are not limited thereto.

[0125] In some embodiments, the channel structure CH may further include a channel pad 136. The channel pad 136 may be formed to be connected to the top of the semiconductor pattern 130. The channel pad 136 may include, for example, polysilicon doped with impurities. However, embodiments of the present disclosure are not limited thereto.

[0126] In some embodiments, the plurality of channel structures CH may be arranged in a zigzag manner. For example, the plurality of channel structures CH may be arranged in a zigzag manner in a first direction Y and a second direction X parallel to the upper surface of the unit substrate 100. The plurality of channel structures CH arranged in a zigzag manner may further improve the integration density of the semiconductor memory device. In some embodiments, the plurality of channel structures CH may be arranged in a honeycomb manner.

[0127] In some embodiments, a dummy channel structure DCH may be formed in the mold structures MS1 and MS2 and the extension region EXT. The dummy channel structure DCH may be formed in a shape similar to that of the channel structure CH to reduce stress applied to the mold structures MS1 and MS2 in the extension region EXT.

[0128] In some embodiments, the first source structures 102 and 104 may be formed on the unit substrate 100. The first source structures 102 and 104 may be interposed between the unit substrate 100 and the mold structures MS1 and MS2. For example, the first source structures 102 and 104 may extend along the upper surface of the unit substrate 100. The first source structures 102 and 104 may be formed to contact the semiconductor pattern 130 of the channel structure CH. For example, the first source structures 102 and 104 may extend through the information storage film 132 to contact the semiconductor pattern 130. The first source structures 102 and 104 may be provided as a common source line (e.g., Fig.11 The first source structures 102 and 104 may include, for example, metal or impurity-doped polysilicon. However, the embodiments of the present disclosure are not limited thereto.

[0129] In some embodiments, the channel structure CH may extend through the first source structures 102 and 104. For example, a lower end of the channel structure CH may extend through the first source structures 102 and 104 to be disposed within the unit substrate 100.

[0130] In some embodiments, the first source structures 102 and 104 may be formed as a stack of multiple layers. For example, the first source structures 102 and 104 may include a first source layer 102 and a second source layer 104 sequentially stacked on the unit substrate 100. Each of the first source layer 102 and the second source layer 104 may include impurity-doped polysilicon or non-impurity-doped polysilicon. However, the embodiments of the present disclosure are not limited thereto. The first source layer 102 may contact the semiconductor pattern 130 to serve as a common source line (e.g., Fig.11 The second source layer 104 may be used as a support layer to reduce the possibility of or prevent the mold stack from collapsing or falling during the replacement process of forming the first source layer 102.

[0131] Although not shown, a base insulating film may be interposed between the unit substrate 100 and the first source structures 102 and 104. For example, the base insulating film may include silicon oxide, silicon nitride, and / or silicon oxynitride, but is not limited thereto.

[0132] In some embodiments, the first source structures 102 and 104 may not be formed in the portion of the extension region EXT where the insulating substrate 101 is formed. The upper surface of the insulating substrate 101 is shown to be coplanar with the upper surfaces of the first source structures 102 and 104. This is just an example. In another example, the vertical height of the upper surface of the insulating substrate 101 (i.e., the height in the third direction Z) may be higher than the vertical height of the upper surfaces of the first source structures 102 and 104.

[0133] In some embodiments, the source sacrificial film 103 may be formed on a portion of the unit substrate 100. For example, the source sacrificial film 103 may be formed on a portion of the unit substrate 100 in the extension region EXT. The source sacrificial film 103 may include a material having an etching selectivity relative to the materials of the mold insulating films 110 and 115. In one example, the mold insulating films 110 and 115 may each include silicon oxide, and the source sacrificial film 103 may include silicon nitride. The source sacrificial film 103 may be a layer remaining after a portion of the source sacrificial film 103 is replaced with the first source layer 102 during the manufacturing process of the first source structures 102 and 104.

[0134] Each of the block isolation region WCf, the first partial isolation region WC1, and the second partial isolation region WC2 may extend in the first direction X to cut the mold structures MS1 and MS2. The block isolation region WCf may cut the entire mold structures MS1 and MS2. For example, the block isolation region WCf may extend continuously in the first direction X. Each of the first partial isolation region WC1 and the second partial isolation region WC2 may cut a portion of the mold structures MS1 and MS2. For example, the first partial isolation regions WC1 arranged in the first row along the first direction X may be spaced apart from each other, and thus the mold structures MS1 and MS2 may be partially cut. The second partial isolation regions WC2 arranged in the first row along the first direction X may be spaced apart from each other, and thus the mold structures MS1 and MS2 may be partially cut.

[0135] The bit line BL may be formed on the mold structures MS1 and MS2. The bit line BL may extend in the second direction Y to intersect the block isolation region WCf. In addition, the bit line BL may extend in the second direction Y to contact a plurality of channel structures CH arranged along the second direction Y. For example, a bit line contact 182 contacting the top of each channel structure CH may be formed in the second interlayer insulating film 140b. The bit line BL may be electrically connected to the channel structure CH via the bit line contact 182.

[0136] The cell contact 162 may contact each of the cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. For example, the cell contact 162 may extend in the third direction Z and in the interlayer insulating films 140a and 140b to contact each of the cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. In some embodiments, the cell contact 162 may have a step portion between the first mold structure MS1 and the second mold structure MS2.

[0137] The source contact 164 may contact the first source structures 102 and 104. For example, the source contact 164 may extend along the third direction in the interlayer insulating films 140a and 140b to contact the unit substrate 100. In some embodiments, the source contact 164 may have a stepped portion between the first and second mold structures MS1 and MS2.

[0138] The through passage 166 may be disposed in the through region THR. For example, the through passage 166 may extend in the third direction Z and be disposed in the mold structures MS1 and MS2 and the through region THR. In some embodiments, the through passage 166 may have a step portion between the first mold structure MS1 and the second mold structure MS2. Only the through passage 166 extending through the mold structures MS1 and MS2 is shown. This is just an example. In another example, the through passage 166 may be disposed outside the mold structures MS1 and MS2 and may not extend through the mold structures MS1 and MS2.

[0139] Each of the cell contact 162, the source contact 164, and the through via 166 may be in contact with a first wiring structure 180 disposed on the interlayer insulating films 140a and 140b. For example, the second wiring insulating film 142 may be formed on the second interlayer insulating film 140b. The first wiring structure 180 may be formed in the second wiring insulating film 142. Each of the cell contact 162, the source contact 164, and the through via 166 may be connected to the first wiring structure 180 via a contact via 184. Although not specifically shown, the first wiring structure 180 may be connected to the bit line BL.

[0140] The peripheral circuit region PERI may include a substrate 200 , a peripheral circuit element PT, and a second wiring structure 270 .

[0141] The peripheral circuit element PT may be formed on the substrate 200. The peripheral circuit element PT may constitute a peripheral circuit (eg, Fig.10 30 in ). For example, the peripheral circuit element PT may include control logic (e.g., Fig.10 37), row decoder (e.g., Fig.10 33) and page buffers (e.g., Fig.10 35). In the following description, the surface of the substrate 200 on which the peripheral circuit element PT is disposed may be referred to as the front side of the substrate 200. On the other hand, the surface of the substrate 200 opposite to the front side of the substrate 200 may be referred to as the back side of the substrate 200.

[0142] The peripheral circuit elements PT may include, for example, Figures 1 to 9 However, the embodiments of the present disclosure are not limited thereto. For example, in addition to the above reference Figures 1 to 9 The peripheral circuit element PT may include various active elements and various passive elements such as capacitors, resistors, and inductors in addition to the described transistors.

[0143] In some embodiments, the back side of the unit substrate 100 may face the front side of the substrate 200. For example, a first inter-wiring insulating film 240 located on and at least partially covering the peripheral circuit element PT may be formed on the front side of the substrate 200. The unit substrate 100 and / or the insulating substrate 101 may be stacked on an upper surface of the first inter-wiring insulating film 240.

[0144] The first wiring structure 180 may contact the peripheral circuit element PT via the through via 166. For example, the second wiring structure 270 contacting the peripheral circuit element PT may be formed in the first inter-wiring insulating film 240. The through via 166 may extend in the third direction Z to connect the first wiring structure 180 and the second wiring structure 270 to each other. Therefore, the bit line BL, the cell gate electrodes ECL, GSL1, GSL2, each of WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2, and / or the first source structures 102 and 104 may be electrically connected to the peripheral circuit element PT.

[0145] In some embodiments, the through via 166 may extend through the insulating substrate 101 to connect the first wiring structure 180 and the second wiring structure 270 to each other. Thus, the through via 166 may be electrically insulated from the unit substrate 100.

[0146] Fig.14 is a schematic diagram showing a semiconductor memory device according to some embodiments. For ease of description, the following description is based on its Figures 10 to 13 The differences described in .

[0147] refer to Fig.14 , in the semiconductor memory device according to some embodiments, the front surface of the unit substrate 100 faces the front surface of the substrate 200 .

[0148] For example, a semiconductor memory device according to some embodiments may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure in which an upper chip including a memory cell region CELL is disposed on a first wafer (e.g., a cell substrate 100), and a lower chip including a peripheral circuit region PERI is disposed on a second wafer (e.g., a substrate 200) different from the first wafer, and then the upper chip and the lower chip are connected to each other in a bonding scheme.

[0149] In one example, the bonding scheme means a scheme of electrically connecting the first bonding metal 190 formed in the uppermost metal layer of the upper chip and the second bonding metal 290 formed in the uppermost metal layer of the lower chip to each other. For example, when the first bonding metal 190 and the second bonding metal 290 are both made of copper (Cu), the bonding scheme can be implemented as a Cu-Cu bonding scheme. However, this is only an example. In another example, the first bonding metal 190 and the second bonding metal 290 can be made of various other metals such as aluminum (Al) or tungsten (W).

[0150] When the first bonding metal 190 and the second bonding metal 290 are bonded to each other, the first wiring structure 180 may be connected to the second wiring structure 270. Therefore, the bit line BL, each cell gate electrode ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2, and / or the first source structures 102 and 104 may be electrically connected to the peripheral circuit element PT.

[0151] Fig.15 is a schematic diagram showing a semiconductor memory device according to some embodiments. For ease of description, the following description is based on its Figures 10 to 13 The differences described in .

[0152] refer to Fig.15 , a semiconductor memory device according to some embodiments includes a memory cell region CELL and a peripheral circuit region PERI.

[0153] and Fig.12Unlike what is shown in the figure, the peripheral circuit region PERI may be arranged around the memory cell region CELL. The peripheral circuit region PERI may include a peripheral circuit element PT. Although not shown, a through-path may be arranged on the peripheral circuit region PERI. The peripheral circuit element PT may be electrically connected to the bit line BL, each cell gate electrode ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, SSL2 and / or the first source structures 102 and 104 via the through-path.

[0154] In the following, reference will be made to Figures 16 to 18 An electronic system including a semiconductor memory device according to illustrative embodiments is described.

[0155] Fig.16 is a block diagram illustrating an electronic system according to some embodiments. Fig.17 is a perspective view illustrating an electronic system according to some embodiments. Fig.18 It is along Fig.17 Schematic cross-sectional view taken along line II.

[0156] refer to Fig.16 , the electronic system 1000 according to some embodiments may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be implemented as a solid state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor memory devices 1100.

[0157] The semiconductor memory device 1100 may be implemented as, for example, a nonvolatile memory device (eg, a NAND flash memory device), and may include, for example, the memory device described above with reference to FIG. Figures 10 to 15 The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0158] The first structure 1100F may include a decoder circuit 1110 (eg, Fig.10 , the row decoder 33 in the page buffer 1120 (eg, Fig.10 , and logic circuits 1130 (eg, Fig.10 The peripheral circuit structure of the control logic 37).

[0159] , the second structure 1100S may include the above reference Figure 2The common source line CSL, multiple bit lines BL and multiple cell strings CSTR may be connected to the decoder circuit 1110 via word lines WL, at least one string selection line SSL and at least one ground selection line GSL. In addition, the cell string CSTR may be connected to the page buffer 1120 via the bit lines BL.

[0160] In some embodiments, the common source line CSL and the cell string CSTR may be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The first connection line 1115 may correspond to the first connection line 1115 used as described above. Figures 10 to 15 That is, the through via 166 can connect each of the cell gate electrodes ECL, GSL1, GSL2, WL, and SSL to the decoder circuit 1110 (eg, Fig.10 The row decoders 33 in are electrically connected to each other.

[0161] In some embodiments, the bit line BL may be electrically connected to the page buffer 1120 via a second connection line 1125 extending from the first structure 1100F to the second structure 1100S. The second connection line 1125 may correspond to the first structure 1100F and the second structure 1100S. Figures 10 to 15 That is, the through-via 166 can connect the bit line BL and the page buffer 1120 (eg, Fig.10 The page buffers 35 in are electrically connected to each other.

[0162] The semiconductor memory device 1100 may be electrically connected to a logic circuit 1130 (eg, Fig.10 The input / output pads 1101 of the control logic 37 in the first structure 1100F communicate with the controller 1200. The input / output pads 1101 may be electrically connected to the logic circuit 1130 via input / output connection lines 1135 extending from the first structure 1100F to the second structure 1100S.

[0163] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100. In this case, the controller 1200 may control the plurality of semiconductor memory devices 1100.

[0164] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate based on predefined firmware, and may control the NAND controller 1220 to access the semiconductor memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor memory device 1100. Through the NAND interface 1221, a control command for controlling the semiconductor memory device 1100, data to be written to the memory cell transistor MCT of the semiconductor memory device 1100, and data to be read from the memory cell transistor MCT of the semiconductor memory device 1100 may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. Upon receiving a control command from an external host via the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

[0165] refer to Figure 17 to Figure 18 , an electronic system according to some embodiments may include a main substrate 2001, a main controller 2002 mounted on the main substrate 2001, at least one semiconductor package 2003, and at least one DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through a wiring pattern 2005 formed on the main substrate 2001.

[0166] The main substrate 2001 may include a connector 2006 containing a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary based on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with an external host using interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), M-Phy (Universal Flash Storage) for UFS, etc. In some embodiments, the electronic system 2000 may operate using power supplied from an external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from an external host to the controller 2002 and the semiconductor package 2003.

[0167] The main controller 2002 may write data to or read data from the semiconductor package 2003 , and may increase the operating speed of the electronic system 2000 .

[0168] The DRAM 2004 may function as a buffer memory for reducing the difference in operating speed between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may function as a cache memory and may provide a space for temporarily storing data therein in a control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the main controller 2002 may include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0169] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be implemented as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 located on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100 to each other, and a mold layer 2500 disposed on the package substrate 2100 and at least partially covering the semiconductor chips 2200 and the connection structure 2400.

[0170] The package substrate 2100 may be implemented as a printed circuit board including the package pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.16 The input / output pad 1101 in.

[0171] In some embodiments, the connection structure 2400 may be implemented as a bonding wire that electrically connects the input / output pad 2210 and the package upper pad 2130 to each other. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire scheme, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including a through electrode (through silicon via: TSV) instead of a connection structure 2400 using a bonding wire scheme.

[0172] In some embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in one package. In some embodiments, the main controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the main controller 2002 and the semiconductor chip 2200 may be connected to each other via wiring formed in the interposer substrate.

[0173] In some embodiments, the package substrate 2100 may be implemented as a printed circuit board. The package substrate 2100 may include: a package substrate body 2120; a package upper pad 2130 disposed on the upper surface of the package substrate body 2120; a package lower pad 2125 disposed on the lower surface of the package substrate body 2120 or exposed through the lower surface thereof; and an internal line 2135 disposed in the package substrate body 2120 to electrically connect the upper pad 2130 and the lower pad 2125 to each other. The upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to the wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 via a conductive connector 2800, such as Fig.18 shown.

[0174] In the electronic system according to some embodiments, each semiconductor chip 2200 may include the above-mentioned Figures 10 to 15 For example, each semiconductor chip 2200 may include a peripheral circuit region PERI and a memory cell region CELL stacked on the peripheral circuit region PERI. In an example, the peripheral circuit region PERI may include the above-described Figures 1 to 9 In addition, in the example, the memory cell region CELL may include the transistors described above. Figures 10 to 15 The unit substrate 100, the mold structures MS1 and MS2, and the channel structure CH.

[0175] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above-described embodiments, but can be implemented in various different forms. It will be appreciated by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or basic characteristics of the present disclosure. Therefore, it should be understood that the above-described embodiments are not restrictive in all aspects, but illustrative.

[0176] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the exemplary embodiments without departing substantially from the principles of the inventive concept. Therefore, the disclosed exemplary embodiments of the present invention are used in a general and descriptive sense only and not for a limiting purpose.

Claims

1. A transistor, comprising: a substrate, the substrate comprising an active region; an element isolation film in the substrate, wherein the element isolation film defines the active area; a first impurity region located on a lower surface of the element isolation film; a second impurity region, the second impurity region being located in the substrate; a gate electrode, the gate electrode being located on the substrate and extending in a second direction; a source / drain region, the source / drain region being located on at least one side of the gate electrode; a first source / drain contact group, the first source / drain contact group being located on the source / drain region; as well as a second source / drain contact set, the second source / drain contact set being located on the source / drain region and spaced apart from the first source / drain contact set in the second direction, The second impurity region is located between the first source / drain contact group and the second source / drain contact group.

2. The transistor according to claim 1, wherein The second impurity region is located in the substrate and extends in a first direction intersecting the second direction.

3. The transistor according to claim 1, wherein: The first impurity region and the second impurity region contain dopants of the same conductivity type.

4. The transistor according to claim 1, wherein The number of source / drain contacts of the first source / drain contact group is equal to the number of source / drain contacts of the second source / drain contact group.

5. The transistor according to claim 1, wherein A distance between the first impurity region and an upper surface of the substrate is different from a distance between the second impurity region and the upper surface of the substrate.

6. The transistor according to claim 1, wherein A distance between the first impurity region and an upper surface of the substrate is equal to a distance between the second impurity region and the upper surface of the substrate.

7. The transistor according to claim 1, wherein Each of the first impurity region and the second impurity region includes a P-type dopant.

8. The transistor according to claim 1, wherein The source / drain region includes: a third impurity region, the third impurity region being in contact with the first source / drain contact group; and a fourth impurity region, the fourth impurity region being located between the third impurity region and the gate electrode, The concentration of the N-type impurities in the third impurity region is greater than the concentration of the N-type impurities in the fourth impurity region.

9. The transistor according to claim 8, wherein: The first source / drain contact group includes a plurality of first source / drain contacts, The third impurity region includes a plurality of sub-impurity regions respectively contacting and overlapping with the plurality of first source / drain electrodes in a third direction perpendicular to the upper surface of the substrate.

10. The transistor of claim 1, further comprising a third source / drain contact set located on the source / drain region and spaced apart from the second source / drain contact set in the second direction, in, The spacing between the first source / drain contact group and the second source / drain contact group in the second direction is equal to the spacing between the second source / drain contact group and the third source / drain contact group in the second direction.

11. A transistor, comprising: a substrate, the substrate comprising an active region; a gate electrode, the gate electrode being located on the substrate and extending in a second direction; an element isolation film in the substrate, wherein the element isolation film defines the active area; a first impurity region located on a lower surface of the element isolation film; a second impurity region located in the substrate and extending in a first direction intersecting the second direction; a source / drain region, the source / drain region being located on at least one side of the gate electrode; a first source / drain contact group, the first source / drain contact group being located on the source / drain region; as well as a second source / drain contact set, the second source / drain contact set being located on the source / drain region and spaced apart from the first source / drain contact set in the second direction, The source / drain region includes: a third impurity region in contact with the first source / drain contact group; and a fourth impurity region located between the third impurity region and the gate electrode. The concentration of the N-type impurities in the third impurity region is greater than the concentration of the N-type impurities in the fourth impurity region. The second impurity region does not overlap with the first source / drain contact group in a third direction perpendicular to the upper surface of the substrate.

12. The transistor according to claim 11, wherein The second impurity region is located between the first source / drain contact group and the second source / drain contact group.

13. The transistor according to claim 11, wherein The first impurity region and the second impurity region contain dopants of the same conductivity type.

14. The transistor according to claim 11, wherein The second impurity region does not overlap with the first source / drain contact group in the second direction.

15. The transistor according to claim 11, wherein In a top view of the transistor, the substrate surrounds the second impurity region.

16. The transistor according to claim 11, wherein The number of source / drain contacts of the first source / drain contact group is equal to the number of source / drain contacts of the second source / drain contact group.

17. The transistor according to claim 11, wherein Each of the first impurity region and the second impurity region includes a P-type dopant.

18. A semiconductor memory device, comprising: a peripheral circuit structure, the peripheral circuit structure comprising a transistor; as well as a unit structure, the unit structure being located on the peripheral circuit structure, The unit structure includes: a unit substrate; a mold structure including a plurality of unit gate electrodes sequentially stacked on the unit substrate; and a channel structure extending through the plurality of unit gate electrodes. The transistor includes: a substrate including an active region; an element isolation film in the substrate defining the active region; a first impurity region located on a lower surface of the element isolation film; a second impurity region located in the substrate; a gate electrode located on the substrate and extending in a second direction; a source / drain region located on at least one side of the gate electrode; a first source / drain contact group located on the source / drain region; and a second source / drain contact group located on the source / drain region and spaced apart from the first source / drain contact group in the second direction. The second impurity region is located between the first source / drain contact group and the second source / drain contact group.

19. The semiconductor memory device according to claim 18, wherein: the second impurity region is located in the substrate and extends in a first direction intersecting the second direction, The first impurity region and the second impurity region contain dopants of the same conductivity type.

20. The semiconductor memory device according to claim 18, wherein The unit structure is stacked on the peripheral circuit structure.

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