Solid-state imaging device with low fixed mode noise

Abstract

An imaging apparatus (201) is provided in which a sidewall spacer (74) width of a transfer gate device (TX) is greater than a sidewall spacer (71, 72, 73) width of other in-pixel devices. According to the invention, GIDL and GISL in a photodiode (PD) region and a floating diffusion (FD) region can be reduced, and contact and grid spacing of devices in pixels can be reduced at the same time.

Description

[0001] This application is a divisional application. The application number of the original application is 202080105567.9, and the original application date is September 30, 2020. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present invention relates to an imaging device and a method for manufacturing the same. Background Art

[0003] High-resolution imaging devices, such as image sensors for cameras in mobile devices, have been developed, and the number of pixels provided in imaging devices is increasing. As the pixel size decreases, it is inevitable to reduce the width of the sidewall spacers of devices such as transistors on the semiconductor substrate. Therefore, the electric field becomes higher to meet the constant voltage scaling. Gate induced drain leakage (GIDL) and gate induced source leakage (GISL) in particular become more serious.

[0004] In the prior art, the sidewall spacers arranged on the photodiode (PD) side are narrower than those arranged on the floating diffusion (FD) side, so that the effective photodiode area is increased and the full well capacity is improved. However, this will cause GISL problems during charge accumulation and produce higher fixed pattern noise and higher dark signal non-uniformity. Summary of the invention

[0005] The present invention provides an imaging device to reduce GIDL and GISL in the photodiode and floating diffusion regions while reducing the contact and gate spacing of devices within the pixel.

[0006] According to a first aspect, an imaging device is provided, comprising a plurality of pixels, each pixel comprising a transfer gate device, a reset device, a source follower device and a row selection device, wherein the transfer gate device has a sidewall spacer width greater than the sidewall spacer widths of other devices in the pixel.

[0007] In a possible implementation manner of the first aspect, a difference between a width of the sidewall spacer of the transmission gate device and a width of the sidewall spacer of the other in-pixel devices is equal to or greater than 3 nanometers.

[0008] According to a second aspect, an imaging device is provided, wherein the sidewall spacer width of a transfer gate device and the sidewall spacer width of a source side of an adjacent device are greater than the sidewall spacer width of a drain side of the adjacent device and the sidewall spacer widths of a source follower device, a row selection device, and other in-pixel devices, wherein the adjacent device is a device other than the transfer gate device and is disposed adjacent to a floating diffusion.

[0009] In a possible implementation of the second aspect, the sidewall spacer width of the transmission gate device and the sidewall spacer width of the source side of the adjacent device are 3 nanometers or more larger than the sidewall spacer width of the drain side of the adjacent device and the sidewall spacer width of the source follower device, row selection device and other in-pixel devices.

[0010] In a third aspect, an imaging device is provided, wherein the imaging device comprises a plurality of pixels, each pixel comprises a transmission gate device, a reset device, a source follower device and a row selection device, and the gate offset spacer width of the transmission gate device is greater than the gate offset spacer width of other devices in the pixel.

[0011] In a possible implementation manner of the third aspect, a difference between a width of the gate offset spacer of the transmission gate device and a width of the gate offset spacer of the other in-pixel devices is equal to or greater than 3 nanometers.

[0012] According to a fourth aspect, an imaging device is provided. A gate offset spacer width of a transfer gate device and a gate offset spacer width on a source side of an adjacent device are greater than a gate offset spacer width on a drain side of the adjacent device and gate offset spacer widths of a source follower device, a row select device, and other in-pixel devices, wherein the adjacent device is a device other than the transfer gate device and is disposed adjacent to a floating diffusion.

[0013] In a possible implementation of the fourth aspect, the gate offset spacer width of the transmission gate device and the gate offset spacer width on the source side of the adjacent device are 3 nanometers or more larger than the gate offset spacer width on the drain side of the adjacent device and the gate offset spacer width of the source follower device, row selection device and other in-pixel devices.

[0014] In a fifth aspect, a method for manufacturing an imaging device is provided. The method comprises: forming a gate offset spacer on both sides of a transmission gate device and other in-pixel devices; forming an insulating film on the transmission gate device and the other in-pixel devices; etching the insulating film on the other in-pixel devices by isotropic etching; etching the insulating film on the transmission gate device and the other in-pixel devices by anisotropic etching.

[0015] In a sixth aspect, a method for manufacturing an imaging device is provided. The method comprises: forming a gate offset spacer on both sides of a transmission gate device, an adjacent device, and other in-pixel devices, wherein the adjacent device is a device other than the transmission gate device and is arranged adjacent to a floating diffusion; forming an insulating film on the transmission gate device, the adjacent device, and the other in-pixel devices; etching the insulating film on the other in-pixel devices and the drain side of the adjacent device by isotropic etching; etching the insulating film on the transmission gate device, the adjacent device, and the other in-pixel devices by anisotropic etching.

[0016] In a seventh aspect, a method for manufacturing an imaging device is provided. The method comprises: forming an insulating film on a transmission gate device and other in-pixel devices; etching the insulating film on the other in-pixel devices by isotropic etching; etching the insulating film on the transmission gate device and the other in-pixel devices by anisotropic etching; and forming sidewall spacers on both sides of the transmission gate device and the other in-pixel devices.

[0017] In an eighth aspect, a method for manufacturing an imaging device is provided. The method comprises: forming an insulating film on a transmission gate device, an adjacent device, and other in-pixel devices, wherein the adjacent device is a device other than the transmission gate device and is arranged adjacent to a floating diffusion; etching the insulating film on the other in-pixel devices and the drain side of the adjacent device by isotropic etching; etching the insulating film on the transmission gate device, the adjacent device, and the other in-pixel devices by anisotropic etching; and forming sidewall spacers on both sides of the transmission gate device, the adjacent device, and the other in-pixel devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly describe the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. The drawings in the following description only illustrate some embodiments of the present invention, and ordinary technicians in this field can also obtain other drawings based on these drawings without creative work.

[0019] Figure 1 is an exemplary block diagram of imaging system 201 .

[0020] Figure 2 is an exemplary circuit diagram of an imaging device.

[0021] Figure 3 An embodiment of the present invention provides a method for Figure 2 A top view of an exemplary circuit layout formed on a semiconductor substrate of an imaging device is shown.

[0022] Figure 4 is a cross-sectional view of a portion of an imaging device formed on a semiconductor substrate provided by an embodiment of the present invention.

[0023] Figure 5 Another embodiment of the present invention provides a method for Figure 2 A top view of an exemplary circuit layout formed on a semiconductor substrate of an imaging device is shown.

[0024] Figure 6 is a cross-sectional view of a portion of an imaging device formed on a semiconductor substrate provided by an embodiment of the present invention.

[0025] Figure 7 is an exemplary circuit diagram of an imaging device.

[0026] Figure 8 An embodiment of the present invention provides a method for Figure 7 A top view of an exemplary circuit layout formed on a semiconductor substrate of an imaging device is shown.

[0027] Fig. 9 is an exemplary circuit diagram of an imaging device, in which two groups of PD and TX share in-pixel devices.

[0028] Fig.10 is an exemplary circuit diagram of an imaging device, in which four groups of PDs and TXs share in-pixel devices.

[0029] Fig.11 Another embodiment of the present invention provides a method for Fig.10 A top view of an exemplary circuit layout formed on a semiconductor substrate of an imaging device is shown.

[0030] Fig.12 is a cross-sectional view of a portion of an imaging device, wherein the difference between the sidewall spacer width of TX and the sidewall spacer width of other in-pixel devices is caused by the source / drain (S / D) sidewall spacer.

[0031] Fig.13 is a cross-sectional view of a portion of an imaging device, wherein the difference between the sidewall spacer width of TX and the sidewall spacer width of other in-pixel devices is caused by the gate offset spacer.

[0032] Figures 14 to 21 Examples of first through eighth cross-sectional views of a substrate used to manufacture an imaging device according to one example of a manufacturing process are shown.

[0033] Figure 22 to Figure 25 Examples of first through fourth cross-sectional views of a substrate used to manufacture an imaging device according to one example of another manufacturing process are shown.

[0034] Fig.26 is another exemplary block diagram of imaging system 201 .

[0035] Fig. 27 Various applications of the camera system are shown. DETAILED DESCRIPTION

[0036] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should belong to the scope of protection of the present invention.

[0037] Figure 1 2 is an exemplary block diagram of an imaging system 201. The imaging system 201 includes a control circuit 205, a pixel array 209, a readout circuit 210, and a signal processing circuit 206. The pixel array 205 is a two-dimensional array of pixels. Each pixel can be Figure 2 The imaging device shown in FIG. Pixels are arranged in rows (R1 to Ry) and columns (C1 to Cx) to obtain image data of a subject. The control circuit 205 controls the pixel array 209, for example, generates a shutter signal. The image data is read out by the readout circuit 210 through the bit line and sent to the signal processing circuit 206.

[0038] Figure 2 is an exemplary circuit diagram of an imaging device, which may be Figure 1 The photodiode (PD) converts light into electric charge. The electric charge is selectively transferred to the floating diffusion (FD) through the transfer gate device (TX). The FD is connected to the gate of the source follower device (SF), and the output signal (Vout) is transmitted to the signal line through the row selection device (SEL). The current source (Icolumn) is connected between SEL and ground. Therefore, if the gates of TX and SEL are turned on, an output signal corresponding to the electric signal from the PD is obtained on the signal line. The reset device (RST) selectively resets the charge accumulated in the FD. The dual conversion gain device (DCG) (not in Figure 2 shown in Figure 7 ) can be connected between RST and FD to achieve a high dynamic range by combining the two types of gain.

[0039] Figure 3 An embodiment of the present invention provides a method for Figure 2FIG. 1 is a top view of an exemplary circuit layout formed on a semiconductor substrate of an imaging device shown in FIG. Figure 4 is a cross-sectional view of a portion of an imaging device formed on a semiconductor substrate provided by an embodiment of the present invention. The sidewall spacer width on the FD side is sensitive to GIDL. Therefore, the sidewall spacer width (Wt) of TX is larger than the sidewall spacer width (Wd) of other in-pixel devices including RST, SF, SEL and DCG. The difference between Wt and Wd is equal to or greater than 3 nanometers (nm). The transmission gate device (TX) can be planar or vertical.

[0040] Figure 5 Another embodiment of the present invention provides a method for Figure 2 A top view of an exemplary circuit layout formed on a semiconductor substrate of an imaging device shown in FIG. It should be noted that the width of the sidewall spacer 74 and the right side of the sidewall spacer 73 (the side where the wiring shown in bold line is provided between FD and RST) are greater than the width of the left side, upper side, and lower side of the sidewall spacer 73 (the sides where no wiring is provided between FD and RST) and the width of the sidewall spacers 71 and 72. Figure 6 1 is a cross-sectional view of a portion of an imaging device formed on a semiconductor substrate provided by an embodiment of the present invention. The sidewall spacer width of TX and the sidewall spacer width of the source side (S) of RST are greater than the width of the drain side (D) of RST and the width of the source and drain (S / D) sides of SF, SEL, and other in-pixel devices.

[0041] As mentioned above, DCG devices can be Figure 7 The connection shown is between the RST device and FD. Figure 8 Another embodiment of the present invention provides a method for Figure 7 A top view of an exemplary circuit layout formed on a semiconductor substrate of an imaging device shown in FIG. It should be noted that the width of the sidewall spacer 74 and the width of the right side of the sidewall spacer 75 (the side where the wiring shown in bold is provided between FD and DCG) are greater than the width of the left side, top side, and bottom side of the sidewall spacer 75 (the sides where no wiring is provided between FD and DCG) and the width of the sidewall spacers 71, 72, and 73. Figure 5 In , RST is a device other than TX and is set adjacent to FD. Figure 8 In the example, RST is a device other than TX and is set adjacent to FD.

[0042] Figure 2 and Figure 7 The imaging device in the PD includes one PD. However, the in-pixel device can be shared by multiple PDs. Fig. 9The imaging device in includes two groups of PD and TX that share other in-pixel devices. Fig.10 The imaging device in includes four groups of PD and TX that share other in-pixel devices. Fig.11 Another embodiment of the present invention provides a method for Fig.10 1 is a top view of an exemplary circuit layout formed on a semiconductor substrate of an imaging device shown in FIG. It should be noted that the width of the sidewall spacer 74 and the width of the lower side of the sidewall spacer 75 (the side where the wiring shown by the thick line is arranged between FD and DCG) are greater than the width of the left side, right side and upper side of the sidewall spacer 75 (the sides where no wiring is arranged between FD and DCG) and the width of the sidewall spacers 71, 72 and 73. The embodiment of the present invention can also be applied to more than 4 groups of PD and TX that share devices in a pixel.

[0043] exist Figure 4 In the example, the difference between the sidewall spacer width of TX and the sidewall spacer width of other devices in the pixel is given by Fig.12 The source / drain (S / D) sidewall spacer shown in FIG. The material of the S / D sidewall spacer can be oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON) or other insulating materials. The S / D sidewall spacer can be a single layer or multiple layers. The above difference can be caused by Fig.13 The gate offset spacer shown in the figure is formed by the gate offset spacer. The material of the gate offset spacer can be oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON) or other insulating materials. Figures 14 to 21 Describes the manufacturing process used in the second case, while reference Figure 22 to Figure 25 Describe the manufacturing process used in the first case.

[0044] refer to Figures 14 to 21 , an example of a manufacturing process of an imaging device provided by an embodiment of the present invention is described below. Figures 14 to 21 Examples of first to eighth cross-sectional views of a substrate used to manufacture an imaging device are shown.

[0045] refer to Fig.14, a raw material, for example, a semiconductor substrate 10 is provided. In order to avoid interference with adjacent imaging devices, a shallow trench isolation (STI) process is performed to form field oxide films 21 and 22 in the substrate 10. In another embodiment, in the absence of STI, each device can only be separated by impurities. A mask is formed to expose an area for forming a PD, and ion impurities are implanted into the substrate 10 to form a PD extending to a predetermined depth. In the case of an n-type photodiode, phosphorus or arsenic or a combination thereof is implanted, and boron or BF2 is used for isolation. In the case of a p-type photodiode, boron or BF2 is implanted, and phosphorus or arsenic or a combination thereof is used for isolation.

[0046] Next, refer to Fig.15 , a gate insulating film is formed on the substrate 10 , a conductive film is formed on the substrate 10 , a patterning process is performed to form gate patterns 41 to 44 (the gate insulating film is divided into 31 to 34 ), and the resist pattern is removed.

[0047] Next, if Fig.16 As shown, an insulating film is formed on the substrate 10 for the deposition of the gate offset spacer. The material of the insulating film can be oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON) or other insulating materials. Fig.17 As shown, a mask is formed to cover PD and TX. In addition to PD and TX, the mask may also cover the right half of RST. Fig.18 As shown, the insulating film in the region where the mask is not formed is etched to some extent by isotropic etching, leaving a thin film.

[0048] Next, refer to Fig.19 , remove the mask, and etch the upper side of the thick film covering PD and TX by anisotropic etching. The upper side of the thin film is over-etched. A first ion implantation mask is formed to cover PD and TX, and lightly doped regions 51 to 54 are formed on both sides of SEL, SF, and RST by implanting ion impurities, and the first ion implantation mask is removed.

[0049] Next, refer to Fig. 20, an insulating film is formed on the substrate 10, and then the insulating film is etched to form spacers 71a to 74b on both sides of SEL, SF, RST and TX. The material of the insulating film can be oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON) or other insulating materials. A second ion implantation mask is formed to cover PD and TX. Ion impurities are implanted into the substrate 10 to form heavily doped regions 61 to 64 and FD. In the case of an n-type photodiode, an n-type conductive layer is made, and in the case of a p-type photodiode, a p-type conductive layer is made. The heavily doped regions 61 to 64 are self-aligned with their corresponding spacers, the lightly doped region 52 between SEL and SF is divided into two parts, and the lightly doped region 53 between SF and RST is divided into two parts. Remove the second ion implantation mask.

[0050] Next, refer to Fig.21 , back end of line (BEOL) processes are performed to form metal interconnects 81 to 88. That is, a thick insulating film is formed, contact holes are formed, and the metal film is deposited and patterned. Then, the imaging device placed on the substrate 10 is connected to the logic circuit placed on another substrate 11 through bonding such as copper-copper bonding or other silicon-to-silicon connections.

[0051] Then, deep trench isolation (DTI) 91 and 92 are formed to reduce crosstalk between PDs. Metal grids 101 and 102 are placed on the insulating film on the back of substrate 10 at the pixel boundary to suppress light spots and ghosting. Color filters are set at positions corresponding to PDs in layer 110. Micro lenses 121 and 122 are set at positions corresponding to PDs. For example, the size of PDs can be different, and PDs can be Fig.21 The two components are staggered in the horizontal direction.

[0052] refer to Figure 22 to Figure 25 , an example of another manufacturing process of an imaging device provided by an embodiment of the present invention is described below. Figure 22 to Figure 25 Examples of first to fourth cross-sectional views of a substrate used to manufacture an imaging device are shown.

[0053] See also Fig. 22 , in the implementation of the combination Figures 14 to 16 After the same process as described above, the upper side of the insulating film is etched by anisotropic etching to form a first ion implantation mask to cover PD and TX, and lightly doped regions are formed on both sides of SEL, SF and RST by implanting ion impurities, and the first ion implantation mask is removed. An insulating film is formed on the substrate 10. The material of the insulating film can be oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON) or other insulating materials.

[0054] Next, refer to Fig.23 , a mask is formed to cover PD and TX. In addition to PD and TX, the mask formed can also cover the right half of RST. The film in the area where the mask is not formed is etched to a certain extent by isotropic etching, leaving a thin film.

[0055] Next, refer to Fig.24 , the mask is removed, and the upper side of the insulating film is etched by anisotropic etching, and the upper side of the thin film is over-etched.

[0056] Next, refer to Fig.25 , a second ion implantation mask is formed to cover PD and TX, and ion impurities are implanted into the substrate to form heavily doped regions 61 to 64 of the N-type conductive layer and FD. The heavily doped regions 61 to 64 are self-aligned with their corresponding spacers, the lightly doped region 52 between SEL and SF is divided into two parts, and the lightly doped region 53 between SF and RST is divided into two parts. The second ion implantation mask is removed. After that, the bonding is performed Fig.21 Same process as described.

[0057] The imaging device provided in the embodiment of the present application can be applied to an imaging system 201, for example, a camera system. Fig.26 2 is another exemplary block diagram of an imaging system 201. The imaging system 201 includes an optical system 202 (e.g., one or more lenses), a shutter device 203, a solid-state image sensor 204, a control circuit 205, a signal processing circuit 206, a display 207, and a memory 208. The solid-state image sensor 204 includes, for example, Figure 1 The pixel array 209 and the readout circuit 210 in the image processing circuit 206 acquire the image data of the subject through the lens 202 and the shutter device 203 under the control of the control circuit 205. The signal processing circuit 206 outputs the acquired image data to the display 207 or stores the image data in the memory 208.

[0058] Fig. 27 Various applications of the camera system are shown. The imaging device provided by the embodiments of the present invention can be applied to, for example, mobile phone cameras, digital cameras, network cameras, security surveillance cameras, video cameras, car and traffic cameras, medical cameras and machine vision.

[0059] Embodiments of the present invention may be applied to array devices and different substrates, such as bulk silicon substrates, silicon-on-insulator substrates, silicon-germanium substrates, and other photosensitive substrates.

[0060] Embodiments of the present invention can reduce GIDL in floating diffusion nodes, resulting in better fixed pattern noise. This can tighten design rules related to devices within the pixel and improve random noise and RTS noise of source follower devices by increasing device size. The sidewall spacers of TX are wider, which can improve conversion gain because of lower parasitic capacitance, resulting in lower pixel and circuit noise.

[0061] The above disclosure is only an exemplary embodiment of the present invention, and is certainly not intended to limit the scope of protection of the present invention. It can be understood by those skilled in the art that all or part of the processes for implementing the above embodiments and the equivalent modifications made according to the claims of the present invention should all fall within the scope of the present invention.

Claims

1. An imaging device, characterized in that: The imaging device includes a plurality of pixels, each pixel including a transfer gate device, a reset device, a source follower device and a row selection device, A transfer gate device of a first pixel of the plurality of pixels has a sidewall spacer width that is greater than sidewall spacer widths of other devices within the first pixel.

2. The imaging device according to claim 1, characterized in that The difference between the sidewall spacer width of the transfer gate device and the sidewall spacer width of other devices in the pixel is equal to or greater than 3 nanometers.

3. An imaging device, characterized in that: The imaging device includes a plurality of pixels, each pixel including a transfer gate device, a reset device, a source follower device and a row selection device, The sidewall spacer width of the transfer gate device of the first pixel among the multiple pixels and the sidewall spacer width of the source side of the adjacent device are larger than the sidewall spacer width of the drain side of the adjacent device and the sidewall spacer widths of the source follower device, the row selection device and other devices within the first pixel, wherein the adjacent device is a device other than the transfer gate device.

4. The imaging device according to claim 3, characterized in that The sidewall spacer width of the transfer gate device and the sidewall spacer width on the source side of the adjacent device are 3 nanometers or more greater than the sidewall spacer width on the drain side of the adjacent device and the sidewall spacer widths of the source follower device, row selection device and other devices within the first pixel.

5. An imaging device, characterized in that: The imaging device includes a plurality of pixels, each pixel including a transfer gate device, a reset device, a source follower device and a row selection device, A transfer gate device of a first pixel of the plurality of pixels has a gate offset spacer width that is greater than gate offset spacer widths of other devices within the first pixel.

6. The imaging device according to claim 5, characterized in that A difference between the gate offset spacer width of the transfer gate device and the gate offset spacer width of other devices within the first pixel is equal to or greater than 3 nanometers.

7. An imaging device, characterized in that: The imaging device includes a plurality of pixels, each pixel including a transfer gate device, a reset device, a source follower device and a row selection device, The gate offset spacer width of the transmission gate device of the first pixel among the multiple pixels and the gate offset spacer width on the source side of the adjacent device are larger than the gate offset spacer width on the drain side of the adjacent device and the gate offset spacer widths of the source follower device, the row selection device and other devices in the first pixel, wherein the adjacent device is a device other than the transmission gate device and is arranged to be adjacent to the transmission gate device.

8. The imaging device according to claim 7, characterized in that The gate offset spacer width of the transfer gate device and the gate offset spacer width on the source side of the adjacent device are 3 nanometers or more larger than the gate offset spacer width on the drain side of the adjacent device and the gate offset spacer widths of the source follower device, row selection device and other devices within the first pixel.

9. A method for manufacturing an imaging device, the imaging device comprising a plurality of pixels, each pixel comprising a transfer gate device, a reset device, a source follower device and a row selection device, characterized in that: The method comprises: forming a gate offset spacer on both sides of a transfer gate device of a first pixel among the plurality of pixels and other devices in the first pixel; forming an insulating film on the transmission gate device and other devices in the first pixel; etching the insulating film on other devices in the first pixel by isotropic etching; The insulating film is etched on the transfer gate device and other devices in the first pixel by anisotropic etching.

10. A method of manufacturing an imaging device, the imaging device comprising a plurality of pixels, each pixel comprising a transfer gate device, a reset device, a source follower device and a row selection device, characterized in that: The method comprises: forming a gate offset spacer on both sides of a transmission gate device of a first pixel among the plurality of pixels, an adjacent device, and other devices in the first pixel, wherein the adjacent device is a device other than the transmission gate device; forming an insulating film on the transmission gate device, the adjacent device and other devices in the first pixel; etching the insulating film on the drain side of other devices in the first pixel and the adjacent device by isotropic etching; The insulating film is etched on the transfer gate device, the adjacent device, and other devices in the first pixel by anisotropic etching.

11. A method for manufacturing an imaging device, the imaging device comprising a plurality of pixels, each pixel comprising a transfer gate device, a reset device, a source follower device and a row selection device, characterized in that: The method comprises: forming an insulating film on a transmission gate device of a first pixel among the plurality of pixels and other devices in the first pixel; etching the insulating film on other devices in the first pixel by isotropic etching; etching the insulating film on the transmission gate device and other devices in the first pixel by anisotropic etching; Sidewall spacers are formed on both sides of the transfer gate device and other devices in the first pixel.

Images