Manufacturing method of back contact solar cell and back contact solar cell

Abstract

The invention provides a manufacturing method of a back contact solar cell and the back contact solar cell, and belongs to the technical field of solar cells. The manufacturing method of the back contact solar cell comprises the steps that a semiconductor substrate is provided, the semiconductor substrate is provided with a first surface and a second surface which are opposite, the first surface is a textured surface or a plane, and the second surface is a plane; and a first carrier collection region, a second carrier collection region and an isolation region between the first carrier collection region and the second carrier collection region are arranged on the second surface of the semiconductor substrate.

Description

Technical Field

[0001] At least one embodiment of the present application relates to a solar cell, and more particularly to a method for manufacturing a back-contact solar cell and a back-contact solar cell. Background Art

[0002] Back-contact solar cells have an absolute advantage in conversion efficiency, but they also face the challenges of complex manufacturing processes and high costs. During the manufacturing process, they undergo multiple wet processes, which damage the semiconductor substrate and form defect recombination centers, limiting the improvement of solar cell efficiency. Therefore, how to simplify the manufacturing process and reduce equipment costs is crucial to the development of high-efficiency, low-cost back-contact solar cells. Summary of the invention

[0003] In view of this, in order to at least partially solve the above-mentioned technical problems, the present application provides a method for manufacturing a back-contact solar cell and a back-contact solar cell.

[0004] According to an embodiment of one aspect of the present application, a method for manufacturing a back-contact solar cell is provided, comprising the following steps:

[0005] S01: providing a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, wherein the second surface comprises a plurality of first carrier collecting regions and a plurality of second carrier collecting regions alternately distributed along a first direction, and an isolation region is provided between adjacent first carrier collecting regions and second carrier collecting regions;

[0006] S02: texturing the first surface, and depositing a passivation anti-reflection layer on the first surface;

[0007] S03: depositing a first interface passivation layer on the second surface of the semiconductor substrate, and forming a first doped semiconductor layer on the first interface passivation layer;

[0008] S04: patterning the first doped semiconductor layer and the first interface passivation layer on the second surface of the semiconductor substrate, retaining the first doped semiconductor layer and the first interface passivation layer in the first carrier collection region and the isolation region, removing the first doped semiconductor layer and the first interface passivation layer in the second carrier collection region, and forming a suede surface in the second carrier collection region;

[0009] S05: sequentially depositing a second interface passivation layer and a second doped semiconductor layer on the second surface of the semiconductor substrate, patterning the second interface passivation layer and the second doped semiconductor layer, removing a portion of the second interface passivation layer and the second doped semiconductor layer on the first carrier collection region, and exposing the first doped semiconductor layer;

[0010] S06: depositing a transparent conductive oxide layer on the second surface of the semiconductor substrate, interrupting the transparent conductive oxide layer, forming a first transparent conductive oxide layer on the first doped semiconductor layer located in the first carrier collection region, and forming a second transparent conductive oxide layer disconnected from the first transparent conductive oxide layer on the second doped semiconductor layer located in the second carrier collection region;

[0011] S07: depositing a first electrode on the first transparent conductive oxide layer, and depositing a second electrode on the second transparent conductive oxide layer.

[0012] According to another embodiment of the present application, a back-contact solar cell obtained by the above-mentioned manufacturing method is provided.

[0013] According to the manufacturing method of the back contact solar cell provided in the above embodiment of the present application, step S02 is arranged before step S03: the first surface is textured, and a passivation anti-reflection layer is deposited on the first surface; then a first interface passivation layer composed of a tunneling oxide and a first intrinsic semiconductor layer are sequentially deposited on the second surface of the semiconductor substrate, and a diffusion process is used to realize the doping of the first intrinsic semiconductor layer to form a first doped semiconductor layer. This is a pre-texturing process, which can reduce the damage of subsequent wet processes to other deposited film layers compared with a post-texturing process (i.e., the velvet surface is formed on the first surface). This embodiment can simplify the process steps and reduce the cost of battery manufacturing.

[0014] According to the manufacturing method of the back-contact solar cell provided by another embodiment of the present application, the step S03 can also be arranged before the step S02: a first interface passivation layer and a first intrinsic semiconductor layer composed of a tunneling oxide are sequentially deposited on the second surface of the semiconductor substrate, and a diffusion process is used to realize the doping of the first intrinsic semiconductor layer to form a first doped semiconductor layer; the first surface is then textured, and a passivation anti-reflection layer is deposited on the first surface. This embodiment can improve the texture quality of the first surface, the texture has better passivation, and the battery can obtain higher efficiency. In addition, according to the preferred embodiment of this embodiment, the second carrier collection area can also be textured at the same time when the second carrier collection area is textured, thereby reducing the process steps, optimizing the process flow, and reducing the manufacturing cost.

[0015] According to one embodiment of the present application, a transparent protective layer is formed on the surface of the passivation anti-reflection layer; the transparent protective layer can protect the passivation anti-reflection film layer on the velvet structure of the first surface of the semiconductor substrate, reduce the damage to the first surface film layer and the velvet in the wet process, have good wear resistance, and protect the first surface of the solar cell during battery transportation and storage to prevent physical damage. At the same time, the optical parameters of the transparent protective layer can be adjusted to match the passivation anti-reflection layer, increase light transmittance, reduce reflection, and increase light absorption. According to a preferred embodiment of the present application, the transparent protective layer is a polytetrafluoroethylene film. At the same time, the material of the transparent protective layer is a polytetrafluoroethylene film, which can have good stability and can isolate water vapor and oxygen. In the process of manufacturing photovoltaic modules, adhesive films such as EVA or POE can be omitted on the front of the photovoltaic module, saving the amount of adhesive film used and reducing the manufacturing cost of photovoltaic modules.

[0016] According to the embodiments of the present application, a variety of mask schemes may be used for patterning the second surface first doped semiconductor layer and the first interface passivation layer to optimize the process, reduce costs, and improve battery efficiency.

[0017] According to a preferred embodiment of the present application, step S04 includes: firstly patterning the phosphosilicate glass layer or borosilicate glass layer formed on the first doped semiconductor layer to form a mask pattern, and then patterning the first doped semiconductor layer and the first interface passivation layer on the second surface of the semiconductor substrate using the phosphosilicate glass or borosilicate glass patterned mask pattern. By utilizing the alkali resistance of phosphosilicate glass or borosilicate glass and the advantage that phosphosilicate glass or borosilicate glass is a byproduct of the polysilicon diffusion doping process, the process can be simplified and the manufacturing cost can be reduced.

[0018] According to another preferred embodiment of the present application, step S04 includes: first removing the phosphosilicate glass layer or borosilicate glass layer formed on the first doped semiconductor layer, then forming a SiNx layer on the first doped semiconductor layer, patterning the SiNx layer to form a mask pattern, and then patterning the first doped semiconductor layer and the first interface passivation layer on the second surface of the semiconductor substrate using the SiNx mask pattern. SiNx has a better selective etching ratio than phosphosilicate glass or borosilicate glass, and improves the patterning effect. At the same time, SiNx is doped with hydrogen during the deposition process, and hydrogen has a good passivation effect on polysilicon, which can repair defects on the surface of polysilicon.

[0019] According to another preferred embodiment of the present application, in step S04, a SiNx layer is formed on the phosphosilicate glass layer or borosilicate glass layer formed on the first doped semiconductor layer, and the stack of the SiNx layer and the phosphosilicate glass layer or the stack of the SiNx layer and the borosilicate glass layer is patterned to form a mask pattern, and then the mask pattern is used to pattern the first doped semiconductor layer and the first interface passivation layer on the second surface of the semiconductor substrate. The composite mask pattern of the SiNx layer superimposed on the phosphosilicate glass layer or the borosilicate glass layer can, on the one hand, enhance the selective etching ratio of the mask pattern and improve the patterning effect, and on the other hand, can utilize the hydrogen in the SiNx to better passivate the polysilicon. In addition, the step of removing the phosphosilicate glass layer or the borosilicate glass layer can be reduced, and the process cost can be reduced.

[0020] According to another embodiment of the present application, when the passivation anti-reflection layer is deposited on the first surface, the passivation anti-reflection layer is formed on the second surface at the same time, the passivation anti-reflection layer on the second surface is patterned to form a mask pattern, and then the mask pattern is used to pattern the first doped semiconductor layer and the first interface passivation layer on the second surface of the semiconductor substrate. The passivation anti-reflection layer used in the present application is an alkali-resistant material, which has a higher selective etching ratio than silicon materials (single crystal silicon, polycrystalline silicon or amorphous silicon materials). At the same time, the passivation anti-reflection layer contains hydrogen, which better passivates polycrystalline silicon. In addition, the step of depositing the mask layer can also be reduced by one step, thereby reducing the process cost. According to another preferred embodiment of this embodiment, the passivation anti-reflection layer can be covered on the phosphosilicate glass layer or borosilicate glass layer formed on the first doped semiconductor layer to form a stacked mask layer, thereby reducing the step of removing the phosphosilicate glass layer or borosilicate glass layer by one step, thereby reducing the process cost.

[0021] According to some of the above-mentioned embodiments of the present application, the above-mentioned graphic formation of the mask pattern can be to form the mask pattern by removing part of the mask layer by laser etching, or other graphic processes such as photolithography and development.

[0022] According to the embodiments of the present application, the passivation anti-reflection layer includes an AlOx / SiNx stack. The passivation anti-reflection layer is deposited by, for example, atomic layer deposition (ALD) to deposit an AlOx film, which has the advantages of good shape retention, good density, and good stability, and has very mature processes and inexpensive equipment. It can passivate and protect the suede surface very well. High-temperature PECVD deposition of SiNx on the AlOx film can not only provide the AlOx film with sufficient hydrogen to ensure passivation, but also have an excellent anti-reflection effect.

[0023] According to another embodiment of the present application, the passivation anti-reflection layer includes a SiOx / SiNx stack, SiOx / SiNx is a high temperature resistant passivation anti-reflection layer, the SiOx passivation layer can significantly reduce the surface state density, reduce the carrier surface recombination rate, and combine with the pre-texturing process, while forming a tunneling oxide layer on the second surface, a SiOx passivation layer can be formed on the velvet surface of the first surface at the same time, which can further simplify the process and reduce costs.

[0024] According to another embodiment of the present application, the passivation anti-reflection layer includes a POx / SiNx stack. The introduction of POx can reduce the surface state density of the first surface of the semiconductor substrate and form a positive charge aggregation area on the first surface of the semiconductor substrate, which can significantly reduce surface defects and reduce surface recombination. POx can be formed by atomic layer deposition (ALD) or PECVD deposition. The SiNx film layer needs to form a dense film layer to cover and protect POx to prevent POx from deliquescing.

[0025] According to a preferred embodiment of the present application, a SiOx interface layer is further formed between the AlOx of the passivation anti-reflection layer and the first surface of the semiconductor substrate. The SiOx interface layer can further reduce the surface defect density of the semiconductor substrate and reduce defect recombination centers to obtain a better passivation effect.

[0026] According to another preferred embodiment of the present application, the AlOx layer of the passivation anti-reflection layer is formed by ALD deposition, the SiNx layer is deposited by PECVD, and a SiNx interface layer is further deposited by ALD between the AlOx layer and the SiNx layer. The SiNx interface layer deposited by ALD can protect the AlOx layer without changing the deposition chamber, and the hydrogen released by AlOx in the subsequent high-temperature process can be well absorbed by SiNx, or SiNx forms a good coverage to prevent hydrogen overflow, thereby preventing AlOx film explosion and causing passivation failure.

[0027] According to the embodiments of the present application, the mask patterns in some of the above embodiments may be removed or retained as an insulating isolation structure formed in the isolation region between the first doped semiconductor layer and the second doped semiconductor layer along the thickness direction to reduce leakage between the first doped semiconductor layer and the second doped semiconductor layer. Alternatively, the transparent conductive oxide layer may be further interrupted on the insulating isolation structure, and the insulating structure may be used as an energy absorption layer or a stop layer to prevent the first or second doped semiconductor layer from being damaged by interruption due to laser or wet etching.

[0028] According to a preferred embodiment of the present application, before depositing the second interface passivation layer and the second doped semiconductor layer in sequence on the second surface of the semiconductor substrate, after patterning the first doped semiconductor layer and the first interface passivation layer on the second surface of the semiconductor substrate, the insulating isolation structure formed in the isolation region along the thickness direction between the first doped semiconductor layer and the second doped semiconductor layer is retained. Or before depositing the transparent conductive oxide layer on the second surface of the semiconductor substrate, after depositing the second interface passivation layer and the second doped semiconductor layer in sequence on the second surface of the semiconductor substrate, the second interface passivation layer, the second doped semiconductor layer and the mask pattern on the second surface are patterned to form a second opening to expose the first doped semiconductor layer, and at the same time, an insulating isolation structure is formed between the first doped semiconductor layer and the second doped semiconductor layer in the isolation region along the thickness direction. Simplify the process steps and reduce damage to the battery structure film layer. Improve battery efficiency.

[0029] According to another embodiment of the present application, the insulating isolation structure of the isolation region between the first carrier collection region and the second carrier collection region of the present application can also be an isolation groove formed between the first carrier collection region and the second carrier collection region as the isolation region. According to a preferred embodiment of the present application, the polytetrafluoroethylene film is deposited by evaporation coating or magnetron sputtering, and after the polytetrafluoroethylene film is deposited, the polytetrafluoroethylene film is annealed. The annealing temperature is 180°C to 220°C, and after annealing, it is cooled to room temperature, and the cooling rate is 1 to 6°C / min, so as to improve the crystallization performance of the polytetrafluoroethylene film and improve the corrosion resistance of the polytetrafluoroethylene film.

[0030] The embodiment of the present application also provides a back-contact solar cell, comprising: a semiconductor substrate having a first surface and a second surface opposite to each other, the first surface being a velvet surface, the second surface of the semiconductor substrate comprising a plurality of first carrier collection regions and a plurality of second carrier collection regions alternately distributed along a first direction, an isolation region being provided between adjacent first carrier collection regions and second carrier collection regions; a first interface passivation layer and a first doped semiconductor layer located in the first carrier collection region and stacked; a second interface passivation layer and a second doped semiconductor layer located in the second carrier collection region and stacked; a passivation anti-reflection layer , located on the first surface of the semiconductor substrate; the passivation anti-reflection layer comprises a passivation layer and an anti-reflection layer stacked in sequence on the first surface, and the passivation layer is closer to the first surface than the anti-reflection layer; wherein the passivation layer comprises at least one of AlOx, SiOx and POx; or, a SiOx interface layer is further formed between the passivation layer and the first surface of the semiconductor substrate; or, the passivation layer comprises an AlOx passivation layer, the anti-reflection layer comprises a SiNx anti-reflection layer, and a SiNx interface layer deposited by atomic layer deposition is further provided between the AlOx passivation layer and the SiNx anti-reflection layer.

[0031] According to a preferred embodiment of the present application, the transparent conductive oxide layer is interrupted, at least the transparent conductive oxide layer in the isolation region is interrupted, and the thickness of the edge portion of the first transparent conductive oxide layer and / or the second transparent conductive oxide layer adjacent to the isolation region gradually decreases in the direction close to the isolation region. The thickness of the transparent conductive layer near both sides of the isolation region is smaller, and at this time, the thickness of the two parts of the transparent conductive layer for transmitting opposite-sex carriers is smaller (the facing area is also smaller), which is conducive to reducing the risk of leakage and improving the electrical reliability of the back-contact solar cell.

[0032] According to a preferred embodiment of the present application, the first doped semiconductor layer and the first interface passivation layer located in the second carrier collection region are removed to form a first opening, wherein the width of the first opening is greater than or equal to 250 μm and less than or equal to 400 μm. Compared with the opening width less than or equal to 200 μm in the existing back contact solar cell, the width of the first opening for exposing the first doped semiconductor layer to the outside in the back contact solar cell formed by the manufacturing method provided is larger, which is beneficial to prevent short circuits, so that the corresponding conductive material electrically connected to the first doped semiconductor layer has a larger formable range, thereby facilitating the increase of the contact area between the first doped semiconductor layer and the corresponding conductive material, reducing transmission loss, and improving the electrical reliability of the manufactured back contact solar cell. Secondly, when the width of the above-mentioned first opening is less than 400 μm, the second interface passivation layer and the second doped semiconductor layer retain more parts after the operation of opening the first opening, while reducing the etching amount, ensuring that the second interface passivation layer and the second doped semiconductor layer have a certain area share on the second surface side, ensuring that the second doped semiconductor layer has a higher carrier collection efficiency.

[0033] According to a preferred embodiment of the present application, in the second surface, the region where the stacked first interface passivation layer and the first doped semiconductor layer are arranged has a tower-shaped texture structure; the thickness of the first interface passivation layer located at the bottom surface of the tower-shaped texture structure is greater than the thickness of the first interface passivation layer located at the side wall of the tower-shaped texture structure. In the second surface, the bottom surface of the tower-shaped texture structure accounts for a larger proportion than its side surface, so when the portion of the first interface passivation layer arranged on the bottom surface of the tower-shaped texture structure has a greater thickness, the first interface passivation layer has a higher passivation effect on the semiconductor substrate. In addition, the portion of the first interface passivation layer arranged on the side wall of the tower-shaped texture structure has a smaller thickness, and at this time, the portion has a relatively low tunneling resistance, which improves the carrier collection efficiency of the first doped semiconductor layer at this location, synergistically improves the passivation effect and electrical collection performance, and further improves the electrical performance of the back-contact solar cell.

[0034] According to another preferred embodiment of the present application, in the second surface, the region where the stacked first interface passivation layer and the first doped semiconductor layer are provided has a tower-like texture structure; the thickness of the first interface passivation layer located at the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer located at the side wall of the tower-like texture structure. In the second surface, the bottom surface of the tower-like texture structure and the side surface of the tower-like texture structure have different crystal orientations. Specifically, the bottom surface of the tower-like texture structure is a

[110] crystal orientation, and the number of dangling bonds on the surface of the

[110] crystal orientation is relatively small; while the side surface of the tower-like texture structure is a

[111] crystal orientation, and the number of dangling bonds on the

[111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure, it is beneficial for the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure to have a relatively high passivation effect, meet the demand for high passivation effect on the side of the tower-shaped texture structure, reduce the carrier recombination rate on the side of the tower-shaped texture structure, and further improve the working efficiency of the back contact solar cell.

[0035] As a possible implementation scheme, the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure away from the semiconductor substrate is greater than or equal to 0.5nm and less than or equal to 1.5nm. In this case, the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure is within the above range, which is conducive to preventing the first interface passivation layer from having a lower passivation effect on the semiconductor substrate due to the smaller thickness of the bottom surface of the tower-shaped texture structure; in addition, it is also conducive to preventing the first interface passivation layer from having a higher tunneling resistance due to the larger thickness of the bottom surface of the tower-shaped texture structure, and is conducive to achieving a balance between the passivation effect and tunneling resistance of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure, thereby reducing the carrier recombination rate on the side of the tower-shaped texture structure while ensuring that the first doped semiconductor layer has a higher carrier collection efficiency and reduces transmission loss. The thickness of the first interface passivation layer located on the side of the tower-shaped texture structure away from the semiconductor substrate is smaller, which is conducive to making the first interface passivation layer located on the side of the tower-shaped texture structure away from the semiconductor substrate have a lower tunneling resistance, ensuring that the first doped semiconductor layer has a higher carrier collection efficiency and reducing transmission losses.

[0036] As a possible implementation scheme, the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure is greater than or equal to 0.5nm and less than or equal to 2nm. In this case, the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure is within the above range, which is conducive to preventing the lower passivation effect of the first interface passivation layer due to the smaller thickness of the part; in addition, it is also conducive to preventing the first interface passivation layer from being located on the side wall of the tower-shaped texture structure due to the larger thickness, which leads to the higher tunneling resistance of the part, and is conducive to achieving the balance between the passivation effect and the tunneling resistance of the part of the first interface passivation layer located on the side wall of the tower-shaped texture structure, thereby reducing the carrier recombination rate on the side of the tower-shaped texture structure, while ensuring that the first doped semiconductor layer has a higher carrier collection efficiency and reduces the transmission loss. The thickness located on the side wall of the tower-shaped texture structure is larger, which is conducive to making the part of the first interface passivation layer located on the side wall of the tower-shaped texture structure have a higher passivation effect, reducing the carrier recombination rate on the side of the tower-shaped texture structure.

[0037] According to a preferred embodiment of the present application, the thickness of the second interface passivation layer is greater than or equal to 8 nm and less than or equal to 14 nm. In this case, the thickness of the second interface passivation layer is relatively large, which is conducive to enhancing the isolation effect of the second interface passivation layer on the first doped semiconductor layer and the second doped semiconductor layer, and reducing the risk of leakage.

[0038] According to a preferred embodiment of the present application, a laser etching process is used to selectively etch the stacked second interface passivation layer and the second doped semiconductor layer. After selective etching, a second opening is formed, and a hole structure is formed in the edge portion of the second doped semiconductor layer adjacent to the second opening. The hole structure is a hollow structure, so when a hole structure is formed in the edge portion of the second doped semiconductor layer, the risk of leakage between the edge portion of the second doped semiconductor layer and the first doped semiconductor layer can be reduced, thereby improving the electrical reliability of the back-contact solar cell. In addition, the presence of the hole structure can also increase the undulation of the edge portion of the stacked second interface passivation layer and the second doped semiconductor layer, thereby enhancing the light trapping effect of this portion, which is beneficial to improving the bifaciality of the back-contact solar cell.

[0039] According to a preferred embodiment of the present application, the first interface passivation layer and the first doped semiconductor layer are located in the first carrier collection region and the isolation region; the second interface passivation layer and the second doped semiconductor layer are located in the second carrier collection region and the isolation region, and cover part of the first interface passivation layer and the first doped semiconductor layer along the extension to the first carrier collection region; the surface of the first carrier collection region is a polished surface structure, and the bottom surface of the first opening is a velvet structure; the thickness of the second doped semiconductor layer located on the velvet structure is less than the thickness of the second doped semiconductor layer located on the polished surface structure. The existence of the first opening causes the first doped semiconductor layer and the second doped semiconductor layer to be staggered in the thickness direction of the semiconductor substrate, reducing the risk of leakage. In addition, compared with the polished surface, the velvet surface has a larger specific surface area. Within the same formation range, the contact area between the part of the second doped semiconductor layer located on the velvet surface and the semiconductor substrate is larger, while the contact area between the part of the second doped semiconductor layer located on the polished surface and the semiconductor substrate is smaller. Based on this, when the thickness of the second doped semiconductor layer located on the velvet surface is relatively small, after ensuring that there is sufficient contact area between the portion of the second doped semiconductor layer located on the velvet surface and the semiconductor substrate, a space that can be reduced can be reserved for setting the thickness of this portion, thereby ensuring a high carrier collection efficiency and reducing the amount of consumables used in manufacturing the portion of the second doped semiconductor layer located on the velvet surface. In addition, the thickness of the second doped semiconductor layer located on the polishing surface is relatively large, so that this portion has a higher field passivation effect and reduces carrier recombination. In this case, the thickness difference between different portions of the second doped semiconductor layer can be set according to the surface roughness of the first carrier collection area and the second carrier collection area, as well as actual needs, and is not specifically limited here.

[0040] According to a preferred embodiment of the present application, the second doped semiconductor layer is doped amorphous silicon, and the second doped semiconductor layer located on the bottom surface of the first opening is irradiated with laser to crystallize the second doped semiconductor layer. After crystallization, the second doped semiconductor layer can be fully or partially crystallized into microcrystalline silicon or nanocrystalline silicon, so that the second doped semiconductor layer is crystallized by heat, and the degree of crystallization of the second doped semiconductor layer is improved, thereby improving the conductivity of the second doped semiconductor layer, reducing the contact resistance between the second doped semiconductor layer and the corresponding conductive material, and reducing the transmission loss. According to a preferred embodiment of the present application, before depositing the transparent conductive oxide layer on the second surface of the semiconductor substrate, after depositing the second interface passivation layer and the second doped semiconductor layer in sequence on the second surface of the semiconductor substrate, the second doped semiconductor layer located on the bottom surface of the first opening is irradiated with laser to crystallize the second doped semiconductor layer.

[0041] According to a preferred embodiment of the present application, the isolation region at least includes an insulating isolation structure between the first doped semiconductor layer and the second doped semiconductor layer, and the insulating isolation structure can prevent the formation of a leakage channel between the first doped semiconductor layer and the second doped semiconductor layer, and prevent the generation and recombination of carriers of different polarities. The isolation insulating structure includes: one or more laminated films of SiNx, phosphosilicate glass, borosilicate glass, and AlOx. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application, rather than limiting the present application.

[0043] Figure 1 A schematic diagram of a process for manufacturing a back-contact solar cell provided in an embodiment of the present application;

[0044] Figure 2 A schematic cross-sectional view of a hybrid back-contact solar cell provided in an embodiment of the present application;

[0045] Figure 3A~Figure 3K A schematic diagram of the manufacturing process of a hybrid back-contact solar cell provided in an embodiment of the present application;

[0046] Figure 4 A schematic cross-sectional view of a hybrid back-contact solar cell provided in another embodiment of the present application;

[0047] Figure 5A to Figure 5I A schematic diagram of a manufacturing process of a hybrid back-contact solar cell provided in another embodiment of the present application;

[0048] Figure 6 A cross-sectional schematic diagram of a hybrid back-contact solar cell provided in yet another embodiment of the present application;

[0049] Figure 7A to Figure 7F A schematic diagram of a manufacturing process of a hybrid back-contact solar cell provided for another embodiment of the present application; and

[0050] Figure 8 A schematic cross-sectional view of a tunnel oxide passivated contact back contact solar cell provided in yet another embodiment of the present application.

[0051] Description of reference numerals:

[0052] 1- semiconductor substrate;

[0053] A-first surface;

[0054] B-second surface;

[0055] C-lateral surface;

[0056] 100-first carrier collection region;

[0057] 200- a second carrier collection region;

[0058] 300-Isolated area;

[0059] 2-first interface passivation layer;

[0060] 3-a first doped semiconductor layer;

[0061] 4- passivation anti-reflection layer;

[0062] 5- Transparent protective layer;

[0063] 6-second interface passivation layer;

[0064] 7-a second doped semiconductor layer;

[0065] 8-transparent conductive oxide layer;

[0066] 81-a first transparent conductive oxide layer;

[0067] 82- a second transparent conductive oxide layer;

[0068] 10- a first electrode;

[0069] 20- a second electrode;

[0070] 11- a first mask layer;

[0071] 12- a second mask layer;

[0072] 13- a third mask layer;

[0073] 14- a fourth mask layer;

[0074] 2001-First opening;

[0075] 2002-Second opening. DETAILED DESCRIPTION

[0076] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. However, the present application can be implemented in different forms and should not be construed as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make the application thorough and complete, and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated, and the same reference numerals represent the same elements throughout.

[0077] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The terms "include", "comprising", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0078] The minority carrier collection area and majority carrier collection area of ​​the back-contact solar cell are designed on the back of the cell, and only the passivation layer and optical anti-reflection layer are designed on the front. Back-contact solar cells face the challenges of complex manufacturing processes and high costs, while also ensuring that the cells have high conversion efficiency.

[0079] In the related art, the back of the back-contact solar cell includes a passivation contact structure. In the process of forming the passivation contact structure on the back, in order to avoid affecting the front, a mask layer needs to be formed on the front, and after the preparation process of the back is completed, the mask layer on the front needs to be removed. On the one hand, this increases the complexity of the process and leads to low production efficiency. On the other hand, after removing the mask layer, the risk of leakage may increase. In addition, in the process of forming the mask layer on the front, the mask layer on the front will be plated around the side of the battery, which may affect the passivation level of the side of the battery.

[0080] In view of this, it is necessary to provide a method for manufacturing a back-contact solar cell and a back-contact solar cell in order to address the technical problems existing in the manufacturing process of the back-contact solar cell.

[0081] According to an embodiment of the present application, the back-contact solar cell may be an interdigitated back-contact solar cell (IBC), a back-contact heterojunction solar cell (HBC), a tunnel oxide passivation back-contact solar cell (TBC) or a hybrid back-contact solar cell.

[0082] Figure 1 A schematic flow chart of a method for manufacturing a back-contact solar cell provided in an embodiment of the present application.

[0083] Figure 2 A schematic cross-sectional view of a hybrid back-contact solar cell provided in an embodiment of the present application.

[0084] According to an exemplary embodiment of the present application, the present application provides a method for manufacturing a back-contact solar cell, referring to Figure 1 , Figure 2 As shown, it includes: step S01 to step S07.

[0085] Step S01: providing a semiconductor substrate 1, wherein the semiconductor substrate 1 has a first surface A and a second surface B opposite to each other, wherein the second surface B comprises a plurality of first carrier collecting regions 100 and a plurality of second carrier collecting regions 200 alternately distributed along a first direction, and an isolation region 300 is provided between adjacent first carrier collecting regions 100 and second carrier collecting regions 200;

[0086] Step S02: texturing the first surface A, and depositing a passivation anti-reflection layer 4 on the first surface A;

[0087] Step S03: depositing a first interface passivation layer 2 on the second surface B of the semiconductor substrate 1, and forming a first doped semiconductor layer 3 on the first interface passivation layer 2;

[0088] Step S04: patterning the first doped semiconductor layer 3 and the first interface passivation layer 2 on the second surface B of the semiconductor substrate 1, retaining the first doped semiconductor layer 3 and the first interface passivation layer 2 in the first carrier collection region 100 and the isolation region 300, removing the first doped semiconductor layer 3 and the first interface passivation layer 2 in the second carrier collection region 200, and forming a velvet surface in the second carrier collection region 200;

[0089] Step S05: depositing a second interface passivation layer 6 and a second doped semiconductor layer 7 on the second surface B of the semiconductor substrate 1 in sequence, patterning the second interface passivation layer 6 and the second doped semiconductor layer 7, removing a portion of the second interface passivation layer 6 and the second doped semiconductor layer 7 on the first carrier collection region 100, and exposing the first doped semiconductor layer 3;

[0090] Step S06: depositing a transparent conductive oxide layer 8 on the second surface B of the semiconductor substrate 1, interrupting the transparent conductive oxide layer 8, forming a first transparent conductive oxide layer 81 on the first doped semiconductor layer 3 located in the first carrier collection region 100, and forming a second transparent conductive oxide layer 82 disconnected from the first transparent conductive oxide layer 81 on the second doped semiconductor layer 7 located in the second carrier collection region 200;

[0091] Step S07 : depositing a first electrode 10 on the first transparent conductive oxide layer 81 , and depositing a second electrode 20 on the second transparent conductive oxide layer 82 .

[0092] According to an embodiment of the present application, the first interface passivation layer 2 and the second interface passivation layer 6 are one or both of a tunneling oxide layer or an intrinsic amorphous silicon passivation layer, and the first doped semiconductor layer 3 and the second doped semiconductor layer 7 are one or more of doped polycrystalline silicon, doped amorphous silicon, doped microcrystalline silicon or doped nanocrystalline silicon. The first doped semiconductor layer 3 and the second doped semiconductor layer 7 have opposite doping types, and carriers of different polarities are collected separately. The first doped semiconductor layer 3 and the second doped semiconductor layer 7 can be formed by first depositing an intrinsic semiconductor layer and then doping by diffusion or ion implantation, or by in-situ doping while depositing, or by in-situ doping followed by diffusion or ion implantation.

[0093] According to the manufacturing method of the back-contact solar cell provided in the above embodiment of the present application, step S02 is arranged before step S03: the first surface A is textured, and a passivation anti-reflection layer 4 is deposited on the first surface A; then a first interface passivation layer 2 composed of a tunneling oxide and a first intrinsic semiconductor layer are sequentially deposited on the second surface B of the semiconductor substrate 1, and a diffusion process is used to realize doping of the first intrinsic semiconductor layer to form a first doped semiconductor layer 3. This is a first-texturing process, and compared with a post-texturing process (i.e., a velvet surface is formed on the first surface A later), it can reduce the damage of subsequent wet processes to other deposited film layers. This embodiment can simplify the process steps and reduce the cost of battery manufacturing.

[0094] According to the manufacturing method of the back-contact solar cell provided by another embodiment of the present application, the step S03 can also be arranged before the step S02: a first interface passivation layer 2 composed of a tunneling oxide and a first intrinsic semiconductor layer are sequentially deposited on the second surface B of the semiconductor substrate 1, and a diffusion process is used to realize the doping of the first intrinsic semiconductor layer to form a first doped semiconductor layer 3; the first surface A is then textured, and a passivation anti-reflection layer 4 is deposited on the first surface A. This embodiment can improve the texture quality of the first surface A, the texture has better passivation, and the battery can obtain higher efficiency. In addition, according to the preferred embodiment of this embodiment, the second carrier collection area can also be textured at the same time when the second carrier collection area is textured, thereby reducing the process steps, optimizing the process flow, and reducing the manufacturing cost.

[0095] According to the embodiment of the present application, the process of forming the first interface passivation layer 2 composed of tunnel oxide in the present application can be formed by a thermal oxidation process, or by a wet oxidation process or by an oxygen plasma process; the first doped semiconductor layer 3 can be formed by depositing intrinsic polysilicon by LPCVD, and then performing a phosphorus diffusion or boron diffusion process to form a first doping type of doped polysilicon, or by PECVD deposition of phosphorus-doped or boron-doped first doping type of doped polysilicon. LPCVD or PECVD can be a single insertion process or a double insertion process for silicon wafers.

[0096] In the embodiment of the present application in which step S02 is arranged before step S03, the process of forming the first interface passivation layer 2 composed of intrinsic amorphous silicon can be formed by a PECVD or hot-wire CVD deposition process, and the first doped semiconductor layer 3 can be in-situ doped with phosphorus or boron by PECVD or hot-wire CVD to form a first doping type of doped amorphous silicon, doped microcrystalline silicon or doped nanocrystalline silicon or a combination of at least one of the three. The first doping type can be n-type doping or p-type doping.

[0097] According to a preferred embodiment of the present application, step S04 includes: firstly patterning a phosphosilicate glass layer or a borosilicate glass layer as a second mask layer 12 formed on the first doped semiconductor layer 3 to form a mask pattern, and then patterning the first doped semiconductor layer 3 and the first interface passivation layer 2 on the second surface B of the semiconductor substrate 1 using the phosphosilicate glass or borosilicate glass patterned mask pattern. By utilizing the alkali resistance of phosphosilicate glass or borosilicate glass and the advantage that phosphosilicate glass or borosilicate glass is a byproduct of the polysilicon diffusion doping process, the process can be simplified and the manufacturing cost can be reduced.

[0098] According to another preferred embodiment of the present application, step S04 includes: first removing the phosphosilicate glass layer or borosilicate glass layer formed on the first doped semiconductor layer 3, then forming a SiNx layer on the first doped semiconductor layer as a second mask layer 12, patterning the SiNx layer to form a mask pattern, and then using the SiNx mask pattern to pattern the first doped semiconductor layer 3 and the first interface passivation layer 2 on the second surface B of the semiconductor substrate 1. SiNx has a better selective etching ratio than phosphosilicate glass or borosilicate glass, and improves the patterning effect. At the same time, during the deposition process of SiNx, hydrogen is doped, and hydrogen has a good passivation effect on polysilicon, which can repair defects on the surface of polysilicon.

[0099] According to another preferred embodiment of the present application, in step S04, a SiNx layer is formed on the phosphosilicate glass layer or borosilicate glass layer formed on the first doped semiconductor layer 3, and the stacked layers of the SiNx layer and the phosphosilicate glass layer or the SiNx layer and the borosilicate glass layer are patterned as the second mask layer 12 to form a mask pattern, and then the mask pattern is used to pattern the first doped semiconductor layer 3 and the first interface passivation layer 2 on the second surface B of the semiconductor substrate 1. The composite mask pattern of the SiNx layer superimposed on the phosphosilicate glass layer or the borosilicate glass layer can, on the one hand, enhance the selective etching ratio of the mask pattern and improve the patterning effect, and on the other hand, can utilize the hydrogen in the SiNx to better passivate the polysilicon. In addition, the step of removing the phosphosilicate glass layer or the borosilicate glass layer can be reduced, and the process cost can be reduced.

[0100] According to another embodiment of the present application, in step S04, after removing the first doped semiconductor layer 3 and the first interface passivation layer 2 located in the second carrier collection region 200, a polishing process is performed in the second carrier collection region 200. Next, step S05 is performed to sequentially deposit the second interface passivation layer 6 and the second doped semiconductor layer 7 on the second surface B of the semiconductor substrate 1, pattern the second interface passivation layer 6 and the second doped semiconductor layer 7, completely remove the second interface passivation layer 6 and the second doped semiconductor layer 7 on the first carrier collection region 100, expose the first doped semiconductor layer 3, and remove the second interface passivation layer 6 and the second doped semiconductor layer 7 between the first carrier collection region 100 and the second carrier collection region 200 to form an isolation groove as the isolation region 300.

[0101] According to another embodiment of the present application, when the passivation anti-reflection layer 4 is deposited on the first surface A, the passivation anti-reflection layer is simultaneously formed on the second surface B as the second mask layer 12, the passivation anti-reflection layer on the second surface B is patterned to form a mask pattern, and then the mask pattern is used to pattern the first doped semiconductor layer 3 and the first interface passivation layer 2 on the second surface B of the semiconductor substrate 1. The passivation anti-reflection layer used in the present application is an alkali-resistant material, which has a higher selective etching ratio than silicon materials (single crystal silicon, polycrystalline silicon or amorphous silicon materials). At the same time, the passivation anti-reflection layer contains hydrogen, which better passivates polycrystalline silicon. In addition, the step of depositing the mask layer can also be reduced by one step, thereby reducing the process cost. According to another preferred embodiment of this embodiment, the passivation anti-reflection layer can be covered on the phosphosilicate glass layer or borosilicate glass layer formed on the first doped semiconductor layer 3 to form a stacked mask layer, thereby reducing the step of removing the phosphosilicate glass layer or borosilicate glass layer by one step, thereby reducing the process cost.

[0102] According to some of the above-mentioned embodiments of the present application, the above-mentioned graphic formation of the mask pattern can be to form the mask pattern by removing part of the mask layer by laser etching, or other graphic processes such as photolithography and development.

[0103] According to the embodiment of the present application, the passivation anti-reflection layer 4 includes an AlOx / SiNx stack, and the passivation anti-reflection layer 4 is deposited by atomic layer deposition (ALD) to deposit an AlOx film, which has the advantages of good shape retention, good compactness, and good stability, and has very mature processes and cheap equipment, and can passivate and protect the velvet surface well. High-temperature PECVD deposition of SiNx on the AlOx film can provide sufficient hydrogen to the AlOx film to ensure passivation, and can also play an excellent anti-reflection role. The atomic layer deposition can be a process such as thermal ALD or plasma ALD (PLD).

[0104] According to another embodiment of the present application, the passivation anti-reflection layer 4 includes a SiOx / SiNx stack, SiOx / SiNx is a high temperature resistant passivation anti-reflection layer, the SiOx passivation layer can significantly reduce the surface state density, reduce the carrier surface recombination rate, and combine with the first texturing process, while forming a tunneling oxide layer on the second surface B, the SiOx passivation layer can be formed on the velvet surface of the first surface A at the same time, which can further simplify the process and reduce the cost. The SiOx layer can be formed by a thermal oxidation process, or by a wet oxidation process or by an oxygen plasma process.

[0105] According to another embodiment of the present application, the passivation anti-reflection layer 4 includes a POx / SiNx stack. The introduction of POx can reduce the surface state density of the first surface A of the semiconductor substrate 1 and form a positive charge accumulation area on the first surface A of the semiconductor substrate 1, which can significantly reduce surface defects and reduce surface recombination. POx can be formed by atomic layer deposition (ALD) or PECVD deposition. The SiNx film layer needs to form a dense film layer to cover the POx and protect it to prevent POx from deliquescing.

[0106] According to a preferred embodiment of the present application, a SiOx interface layer is further formed between the AlOx layer of the passivation anti-reflection layer 4 and the first surface A of the semiconductor substrate 1. The SiOx interface layer can further reduce the surface defect density of the semiconductor substrate and reduce defect recombination centers to obtain a better passivation effect.

[0107] According to another preferred embodiment of the present application, the AlOx layer of the passivation anti-reflection layer 4 is formed by ALD deposition, the SiNx layer is deposited by PECVD, and a SiNx interface layer is further deposited by ALD between the AlOx layer and the SiNx layer. The SiNx interface layer deposited by ALD can protect the AlOx layer without changing the deposition chamber, and the hydrogen released by AlOx in the subsequent high-temperature process can be well absorbed by SiNx, or SiNx forms a good coverage to prevent hydrogen overflow, thereby preventing AlOx explosion and causing passivation failure.

[0108] According to the embodiments of the present application, the mask patterns in some of the above embodiments can be removed or retained as the insulating isolation structure formed in the isolation region 300 between the first doped semiconductor layer 3 and the second doped semiconductor layer 7 along the thickness direction, so as to reduce the leakage between the first doped semiconductor layer 3 and the second doped semiconductor layer 7. Alternatively, the transparent conductive oxide layer 8 is further interrupted on the insulating isolation structure, and the insulating structure is used as an energy absorption layer or a stop layer to prevent the laser or wet etching from interrupting and damaging the first or second doped semiconductor layer. According to a preferred embodiment of the present embodiment, before the second interface passivation layer 6 and the second doped semiconductor layer 7 are sequentially deposited on the second surface B of the semiconductor substrate 1, after the first doped semiconductor layer 3 and the first interface passivation layer 2 on the second surface B of the semiconductor substrate 1 are patterned, the insulating isolation structure formed in the isolation region 300 between the first doped semiconductor layer 3 and the second doped semiconductor layer 7 along the thickness direction is retained. Specifically, it can be formed before the second interface passivation layer 6 is deposited or before the second doped semiconductor layer 7 is deposited. Alternatively, before the transparent conductive oxide layer 8 is deposited on the second surface B of the semiconductor substrate 1, after the second interface passivation layer 6 and the second doped semiconductor layer 7 are sequentially deposited on the second surface B of the semiconductor substrate 1, the second interface passivation layer 6, the second doped semiconductor layer 7 and the mask pattern on the second surface B are patterned to form a second opening 2002 to expose the first doped semiconductor layer 3, and at the same time, an insulating isolation structure is formed between the first doped semiconductor layer 3 and the second doped semiconductor layer 7 in the isolation region 300 along the thickness direction. The process steps can be simplified, and the damage to the battery structure film layer can be reduced. The battery efficiency is improved.

[0109] According to another embodiment of the present application, the insulating isolation structure of the isolation region 300 between the first carrier collecting region 100 and the second carrier collecting region 200 of the present application can also be an isolation groove formed between the first carrier collecting region 100 and the second carrier collecting region 200 as the isolation region 300.

[0110] According to another embodiment of the present application, step S06 of the present application may also be to form the first electrode 10 and the second electrode 20 on the first doped semiconductor 3 and the second doped semiconductor 7 on the second surface B of the semiconductor substrate 1 by screen printing or electroplating, without performing step S07.

[0111] According to an embodiment of the present application, the above manufacturing method further includes: depositing a transparent protective layer 5 on the surface of the passivation anti-reflection layer 4 .

[0112] According to an embodiment of the present application, the transparent protective layer 5 is a polytetrafluoroethylene film.

[0113] According to an embodiment of the present application, a polytetrafluoroethylene film is deposited by evaporation coating or magnetron sputtering. After the polytetrafluoroethylene film is deposited, the polytetrafluoroethylene film is annealed. The annealing temperature is 180°C to 220°C, for example, 180°C, 190°C, 200°C, 210°C, 220°C, but not limited to the values ​​listed above; after annealing, the temperature is cooled to room temperature, and the cooling rate is 1 to 6°C / min.

[0114] According to a preferred embodiment of the present application, the transparent protective layer 5 formed on the passivation anti-reflection layer 4 is formed before the second surface B of the second carrier collection region 200 is textured.

[0115] According to the embodiment of the present application, the refractive index of the polytetrafluoroethylene film in the wavelength range of 400-1200nm is between 1.28-1.31, which is lower than the refractive index of silicon nitride, silicon oxide and aluminum oxide in the wavelength range of 400-1200nm, and can cooperate with the passivation anti-reflection layer 4 to further improve the anti-reflection effect. The thickness is 50-200nm, which can optimize the reflectivity of the first surface A film layer.

[0116] According to the embodiments of the present application, the deposited polytetrafluoroethylene film is hydrophobic, and the contact angle (CA) is greater than 106°, which can prevent water vapor from corroding the battery cell, and has good density, does not absorb oxygen, and prevents oxygen from corroding the battery cell.

[0117] According to the embodiments of the present application, reference Figure 2 As shown, the hybrid back contact solar cell comprises:

[0118] A semiconductor substrate 1 has a first surface A and a second surface B relative to each other, and a plurality of side surfaces C adjacent to the first surface A and the second surface B. The first surface A is a velvet surface, and the second surface B is formed with an electrode collecting area. The electrode collecting area includes a plurality of first carrier collecting areas 100 and a plurality of second carrier collecting areas 200 alternately distributed along a first direction, and an isolation area 300 is provided between adjacent first carrier collecting areas 100 and second carrier collecting areas 200.

[0119] According to an embodiment of the present application, the first carrier collecting region 100 may be, for example, a majority carrier collecting region, and the second carrier collecting region 200 may be, for example, a minority carrier collecting region.

[0120] According to an embodiment of the present application, the hybrid back-contact solar cell further includes a first interface passivation layer 2 and a first doped semiconductor layer 3 located in the first carrier collection region 100, wherein the first interface passivation 2 is located on the second surface B of the semiconductor substrate 1, and the first doped semiconductor layer 3 is located on the surface of the first interface passivation 2 away from the semiconductor substrate 1. The first interface passivation layer 2 is preferably a tunneling oxide layer, and the first doped semiconductor layer 3 is a polycrystalline silicon layer doped with a multi-substrate having the same doping type as the semiconductor substrate 1.

[0121] According to an embodiment of the present application, the hybrid back-contact solar cell further includes a second interface passivation layer 6 and a second doped semiconductor layer 7 located in the second carrier collection region 200, wherein the second interface passivation layer 6 is located on the second surface B of the semiconductor substrate 1, and the second doped semiconductor layer 7 is located on the surface of the second interface passivation layer 6 away from the semiconductor substrate 1. The second interface passivation layer 6 is preferably an intrinsic amorphous silicon layer, and the second doped semiconductor layer 7 is a minority-doped amorphous silicon or microcrystalline silicon layer having a doping type opposite to that of the semiconductor substrate 1.

[0122] According to the embodiment of the present application, the passivation anti-reflection layer 4 is one of an AlOx / SiNx stack, a SiOx / SiNx stack, and a POx / SiNx stack. Deposition of the AlOx / SiNx stack passivation anti-reflection layer 4, such as using atomic layer deposition (ALD) to deposit an AlOx film, has the advantages of good shape retention, good density, and good stability, and has very mature processes and cheap equipment, and can passivate and protect the velvet surface well. High-temperature PECVD deposition of SiNx on the AlOx film can not only provide sufficient hydrogen to the AlOx film to ensure passivation, but also play an excellent anti-reflection role. A SiOx / SiNx stacked passivation anti-reflection layer 4 is formed. SiOx / SiNx is a high temperature resistant passivation anti-reflection layer. The SiOx passivation layer can significantly reduce the surface state density and reduce the carrier surface recombination rate. Combined with the first texturing process, a tunneling oxide layer can be formed on the second surface B while a SiOx passivation layer is formed on the velvet surface of the first surface A, which can further simplify the process and reduce costs. A POx / SiNx stacked passivation anti-reflection layer 4 is deposited. The introduction of POx can reduce the surface state density of the first surface A of the semiconductor substrate and form a positive charge accumulation area on the first surface A of the semiconductor substrate, which can significantly reduce surface defects and reduce surface recombination. POx can be formed by atomic layer deposition (ALD) or PECVD deposition. The SiNx film layer needs to form a dense film layer to cover and protect POx to prevent POx from deliquescing.

[0123] According to the embodiment of the present application, an example is taken in which the semiconductor substrate 1 is of N type, the first doped semiconductor layer 3 is of n type, and the second doped semiconductor layer 7 is of p type for description.

[0124] Figure 3A~Figure 3K Schematic diagram of the manufacturing process of the hybrid back-contact solar cell provided in an embodiment of the present application.

[0125] According to an exemplary embodiment of the present application, the present application provides a method for manufacturing a hybrid back contact solar cell, referring to Figure 2 , Figure 3A~Figure 3K As shown, it includes: step S101 to step S107.

[0126] Step S101 : performing a texturing treatment on the first surface A of the semiconductor substrate 1 , so that the first surface A of the semiconductor substrate 1 forms a textured surface.

[0127] According to the embodiments of the present application, reference Figure 2 As shown, the semiconductor substrate 1 has a first surface A and a second surface B relative to each other. The first surface A is the front of the battery, and the second surface B is the back of the battery. The first surface A is a velvet surface, which can reduce the reflection of sunlight on the front of the battery and increase the absorption rate of sunlight. Among them, the second surface B includes a plurality of first carrier collection regions 100 and a plurality of second carrier collection regions 200 alternately distributed along the first direction, and an isolation region 300 is provided between adjacent first carrier collection regions 100 and second carrier collection regions 200.

[0128] According to a preferred embodiment of the present application, the second surface B is a polished surface having a tower base-shaped texture structure. The tower base-shaped texture structure can reduce light reflection, improve light trapping effect, increase the contact area of ​​the conductive layer, and improve contact performance.

[0129] Step S102, depositing a passivation anti-reflection layer 4 on the first surface A and the side surface C of the semiconductor substrate 1 (the passivation anti-reflection layer on the side surface is not formed on the first surface A and the side surface C of the semiconductor substrate 1). Figure 3B-3K As shown in FIG. 1 ), a passivation anti-reflection layer is deposited on the side surface C and retained until the final cell structure, so that the side surface of the semiconductor substrate can be passivated, defects can be reduced, and the cell conversion efficiency can be improved.

[0130] According to an embodiment of the present application, the passivation anti-reflection layer 4 may include, for example, an AlOx layer and a SiNx layer formed on the AlOx layer, wherein the SiNx can provide sufficient hydrogen to the AlOx film to ensure the passivation effect and also play an excellent anti-reflection role.

[0131] According to an embodiment of the present application, AlOx is deposited on the first surface A of the semiconductor substrate 1 by atomic layer deposition (ALD), and SiNx is deposited on the surface of the AlOx layer by PECVD.

[0132] According to the embodiments of the present application, the AlOx film deposited by ALD has the advantages of high density, good shape retention and good stability; and compared with the preparation of the passivation anti-reflection layer by depositing the amorphous silicon layer by PECVD, the ALD equipment and process are very mature, and the preparation of the passivation anti-reflection layer by depositing the AlOx film by ALD has greater cost advantages.

[0133] Step S103, a first interface passivation layer 2 composed of a tunneling oxide layer and a first intrinsic semiconductor layer are sequentially formed on the second surface B and the side surface C of the semiconductor substrate 1, and a phosphorus diffusion process is used to achieve doping of the first intrinsic semiconductor layer to form a first doped semiconductor layer 3, wherein a phosphosilicate glass layer is synchronously formed on the first doped semiconductor layer 3 during the process of forming the first doped semiconductor layer 3.

[0134] According to an embodiment of the present application, before forming the tunneling oxide layer on the second surface B of the semiconductor substrate 1 , the passivation anti-reflection layer coated on the second surface B of the semiconductor substrate 1 is removed.

[0135] According to an embodiment of the present application, the tunneling oxide layer is SiOx, and SiOx is formed on the second surface B of the semiconductor substrate 1 by using a thermal oxidation method.

[0136] According to a preferred embodiment of the present application, in the second surface B, the region where the stacked first interface passivation layer 2 and the first doped semiconductor layer 3 are provided has a tower-shaped texture structure; the thickness of the first interface passivation layer 2 located at the bottom surface of the tower-shaped texture structure is greater than the thickness of the first interface passivation layer 2 located at the side wall of the tower-shaped texture structure. In the second surface B, the bottom surface of the tower-shaped texture structure accounts for a larger proportion than its side surface, so when the portion of the first interface passivation layer 2 provided on the bottom surface of the tower-shaped texture structure has a greater thickness, the first interface passivation layer 2 has a higher passivation effect on the semiconductor substrate. In addition, the portion of the first interface passivation layer 2 provided on the side wall of the tower-shaped texture structure has a smaller thickness, and at this time, the portion has a relatively low tunneling resistance, which improves the carrier collection efficiency of the first doped semiconductor layer 3 at this location, synergistically improves the passivation effect and electrical collection performance, and further improves the electrical performance of the back contact solar cell.

[0137] According to another preferred embodiment of the present application, in the second surface B, the region where the stacked first interface passivation layer 2 and the first doped semiconductor layer 3 are provided has a tower-like texture structure; the thickness of the first interface passivation layer 2 located at the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer 2 located at the side wall of the tower-like texture structure. In the second surface B, the bottom surface of the tower-like texture structure and the side surface of the tower-like texture structure have different crystal orientations. Specifically, the bottom surface of the tower-like texture structure is a

[110] crystal orientation, and the number of dangling bonds on the surface of the

[110] crystal orientation is relatively small; while the side surface of the tower-like texture structure is a

[111] crystal orientation, and the number of dangling bonds on the

[111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer 2 located on the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer 2 located on the side wall of the tower-shaped texture structure, it is beneficial for the thickness of the first interface passivation layer 2 located on the side wall of the tower-shaped texture structure to have a relatively high passivation effect, meet the demand for high passivation effect on the side of the tower-shaped texture structure, reduce the carrier recombination rate on the side of the tower-shaped texture structure, and further improve the working efficiency of the back-contact solar cell.

[0138] As a possible implementation scheme, the thickness of the first interface passivation layer 2 located on the bottom surface of the tower-shaped texture structure away from the semiconductor substrate 1 is greater than or equal to 0.5nm and less than or equal to 1.5nm. In this case, the thickness of the first interface passivation layer 2 located on the bottom surface of the tower-shaped texture structure is within the above range, which is conducive to preventing the first interface passivation layer 2 from having a lower passivation effect on the semiconductor substrate 1 due to the smaller thickness of the bottom surface of the tower-shaped texture structure; in addition, it is also conducive to preventing the first interface passivation layer 2 from having a higher tunneling resistance due to the larger thickness of the bottom surface of the tower-shaped texture structure, and is conducive to achieving a balance between the passivation effect and tunneling resistance of the first interface passivation layer 2 located on the bottom surface of the tower-shaped texture structure, thereby reducing the carrier recombination rate on the side of the tower-shaped texture structure while ensuring that the first doped semiconductor layer 3 has a higher carrier collection efficiency and reduces transmission loss. The thickness of the first interface passivation layer 2 located on the side of the tower-shaped texture structure away from the semiconductor substrate 1 is smaller, which is conducive to making the part of the first interface passivation layer 2 located on the side of the tower-shaped texture structure away from the semiconductor substrate 1 have a lower tunneling resistance, ensuring that the first doped semiconductor layer 3 has a higher carrier collection efficiency and reducing transmission losses.

[0139] As a possible implementation scheme, the thickness of the first interface passivation layer 2 located on the side wall of the tower-shaped texture structure is greater than or equal to 0.5nm and less than or equal to 2nm. In this case, the thickness of the first interface passivation layer 2 located on the side wall of the tower-shaped texture structure is within the above range, which is conducive to preventing the lower passivation effect of the first interface passivation layer 2 due to the smaller thickness of the part; in addition, it is also conducive to preventing the first interface passivation layer 2 from being located on the side wall of the tower-shaped texture structure due to the larger thickness, which leads to the higher tunneling resistance of the part, and is conducive to achieving the balance between the passivation effect and tunneling resistance of the part of the first interface passivation layer 2 located on the side wall of the tower-shaped texture structure, thereby reducing the carrier recombination rate on the side of the tower-shaped texture structure, while ensuring that the first doped semiconductor layer 3 has a higher carrier collection efficiency and reduces the transmission loss. The thickness located on the side wall of the tower-shaped texture structure is larger, which is conducive to making the part of the first interface passivation layer 3 located on the side wall of the tower-shaped texture structure have a higher passivation effect, reducing the carrier recombination rate on the side of the tower-shaped texture structure.

[0140] According to an embodiment of the present application, after the first doped semiconductor layer 3 is formed on the second surface B of the semiconductor substrate 1 , the phosphosilicate glass layer formed on the first doped semiconductor layer 3 on the second surface B is removed by acid washing.

[0141] Step S104 , depositing a first mask layer 11 on the passivation anti-reflection layer 4 on the first surface A of the semiconductor substrate 1 , and depositing a second mask layer 12 on the first doped semiconductor layer 3 on the second surface B of the semiconductor substrate 1 .

[0142] According to an embodiment of the present application, the material of the first mask layer 11 and the second mask layer 12 is SiNx.

[0143] The first doped semiconductor layer 3 and the first interface passivation layer 2 on the second surface B are patterned to form a first opening 2001 in the second carrier collection region 200 on the second surface B of the semiconductor substrate 1, wherein the second carrier collection region 200 and the first carrier collection region 100 retaining the first interface passivation layer 2 and the first doped semiconductor layer 3 are alternately distributed in the first direction.

[0144] According to an embodiment of the present application, laser etching is used to pattern the second mask layer 12, and the first doped semiconductor layer 3 and the first interface passivation layer 2 are etched to the semiconductor substrate 1 using the patterned second mask layer 12 to form a first opening 2001 in the second carrier collection region 200 on the second surface B of the semiconductor substrate 1. The second carrier collection region 200 is subjected to a texturing treatment, so that the second surface B of the semiconductor substrate 1 located in the second carrier collection region 200 has a texturing structure.

[0145] According to an embodiment of the present application, after the second carrier collecting region 200 is textured, the second mask layer 12 located on the second surface B and the first mask layer 11 located on the first surface A are removed by using HF.

[0146] According to another embodiment of the present application, in the process of forming the texture on the second surface B, it is not necessary to use the first mask layer 11 and the second mask layer 12 as masks. Specifically, when the first doped semiconductor layer 3 is formed on the second surface B, a phosphosilicate glass layer is simultaneously generated on the surface of the first doped semiconductor layer 3, and the phosphosilicate glass layer covers the side surface C. The phosphosilicate glass layer on the second carrier collection area 200 of the second surface B is removed by laser, and the patterned phosphosilicate glass layer is used as a mask to perform a texture treatment on the second surface B located in the second carrier collection area 200. In this way, the process of forming a mask once can be reduced, and the complexity of the process can be reduced.

[0147] According to a preferred embodiment of the present application, the width of the first opening 2001 is greater than or equal to 250 μm and less than or equal to 400 μm. Compared with the opening width of the existing back-contact solar cell less than or equal to 200 μm, the width of the first opening 2001 for exposing the first doped semiconductor layer 3 to the outside is larger in the back-contact solar cell formed by the manufacturing method provided, which is beneficial to prevent short circuits, so that the corresponding conductive material electrically connected to the first doped semiconductor layer 3 has a larger formable range, thereby facilitating the increase of the contact area between the first doped semiconductor layer and the corresponding conductive material, reducing transmission loss, and improving the electrical reliability of the manufactured back-contact solar cell. Secondly, when the width of the first opening 2001 is less than 400 μm, the second interface passivation layer 6 and the second doped semiconductor layer 7 are retained in a larger portion after the operation of opening the first opening 2001, while reducing the etching amount, ensuring that the second interface passivation layer 6 and the second doped semiconductor layer 7 have a certain area share on the side of the second surface B, ensuring that the second doped semiconductor layer 7 has a higher current collection efficiency.

[0148] Step S105 , depositing a second interface passivation layer 6 and a second doped semiconductor layer 7 in the second carrier collection region 200 .

[0149] According to an embodiment of the present application, PECVD is used to deposit an intrinsic amorphous silicon layer as a second interface passivation layer 6 and doped amorphous silicon or microcrystalline silicon as a second doped semiconductor layer 7 on the second surface B of the semiconductor substrate 1. Laser is used to remove the second interface passivation layer 6 and the second doped semiconductor layer 7 located in the first carrier collection region 100.

[0150] According to a preferred embodiment of the present application, the thickness of the second interface passivation layer 6 is greater than or equal to 8 nm and less than or equal to 14 nm. In this case, the thickness of the second interface passivation layer 6 is relatively large, which is conducive to enhancing the isolation effect of the second interface passivation layer 6 on the first doped semiconductor layer 3 and the second doped semiconductor layer 7, and reducing the risk of leakage.

[0151] According to a preferred embodiment of the present application, a laser etching process is used to selectively etch the stacked second interface passivation layer 6 and the second doped semiconductor layer 7. After selective etching, a second opening 2002 is formed, and a hole structure is formed in the edge portion of the second doped semiconductor layer 7 adjacent to the second opening 2002. The hole structure is a hollow structure, so when a hole structure is formed in the edge portion of the second doped semiconductor layer 7, the risk of leakage between the edge portion of the second doped semiconductor layer 7 and the first doped semiconductor layer 3 can be reduced, thereby improving the electrical reliability of the back-contact solar cell. In addition, the presence of the hole structure can also increase the undulation of the edge portion of the stacked second interface passivation layer 6 and the second doped semiconductor layer 7, thereby enhancing the light trapping effect of this portion, which is beneficial to improving the bifaciality of the back-contact solar cell.

[0152] According to a preferred embodiment of the present application, the first interface passivation layer 2 and the first doped semiconductor layer 3 are located in the first carrier collection region 100 and the isolation region 300; the second interface passivation layer 6 and the second doped semiconductor layer 7 are located in the second carrier collection region 200 and the isolation region 300, and cover part of the first interface passivation layer 2 and the first doped semiconductor layer 3 along the extension to the first carrier collection region 100; the surface of the first carrier collection region 100 is a polished surface structure, and the bottom surface of the first opening 2001 is a velvet structure; the thickness of the second doped semiconductor layer 7 located on the velvet structure is less than the thickness of the second doped semiconductor layer 7 located on the polished surface structure. The existence of the first opening 2001 makes the first doped semiconductor layer 3 and the second doped semiconductor layer 7 staggered along the thickness direction of the semiconductor substrate 1, reducing the risk of leakage. In addition, compared with the polished surface, the specific surface area of ​​the velvet surface is larger. In the same formation range, the contact area between the part of the second doped semiconductor layer 7 located on the velvet surface and the semiconductor substrate 1 is larger, while the contact area between the part of the second doped semiconductor layer 7 located on the polished surface and the semiconductor substrate 1 is smaller. Based on this, when the thickness of the second doped semiconductor layer 7 on the velvet surface is relatively small, after ensuring that the portion of the second doped semiconductor layer 7 on the velvet surface has sufficient contact area with the semiconductor substrate 1, a space that can be reduced can be reserved for setting the thickness of the portion, and the amount of consumables used in manufacturing the portion of the second doped semiconductor layer 7 on the velvet surface can be reduced while ensuring a high carrier collection efficiency. In addition, the thickness of the second doped semiconductor layer 7 on the polished surface is relatively large, so that the portion has a higher field passivation effect and reduces carrier recombination. In this case, the thickness difference between different portions of the second doped semiconductor layer 7 can be set according to the surface roughness of the first carrier collection area 100 and the second carrier collection area 200, and actual needs, and is not specifically limited here. According to a preferred embodiment of the present application, the second doped semiconductor layer 7 is doped amorphous silicon, and before the transparent conductive oxide layer 8 is deposited on the second surface B of the semiconductor substrate 1, after the second interface passivation layer 6 and the second doped semiconductor layer 7 are sequentially deposited on the second surface B of the semiconductor substrate 1, the second doped semiconductor layer 7 located on the bottom surface of the first opening 2001 is laser irradiated to crystallize the second doped semiconductor layer 7. After crystallization, all or part of the second doped semiconductor layer 7 can be crystallized into microcrystalline silicon or nanocrystalline silicon, so that the second doped semiconductor layer 7 is crystallized by heat, the degree of crystallization of the second doped semiconductor layer 7 is improved, thereby improving the conductivity of the second doped semiconductor layer, reducing the contact resistance between the second doped semiconductor layer and the corresponding conductive material, and reducing transmission loss.

[0153] According to an embodiment of the present application, the second interface passivation layer (for example, the intrinsic semiconductor layer) 6 and the second doped semiconductor layer 7 that are disposed around the first surface A are removed by alkaline washing; and then the oxide layer on the second surface B is removed by acid washing, wherein the oxide layer is generated in the process of removing the second interface passivation layer 6 and the second doped semiconductor layer 7 of the first carrier collection region 100 by laser.

[0154] According to the embodiment of the present application, in the process of forming the first interface passivation layer 2 and the first doped semiconductor layer 3 on the second surface B, the first interface passivation layer 2 and the first doped semiconductor layer 3 are plated around the side surface C, and the first doped semiconductor layer 3 is plated around the first surface A to form a natural double-layer mask layer, wherein the phosphosilicate glass layer is alkali-resistant and the first doped semiconductor layer 3 is acid-resistant. Therefore, in the process of using an alkali solution to texture the second surface B of the semiconductor substrate 1 in the second carrier collection area 200, there is no need to deposit a mask layer on the first surface A to prevent the alkali solution from etching the first surface A.

[0155] Step S106, depositing a transparent conductive oxide layer 8 on the first doped semiconductor layer 3 located in the first carrier collection region 100, interrupting the transparent conductive oxide layer 8 to form a first transparent conductive oxide layer 81, and forming a second transparent conductive oxide layer 82 on the second doped semiconductor layer 7 located in the second carrier collection region 200, wherein the first transparent conductive oxide layer 81 is electrically isolated from the second transparent conductive oxide layer 82.

[0156] According to an embodiment of the present application, a transparent conductive oxide layer 8 is deposited on the second surface B of the semiconductor substrate 1 by magnetron sputtering; and the transparent conductive oxide layer 8 is etched by laser to form a first transparent conductive oxide layer 81 and a second transparent conductive oxide layer 82 .

[0157] According to the embodiment of the present application, the transparent conductive oxide layer 8 is interrupted, at least the transparent conductive oxide layer 8 of the isolation region 300 is interrupted, and the thickness of the edge portion of the first transparent conductive oxide layer 81 and / or the second transparent conductive oxide layer 82 adjacent to the isolation region 300 gradually decreases in the direction close to the isolation region 300. The thickness of the transparent conductive layer close to both sides of the isolation region 300 is smaller, and at this time, the thickness of the two parts of the transparent conductive layer for transmitting opposite-sex carriers is smaller (the facing area is also smaller), which is conducive to reducing the risk of leakage and improving the electrical reliability of the back-contact solar cell.

[0158] Step S107 , depositing the first electrode 10 on the first transparent conductive oxide layer 81 , and depositing the second electrode 20 on the second transparent conductive oxide layer 82 .

[0159] Figure 4 A schematic cross-sectional view of a hybrid back-contact solar cell provided in accordance with another embodiment of the present application.

[0160] Figure 5A to Figure 5I FIG. 1 is a schematic diagram of a manufacturing process of a hybrid back-contact solar cell according to another embodiment of the present application.

[0161] According to an exemplary embodiment of the present application, the present application provides a method for manufacturing a hybrid back contact solar cell, referring to Figure 4 , Figure 5A to Figure 5I As shown, it includes: step S201 to step S207.

[0162] Step S201, providing a conductor substrate 1, wherein the semiconductor substrate 1 has a first surface A and a second surface B opposite to each other, and both the first surface A and the second surface B are polished surfaces. The second surface B includes a plurality of first carrier collecting regions 100 and a plurality of second carrier collecting regions 200 alternately distributed along a first direction, and an isolation region 300 is provided between adjacent first carrier collecting regions 100 and second carrier collecting regions 200.

[0163] Step S202 , depositing a first interface passivation layer 2 composed of a tunneling oxide layer and a first intrinsic semiconductor layer on the second surface B and the side surface C of the semiconductor substrate 1 , and adopting a phosphorus diffusion process to dope the first intrinsic semiconductor layer to form a first doped semiconductor layer 3 .

[0164] According to an embodiment of the present application, in the process of forming the first interface passivation layer 2 and the first doped semiconductor layer 3 on the second surface B and the side surface C of the semiconductor substrate 1, the first interface passivation layer and the first doped semiconductor layer are formed by plating on the first surface A of the semiconductor substrate 1, wherein in the process of forming the first doped semiconductor layer 3, a phosphosilicate glass layer (PSG) is simultaneously formed on the first doped semiconductor layer 3.

[0165] Step S203 , performing a texturing treatment on the first surface A of the semiconductor substrate 1 , so that the first surface A forms a texturing structure.

[0166] According to an embodiment of the present application, before the first surface A of the semiconductor substrate 1 is textured, the phosphosilicate glass layer, the first doped semiconductor layer 3 and the first surface passivation layer 2 coated on the first surface A of the semiconductor substrate 1 are removed.

[0167] A passivation anti-reflection layer 4 is deposited on the first surface A of the semiconductor substrate 1 .

[0168] According to an embodiment of the present application, during the process of depositing the passivation anti-reflection layer 4 on the first surface A of the semiconductor substrate 1 , the passivation anti-reflection layer 4 is formed on the second surface B of the semiconductor substrate 1 by wrapping plating.

[0169] According to the embodiment of the present application, during the process of depositing the passivation anti-reflection layer 4 on the first surface A, AlOx is deposited by ALD, and SiNx is deposited on AlOx by ALD. It should be noted that AlOx is usually deposited in a hydrogen atmosphere, and the deposited AlOx layer also contains hydrogen atoms; in the temperature environment of the subsequent deposition of the second doped semiconductor layer, the hydrogen atoms polymerize to generate hydrogen, and the escape of hydrogen may cause the passivation anti-reflection layer to explode, affecting the passivation performance. By depositing dense SiNx on AlOx by ALD, the explosion of the film can be avoided.

[0170] Step S204 , depositing SiNx on the passivation anti-reflection layer 4 on the first surface A as a third mask layer 13 .

[0171] The second doped semiconductor layer 3 and the first interface passivation layer 2 on the second surface B are patterned to form a first opening 2001 in the second carrier collection region 200 on the second surface B of the semiconductor substrate 1, wherein the second carrier collection region 200 and the first carrier collection region 100 retaining the first interface passivation 2 and the first doped semiconductor layer 3 are alternately distributed in a first direction.

[0172] According to an embodiment of the present application, laser etching is used to pattern the first doped semiconductor layer 3 and the first interface passivation layer 2 to the semiconductor substrate 1 to form a first opening 2001 in the second carrier collection region 200 at the second surface B of the semiconductor substrate 1 .

[0173] According to an embodiment of the present application, the semiconductor substrate 1 located in the second carrier collecting region 200 is a polished surface.

[0174] Alternatively, according to an embodiment of the present application, the semiconductor substrate 1 located in the second carrier collection region 200 is a velvet surface. After the first opening 2001 of the second carrier collection region 200 is formed on the second surface B of the semiconductor substrate 1, a velvet treatment is performed on the second surface B located in the second carrier collection region 200, so that the second surface B located in the second carrier collection region 200 forms a velvet surface.

[0175] Step S205, depositing an intrinsic amorphous silicon layer as a second interface passivation layer 6 and a doped amorphous silicon layer or a microcrystalline silicon layer as a second doped semiconductor layer 7 in the second carrier collection region 200. Patterning the second interface passivation layer 6 and the second doped semiconductor layer 7, removing portions of the second interface passivation layer 6 and the second doped semiconductor layer 7 on the first carrier collection region 100, exposing the first doped semiconductor layer 3.

[0176] Step S206, depositing a transparent conductive oxide layer 8 on the first doped semiconductor layer 3 located in the first carrier collection region 100, interrupting the transparent conductive oxide layer 8 to form a first transparent conductive oxide layer 81, and forming a second transparent conductive oxide layer 82 on the second doped semiconductor layer 7 located in the second carrier collection region 200, wherein the first transparent conductive oxide layer 81 is electrically isolated from the second transparent conductive oxide layer 82.

[0177] Step S207 , depositing the first electrode 10 on the first transparent conductive oxide layer 81 , and depositing the second electrode 20 on the second transparent conductive oxide layer 82 .

[0178] Figure 6 A schematic cross-sectional view of a hybrid back-contact solar cell provided in yet another embodiment of the present application.

[0179] Figure 7A to Figure 7F A schematic diagram of the manufacturing process of a hybrid back-contact solar cell provided in yet another embodiment of the present application.

[0180] According to an exemplary embodiment of the present application, the present application provides a method for manufacturing a hybrid back contact solar cell, referring to Figure 6 , Figure 7A to Figure 7F As shown, it includes: step S301 to step S309.

[0181] Step S301, providing a conductor substrate 1, wherein the semiconductor substrate 1 has a first surface A and a second surface B opposite to each other, and both the first surface A and the second surface B are polished surfaces. The second surface B includes a plurality of first carrier collecting regions 100 and a plurality of second carrier collecting regions 200 alternately distributed along a first direction, and an isolation region 300 is provided between adjacent first carrier collecting regions 100 and second carrier collecting regions 200.

[0182] Step S302, depositing a first interface passivation layer 2 and a first intrinsic semiconductor layer composed of a tunneling oxide layer on the second surface B and the side surface C of the semiconductor substrate 1, and using a phosphorus diffusion process to dope the first intrinsic semiconductor layer to form a first doped semiconductor layer 3. It should be noted that, referring to Fig. 7A As shown, the first interface passivation layer and the first intrinsic semiconductor layer are deposited on the second surface B and the side surface C of the semiconductor substrate 1, and in the subsequent phosphorus diffusion process, the first interface passivation and the first doped semiconductor layer 3 are coated on the first surface A of the semiconductor substrate 1, wherein a phosphosilicate glass layer is simultaneously formed on the first doped semiconductor layer 3 during the formation of the first doped semiconductor 3.

[0183] According to an embodiment of the present application, a first interface passivation layer 2 and a first doped semiconductor layer 3 can be formed on the second surface B of the semiconductor substrate 1 by a single-sided deposition method to avoid plating around the first surface A; and since the first interface passivation layer 2 and the first doped semiconductor layer 3 can be formed on two semiconductor substrates at the same time in a back-to-back manner, the preparation efficiency can be improved.

[0184] Step S303 , depositing a fourth mask layer 14 on the second surface B of the semiconductor substrate 1 .

[0185] According to an embodiment of the present application, the material of the fourth mask layer 14 may be SiNx, and the thickness may be 50-200 nm, for example, 50 nm, 80 nm, 100 nm, 150 nm, 200 nm, but is not limited to the above values.

[0186] The first surface A of the semiconductor substrate 1 is subjected to a texturing treatment so that the first surface A of the semiconductor substrate 1 forms a textured surface.

[0187] According to an embodiment of the present application, before the second surface A is textured, the first interface passivation layer 2 , the first doped semiconductor layer 3 , and the phosphosilicate glass layer coated on the first surface A are removed.

[0188] According to an embodiment of the present application, a fourth mask layer 14 is deposited on the second surface B of the semiconductor 1 to prevent the second surface B from being damaged during the texturing process of the first surface A using an alkali solution.

[0189] A passivation anti-reflection layer 4 and a transparent protective layer 5 are sequentially deposited on the textured structure of the first surface A of the semiconductor substrate 1 .

[0190] According to an embodiment of the present application, the material of the transparent protective layer 5 may be polytetrafluoroethylene (PTFE) with a thickness of 50-200 nm, for example, 50 nm, 100 nm, 120 nm, 150 nm, 200 nm, but not limited to the above values.

[0191] According to the embodiment of the present application, the transparent protective layer 5 is hydrophobic, and the transparent protective layer 5 is also beneficial to reduce the water residue of the entire battery after the second carrier collection area 200 is textured, thereby improving the open circuit voltage and fill factor of the battery. It should be noted that a water-rich atmosphere will reduce the open circuit voltage and fill factor of the battery.

[0192] According to the embodiment of the present application, PTFE is deposited by evaporation coating or magnetron sputtering, and after the PTFE is deposited, the PTFE film is annealed. The annealing temperature is 180°C to 220°C, and after annealing, the temperature is lowered to room temperature at a cooling rate of 1 to 6°C / min to improve the crystallization performance of the PTFE film and improve the corrosion resistance of the PTFE film.

[0193] In step S304, the second doped semiconductor layer 3 and the first interface passivation layer 2 on the second surface B are patterned to form a first opening 2001 in the second carrier collection region 200 on the second surface B of the semiconductor substrate 1, wherein the second carrier collection region 200 and the first carrier collection region 100 retaining the first interface passivation layer 2 and the first doped semiconductor layer 3 are alternately distributed in a first direction.

[0194] According to an embodiment of the present application, the fourth mask layer 14 is patterned, and the first doped semiconductor layer 3 and the first interface passivation layer 2 are laser etched to the semiconductor substrate 1 using the patterned fourth mask layer 14 to form an opening 2001 in the second carrier collection region 200 on the second surface B of the semiconductor substrate 1.

[0195] The second surface B of the semiconductor substrate 1 located in the second carrier collecting region 200 is subjected to a texturing treatment so that the second surface B of the second carrier collecting region 200 forms a texturing structure.

[0196] According to another embodiment of the present application, the fourth mask layer is not required in the process of forming the texture on the second surface B. Specifically, the passivation anti-reflection layer 4 is wrapped around the second surface B and the side surface C of the semiconductor substrate 1, and the passivation anti-reflection layer 4 on the second carrier collection area 200 of the second surface B is removed by laser, and the patterned passivation anti-reflection layer 4 is used as a mask to perform a texture treatment on the second surface B located in the second carrier collection area 200.

[0197] Step S305, PECVD is used to deposit a second interface passivation layer 6 composed of intrinsic amorphous silicon and a second doped semiconductor layer 7 composed of doped amorphous silicon or doped microcrystalline silicon on the second surface B of the semiconductor substrate 1. The second interface passivation layer (intrinsic semiconductor layer) and the second doped semiconductor layer 7 located in the first carrier collection region 100 are removed by laser.

[0198] According to an embodiment of the present application, before depositing the second interface passivation layer 6 , the residual fourth mask layer 14 on the second surface B is removed.

[0199] Step S306, depositing a transparent conductive oxide layer 8 on the first doped semiconductor layer 3 located in the first carrier collection region 100, interrupting the transparent conductive oxide layer 8 to form a first transparent conductive oxide layer 81, and forming a second transparent conductive oxide layer 82 on the second doped semiconductor layer 7 located in the second carrier collection region 200, wherein the first transparent conductive oxide layer 81 is electrically isolated from the second transparent conductive oxide layer 82.

[0200] Step S307 , depositing the first electrode 10 on the first transparent conductive oxide layer 81 , and depositing the second electrode 20 on the second transparent conductive oxide layer 82 .

[0201] Figure 8 A schematic cross-sectional view of a hybrid back-contact solar cell provided in yet another embodiment of the present application.

[0202] According to an embodiment of the present application, the insulating isolation structure of the isolation region 300 between the first carrier collection region 100 and the second carrier collection region 200 can also be an isolation groove formed between the first carrier collection region 100 and the second carrier collection region 200 as the isolation region 300. The first electrode 10 and the second electrode 20 are respectively formed on the first doped semiconductor 3 and the second doped semiconductor 7 by screen printing or electroplating. No transparent conductive oxide layer is required.

[0203] According to the manufacturing method of the back-contact solar cell provided in the above-mentioned embodiment of the present application, after the passivation anti-reflection layer 4 is deposited on the first surface A of the semiconductor substrate 1, the second surface B of the semiconductor substrate 1 located in the second carrier collection area 200 is subjected to a texturing treatment, thereby ensuring that the texturized surface of the semiconductor substrate 1 in the second carrier collection area 200 is not contaminated by plating when the passivation anti-reflection layer 4 is deposited.

[0204] According to the manufacturing method of the back-contact solar cell provided in the above-mentioned embodiment of the present application, a transparent protective layer 5 is deposited on the passivation anti-reflection layer 4, which can prevent the first passivation anti-reflection layer 4 from being corroded during the texturing process of the second surface B of the semiconductor substrate 1 located in the second carrier collection area 200, thereby preventing the passivation quality of the first surface A from being affected.

[0205] According to the embodiment of the present application, the transparent protective layer 5 itself has high light transmittance and can be used together with the passivation anti-reflection layer 4 to reduce reflection on the first surface A. The transparent protective layer 5 does not need to be removed after the battery is prepared.

[0206] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the corresponding elements, do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0207] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for manufacturing a back contact solar cell, characterized in that: The steps include: S01: providing a semiconductor substrate (1), the semiconductor substrate (1) having a first surface (A) and a second surface (B) opposite to each other, wherein the second surface (B) comprises a plurality of first carrier collecting regions (100) and a plurality of second carrier collecting regions (200) alternately distributed along a first direction, and an isolation region (300) is provided between adjacent first carrier collecting regions (100) and second carrier collecting regions (200); S02: texturing the first surface (A), and depositing a passivation anti-reflection layer (4) on the first surface (A); S03: depositing a first interface passivation layer (2) on the second surface (B) of the semiconductor substrate (1), and forming a first doped semiconductor layer (3) on the first interface passivation layer (2); S04: patterning the first doped semiconductor layer (3) and the first interface passivation layer (2) on the second surface (B) of the semiconductor substrate (1), retaining the first doped semiconductor layer (3) and the first interface passivation layer (2) in the first carrier collection region (100) and the isolation region (300), removing the first doped semiconductor layer (3) and the first interface passivation layer (2) in the second carrier collection region (200), and forming a velvet surface in the second carrier collection region (200); S05: depositing a second interface passivation layer (6) and a second doped semiconductor layer (7) in sequence on the second surface (B) of the semiconductor substrate (1), patterning the second interface passivation layer (6) and the second doped semiconductor layer (7), removing a portion of the second interface passivation layer (6) and the second doped semiconductor layer (7) on the first carrier collection region (100), and exposing the first doped semiconductor layer (3); S06: depositing a transparent conductive oxide layer (8) on the second surface (B) of the semiconductor substrate (1), interrupting the transparent conductive oxide layer (8), forming a first transparent conductive oxide layer (81) on the first doped semiconductor layer (3) located in the first carrier collection region (100), and forming a second transparent conductive oxide layer (82) disconnected from the first transparent conductive oxide layer (81) on the second doped semiconductor layer (7) located in the second carrier collection region (200); S07: depositing a first electrode (10) on the first transparent conductive oxide layer (81), and depositing a second electrode (20) on the second transparent conductive oxide layer (82).

2. The manufacturing method according to claim 1, characterized in that: Set step S02 before step S03: Texturing the first surface (A) and depositing a passivation anti-reflection layer (4) on the first surface (A); Then, a first interface passivation layer (2) composed of a tunneling oxide and a first intrinsic semiconductor layer are sequentially deposited on the second surface (B) of the semiconductor substrate (1), and a diffusion process is used to achieve doping of the first intrinsic semiconductor layer to form a first doped semiconductor layer (3); Alternatively, the step S03 is set before the step S02: A first interface passivation layer (2) composed of a tunneling oxide and a first intrinsic semiconductor layer are sequentially deposited on the second surface (B) of the semiconductor substrate (1), and a diffusion process is used to achieve doping of the first intrinsic semiconductor layer to form a first doped semiconductor layer (3); The first surface (A) is then textured, and a passivation anti-reflection layer (4) is deposited on the first surface (A).

3. The manufacturing method according to claim 1, characterized in that: After a passivation anti-reflection layer (4) is deposited on the first surface (A), a transparent protective layer (5) is formed on the surface of the passivation anti-reflection layer (4) before a suede surface is formed in the second carrier collection region (200).

4. The manufacturing method according to claim 2, characterized in that: Step S04 comprises: firstly patterning the phosphosilicate glass layer or borosilicate glass layer formed on the first doped semiconductor layer (3) to form a mask pattern, and then patterning the first doped semiconductor layer (3) and the first interface passivation layer (2) on the second surface (B) of the semiconductor substrate (1) using the phosphosilicate glass or borosilicate glass patterned mask pattern; Alternatively, step S04 comprises: first removing the phosphosilicate glass layer or borosilicate glass layer formed on the first doped semiconductor layer (3), then forming a SiNx layer on the first doped semiconductor layer (3), patterning the SiNx layer to form a mask pattern, and then patterning the first doped semiconductor layer (3) and the first interface passivation layer (2) on the second surface (B) of the semiconductor substrate (1) using the SiNx mask pattern; Alternatively, in step S04, a SiNx layer is formed on the phosphosilicate glass layer or the borosilicate glass layer formed on the first doped semiconductor layer (3), the stack of the SiNx layer and the phosphosilicate glass layer or the stack of the SiNx layer and the borosilicate glass layer is patterned to form a mask pattern, and then the mask pattern is used to pattern the first doped semiconductor layer (3) and the first interface passivation layer (2) on the second surface (B) of the semiconductor substrate (1).

5. The manufacturing method according to claim 2, characterized in that: When a passivation anti-reflection layer (4) is deposited on the first surface (A), a passivation anti-reflection layer (4) is simultaneously formed on the second surface (B), the passivation anti-reflection layer (4) on the second surface (B) is patterned to form a mask pattern, and the mask pattern is then used to pattern the first doped semiconductor layer (3) and the first interface passivation layer (2) on the second surface (B) of the semiconductor substrate (1).

6. The manufacturing method according to claim 1, characterized in that: The passivation anti-reflection layer (4) is one of an AlOx / SiNx stack, a SiOx / SiNx stack and a POx / SiNx stack.

7. The manufacturing method according to claim 1, characterized in that: The passivation anti-reflection layer (4) comprises an AlOx / SiNx stack, A SiOx interface layer is also formed between the AlOx of the passivation anti-reflection layer (4) and the first surface (A) of the semiconductor substrate (1).

8. The manufacturing method according to claim 1, characterized in that: The passivation anti-reflection layer (4) comprises an AlOx / SiNx stack; The AlOx layer of the passivation anti-reflection layer (4) is formed by deposition using an atomic layer deposition method. The SiNx layer of the passivation anti-reflection layer (4) is formed by deposition using a plasma enhanced chemical vapor deposition method. A SiNx interfacial layer is also deposited between the AlOx layer and the SiNx layer by atomic layer deposition.

9. The manufacturing method according to claim 4 or 5, characterized in that: After the first doped semiconductor layer (3) and the first interface passivation layer (2) are patterned, removing the mask pattern on the second surface (B); Alternatively, before the second interface passivation layer (6) and the second doped semiconductor layer (7) are sequentially deposited on the second surface (B) of the semiconductor substrate (1), after the first doped semiconductor layer (3) and the first interface passivation layer (2) on the second surface (B) of the semiconductor substrate (1) are patterned, the mask pattern on the second surface (B) is patterned again to form an insulating isolation structure between the first doped semiconductor layer (3) and the second doped semiconductor layer (7) in the isolation region (300) along the thickness direction; Alternatively, before depositing the transparent conductive oxide layer (8) on the second surface (B) of the semiconductor substrate (1), after depositing the second interface passivation layer (6) and the second doped semiconductor layer (7) on the second surface (B) of the semiconductor substrate (1) in sequence, the second interface passivation layer (6), the second doped semiconductor layer (7) and the mask pattern on the second surface (B) are patterned to form a second opening (2002) to expose the first doped semiconductor layer (3), and at the same time, an insulating isolation structure is formed between the first doped semiconductor layer (3) and the second doped semiconductor layer (7) in the isolation region (300) along the thickness direction.

10. The manufacturing method according to claim 3, characterized in that: The transparent protective layer (5) is a polytetrafluoroethylene film.

11. The manufacturing method according to claim 10, characterized in that: The polytetrafluoroethylene film is deposited by evaporation coating or magnetron sputtering. After the polytetrafluoroethylene film is deposited, the polytetrafluoroethylene film is annealed. The annealing temperature is 180°C to 220°C, and the temperature is lowered to room temperature after annealing at a cooling rate of 1 to 6°C / min.

12. The manufacturing method according to claim 1, characterized in that: The thickness of the edge portion of the first transparent conductive oxide layer (81) and / or the second transparent conductive oxide layer (82) adjacent to the isolation region (300) gradually decreases in a direction approaching the isolation region (300).

13. The manufacturing method according to claim 1, characterized in that: The first doped semiconductor layer (3) and the first interface passivation layer (2) located in the second carrier collection region (200) are removed to form a first opening (2001), wherein the width of the first opening (2001) is greater than or equal to 250 μm and less than or equal to 400 μm.

14. The manufacturing method according to claim 1, characterized in that: In the second surface (B), a region where the stacked first interface passivation layer (2) and the first doped semiconductor layer (3) are provided has a tower-like texture structure; the thickness of the first interface passivation layer (2) at the bottom surface of the tower-like texture structure is greater than the thickness of the first interface passivation layer (2) at the side wall of the tower-like texture structure.

15. The manufacturing method according to claim 1, characterized in that: In the second surface (B), a region where the stacked first interface passivation layer (2) and the first doped semiconductor layer (3) are provided has a tower-like texture structure; the thickness of the first interface passivation layer (2) at the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer (2) at the side wall of the tower-like texture structure.

16. The manufacturing method according to claim 1, characterized in that: The thickness of the second interface passivation layer (6) is greater than or equal to 8 nm and less than or equal to 14 nm.

17. The manufacturing method according to claim 1, characterized in that: The second interface passivation layer (6) and the second doped semiconductor layer (7) are patterned, and portions of the second interface passivation layer (6) and the second doped semiconductor layer (7) on the first carrier collection region (100) are removed to expose the first doped semiconductor layer (3), thereby forming a second opening (2002), and a hole structure is formed in an edge portion of the second doped semiconductor layer adjacent to the second opening (2002).

18. The manufacturing method according to claim 13, characterized in that: The first interface passivation layer (2) and the first doped semiconductor layer (3) are located in the first carrier collection region (100) and the isolation region (300); the second interface passivation layer (6) and the second doped semiconductor layer (7) are located in the second carrier collection region (200) and the isolation region (300), and extend to the first carrier collection region (100) to cover a portion of the first interface passivation layer (2) and the first doped semiconductor layer (3); the surface of the first carrier collection region (100) is a polished surface structure, and the bottom surface of the first opening (2001) is a velvet structure; the thickness of the second doped semiconductor layer (7) located on the velvet structure is less than the thickness of the second doped semiconductor layer (7) located on the polished surface structure.

19. The manufacturing method according to claim 13, characterized in that: The second doped semiconductor layer (7) is doped amorphous silicon. Before depositing a transparent conductive oxide layer (8) on the second surface (B) of the semiconductor substrate (1), and after depositing a second interface passivation layer (6) and a second doped semiconductor layer (7) on the second surface (B) of the semiconductor substrate (1) in sequence, the second doped semiconductor layer (7) located on the bottom surface of the first opening (2001) is irradiated with a laser to crystallize the second doped semiconductor layer (7).

20. A back contact solar cell, characterized in that: include: A semiconductor substrate (1) having a first surface (A) and a second surface (B) opposite to each other, the first surface (A) being a velvet surface, the second surface (B) of the semiconductor substrate (1) comprising a plurality of first carrier collection regions (100) and a plurality of second carrier collection regions (200) alternately distributed along a first direction, and an isolation region (300) being provided between adjacent first carrier collection regions (100) and second carrier collection regions (200); A first interface passivation layer (2) and a first doped semiconductor layer (3) located in the first carrier collection region (100) and stacked; A second interface passivation layer (6) and a second doped semiconductor layer (7) located in the second carrier collection region (200) and arranged in a stacked manner; A passivation anti-reflection layer (4) located on the first surface (A) of the semiconductor substrate (1); The passivation anti-reflection layer (4) comprises a passivation layer and an anti-reflection layer which are sequentially stacked on the first surface (A), and the passivation layer is closer to the first surface (A) than the anti-reflection layer; Wherein, the passivation layer includes at least one of AlOx, SiOx and POx; Alternatively, a SiOx interface layer is formed between the passivation layer and the first surface (A) of the semiconductor substrate (1); Alternatively, the passivation layer comprises an AlOx passivation layer, the anti-reflection layer comprises a SiNx anti-reflection layer, and a SiNx interface layer deposited by atomic layer deposition is provided between the AlOx passivation layer and the SiNx anti-reflection layer.

21. The back contact solar cell according to claim 20, characterized in that: The isolation region (300) at least comprises an insulating isolation structure between the first doped semiconductor layer (3) and the second doped semiconductor layer (7), The insulating isolation structure includes: one or more laminated insulating films of SiNx, phosphosilicate glass, borosilicate glass, and AlOx.

22. The back contact solar cell according to claim 20, characterized in that: Also includes: A transparent protective layer (5) is located on the passivation anti-reflection layer (4).

23. The back contact solar cell according to claim 22, characterized in that The transparent protective layer (5) is a polytetrafluoroethylene film.

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