Display device

Abstract

There is provided a display device including a base layer and a pixel defining film on the base layer and having a light emitting opening defined therein. The display device further includes a barrier rib including a first barrier rib layer on the pixel defining film and a second barrier rib layer on the first barrier rib layer. The barrier rib includes a barrier rib opening defined in the barrier rib and overlapping the light emitting opening. The display device further includes a light emitting element overlapping the light emitting opening, and the light emitting element includes a first electrode, a light emitting pattern on the first electrode and emitting light, and a second electrode on the light emitting pattern. The display device further includes an auxiliary electrode on the second electrode, and the auxiliary electrode includes a lower auxiliary electrode having indium zinc tin oxide and an upper auxiliary electrode having indium tin oxide.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0119342 filed in the Korean Intellectual Property Office on September 8, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the display device, and, for example, to a display device including an auxiliary electrode. Background Art

[0004] Various display devices such as televisions, monitors, smart phones and / or tablet computers provide images to users using, for example, display panels for displaying images. As display panels, various display panels have been developed, such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels and / or electrophoretic display panels.

[0005] The organic light emitting display panel may include an anode, a cathode, and / or a light emitting pattern, etc. The light emitting pattern may be separated for each light emitting region, and the cathode may provide a common voltage for each light emitting region. Summary of the invention

[0006] One or more aspects of the embodiments of the present disclosure are directed to a display device including an auxiliary electrode having excellent or suitable (e.g., relatively high) light transmittance and a method for manufacturing the display device. Additional aspects will be partially set forth in the following description and will partially become apparent from the description, or may be learned by practicing the embodiments of the present disclosure.

[0007] One or more embodiments of the present disclosure provide a display device, including a substrate layer and a pixel defining film, the pixel defining film being on the substrate layer and having a light-emitting opening defined in the pixel defining film. The display device may also include barrier ribs, the barrier ribs may include a first barrier rib layer provided on the pixel defining film and a second barrier rib layer provided on the first barrier rib layer. The barrier ribs may have barrier rib openings defined in the barrier ribs, the barrier rib openings overlapping the light-emitting openings. The display device may also include a light-emitting element, the light-emitting element overlapping the light-emitting openings, and the light-emitting element including a first electrode, a light-emitting pattern provided on the first electrode and emitting (e.g., positively emitting) light, and a second electrode provided on the light-emitting pattern. The display device may also include an auxiliary electrode provided on (e.g., contacting) the second electrode and each of the barrier ribs, wherein the auxiliary electrode includes a lower auxiliary electrode on (e.g., contacting) the second electrode and each of the barrier ribs and including (e.g., containing) indium zinc tin oxide (IZTO), and an upper auxiliary electrode provided on the lower auxiliary electrode and including (e.g., containing) indium tin oxide (ITO).

[0008] In one or more embodiments, the lower auxiliary electrode may have a thickness equal to or greater than (eg, at least) about 50 angstroms. and equal to or less than (e.g., at most) approximately The thickness between (eg, is equal to or greater than (eg, at least) about 50 angstroms and is equal to or less than (e.g., at most) approximately thickness).

[0009] In one or more embodiments, the upper auxiliary electrode may have a thickness equal to or greater than (eg, at least) about and equal to or less than (e.g., at most) approximately The thickness between (e.g., is equal to or greater than (e.g., at least) about and is equal to or less than (e.g., at most) approximately thickness).

[0010] In one or more embodiments, the lower auxiliary electrode may contact (eg, on) a first inner surface of the barrier rib opening of the first barrier rib layer and may be electrically connected to the barrier rib.

[0011] In one or more embodiments, the upper auxiliary electrode may not contact ( ) the first barrier rib layer (eg, not be on the first barrier rib layer).

[0012] In one or more embodiments, the indium zinc tin oxide (IZTO) may have substantially the same number of indium atoms and zinc atoms (e.g., the number of indium atoms may be substantially the same as the number of zinc atoms), and the amount of tin atoms is between equal to or greater than (e.g., at least) approximately 14 atomic weight percent (at%) and equal to or less than (e.g., at most) approximately 22 at% based on 100 at% of the total amount of IZTO.

[0013] In one or more embodiments, the indium tin oxide (ITO) may have about 90 wt % of indium oxide and about 10 wt % of tin oxide based on 100 wt % of the total amount of ITO.

[0014] In one or more embodiments, the second barrier rib layer may include a tip portion protruding from the first barrier rib layer toward the barrier rib opening.

[0015] In one or more embodiments, the lower auxiliary electrode and the upper auxiliary electrode may each have an amorphous phase.

[0016] In one or more embodiments, the lower auxiliary electrode may extend along a first inner surface of the first barrier rib layer and a lower surface of the second barrier rib layer.

[0017] In one or more embodiments, the lower auxiliary electrode and the upper auxiliary electrode may each have a light transmittance equal to or greater than about 90%.

[0018] In one or more embodiments of the present disclosure, a display device includes a substrate layer and a pixel defining film, the pixel defining film is on the substrate layer and has a light-emitting opening defined in the pixel defining film. The display device may also include barrier ribs, the barrier ribs may include a first barrier rib layer provided on the pixel defining film and a second barrier rib layer provided on the first barrier rib layer. The barrier ribs may have barrier rib openings defined in the barrier ribs, and the barrier rib openings overlap with the light-emitting openings. The display device may also include a light-emitting element, the light-emitting element overlaps with the light-emitting opening, and the light-emitting element includes a first electrode, a light-emitting pattern provided on the first electrode and emitting (e.g., positively emitting) light, and a second electrode provided on the light-emitting pattern. The display device may also include an auxiliary electrode provided on (e.g., contacting) the second electrode and each of the barrier ribs, wherein the auxiliary electrode includes a lower auxiliary electrode on (e.g., contacting) the second electrode and each of the barrier ribs, and an upper auxiliary electrode provided on the lower auxiliary electrode, the lower auxiliary electrode including a transparent conductive oxide containing (e.g., comprising) zinc, and the upper auxiliary electrode including a transparent conductive oxide.

[0019] In one or more embodiments, the lower auxiliary electrode and the upper auxiliary electrode may each have a thickness equal to or greater than (eg, at least) about and equal to or less than (e.g., at most) approximately The thickness between (e.g., is equal to or greater than (e.g., at least) about and is equal to or less than (e.g., at most) approximately thickness).

[0020] In one or more embodiments, the lower auxiliary electrode may include indium zinc tin oxide (IZTO), and the upper auxiliary electrode may include indium tin oxide (ITO).

[0021] In one or more embodiments, the indium zinc tin oxide (IZTO) may have substantially the same number of indium atoms and zinc atoms (e.g., the number of indium atoms may be substantially the same as the number of zinc atoms), and the number of tin atoms is between equal to or greater than (e.g., at least) approximately 14 at % and equal to or less than (e.g., at most) approximately 22 at % based on 100 at % of the total amount of IZTO (e.g., is equal to or greater than (e.g., at least) approximately 14 at % and equal to or less than (e.g., at most) approximately 22 at %).

[0022] In one or more embodiments, the lower auxiliary electrode may be on (eg, contacting) a first inner surface of the barrier rib opening of the first barrier rib layer and may be electrically connected to the barrier rib.

[0023] In one or more embodiments of the present disclosure, a method for manufacturing a display device includes providing (e.g., applying) a preliminary display panel, the preliminary display panel including a substrate layer, a pixel defining film provided on the substrate layer, a first preliminary barrier rib layer provided on the pixel defining film, and a second preliminary barrier rib layer provided on the first preliminary barrier rib layer. The method may also include etching the first preliminary barrier rib layer (e.g., to have a barrier rib opening) and the second preliminary barrier rib layer (e.g., to have a barrier rib opening) to form (e.g., each) a first barrier rib layer and a second barrier rib layer having a barrier rib opening defined therein. The method may also include forming (e.g., providing or applying) a light-emitting element (e.g., in the barrier rib opening), the light-emitting element including a first electrode, a light-emitting pattern, and a second electrode. The method may also include forming (e.g., providing or applying) a lower auxiliary electrode, the lower auxiliary electrode contacting each of the second electrode and the barrier rib, and including (e.g., containing) indium zinc tin oxide (IZTO). The method may also include forming (e.g., providing or applying) an upper auxiliary electrode provided on the lower auxiliary electrode and including (e.g., containing) indium tin oxide (ITO).

[0024] In one or more embodiments, the forming of the light emitting element (eg, forming the light emitting pattern and the second electrode) may each include a thermal evaporation process, and the forming of the lower auxiliary electrode and the upper auxiliary electrode may each include a sputtering process.

[0025] In one or more embodiments, the lower auxiliary electrode and the upper auxiliary electrode may each have a thickness equal to or greater than about and equal to or less than approximately The thickness between.

[0026] In one or more embodiments, the lower auxiliary electrode and the upper auxiliary electrode may each have (eg, include) an amorphous phase. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0028] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0029] Figure 2 is an exploded perspective view of a display device according to one or more embodiments of the present disclosure;

[0030] Figure 3 is a cross-sectional view of a display module according to one or more embodiments of the present disclosure;

[0031] Figure 4 is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0032] Figure 5 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure;

[0033] Figure 6 is a plan view of an enlarged portion of a display area of ​​a display panel according to one or more embodiments of the present disclosure;

[0034] Figure 7 According to one or more embodiments of the present disclosure, Figure 4 A cross-sectional view of the display panel taken along line II';

[0035] Figure 8 According to one or more embodiments of the present disclosure Figure 7 A view of an enlarged area AA';

[0036] Fig. 9 According to one or more embodiments of the present disclosure, Figure 6 A cross-sectional view taken along line II-II'; and

[0037] FIG. 10A to FIG. 10I are cross-sectional views each illustrating a part of a method for manufacturing a display device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0038] The present disclosure can be modified in various alternative forms, and therefore specific embodiments will be illustrated in the drawings and described in more detail in the detailed description. However, it should be understood that this is not intended to limit the present disclosure to the particular form disclosed, but is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present disclosure.

[0039] As used herein, when an element (or region, layer and / or portion, etc.) is referred to as being “on”, “connected to” or “joined to” another element, it means that the element may be directly provided on / connected to / joined to the other element, or a third element may be provided between the element and the other element.

[0040] When explaining each of the drawings, the same reference numerals refer to the same elements. In one or more embodiments, in the drawings, the thickness, ratio, and size of elements are exaggerated to effectively describe the technical content.

[0041] As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0042] As used herein, expressions such as "at least one of...", "one of...", "selected from...", and "selected from...", when preceding (following) a list of elements, modify the entire list of elements, rather than the individual elements in the list. For example, the expressions "at least one of a to c" and "at least one of a, b, and c" may mean only a, only b, only c, both a and b (e.g., a and b simultaneously), both a and c (e.g., a and c simultaneously), both b and c (e.g., b and c simultaneously), all of a, b, and c, or variations thereof.

[0043] The term "and / or" includes all combinations of one or more that the relevant configurations can define.

[0044] It will be understood that, although the terms "first" and / or "second" etc. may be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the teachings of the present disclosure. Unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "the (the)" are also intended to include plural forms.

[0045] Terms such as "below", "on the lower side", "above", and / or "on the upper side" may be used to describe the relationship of the components shown in the drawings. These terms are used as relative concepts and are described with reference to the directions shown in the drawings. It will be understood that these terms have relative concepts and are described based on the orientations described in the drawings. It will be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, if (for example, when) the device is turned over in the drawings, the elements described as "below" other elements or features will be positioned "above" or "on" other elements or features. Therefore, the term "below" can cover both above and below orientations. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used in this article should be interpreted accordingly.

[0046] It should be understood that the terms “include, includes, including,” “comprise, comprises, comprising,” and / or “has, having, have” are intended to illustrate the presence of the stated features, integers, steps, operations, elements, components, or combinations thereof in the present disclosure, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0047] As used herein, the term "may" will be understood to refer to "one or more embodiments of the present disclosure," some of which include the described elements, and some of which exclude the described elements and / or include alternative elements. Similarly, alternative language such as "or" refers to "one or more embodiments of the present disclosure," each of which includes the corresponding listed items.

[0048] Unless otherwise defined, all terms used herein (including chemical terms, technical terms, and scientific terms) have the same meanings as those generally understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined as such herein, terms defined in general dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and not interpreted in an idealized or overly formalized sense. In one or more embodiments, terms such as terms defined in general dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined herein.

[0049] As used herein, the phrase "consisting essentially of" means that any additional components will not have a substantial effect on the chemical, physical, optical, or electrical properties of the semiconductor film.

[0050] As used herein, the phrase “on a plane” or “plan view” means observing a target portion from the top, and the phrase “in cross section” means observing a cross-sectional view formed by vertically cutting the target portion from the side.

[0051] In the present disclosure, "not including one or any 'component (ingredient)'", "excluding one or any 'component (ingredient)'" and / or "no 'component (ingredient)'" etc. means that the "component (ingredient)" is not added, selected or utilized as a component (ingredient) in the composition / structure, but due to other impurities and / or external factors, the "component (ingredient)" may still be contained in less than an appropriate amount.

[0052] The term "at%" used herein may be "atomic weight percentage", that is, the percentage of the atomic weight of an element based on the total atomic weight of each element in a compound or the like.

[0053] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view of a display device DD according to one or more embodiments of the present disclosure, and Figure 2 is an exploded perspective view of a display device DD according to one or more embodiments of the present disclosure.

[0055] In one or more embodiments, the display device DD may be a large electronic device such as a television, a monitor, and / or an outdoor billboard, etc. In one or more embodiments, the display device DD may be a small and medium-sized electronic device such as a personal computer (e.g., a notebook computer, a tablet computer), a personal digital terminal, a car navigation system, a game console, a smart phone, and a camera. However, these are presented only as examples, and thus they may also be applied to other display devices without departing from the present disclosure. As an example, Figure 1 and Figure 2 A smartphone is shown as the display device DD.

[0056] Reference Figure 1 and Figure 2 , the display device DD may display an image IM on a display surface FS toward a third direction DR3, the display surface FS being parallel to each of the first direction DR1 and the second direction DR2. The third direction DR3 may be a normal direction relative to a plane defined by the first direction DR1 and the second direction DR2. The image IM may include a static image as well as a dynamic image. Figure 1 , the viewing window and the icon are illustrated as examples of the image IM. The display surface FS displaying the image IM may correspond to the front surface of the display device DD.

[0057] In the present embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each component are defined relative to the direction in which the image IM is displayed. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. In one or more embodiments, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may therefore be changed to other directions. In this article, "when viewed on a plane" may be defined as viewed from the third direction DR3.

[0058] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be joined to form an outer portion of the display device DD.

[0059] The window WP may include an optically transparent insulating material. For example, the window WP may include glass and / or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0060] The border area BZA may be an area having a relatively low transmittance (e.g., a transmittance lower than that of the transmission area TA). The border area BZA may define the planar shape of the transmission area TA. The border area BZA may be adjacent to the transmission area TA and may surround (e.g., surround) the transmission area TA. However, this is shown only as an example, and the border area BZA of the window WP may not be provided. The window WP may include at least (e.g., any) functional layer selected from an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, but is not limited to any one embodiment.

[0061] A display module DM may be provided (eg, a display module DM may be provided under the window WP). The display module DM may be configured to substantially generate an image IM. The image IM generated from the display module DM may be displayed on a display surface IS of the display module DM and may be observed from the outside by a user through the transmissive area TA.

[0062] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area activated according to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround (e.g., surround) the display area DA. The non-display area NDA may be an area covered by a bezel area BZA and thus may not be observed from the outside.

[0063] The housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide a set or predetermined inner space. The display module DM may be accommodated in (eg, located in) the inner space.

[0064] The housing HAU may include a material having relatively high rigidity. For example, the housing HAU may include a plurality of frames and / or plates including glass, plastic, and / or metal or a combination thereof. The housing HAU may stably protect components of the display device DD housed in (e.g., located in) the internal space from external impacts.

[0065] Figure 3 is a cross-sectional view of a display module according to one or more embodiments of the present disclosure.

[0066] Reference Figure 3The display module DM may include a display panel DP and an input sensor INS. According to one or more embodiments, the display device DD (see Figure 1 ) may further include a protection member provided on the lower surface of the display panel DP and / or an anti-reflection member and / or a window member provided on the upper surface of the input sensor INS.

[0067] The display panel DP may be a light-emitting display panel. However, this is presented only as an example, and the embodiments of the present disclosure are not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods and / or micro organic light-emitting diodes (LEDs), etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0068] The display panel DP may include a base layer BL, a circuit element layer DP-CL provided on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS may be provided directly on the thin film encapsulation layer TFE. In this article, "component A is provided directly on component B" means that no adhesive layer is provided between component A and component B.

[0069] The base layer BL may include at least one plastic film. The base layer BL may include a plastic substrate, a glass substrate, a metal substrate, and / or an organic / inorganic composite material substrate, etc. as a flexible substrate. Figure 2 The display area DA and the non-display area NDA described in may be identically defined in the base layer BL.

[0070] The circuit element layer DP-CL may include at least one insulating layer and a circuit element. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit element includes a signal line and / or a pixel driving circuit, etc.

[0071] The display element layer DP-OLED may include barrier ribs and a light emitting element. The light emitting element may include an anode, an intermediate layer and a cathode.

[0072] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be provided to improve optical efficiency, and some of which may be provided to protect the organic light emitting diode.

[0073] The input sensor INS acquires information about the coordinates of the external input. The input sensor INS has a multi-layer structure. The input sensor INS may have a single conductive layer or multiple conductive layers. In one or more embodiments, the input sensor INS may include a single insulating layer or multiple insulating layers. The input sensor INS may detect the external input in a capacitive mode. However, this is presented only as an example, and the embodiments of the present disclosure are not limited thereto. For example, in one or more embodiments, the input sensor INS may detect the external input by an electromagnetic induction method or a pressure sensing method. In one or more embodiments of the present disclosure, the input sensor INS may not be provided.

[0074] Figure 4 is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0075] Reference Figure 4 In the display panel DP, a display area DA and a non-display area NDA surrounding the display area DA may be defined. The display area DA and the non-display area NDA may be defined with respect to the presence and / or absence of the pixel PX. For example, the pixel PX may be provided in the display area DA, and the pixel PX may not be provided in the non-display area NDA.

[0076] The display panel DP may include pixels PX, initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, light emission control lines ECL1 to ECLm, data lines DL1 to DLn, first control lines CSL1 and second control lines CSL2, driving voltage lines PL, scan drivers SDV, data drivers, light emission drivers EDV, driving chips DIC, and pads PD. In this case, m and n may each independently be a natural number of 2 or more. The data driver may be some of the circuits configured in the driving chip DIC.

[0077] The pixels PX may be connected to initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, and data lines DL1 to DLn.

[0078] Initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, and black scan lines GBL1 to GBLm may extend in a first direction DR1 and be electrically connected to a scan driver SDV. Data lines DL1 to DLn may extend in a second direction DR2 and be electrically connected to a drive chip DIC. Light emission control lines ECL1 to ECLm may extend in a first direction DR1 and be electrically connected to a light emission driver EDV.

[0079] The driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be provided on different layers. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0080] The first control line CSL1 may be connected to the scan driver SDV. The second control line CSL2 may be connected to the light emitting driver EDV.

[0081] The driving chip DIC, the driving voltage line PL, the first control line CSL1 and the second control line CSL2 may be electrically connected to the pad PD. The flexible circuit film FCB may be electrically connected to the pad PD through an anisotropic conductive adhesive layer. The pad PD may be a pad for electrically connecting the flexible circuit film FCB to the display panel DP. The pad PD may be connected to the corresponding pixel PX through the driving voltage line PL, the first control line CSL1 and the second control line CSL2.

[0082] In one or more embodiments, the pads PD may also include input pads. The input pads may be used to connect the flexible circuit film FCB to the input sensor INS (see Figure 3 ) pad. However, the embodiments of the present disclosure are not limited thereto, and the input pad may be provided on the input sensor INS and connected to the pad PD and a separate circuit board. In one or more embodiments, the input sensor INS may not be provided, and the input pad may not be further included.

[0083] Figure 5 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0084] Figure 5 A plurality of pixels PX are shown (see Figure 4 ) is taken as an example. Multiple pixels PX may each share the same circuit structure, and therefore, since the description of the circuit structure of the pixel PXij is alternative (e.g., equivalent in other aspects), a detailed description of other pixels PX will not be given.

[0085] Reference Figure 4 and Figure 5 , the pixel PXij may be connected to the i-th data line DLi among the data lines DL1 to DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, the j-th write scan line GWLj among the write scan lines GWL1 to GWLm, the j-th black scan line GBLj among the black scan lines GBL1 to GBLm, the j-th light emission control line ECLj among the light emission control lines ECL1 to ECLm, the first driving voltage line VL1 and the second driving voltage line VL2, and the first initialization voltage line VL3 and the second initialization voltage line VL4. In one or more embodiments, i may be an integer from 1 to n, and j may be an integer from 1 to m.

[0086] The pixel PXij includes a light emitting element ED and a pixel circuit PDC. The light emitting element ED may be a light emitting diode. As an example of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but is not particularly limited thereto. The pixel circuit PDC may control the amount of current flowing through the light emitting element ED in response to a data signal Di. The light emitting element ED may emit light having a set or predetermined brightness in response to the amount of current provided from the pixel circuit PDC.

[0087] The pixel circuit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a first capacitor Cst, a second capacitor Cbst, and a third capacitor Nbst. The components of the pixel circuit PDC according to one or more embodiments of the present disclosure are not limited to Figure 5 The embodiment shown in . Figure 5 The pixel circuit PDC shown in FIG. 1 is merely an example, and components of the pixel circuit PDC may include one or more suitable configurations and / or operations.

[0088] At least one selected from the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. At least one selected from the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be LTPS transistors.

[0089] For example, the first transistor T1 that directly affects the brightness of the light-emitting element ED is configured to include a semiconductor layer formed of polycrystalline silicon with high reliability, and therefore, a relatively high-resolution display device can be obtained. In one or more embodiments, the oxide semiconductor may have a relatively high carrier mobility and a low leakage current, and therefore may not experience a considerable voltage drop even under a relatively long driving time. For example, even under a relatively low-frequency drive, the color change of the image according to the voltage drop will not be quite large (e.g., drastic), and therefore a relatively low-frequency drive can be allowed. As described herein, an oxide semiconductor provides the advantage of low leakage current, and therefore, at least one selected from the third transistor T3 and the fourth transistor T4 (e.g., connected to the gate electrode of the first transistor T1) can be used as an oxide semiconductor to prevent or reduce leakage current (e.g., which may flow to the gate electrode and reduce power consumption).

[0090] At least one selected from the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a P-type or kind of transistor, and the other transistors (any remaining transistors among the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7) may be N-type or kind of transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type or kind of transistors, and the third transistor T3 and the fourth transistor T4 may be N-type or kind of transistors.

[0091] The components of the pixel circuit PDC according to one or more embodiments of the present disclosure are not limited to Figure 5 The embodiment shown in . Figure 5 The pixel circuit PDC shown in is only an example, and the components of the pixel circuit PDC may include one or more suitable configurations and / or operations. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be P-type or kind transistors or N-type or kind transistors. In one or more embodiments, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be P-type or kind transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be N-type or kind transistors.

[0092] The jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj can transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have the same value as that input to the display device DD (see Figure 1 )’s image signal corresponding to the voltage level.

[0093] The first and second driving voltage lines VL1 and VL2 may transmit first and second driving voltages ELVDD and ELVSS to the pixels PXij, respectively. In one or more embodiments, the first and second initialization voltage lines VL3 and VL4 may transmit first and second initialization voltages VINT and VAINT to the pixels PXij, respectively.

[0094] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (also referred to as an anode) of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the first capacitor Cst. The first transistor T1 may receive an i-th data signal Di received from the i-th data line DLi according to a switching operation of the second transistor T2, and supply a driving current to the light emitting element ED.

[0095] The second transistor T2 is connected between the data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the jth write scan line GWLj. The second transistor T2 may be turned on according to the write scan signal GWj received through the jth write scan line GWLj to transmit the i-th data signal Di received through the i-th data line DLi to the first electrode of the first transistor T1. One end of the second capacitor Cbst may be connected to the third electrode of the second transistor T2, and the other end of the second capacitor Cbst may be connected to the first node N1.

[0096] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line GCLj. The third transistor T3 may be turned on according to the j-th compensation scan signal GCj received through the j-th compensation scan line GCLj to connect the third electrode of the first transistor T1 and the second electrode of the first transistor T1, thereby connecting the first transistor T1 to the diode. One end of the third capacitor Nbst may be connected to the third electrode of the third transistor T3, and the other end of the third capacitor Nbst may be connected to the first node N1.

[0097] The fourth transistor T4 is connected between the first initialization voltage line VL3 to which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT is applied, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line GILj. The fourth transistor T4 is turned on according to the jth initialization scan signal GIj received through the jth initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1 to initialize the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0098] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode of the light emitting element ED, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line ECLj.

[0099] The fifth transistor T5 and the sixth transistor T6 are turned on together according to the jth emission control signal EMj received through the jth emission control line ECLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 can be compensated by the diode-connected first transistor T1 and then transmitted to the light emitting element ED through the sixth transistor T6.

[0100] The seventh transistor T7 includes a first electrode connected to the second initialization voltage line VL4 to which the second initialization voltage VAINT is transmitted, a second electrode connected to the second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line GBLj. The second initialization voltage VAINT may have a voltage level equal to or lower than the voltage level of the first initialization voltage VINT.

[0101] One end of the first capacitor Cst may be connected to the third electrode of the first transistor T1, and the other end of the first capacitor Cst may be connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 to which the second driving voltage ELVSS is supplied. The second driving voltage ELVSS may have a voltage level lower than that of the first driving voltage ELVDD.

[0102] Figure 6 is a plan view of an enlarged portion of a display area of ​​a display panel according to one or more embodiments of the present disclosure. Figure 6 Shown when the display module DM (see Figure 2 ) of the display surface IS (see Figure 2 ) is a plane of the display module DM when viewed from above (eg, is a plan view of the display module DM), and shows the arrangement of the light emitting areas PXA-R, PXA-G, and PXA-B.

[0103] Reference Figure 6 , the display area DA may include a first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B and a peripheral area NPXA surrounding (e.g., surrounding) the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B. The first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may each correspond to an area in which light provided from the light emitting element is emitted. The first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may be arranged according to the direction toward the display module DM (see Figure 2 ) is distinguished by the color of the light emitted externally.

[0104] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may provide first to third color lights each having a different color. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, examples of the first to third color lights are not necessarily limited to the examples described herein.

[0105] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may each be defined as a region in which the upper surface of the anode is exposed through the light emitting opening, which will be described in more detail elsewhere herein. The peripheral region NPXA may set a boundary among the light emitting regions PXA-R, PXA-G, and PXA-B, and prevent or reduce color mixing in the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B.

[0106] Each of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be provided in plurality and repeatedly arranged in the display area DA in a set or predetermined arrangement form (e.g., grouping). For example, the first light emitting region PXA-R and the third light emitting region PXA-B may be alternately arranged along the first direction DR1 to form a "first group". The second light emitting region PXA-G may be arranged along the first direction DR1 to form a "second group". The "first group" and the "second group" may each be provided in plurality, and the "first group" and the "second group" may be alternately arranged along the second direction DR2.

[0107] One second light emitting region PXA-G may be provided to be spaced apart and / or separated from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0108] In one or more embodiments, Figure 6 The arrangement form of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B is shown as an example, but the arrangement form is not limited thereto, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be arranged in one or more suitable forms. In one or more embodiments, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have a configuration as follows: Figure 6 The pentile shown in In one or more embodiments, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have stripes or diamonds. ) layout, ( and Diamond is a registered trademark owned by Samsung Display Co., Ltd.).

[0109] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have one or more suitable shapes when viewed on a plane. For example, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have a shape such as a polygon, a circle, or an ellipse when viewed on a plane. Figure 6 The first and third light emitting regions PXA-R and PXA-B having quadrilaterals (or rhombuses) and the second light emitting region PXA-G having an octagon when viewed on a plane are shown.

[0110] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have the same shape when viewed on a plane, or at least some of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have different shapes when viewed on a plane. Figure 6 The first and third light emitting regions PXA-R and PXA-B having the same shape when viewed on a plane and the second light emitting region PXA-G having a shape different from the first and third light emitting regions PXA-R and PXA-B are shown as examples.

[0111] At least some of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have areas of different sizes when viewed on a plane. In one or more embodiments, the area of ​​the first light emitting region PXA-R emitting red light may be larger than the area of ​​the second light emitting region PXA-G emitting green light, and may be smaller than the area of ​​the third light emitting region PXA-B emitting blue light. However, the size relationship of the area according to the color of the emitted light among the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B is not limited thereto, and may be determined according to the display module DM (see Figure 2 In one or more embodiments, the embodiments of the present disclosure are not limited thereto, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have the same size of area when viewed on a plane.

[0112] In one or more embodiments, the display module DM (see Figure 2 The shapes, areas, and arrangements of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B can be determined according to the color of the emitted light or the display module DM (see Figure 2 ) are designed in one or more suitable ways, and this is not limited to Figure 6 The embodiment shown in .

[0113] Figure 7 According to one or more embodiments of the present disclosure, Figure 4 A cross-sectional view of the display panel taken along line II'. Figure 8 According to one or more embodiments of the present disclosure Figure 7 The enlarged area AA' of FIG. Figure 3 describe Figure 7 and Figure 8 , and description of the same figure numerals will not be given.

[0114] Figure 7 is the enlarged display area DA (see Figure 6 ) in a light emitting area PXA, and Figure 7 The light emitting area PXA may correspond to Figure 6 Any one of the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B. Figure 7 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0115] Reference Figure 7 and Figure 8 , the display panel DP may include a plurality of insulating layers, semiconductor patterns and / or conductive patterns (for forming, for example, signal lines), etc. The insulating layers, semiconductor layers and conductive layers may be formed by processes such as coating or deposition. Thereafter, the insulating layers, semiconductor layers and conductive layers may be selectively patterned by photolithography and etching. The semiconductor patterns and / or conductive patterns included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed by the processes described herein.

[0116] The circuit element layer DP-CL may be provided on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, an electrode EE, and a plurality of connection electrodes CNE1 and / or CNE2.

[0117] A buffer layer BFL may be provided on the base layer BL. The buffer layer BFL may improve a bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and / or a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0118] A semiconductor pattern may be provided on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, the embodiments of the present disclosure are not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. Figure 7Only a portion of the semiconductor pattern is shown as an example, and the semiconductor pattern may also be provided in a plurality of light emitting regions PXA-R (see FIG. Figure 6 )、PXA-G(see Figure 6 ) and PXA-B (see Figure 6 ). The semiconductor pattern may be arranged throughout the plurality of light emitting regions PXA-R, PXA-G, and PXA-B according to certain rules. The semiconductor pattern may have different electrical characteristics depending on whether it is doped or undoped. The semiconductor pattern may include a first region having a high doping concentration and a second region having a low doping concentration. The first region may be doped with an N-type or species dopant or a P-type or species dopant. The P-type or species transistor may include a first region doped with a P-type or species dopant.

[0119] The first region may have greater conductivity than the second region and may be substantially used as an electrode or a signal line. The second region may substantially correspond to an active region (or channel) of a transistor. For example, a portion of the semiconductor pattern may be an active region of a transistor, another portion may be a source or drain of the transistor, and the other portion may be a conductive region.

[0120] The source S, the active region A, and the drain D of the transistor TR may be formed of a semiconductor pattern. Figure 7 A portion of a signal transmission region SCL formed from a semiconductor pattern is shown. In one or more embodiments, the signal transmission region SCL may be connected to the drain DR of the transistor TR1 when viewed on a plane.

[0121] The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may be provided on the buffer layer BFL. The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may be an inorganic layer and / or an organic layer.

[0122] A first insulating layer 10 may be provided on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active region A, the drain D, and the signal transmission region SCL of the transistor TR1 provided on the buffer layer BFL. A gate G of the transistor TR1 may be provided on the first insulating layer 10. A second insulating layer 20 may be provided on the first insulating layer 10 to cover the gate G. An electrode EE may be provided on the second insulating layer 20. A third insulating layer 30 may be provided on the second insulating layer 20 to cover the electrode EE.

[0123] The first connection electrode CNE1 may be provided on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The fourth insulating layer 40 may be provided on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0124] The second connection electrode CNE2 may be provided on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. A fifth insulating layer 50 may be provided on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0125] The display element layer DP-OLED may be provided on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a sacrificial pattern SP, a pixel defining film PDL, a barrier rib PW, an auxiliary electrode SE, and a dummy pattern DMP.

[0126] The light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP (or an intermediate layer), and a cathode CE (or a second electrode).

[0127] The anode AE ​​may be provided on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive and semi-reflective electrode, or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 through the connection contact hole CNT-3 defined through the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and / or the second connection electrode CNE2, and electrically connected to the corresponding circuit element. The anode AE ​​may include a single-layer structure or a multi-layer structure. The anode AE ​​may include a plurality of layers including ITO and Ag. For example, the anode AE ​​may include a layer including ITO (hereinafter referred to as a lower ITO layer), a layer including Ag provided on the lower ITO layer (hereinafter referred to as an Ag layer), and a layer including ITO provided on the Ag layer (referred to as an upper ITO layer).

[0128] A sacrificial pattern SP may be provided between the anode AE ​​and the pixel defining film PDL. A sacrificial opening OP-S exposing a portion of the upper surface of the anode AE ​​may be defined in the sacrificial pattern SP. The sacrificial opening OP-S may overlap with the light emitting opening OP-E, which will be described later.

[0129] The pixel defining film PDL may be provided on the base layer BL. More specifically, the pixel defining film PDL may be provided on the fifth insulating layer 50 of the circuit element layer DP-CL. A light emitting opening OP-E may be defined in the pixel defining film PDL. The light emitting opening OP-E may correspond to the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​through the light emitting opening OP-E.

[0130] In one or more embodiments, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to one or more embodiments of the present disclosure, the upper surface of the anode AE ​​may be spaced apart and / or separated from the pixel defining film PDL in a cross section, and the sacrificial pattern SP is located between the upper surface of the anode AE ​​and the pixel defining film PDL, and therefore, in the process of forming (e.g., providing or applying) the light emitting opening OP-E, the anode AE ​​may be protected from damage.

[0131] When viewed on a plane (e.g., in a plan view), the area of ​​the light emitting opening OP-E may be smaller than the area of ​​the sacrificial opening OP-S. For example, the inner surface of the pixel defining film PDL defining the light emitting opening OP-E may be closer to the center of the anode AE ​​than the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, the embodiments of the present disclosure are not limited thereto, and the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S may be substantially aligned with the inner surface of the pixel defining film PDL defining the light emitting opening OP-E.

[0132] The pixel definition layer PDL may include an inorganic insulating material. For example, the pixel definition layer PDL may include silicon nitride (SiN x ). A pixel defining film PDL may be provided between the anode AE ​​and the barrier rib PW to prevent or reduce electrical connection between the anode AE ​​and the barrier rib PW.

[0133] The barrier rib PW may be provided on the pixel defining film PDL. The barrier rib opening OP-P may be defined in the barrier rib PW. The barrier rib opening OP-P may overlap with the light emitting opening OP-E and may expose at least a portion of the anode AE.

[0134] The barrier ribs PW may have an undercut shape in cross section. The barrier ribs PW may include a plurality of sequentially stacked layers, and at least one of the plurality of layers may be recessed relative to the other layers. Therefore, the barrier ribs PW may include a tip portion TP.

[0135] The barrier rib PW may include a first barrier rib layer L1 and a second barrier rib layer L2. The first barrier rib layer L1 may be provided on the pixel definition film PDL, and the second barrier rib layer L2 may be provided on the first barrier rib layer L1. Figure 7As shown in FIG. 8 , the first barrier rib layer L1 may have a greater thickness than the second barrier rib layer L2 , but embodiments of the present disclosure are not limited thereto.

[0136] The first barrier rib layer L1 may be relatively recessed relative to the light emitting area PXA compared to the second barrier rib layer L2. The first barrier rib layer L1 may be formed to have an undercut relative to the second barrier rib layer L2. A portion of the second barrier rib layer L2 protruding from the first barrier rib layer L1 toward the light emitting area PXA may define a tip portion TP in the barrier rib PW. For example, the second barrier rib layer L2 may include a tip portion TP protruding from the first barrier rib layer L1 toward the barrier rib opening OP-P.

[0137] The length TD of the tip portion TP in the first direction DR1 may be a length from a first inner surface S-L1 of the first barrier rib layer L1 overlapping the pixel defining film PDL to a second inner surface S-L2 of the second barrier rib layer L2.

[0138] The barrier rib opening OP-P defined in the barrier rib PW may include a first portion (first area) AA1 and a second portion (second area) AA2. The first barrier rib layer L1 may include a first inner surface S-L1 defining the first area AA1 of the barrier rib opening OP-P, and the second barrier rib layer L2 may include a second inner surface S-L2 defining the second area AA2. In a cross section, the second inner surface S-L2 of the second barrier rib layer L2 may be closer to the center of the anode AE ​​than the first inner surface S-L1 of the first barrier rib layer L1. The first inner surface S-L1 may be recessed in a direction away from the center of the anode AE ​​than the second inner surface S-L2.

[0139] The width of the first area AA1 and the width of the second area AA2 may be different. The first area AA1 may have a greater width than the second area AA2. In this case, the second area AA2 of the barrier rib opening OP-P may be an area defining the tip portion TP.

[0140] The first barrier rib layer L1 and the second barrier rib layer L2 may each include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0141] Figure 7It is shown that each of the first inner surface S-L1 and the second inner surface S-L2 is perpendicular to the upper surface of the pixel defining film PDL, but the embodiments of the present disclosure are not limited thereto. For example, the barrier rib PW may have a tapered shape or a reverse tapered shape.

[0142] The light emitting pattern EP may be provided on the anode AE ​​to emit light. The light emitting pattern EP may include a light emitting layer including a light emitting material. The light emitting pattern EP may also include a hole injection layer (HIL) and a hole transport layer (HTL) provided between the anode AE ​​and the light emitting layer, and may also include an electron transport layer (ETL) and an electron injection layer (EIL) provided on the light emitting layer. The light emitting pattern EP may also be referred to as an "organic layer" or an "intermediate layer".

[0143] The light-emitting pattern EP may be patterned by a tip portion TP defined in the barrier rib PW. The light-emitting pattern EP may be provided inside the sacrificial opening OP-S, the light-emitting opening OP-E and / or the barrier rib opening OP-P. The portion of the upper surface of the pixel-defining film PDL exposed from the barrier rib opening OP-P may be deposited with the light-emitting pattern EP. For example, both ends of the light-emitting pattern EP (for example, both ends at the same time) may be formed on the upper surface of the pixel-defining film PDL. When viewed on a plane, the light-emitting pattern EP may be spaced apart and / or separated from the side of the barrier rib PW. For example, when viewed on a plane, the light-emitting pattern EP may be spaced apart and / or separated from the first inner surface S-L1 of the first barrier rib layer L1. For example, the light-emitting pattern EP may not contact the barrier rib PW.

[0144] Among the plurality of hole injection layers included in the light emitting pattern EP, the P-doped hole injection layer may have conductivity. In this case, when the light emitting pattern EP is formed to contact the barrier ribs PW, the barrier ribs PW containing a conductive material and the light emitting pattern EP may be electrically connected, thereby causing leakage current. According to one or more embodiments of the present disclosure, for example, even if a portion of the light emitting pattern EP (e.g., the P-doped hole injection layer) is conductive, since the light emitting pattern EP is spaced and / or separated from the barrier ribs PW when viewed on a plane, the occurrence of leakage current can be prevented or reduced.

[0145] The cathode CE may be provided on the light emitting pattern EP. The cathode CE may be patterned by a tip portion defined in the barrier rib PW. At least a portion of the cathode CE may be provided in the barrier rib opening OP-P. The upper surface of the pixel defining film PDL exposed from the barrier rib opening OP-P may be deposited with the cathode CE. For example, both ends of the cathode CE (e.g., both ends simultaneously) may be formed on the pixel defining film PDL.

[0146] Both ends of the cathode CE may be electrically connected by contacting the side surfaces of the barrier rib PW. Figure 7, the cathode CE is shown as being in contact with the side of the barrier rib PW as an example, but the embodiments of the present disclosure are not limited thereto. For example, when viewed on a plane, both ends of the cathode CE (e.g., both ends at the same time) may be spaced apart and / or separated from the side of the barrier rib PW. For example, when viewed on a plane (e.g., in a plan view), the cathode CE may be spaced apart and / or separated from the first inner surface S-L1 of the first barrier rib layer L1. In this case, the cathode CE may be electrically connected to the barrier rib PW via the auxiliary electrode SE.

[0147] The cathode CE may have electrical conductivity. The cathode CE may be formed of one or more suitable materials as long as the material such as metal, transparent conductive oxide (TCO) or conductive polymer material has electrical conductivity. For example, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pu), copper (Cu) or a compound thereof.

[0148] The auxiliary electrode SE may be provided on the light emitting element ED. The auxiliary electrode SE may be provided on the cathode CE. The auxiliary electrode SE may contact the barrier rib PW and the cathode CE. For example, the auxiliary electrode SE may be electrically connected to the barrier rib PW and the cathode CE. The barrier rib PW may receive the second driving voltage ELVSS (see Figure 5 ), and the auxiliary electrode SE may be electrically connected to the barrier rib PW to receive the second driving voltage ELVSS. Therefore, the cathode CE electrically connected to the auxiliary electrode SE may receive the second driving voltage ELVSS.

[0149] The auxiliary electrode SE may contact a portion of the lower surface of the tip portion TP. The auxiliary electrode SE may not contact at least a portion of the lower surface of the tip portion TP. The auxiliary electrode SE may be conductive. According to one or more embodiments of the present disclosure, the cathode CE may be electrically connected to the barrier rib PW through the auxiliary electrode SE. The adhesion between the auxiliary electrode SE and the cathode CE and the adhesion between the auxiliary electrode SE and the barrier rib PW may be greater than the adhesion between the cathode CE and the barrier rib PW. Therefore, the cathode CE in contact with the barrier rib PW through the auxiliary electrode SE can be prevented or reduced from lifting, and thus foreign matter can be prevented or reduced from entering the display element layer DP-OLED.

[0150] The auxiliary electrode SE may include a lower auxiliary electrode LSE and an upper auxiliary electrode USE. The lower auxiliary electrode LSE may contact the cathode CE and the barrier rib PW to electrically connect the cathode CE and the barrier rib PW. The lower auxiliary electrode LSE may contact the first inner surface S-L1 of the barrier rib opening OP-P defining the first barrier rib layer L1. The lower auxiliary electrode LSE may extend along the first inner surface S-L1 of the first barrier rib layer L1 and the lower surface of the second barrier rib layer L2. The lower auxiliary electrode LSE may not contact at least a portion of the lower surface of the second barrier rib layer L2. The lower auxiliary electrode LSE may be arranged to be spaced apart and / or separated from the third dummy pattern D3 formed by the tip portion TP through the same process.

[0151] The lower auxiliary electrode LSE may include a transparent conductive oxide (TCO) containing zinc. The lower auxiliary electrode LSE contains zinc, and thus the lower auxiliary electrode LSE is not corroded even when the lower auxiliary electrode LSE contacts the first barrier rib layer L1. For example, electrochemical corrosion caused by a potential difference between the first barrier rib layer L1 and the lower auxiliary electrode LSE may be prevented or reduced.

[0152] For example, when the first barrier rib layer L1 includes aluminum and the lower auxiliary electrode LSE includes indium tin oxide (ITO), corrosion may be caused due to the standard reduction potential difference between the first barrier rib layer L1 and the lower auxiliary electrode LSE. In this case, when indium zinc tin oxide (IZTO) containing zinc is used as the lower auxiliary electrode LSE, the standard reduction potential is lowered due to zinc, and therefore, the corrosion of the lower auxiliary electrode LSE can be prevented or reduced.

[0153] The lower auxiliary electrode LSE may include indium zinc tin oxide. As described herein, when indium zinc tin oxide is used as the lower auxiliary electrode LSE, corrosion of the lower auxiliary electrode LSE may be prevented or reduced. The lower auxiliary electrode LSE may have a transmittance of about 90% or more. The transmittance of the lower auxiliary electrode LSE may be about 90% or more for each of red light, green light, and blue light (e.g., any one or all).

[0154] The lower auxiliary electrode LSE may have a thickness of approximately To about When the first thickness TH1 of the lower auxiliary electrode LSE is less than about When the first thickness TH1 of the lower auxiliary electrode LSE is greater than about 100 mm, the lower auxiliary electrode LSE may not be able to prevent or reduce the lifting of the cathode CE, or prevent or reduce the entry of foreign matter into the light emitting element ED. When the lower auxiliary electrode LSE is crystallized, for example, in (for example, as in reference FIG. 10A to FIG. 10IIt is difficult to etch the lower auxiliary electrode LSE during the subsequent steps of the preparation process described in more detail in the description of the method for manufacturing a display device. Therefore, the lower auxiliary electrode LSE may have a thickness of about To about In one or more embodiments, the first thickness TH1 of the lower auxiliary electrode LSE may be approximately

[0155] When the lower auxiliary electrode LSE contains indium zinc tin oxide (IZTO), the amount of indium atoms and zinc atoms may be substantially the same, and the amount of tin atoms may be between about 14 at % and about 22 at % based on 100 at % of the total amount of IZTO. For example, the amount of indium atoms may be substantially the same as the amount of zinc atoms. The lower auxiliary electrode LSE may be formed of indium zinc tin oxide having the described composition, and therefore, the lower auxiliary electrode LSE may have an amorphous phase. As described in more detail elsewhere herein, when the lower auxiliary electrode LSE is in an amorphous state, an etching process may be easily performed in a method for manufacturing a display device.

[0156] The upper auxiliary electrode USE may be provided on the lower auxiliary electrode LSE and may be electrically connected to the lower auxiliary electrode LSE. Thus, the lower auxiliary electrode LSE, the upper auxiliary electrode USE, the cathode CE, and the first barrier rib layer L1 may be electrically connected. The upper auxiliary electrode USE may extend along the lower auxiliary electrode LSE. The upper auxiliary electrode USE may be arranged to be spaced apart and / or separated from the fourth dummy pattern D4 formed by the tip portion TP through the same process.

[0157] The upper auxiliary electrode USE may include a transparent conductive oxide. The upper auxiliary electrode USE may include indium tin oxide. The upper auxiliary electrode USE may not contact the first barrier rib layer L1. A lower auxiliary electrode LSE containing zinc and resistant to corrosion may be provided between the upper auxiliary electrode USE and the first barrier rib layer L1. By preventing or reducing direct contact between the upper auxiliary electrode USE and the first barrier rib layer L1, the upper auxiliary electrode USE may be prevented or reduced from being corroded.

[0158] For example, when the first barrier rib layer L1 contains aluminum, the upper auxiliary electrode USE includes indium tin oxide, and the first barrier rib layer L1 contacts the upper auxiliary electrode USE, the upper auxiliary electrode USE may be damaged due to electrochemical corrosion. In this case, by preventing or reducing the contact between the upper auxiliary electrode USE and the first barrier rib layer L1, the lower auxiliary electrode LSE containing indium zinc tin oxide can prevent or reduce damage to the upper auxiliary electrode USE.

[0159] In the indium tin oxide (ITO) of the upper auxiliary electrode USE, based on 100 wt % of the total amount of ITO, indium oxide (In 2 O3 ) may be about 90wt%, and the weight percentage of tin oxide (SnO) may be about 10wt%. The upper auxiliary electrode USE is formed of indium tin oxide of such a composition, and the upper auxiliary electrode USE may have an amorphous phase. As described in more detail elsewhere herein, when the upper auxiliary electrode USE has an amorphous phase, an etching process may be easily performed in a method for manufacturing a display device.

[0160] The upper auxiliary electrode USE may have a size of approximately To about When the second thickness TH2 of the upper auxiliary electrode USE is less than about When the second thickness TH2 of the upper auxiliary electrode USE is greater than about When the upper auxiliary electrode USE is etched, the upper auxiliary electrode USE may be crystallized, making it difficult to etch the lower auxiliary electrode LSE during subsequent steps of the preparation process. In one or more embodiments, the second thickness TH2 of the upper auxiliary electrode USE may be about

[0161] The light transmittance of the upper auxiliary electrode USE may be about 90% or more.The light transmittance of the upper auxiliary electrode USE may be about 90% or more for each (eg, any one or all) of red light, green light, and blue light.

[0162] Table 1 included herein is a table showing light transmittance of auxiliary electrodes according to the wavelength of light in Comparative Example, Example 1, and Example 2. The Comparative Example is a table using indium zinc oxide (IZO) as an auxiliary electrode and the auxiliary electrode has approximately Example 1 is a case where indium tin oxide is used as the auxiliary electrode and the auxiliary electrode has a thickness of about Example 2 is a case where indium zinc tin oxide is used as the auxiliary electrode and the auxiliary electrode has a thickness of about The thickness of the case.

[0163] Table 1

[0164] Wavelength of light (nm) Comparison Examples Example 1 Example 2 450 79％ 94.04％ 95.04％ 550 81.8％ 96.62％ 97.16％ 650 85.8％ 97.9％ 98.06％

[0165] Referring to Table 1, it can be seen that the case of using indium tin oxide as the auxiliary electrode (Example 1) or using indium zinc tin oxide as the auxiliary electrode (Example 2) has a higher light transmittance than the case of using indium zinc oxide as the auxiliary electrode (Comparative Example). This can be applied to the case where the wavelength of light is 450nm (blue light), the case where the wavelength of light is 550nm (green light), and / or the case where the wavelength of light is 650nm (red light), for example, each case or all cases. It can be seen that when the thickness of the auxiliary electrode is about (Example 1 and Example 2), the light transmittance of the auxiliary electrode is greater than that when the thickness of the auxiliary electrode is about In the case of (Comparative Example), the light transmittance of the auxiliary electrode is large.

[0166] In Examples 1 and 2, the light transmittance of the auxiliary electrode for blue light, green light, and red light is each (e.g., all) about 90% or more. In Examples 1 and 2, the light transmittance of the auxiliary electrode for blue light, green light, and red light is each (e.g., all) about 94% or more. Considering the results in Table 1, by using indium tin oxide or indium zinc tin oxide as the auxiliary electrode and setting the thickness of the auxiliary electrode to about The light transmittance of the auxiliary electrode can be improved. Therefore, the display device can have improved brightness.

[0167] Reference Figure 7 and Figure 8 , the capping pattern CPL may be provided in the barrier rib opening OP-P. The capping pattern CPL may be provided on the cathode CE or on the auxiliary electrode SE. The capping pattern CPL may be patterned by a tip portion TP formed in the barrier rib PW. The capping pattern CPL may overlap with the light emitting opening OP-E.

[0168] The dummy pattern DMP may be provided on the barrier rib PW. The dummy pattern DMP may include a first dummy pattern D1, a second dummy pattern D2, a third dummy pattern D3, a fourth dummy pattern D4, and a fifth dummy pattern D5. The first dummy pattern D1, the second dummy pattern D2, the third dummy pattern D3, the fourth dummy pattern D4, and the fifth dummy pattern D5 may be sequentially stacked on the upper surface of the second barrier rib layer L2 of the barrier rib PW along the third direction DR3.

[0169] The first dummy pattern D1 may include an organic material. For example, the first dummy pattern D1 may include the same material as the light emitting pattern EP. The first dummy pattern D1 may be formed together with the light emitting pattern EP through a single process and separated from the light emitting pattern EP by the undercut shape of the barrier rib PW.

[0170] The second dummy pattern D2 may include a conductive material. For example, the second dummy pattern D2 may include the same material as the cathode CE. The second dummy pattern D2 may be formed together with the cathode CE through a single process and separated from the cathode CE by the undercut shape of the barrier rib PW.

[0171] The third dummy pattern D3 may include a conductive material. For example, the third dummy pattern D3 may include the same material as the lower auxiliary electrode LSE. The third dummy pattern D3 may be formed together with the lower auxiliary electrode LSE through a single process and separated from the lower auxiliary electrode LSE by the undercut shape of the barrier rib PW.

[0172] The fourth dummy pattern D4 may include a conductive material. For example, the fourth dummy pattern D4 may include the same material as the upper auxiliary electrode USE. The fourth dummy pattern D4 may be formed together with the upper auxiliary electrode USE through a single process and separated from the upper auxiliary electrode USE by the undercut shape of the barrier rib PW.

[0173] The fifth dummy pattern D5 may include the same material as the capping pattern CPL. The fifth dummy pattern D5 may be formed together with the capping pattern CPL through a single process and separated from the capping pattern CPL by the undercut shape of the barrier rib PW.

[0174] The dummy opening OP-D may be defined in the dummy pattern DMP. The dummy opening OP-D may overlap with the light emitting opening OP-E. When viewed on a plane, the first dummy pattern D1, the second dummy pattern D2, the third dummy pattern D3, the fourth dummy pattern D4, and the fifth dummy pattern D5 may each have a closed line shape surrounding (e.g., surrounding) the light emitting area PXA.

[0175] Figure 7 As an example, it is shown that the inner surfaces of the first dummy pattern D1, the second dummy pattern D2, the third dummy pattern D3, the fourth dummy pattern D4 and the fifth dummy pattern D5 are aligned with the second inner surface S-L2 of the second barrier rib layer L2, but the embodiments of the present disclosure are not limited thereto, and the first dummy pattern D1, the second dummy pattern D2, the third dummy pattern D3, the fourth dummy pattern D4 and the fifth dummy pattern D5 may cover the second inner surface S-L2 of the second barrier rib layer L2.

[0176] A thin film encapsulation layer TFE may be provided on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0177] A lower encapsulation inorganic pattern LIL may be provided on the auxiliary electrode SE. The lower encapsulation inorganic pattern LIL may be formed to correspond to the light emitting opening OP-E. The lower encapsulation inorganic pattern LIL may be in direct contact with the upper auxiliary electrode USE. The lower encapsulation inorganic pattern LIL may contact the lower surface of the tip portion TP. A portion of the lower encapsulation inorganic pattern LIL may cover the upper auxiliary electrode USE in the barrier rib opening OP-P.

[0178] The encapsulation organic film OL may cover the lower encapsulation inorganic pattern LIL and provide a flat upper surface. An upper encapsulation inorganic film UIL may be provided on the encapsulation organic film OL.

[0179] The lower encapsulation inorganic pattern LIL and the upper encapsulation inorganic film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the encapsulation organic film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0180] Fig. 9 According to one or more embodiments of the present disclosure, Figure 6 A cross-sectional view taken along line II-II'.

[0181] Fig. 9 is a view of enlarging a first light emitting region PXA-R, a second light emitting region PXA-G, and a third light emitting region PXA-B, and Figure 7 The description of one light emitting region PXA in the embodiment may be similarly applied to each (eg, all) of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B.

[0182] Reference Fig. 9 The display panel DP according to the present embodiment may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light emitting elements ED1, ED2 and ED3, sacrificial patterns SP1, SP2 and SP3, a pixel defining film PDL, a barrier rib PW, auxiliary electrodes SE1, SE2 and SE3 and a dummy pattern DMP.

[0183] The light emitting elements ED1, ED2 and ED3 may include a first light emitting element ED1, a second light emitting element ED2 and a third light emitting element ED3. The first light emitting element ED1 may overlap with the first light emitting opening OP1-E. The second light emitting element ED2 may overlap with the second light emitting opening OP2-E. The third light emitting element ED3 may overlap with the third light emitting opening OP3-E.

[0184] The first light emitting element ED1 may include a first anode AE1, a first light emitting pattern EP1, and a first cathode CE1. The second light emitting element ED2 may include a second anode AE2, a second light emitting pattern EP2, and a second cathode CE2. The third light emitting element ED3 may include a third anode AE3, a third light emitting pattern EP3, and a third cathode CE3. The first anode AE1, the second anode AE2, and the third anode AE3 may be provided in a variety of patterns. In one or more embodiments, the first light emitting pattern EP1 may provide red light, the second light emitting pattern EP2 may provide green light, and the third light emitting pattern EP3 may provide blue light.

[0185] In the pixel definition film PDL, a first light emitting opening OP1-E, a second light emitting opening OP2-E, and a third light emitting opening OP3-E may be defined. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3.

[0186] The sacrificial patterns SP1, SP2 and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2 and a third sacrificial pattern SP3. The first sacrificial pattern SP1, the second sacrificial pattern SP2 and the third sacrificial pattern SP3 may be provided on the upper surfaces of the first anode AE1, the second anode AE2 and the third anode AE3, respectively. In the first sacrificial pattern SP1, the second sacrificial pattern SP2 and the third sacrificial pattern SP3, a first sacrificial opening OP1-S, a second sacrificial opening OP2-S and a third sacrificial opening OP3-S respectively overlapping with the first light emitting opening OP1-E, the second light emitting opening OP2-E and the third light emitting opening OP3-E may be defined.

[0187] In the present embodiment, in the barrier rib PW, a first barrier rib opening OP1-P, a second barrier rib opening OP2-P, and a third barrier rib opening OP3-P respectively overlapping with the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E may be defined. The first light emitting region PXA-R may be defined as a region exposed by the first barrier rib opening OP1-P on the upper surface of the first anode AE1. The second light emitting region PXA-G may be defined as a region exposed by the second barrier rib opening OP2-P on the upper surface of the second anode AE2. The third light emitting region PXA-B may be defined as a region exposed by the third barrier rib opening OP3-P on the upper surface of the third anode AE3.

[0188] The first barrier rib opening OP1-P, the second barrier rib opening OP2-P, and the third barrier rib opening OP3-P may have respective widths corresponding to the first area AA1 (see Figure 7) corresponding to the first area AA1-1, AA1-2 and AA1-3, and the second area AA2 (see Figure 7 ) corresponding to the second area AA2-1, AA2-2 and AA2-3, which are described in this article Figure 7 The first barrier rib layer L1 may include a first inner surface S-L1 (see Figure 7 ), the first inner surface S-L1 defines first areas AA1-1, AA1-2, and AA1-3 of the first barrier rib opening OP1-P, the second barrier rib opening OP2-P, and the third barrier rib opening OP3-P, and the second barrier rib layer L2 may include a second inner surface S-L2 (see Figure 7 ), the second inner surface S-L2 defines second areas AA2-1, AA2-2, and AA2-3 of the first barrier rib openings OP1-P, the second barrier rib openings OP2-P, and the third barrier rib openings OP3-P.

[0189] The first emission pattern EP1 and the first cathode CE1 may be provided in the first barrier rib opening OP1-P, the second emission pattern EP2 and the second cathode CE2 may be provided in the second barrier rib opening OP2-P, and the third emission pattern EP3 and the third cathode CE3 may be provided in the third barrier rib opening OP3-P.

[0190] In the present embodiment, the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 and the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be physically separated by the second barrier rib layer L2 forming the tip portions TP1, TP2, and TP3, and formed in the light emitting openings OP1-E, OP2-E, and OP3-E and the barrier rib openings OP1-P, OP2-P, and OP3-P. The first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 may each be spaced apart and / or separated from the barrier rib PW when viewed on a plane. For example, the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 may each not contact the first inner surface S-L1 of the first barrier rib layer L1.

[0191] According to one or more embodiments of the present disclosure, a plurality of first light emitting patterns EP1 may be patterned and deposited in pixel units by the tip portions TP1, TP2, and TP3 defined in the barrier ribs PW. For example, the first light emitting patterns EP1 may be commonly formed using an open mask, but may be easily divided into pixel units by the barrier ribs PW.

[0192] In one or more embodiments, when the first light emitting pattern EP1 is patterned using a fine metal mask (FMM), a support spacer protruding from the conductive barrier rib is required to support the fine metal mask. In one or more embodiments, the fine metal mask is spaced apart from the substrate surface where patterning is performed and / or separates the height of the barrier rib and the spacer, and thus may be limited in obtaining high resolution. In one or more embodiments, the fine metal mask is in contact with the spacer, and thus after the patterning process of the first light emitting pattern EP1, foreign matter may remain on the spacer, or the spacer may be damaged due to the extrusion of the fine metal mask. Therefore, a defective display panel may be formed.

[0193] According to the present embodiment, by including the barrier ribs PW, physical separation between the light emitting elements ED1, ED2, and ED3 can be easily achieved. Therefore, current leakage or driving errors between adjacent light emitting regions PXA-R, PXA-G, and PXA-B can be prevented or reduced, and independent driving of each of the light emitting elements ED1, ED2, and ED3 can be achieved.

[0194] Specifically, in the absence of Figure 2 ), by patterning the plurality of first light emitting patterns EP1 without a mask that contacts the internal components in the display panel DP, defects can be reduced, and thus a display panel DP with improved process reliability can be provided. Since patterning is possible even when a separate supporting spacer protruding from the barrier rib PW is not provided, the areas of the light emitting regions PXA-R, PXA-G, and PXA-B can be refined, and thus a display panel DP in which high resolution is highly applicable can be provided.

[0195] In one or more embodiments, when manufacturing a large-area display panel DP, process costs can be reduced by skipping the production of a large-area mask, and the process is not affected by defects that may occur in the large-area mask, and therefore, a display panel DP with improved process reliability can be provided. The description of the plurality of first emission patterns EP1 can be similarly applied to the plurality of second emission patterns EP2 and the plurality of third emission patterns EP3.

[0196] The auxiliary electrodes SE1, SE2, and SE3 may include a first auxiliary electrode SE1, a second auxiliary electrode SE2, and a third auxiliary electrode SE3. The first auxiliary electrode SE1 may be provided on the first light emitting element ED1, the second auxiliary electrode SE2 may be provided on the second light emitting element ED2, and the third auxiliary electrode SE3 may be provided on the third light emitting element ED3. The first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 may be provided along the first inner surface S-L1 (see FIG. 1 ) of the first barrier rib layer L1. Figure 7). The first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 may respectively cover both ends of the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 (for example, simultaneously cover both ends of the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3) and both ends of the first cathode CE1, the second cathode CE2, and the third cathode CE3 (for example, simultaneously cover both ends of the first cathode CE1, the second cathode CE2, and the third cathode CE3).

[0197] The first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 may be electrically connected by contacting the first barrier rib layer L1 and thus may receive a common voltage, and the first cathode CE1, the second cathode CE2, and the third cathode CE3 may receive a common cathode voltage by contacting the first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3.

[0198] The first auxiliary electrode SE1 may include a first lower auxiliary electrode LSE1 and a first upper auxiliary electrode USE1. The second auxiliary electrode SE2 may include a second lower auxiliary electrode LSE2 and a second upper auxiliary electrode USE2. The third auxiliary electrode SE3 may include a third lower auxiliary electrode LSE3 and a third upper auxiliary electrode USE3.

[0199] The first lower auxiliary electrode LSE1, the second lower auxiliary electrode LSE2, and the third lower auxiliary electrode LSE3 may contact the first inner surface S-L1 of the first barrier rib layer L1, and may contact the first cathode CE1, the second cathode CE2, and the third cathode CE3. For example, the first lower auxiliary electrode LSE1 may be electrically connected to the first barrier rib layer L1 and the first cathode CE1, the second lower auxiliary electrode LSE2 may be electrically connected to the first barrier rib layer L1 and the second cathode CE2, and the third lower auxiliary electrode LSE3 may be electrically connected to the first barrier rib layer L1 and the third cathode CE3.

[0200] The first lower auxiliary electrode LSE1, the second lower auxiliary electrode LSE2, and the third lower auxiliary electrode LSE3 may be connected to Figure 7 and Figure 8 The lower auxiliary electrodes LSE described in the above have the same characteristics. For example, the first lower auxiliary electrode LSE1, the second lower auxiliary electrode LSE2, and the third lower auxiliary electrode LSE3 may each have approximately To about The first lower auxiliary electrode LSE1, the second lower auxiliary electrode LSE2, and the third lower auxiliary electrode LSE3 may each include indium zinc tin oxide. The first lower auxiliary electrode LSE1, the second lower auxiliary electrode LSE2, and the third lower auxiliary electrode LSE3 may each have substantially the same amount of indium atoms and zinc atoms, and the amount of tin atoms is between about 14 at % and about 22 at %. For example, the amount of indium atoms may be substantially the same as the amount of zinc atoms. The first lower auxiliary electrode LSE1, the second lower auxiliary electrode LSE2, and the third lower auxiliary electrode LSE3 may have an amorphous phase. The first lower auxiliary electrode LSE1, the second lower auxiliary electrode LSE2, and the third lower auxiliary electrode LSE3 may have a light transmittance of about 90% or more.

[0201] The first upper auxiliary electrode USE1, the second upper auxiliary electrode USE2, and the third upper auxiliary electrode USE3 may not contact the first barrier rib layer L1. The first upper auxiliary electrode USE1, the second upper auxiliary electrode USE2, and the third upper auxiliary electrode USE3 may not contact the first cathode CE1, the second cathode CE2, and the third cathode CE3. The first upper auxiliary electrode USE1, the second upper auxiliary electrode USE2, and the third upper auxiliary electrode USE3 may not contact the first barrier rib layer L1, and thus electrochemical corrosion of the first upper auxiliary electrode USE1, the second upper auxiliary electrode USE2, and the third upper auxiliary electrode USE3 due to a potential difference with the first barrier rib layer L1 may be prevented or reduced.

[0202] The first upper auxiliary electrode USE1, the second upper auxiliary electrode USE2, and the third upper auxiliary electrode USE3 may be connected to Figure 7 and Figure 8 The upper auxiliary electrodes USE described in the foregoing have the same characteristics. For example, the first upper auxiliary electrode USE1, the second upper auxiliary electrode USE2, and the third upper auxiliary electrode USE3 may each have approximately To about The first upper auxiliary electrode USE1, the second upper auxiliary electrode USE2, and the third upper auxiliary electrode USE3 may each include indium tin oxide. Based on the total amount of indium oxide and tin oxide 100wt%, the first lower auxiliary electrode LSE1, the second lower auxiliary electrode LSE2, and the third lower auxiliary electrode LSE3 may each have a weight percentage of indium oxide of approximately 90wt% and a weight percentage of tin oxide of 10wt%. The first upper auxiliary electrode USE1, the second upper auxiliary electrode USE2, and the third upper auxiliary electrode USE3 may have an amorphous phase. The first upper auxiliary electrode USE1, the second upper auxiliary electrode USE2, and the third upper auxiliary electrode USE3 may have a light transmittance of approximately 90% or more.

[0203] The dummy patterns DMP may include a plurality of first dummy patterns D1 , a plurality of second dummy patterns D2 , and a plurality of third dummy patterns D3 .

[0204] When viewed on a plane, the first dummy pattern D1 may include a (1-1)th dummy pattern D11, a (1-2)th dummy pattern D12, a (1-3)th dummy pattern D13, a (1-4)th dummy pattern D14, and a (1-5)th dummy pattern D15 surrounding (e.g., surrounding) the first light emitting region PXA-R. The (1-1)th dummy pattern D11, the (1-2)th dummy pattern D12, the (1-3)th dummy pattern D13, the (1-4)th dummy pattern D14, and the (1-5)th dummy pattern D15 may include the same material as the first light emitting pattern EP1, the first cathode CE1, the first lower auxiliary electrode LSE1, the first upper auxiliary electrode USE1, and the first capping pattern CPL1, respectively, and be formed by the same process as the first light emitting pattern EP1, the first cathode CE1, the first lower auxiliary electrode LSE1, the first upper auxiliary electrode USE1, and the first capping pattern CPL1, respectively.

[0205] When viewed on a plane, the second dummy pattern D2 may include a (2-1)th dummy pattern D21, a (2-2)th dummy pattern D22, a (2-3)th dummy pattern D23, a (2-4)th dummy pattern D24, and a (2-5)th dummy pattern D25 surrounding (e.g., surrounding) the second light emitting region PXA-G. The (2-1)th dummy pattern D21, the (2-2)th dummy pattern D22, the (2-3)th dummy pattern D23, the (2-4)th dummy pattern D24, and the (2-5)th dummy pattern D25 may include the same material as the second light emitting pattern EP2, the second cathode CE2, the second lower auxiliary electrode LSE2, the second upper auxiliary electrode USE2, and the second capping pattern CPL2, respectively, and be formed by the same process as the second light emitting pattern EP2, the second cathode CE2, the second lower auxiliary electrode LSE2, the second upper auxiliary electrode USE2, and the second capping pattern CPL2, respectively.

[0206] When viewed on a plane, the third dummy pattern D3 may include a (3-1)th dummy pattern D31, a (3-2)th dummy pattern D32, a (3-3)th dummy pattern D33, a (3-4)th dummy pattern D34, and a (3-5)th dummy pattern D35 surrounding (e.g., surrounding) the third light emitting region PXA-B. The (3-1)th dummy pattern D31, the (3-2)th dummy pattern D32, the (3-3)th dummy pattern D33, the (3-4)th dummy pattern D34, and the (3-5)th dummy pattern D35 may include the same material as the third light emitting pattern EP3, the third cathode CE3, the third lower auxiliary electrode LSE3, the third upper auxiliary electrode USE3, and the third capping pattern CPL3, respectively, and be formed by the same process as the third light emitting pattern EP3, the third cathode CE3, the third lower auxiliary electrode LSE3, the third upper auxiliary electrode USE3, and the third capping pattern CPL3, respectively.

[0207] In the dummy pattern DMP, first, second, and third dummy openings OP1 -D, OP2 -D, and OP3 -D corresponding to the first, second, and third light emitting openings OP1 -E, OP2 -E, and OP3 -E may be defined.

[0208] The thin film encapsulation layer TFE may include lower encapsulation inorganic patterns LIL1, LIL2 and LIL3, an encapsulation organic film OL and an upper encapsulation inorganic film UIL. In the present embodiment, the lower encapsulation inorganic patterns LIL1, LIL2 and LIL3 may include a first lower encapsulation inorganic pattern LIL1, a second lower encapsulation inorganic pattern LIL2 and a third lower encapsulation inorganic pattern LIL3. The first lower encapsulation inorganic pattern LIL1, the second lower encapsulation inorganic pattern LIL2 and the third lower encapsulation inorganic pattern LIL3 may overlap with the first light emitting opening OP1-E, the second light emitting opening OP2-E and the third light emitting opening OP3-E, respectively.

[0209] The first lower encapsulation inorganic pattern LIL1 may cover the first auxiliary electrode SE1 and the first dummy pattern D1, and a portion of the first lower encapsulation inorganic pattern LIL1 may be provided within the first barrier rib opening OP1-P. The second lower encapsulation inorganic pattern LIL2 may cover the second auxiliary electrode SE2 and the second dummy pattern D2, and a portion of the second lower encapsulation inorganic pattern LIL2 may be provided within the second barrier rib opening OP2-P. The third lower encapsulation inorganic pattern LIL3 may cover the third auxiliary electrode SE3 and the third dummy pattern D3, and a portion of the third lower encapsulation inorganic pattern LIL3 may be provided within the third barrier rib opening OP3-P. The first lower encapsulation inorganic pattern LIL1, the second lower encapsulation inorganic pattern LIL2, and the third lower encapsulation inorganic pattern LIL3 may be provided in a pattern form spaced apart and / or separated from each other.

[0210] The encapsulation organic film OL can cover the lower encapsulation inorganic pattern LIL (see Figure 8 ) and provide a flat upper surface. An upper encapsulation inorganic film UIL may be provided on the encapsulation organic film OL.

[0211] FIG. 10A to FIG. 10I are cross-sectional views each illustrating a part of a method for manufacturing a display device according to one or more embodiments of the present disclosure.

[0212] Reference Fig. 10A According to one or more embodiments, the method for manufacturing a display panel may include providing a preliminary display panel DP-I. The preliminary display panel DP-I provided in this embodiment may include a base layer BL, a circuit element layer DP-CL, a first anode AE1, a second anode AE2, and a third anode AE3, a first preliminary sacrificial pattern SP1-I, a second preliminary sacrificial pattern SP2-I, and a third preliminary sacrificial pattern SP3-I, a pixel defining film PDL, a first preliminary barrier rib layer L1-I, and a second preliminary barrier rib layer L2-I.

[0213] The circuit element layer DP-CL can be formed by a typical circuit element manufacturing process, which forms an insulating layer, a semiconductor layer and a conductive layer by methods such as coating and deposition, selectively patterns the insulating layer, the semiconductor layer and the conductive layer by photolithography and etching processes, and then forms a semiconductor pattern and / or a conductive pattern, etc.

[0214] The first anode AE1 and the first preliminary sacrificial pattern SP1-I may be formed by substantially the same patterning process, and the second anode AE2 and the second preliminary sacrificial pattern SP2-I may be formed by substantially the same patterning process. The third anode AE3 and the third preliminary sacrificial pattern SP3-I may be formed by substantially the same patterning process. A pixel defining film PDL may be provided on the base layer BL. The pixel defining film PDL may cover the first anode AE1, the second anode AE2, and the third anode AE3 and each (e.g., all) of the first preliminary sacrificial pattern SP1-I, the second preliminary sacrificial pattern SP2-I, and the third preliminary sacrificial pattern SP3-I.

[0215] The first preliminary barrier rib layer L1-I may be provided on the pixel defining film PDL. The first preliminary barrier rib layer L1-I may be formed by a deposition process of a conductive material. The second preliminary barrier rib layer L2-I may be provided on the first preliminary barrier rib layer L1-I. The second preliminary barrier rib layer L2-I may also be formed by a deposition process of a conductive material. In the present embodiment, the first preliminary barrier rib layer L1-I may include aluminum (Al) or molybdenum (Mo), and the second preliminary barrier rib layer L2-I may include titanium (Ti), but the materials of the first preliminary barrier rib layer L1-I and the second preliminary barrier rib layer L2-I are not limited thereto. The first preliminary barrier rib layer L1-I and the second preliminary barrier rib layer L2-I may form a preliminary barrier rib PW-I.

[0216] Thereafter, the method for manufacturing a display panel according to the present embodiment may include forming (e.g., applying or providing) a first photoresist layer PR1 on the preliminary barrier ribs PW-I. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the preliminary barrier ribs PW-I and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, a first optical opening OP-PR1 may be formed in the first photoresist layer PR1. The first optical opening OP-PR1 may overlap with the first anode AE1, the second anode AE2, and the third anode AE3.

[0217] Thereafter, preliminarily etching the first preliminary barrier rib layer L1-I and the second preliminary barrier rib layer L2-I may include using the first photoresist layer PR1 as a mask and dry etching the first preliminary barrier rib layer L1-I and the second preliminary barrier rib layer L2-I to form preliminary barrier rib openings OP1-PI, OP2-PI, and OP3-PI in the preliminary barrier rib PW-I. The preliminary barrier rib openings OP1-PI, OP2-PI, and OP3-PI may include a first preliminary barrier rib opening OP1-PI, a second preliminary barrier rib opening OP2-PI, and a third preliminary barrier rib opening OP3-PI. The first preliminary barrier rib opening OP1-PI may be formed to overlap the first anode AE1, and the second preliminary barrier rib opening OP2-PI may be formed to overlap the second anode AE2. The third preliminary barrier rib opening OP3-PI may be formed to overlap the third anode AE3.

[0218] The first dry etching process in the present embodiment may be performed in an etching environment in which the etching selectivity between the first preliminary barrier rib layer L1-I and the second preliminary barrier rib layer L2-I is substantially the same. Therefore, the inner surface of the first preliminary barrier rib layer L1-I defining the preliminary barrier rib openings OP1-PI, OP2-PI, and OP3-PI and the inner surface of the second preliminary barrier rib layer L2-I defining the preliminary barrier rib openings OP1-PI, OP2-PI, and OP3-PI may be substantially aligned.

[0219] Afterwards, refer to Fig. 10B , the first preliminary barrier rib layer L1-I can be etched (see Fig. 10A ) and the second preliminary barrier rib layer L2-I (see Fig. 10A ) to form a first barrier rib layer L1 and a second barrier rib layer L2 in which barrier rib openings OP1-P, OP2-P, and OP3-P are defined. The first preliminary barrier rib layer L1-I (see Fig. 10A ) may include using the first photoresist layer PR1 as a mask and wet etching the first preliminary barrier rib layer L1-I to form preliminary barrier rib openings OP1-PI, OP2-PI, and OP3-PI (see Fig. 10A ) form barrier rib openings OP1-P, OP2-P, and OP3-P. The barrier rib openings OP1-P, OP2-P, and OP3-P may include a first barrier rib opening OP1-P, a second barrier rib opening OP2-P, and a third barrier rib opening OP3-P. The first barrier rib opening OP1-P may be formed to overlap the first anode AE1, and the second barrier rib opening OP2-P may be formed to overlap the second anode AE2. The third barrier rib opening OP3-P may be formed to overlap the third anode AE3.

[0220] The barrier rib openings OP1-P, OP2-P, OP3-P may include first areas AA1-1, AA1-2, and AA1-3 and second areas AA2-1, AA2-2, and AA2-3 sequentially arranged in the thickness direction (i.e., the third direction DR3), respectively. The first barrier rib layer L1 may include a first inner surface S-L1 defining the first areas AA1-1, AA1-2, and AA1-3 of the barrier rib openings OP1-P, OP2-P, and OP3-P, and the second barrier rib layer L2 may include a second inner surface S-L2 defining the second areas AA2-1, AA2-2, and AA2-3 of the barrier rib openings OP1-P, OP2-P, and OP3-P.

[0221] The formation of the first barrier rib layer L1 and the second barrier rib layer L2 may include forming tip portions TP1, TP2, and TP3 protruding from the first barrier rib layer L1 toward the barrier rib openings OP1-P, OP2-P, and OP3-P in the second barrier rib layer L2. The secondary wet etching process in this embodiment may be performed in which the first preliminary barrier rib layer L1-I and the second preliminary barrier rib layer L2-I (see Fig. 10A) is performed in an environment where the etching selectivity between the barrier ribs PW and the barrier rib openings OP1-P, OP2-P, and OP3-P is relatively large or high. Therefore, the inner surface of the barrier rib PW that defines the barrier rib openings OP1-P, OP2-P, and OP3-P may have an undercut shape in cross section. For example, since the etching rate of the first barrier rib layer L1 relative to the etching solution is greater than the etching rate of the second barrier rib layer L2, the first barrier rib layer L1 will be significantly (e.g., mainly) etched. Therefore, the first inner surface S-L1 of the first barrier rib layer L1 may be formed to be much more recessed inward than the second inner surface S-L2 of the second barrier rib layer L2. The tip portions TP1, TP2, and TP3 may be formed in the barrier rib PW by a portion of the second barrier rib layer L2 that protrudes farther than the first barrier rib layer L1.

[0222] The tip portions TP1, TP2 and TP3 of the second barrier rib layer L2 are disposed in the first direction DR1 (see FIG. Figure 8 ) may be a length from a first inner surface S-L1 of the first barrier rib layer L1 overlapping the pixel defining film PDL to a second inner surface S-L2 of the second barrier rib layer L2.

[0223] Then, refer to Fig. 10C The method for manufacturing a display panel according to the present embodiment may include etching a pixel definition film PDL and etching preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I (see Fig. 10B ). The etching process of the pixel defining film PDL may be performed using a dry etching method, and the first photoresist layer PR1 and the barrier rib PW (e.g., the second barrier rib layer L2) may be used as a mask for etching. In the pixel defining film PDL, light emitting openings OP1-E, OP2-E, and OP3-E corresponding to the barrier rib openings OP1-P, OP2-P, and OP3-P may be formed. The light emitting openings OP1-E, OP2-E, and OP3-E may include a first light emitting opening OP1-E, a second light emitting opening OP2-E, and a third light emitting opening OP3-E.

[0224] The etching process of the preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I may be performed using a wet etching method, and the first photoresist layer PR1 and the barrier rib PW (e.g., the second barrier rib layer L2) may be used as a mask for etching. In the sacrificial patterns SP1, SP2, and SP3 formed by etching the preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I, sacrificial openings OP1-S, OP2-S, and OP3-S overlapping the light emitting openings OP1-E, OP2-E, and OP3-E may be formed.

[0225] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. A first sacrificial opening OP1-S overlapping the first light emitting opening OP1-E may be formed in the first sacrificial pattern SP1, a second sacrificial opening OP2-S overlapping the second light emitting opening OP2-E may be formed in the second sacrificial pattern SP2, and a third sacrificial opening OP3-S overlapping the third light emitting opening OP3-E may be formed in the third sacrificial pattern SP3. At least a portion of the first anode AE1 may be exposed from the first sacrificial pattern SP1 and the pixel defining film PDL through the first sacrificial opening OP1-S and the first light emitting opening OP1-E, and at least a portion of the second anode AE2 may be exposed from the second sacrificial pattern SP2 and the pixel defining film PDL through the second sacrificial opening OP2-S and the second light emitting opening OP2-E. At least a portion of the third anode AE3 may be exposed from the third sacrificial pattern SP3 and the pixel defining film PDL through the third sacrificial opening OP3-S and the third light emitting opening OP3-E.

[0226] The etching process of the sacrificial patterns SP1, SP2, and SP3 may be performed in an environment in which the etching selectivity between the sacrificial patterns SP1, SP2, and SP3 and the anodes AE1, AE2, and AE3 is relatively large or high, and thus, the anodes AE1, AE2, and AE3 may be prevented from or reduced from being etched together. For example, by providing the sacrificial patterns SP1, SP2, and SP3 (e.g., sacrificial patterns SP1, SP2, and SP3 having a higher etching rate than the anodes AE1, AE2, and AE3, respectively) between the pixel defining film PDL and the anodes AE1, AE2, and AE3, the anodes AE1, AE2, and AE3 may be prevented from or reduced from being etched together and / or damaged during the etching process.

[0227] Then, refer to Fig. 10D A first light emitting element ED1 including a first anode AE1, a first light emitting pattern EP1, and a first cathode CE1 may be formed in the first barrier rib opening OP1-P. The first light emitting pattern EP1 and the first cathode CE1 may be formed by a thermal evaporation process.

[0228] The first light emitting pattern EP1 may be formed on the first anode AE1. In the formation of the first light emitting pattern EP1, the first light emitting pattern EP1 may be separated from the preliminary (1-1)th dummy pattern D11-I by the first tip portion TP formed on the barrier rib PW-I. The first light emitting pattern EP1 may be provided in the first light emitting opening OP1-E and the first barrier rib opening OP1-P. In the formation of the first light emitting pattern EP1, the preliminary (1-1)th dummy pattern D11-I spaced apart and / or separated from the first light emitting pattern EP1 may be formed on the barrier rib PW.

[0229] The first cathode CE1 may be formed on the first light emitting pattern EP1. The first cathode CE1 may be separated from the preliminary (1-2) dummy pattern D12-I by a first tip portion TP formed in the barrier rib PW. The first cathode CE1 may be provided in the first barrier rib opening OP1-P. In the formation of the first cathode CE1, the preliminary (1-2) dummy pattern D12-I spaced apart and / or separated from the first cathode CE1 may be formed on the barrier rib PW.

[0230] Afterwards, refer to Fig.10E A first lower auxiliary electrode LSE1 contacting the first cathode CE1 and the barrier rib PW and containing indium zinc tin oxide, and a first upper auxiliary electrode USE1 provided on the first lower auxiliary electrode LSE1 and containing indium tin oxide may be formed in the first barrier rib opening OP1 -P.

[0231] The first lower auxiliary electrode LSE1 may be provided on the first cathode CE1 and may cover the first cathode CE1. The first lower auxiliary electrode LSE1 may be separated from the preliminary (1-3)th dummy pattern D13-I by a first tip portion TP formed on the barrier rib PW. The first lower auxiliary electrode LSE1 may be deposited to cover both ends of the first cathode CE1 (e.g., to simultaneously cover both ends of the first cathode CE1). In the formation of the first lower auxiliary electrode LSE1, the preliminary (1-3)th dummy pattern D13-I spaced apart and / or separated from the first lower auxiliary electrode LSE1 may be formed on the barrier rib PW.

[0232] In one or more embodiments, the first lower auxiliary electrode LSE1 may be formed by a sputtering process. The first lower auxiliary electrode LSE1 may be formed to contact the first barrier rib layer L1. The first lower auxiliary electrode LSE1 may be formed to extend along the first inner surface S-L1 of the first barrier rib layer L1. The first lower auxiliary electrode LSE1 may extend along a portion of the lower surface of the first tip portion TP.

[0233] The first lower auxiliary electrode LSE1 may have an approximate To about Since the thickness of the first lower auxiliary electrode LSE1 is approximately or less, and thus the first lower auxiliary electrode LSE1 may have an amorphous phase.

[0234] The first upper auxiliary electrode USE1 may be provided on the first lower auxiliary electrode LSE1. The first upper auxiliary electrode USE1 may be separated from the preliminary (1-4)th dummy pattern D14-I by a first tip portion TP formed on the barrier rib PW. In the formation of the first upper auxiliary electrode USE1, the preliminary (1-4)th dummy pattern D14-I spaced apart and / or separated from the first upper auxiliary electrode USE1 may be formed on the barrier rib PW.

[0235] In one or more embodiments, the first upper auxiliary electrode USE1 may be formed through a sputtering process. The first upper auxiliary electrode USE1 may be formed to extend along the first lower auxiliary electrode LSE1.

[0236] The first upper auxiliary electrode USE1 may have a thickness of approximately To about Since the thickness of the first upper auxiliary electrode USE1 is approximately or less, and thus the first upper auxiliary electrode USE1 may have an amorphous phase.

[0237] Afterwards, refer to Fig.10F , a first capping pattern CPL1 provided on the first auxiliary electrode SE1 and in the first barrier rib opening OP1-P may be formed. In forming the first capping pattern CPL1, preliminary (1-5)th dummy patterns D15-I spaced apart and / or separated from the first capping pattern CPL1 may be formed on the barrier rib PW.

[0238] Thereafter, a preliminary first lower encapsulation inorganic layer LIL1-I covering the first light emitting element ED1, the first auxiliary electrode SE1, and the first capping pattern CPL1 may be formed. The preliminary first lower encapsulation inorganic layer LIL1-I may be formed by a deposition process. In one or more embodiments, the preliminary first lower encapsulation inorganic layer LIL1-I may be formed by a chemical vapor deposition (CVD) process. The preliminary first lower encapsulation inorganic layer LIL1-I may be formed on the barrier rib PW and the first auxiliary electrode SE1.

[0239] Thereafter, a second photoresist layer PR2 may be formed. In the formation of the second photoresist layer PR2, the second photoresist layer PR2 may be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2 may be formed into a pattern shape corresponding to the first light emitting opening OP1-E.

[0240] Afterwards, refer to Figure 10G , the initial (1-1) virtual pattern D11-I (see Fig.10F ), the initial (1-2) virtual pattern D12-I (see Fig.10F), the initial (1-3) virtual pattern D13-I (see Fig.10F )、Preliminary (1-4) virtual pattern D14-I (see Fig.10F ) and the preliminary (1-5) dummy pattern D15-I (see Fig.10F ) and the preliminary first lower encapsulation inorganic layer LIL1-I (see Fig.10F ) is patterned to form a first dummy pattern D1 and a first lower encapsulation inorganic layer LIL1.

[0241] Reference Fig.10F and 10G In the patterning of the preliminary first lower encapsulation inorganic layer LIL1-I, the preliminary first lower encapsulation inorganic layer LIL1-I may be dry-etched to remove a portion of the preliminary first lower encapsulation inorganic layer LIL1-I that does not overlap with the second photoresist layer PR2 (e.g., does not overlap with the second photoresist layer PR2). The patterned first lower encapsulation inorganic layer LIL1 may overlap with the first light emitting opening OP1-E.

[0242] In the patterning of the preliminary (1-5) dummy pattern D15-I, the preliminary (1-5) dummy pattern D15-I can be dry etched to remove the portion of the preliminary (1-5) dummy pattern D15-I that does not overlap with the second photoresist layer PR2 (for example, does not overlap with the second photoresist layer PR2).

[0243] In the patterning of the preliminary (1-3) dummy pattern D13-I and the preliminary (1-4) dummy pattern D14-I, the preliminary (1-3) dummy pattern D13-I and the preliminary (1-4) dummy pattern D14-I may be wet-etched, and portions of the preliminary (1-3) dummy pattern D13-I and the preliminary (1-4) dummy pattern D14-I that do not overlap with the second photoresist layer PR2 (e.g., do not overlap with the second photoresist layer PR2) may be removed using a stripper. In this case, when the preliminary (1-3) dummy pattern D13-I and the preliminary (1-4) dummy pattern D14-I are in a crystalline state, the preliminary (1-3) dummy pattern D13-I and the preliminary (1-4) dummy pattern D14-I may not be removed by wet etching and / or a stripper.

[0244] Therefore, in order to facilitate the process of etching the preliminary (1-3) dummy pattern D13-I and the preliminary (1-4) dummy pattern D14-I, the preliminary (1-3) dummy pattern D13-I and the preliminary (1-4) dummy pattern D14-I need to have an amorphous phase. When indium tin oxide and indium zinc tin oxide are used as the preliminary (1-3) dummy pattern D13-I and the preliminary (1-4) dummy pattern D14-I, a larger thickness may cause crystallization. Therefore, the thickness of each of the preliminary (1-3) dummy pattern D13-I and the preliminary (1-4) dummy pattern D14-I can be limited to about or less to prevent or reduce the crystallization of the preliminary (1-3)th dummy pattern D13-I and the preliminary (1-4)th dummy pattern D14-I, and to facilitate the etching process.

[0245] In the patterning of the preliminary (1-2) dummy pattern D12-I and the preliminary (1-1) dummy pattern D11-I, wet etching and / or a stripper may be used. Portions of the preliminary (1-2) dummy pattern D12-I and the preliminary (1-1) dummy pattern D11-I that do not overlap with the second photoresist layer PR2 (e.g., do not overlap with the second photoresist layer PR2) may be removed.

[0246] Afterwards, refer to Fig. 10H The second light emitting element ED2, the second auxiliary electrode SE2, the second capping pattern CPL2, the second dummy pattern D2 and the second lower encapsulation inorganic layer LIL2 may be formed in the second light emitting region PXA-G (see Fig.10I ). In this case, by Figures 10D to 10G The second light emitting element ED2 , the second auxiliary electrode SE2 , the second capping pattern CPL2 , the second dummy pattern D2 , and the second lower encapsulation inorganic layer LIL2 may be formed by substantially the same process as described above.

[0247] The third light emitting element ED3, the third auxiliary electrode SE3, the third capping pattern CPL3, the third dummy pattern D3, and the third lower encapsulation inorganic layer LIL3 may be formed at the same level as the third light emitting region PXA-B (see Fig.10I ). In this case, by Figures 10D to 10G The third light emitting element ED3, the third auxiliary electrode SE3, the third capping pattern CPL3, the third dummy pattern D3, and the third lower encapsulation inorganic layer LIL3 may be formed by substantially the same process as described above.

[0248] Afterwards, refer to Fig.10I, the method for manufacturing a display panel according to the present embodiment may include forming an encapsulation organic film OL and an upper encapsulation inorganic film UIL to complete a display panel DP. The encapsulation organic film OL may be formed by applying an organic material using an inkjet method, but is not limited thereto. The encapsulation organic film OL provides a flat upper surface. Thereafter, an upper encapsulation inorganic film UIL may be formed by deposition of an inorganic material. Thus, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE may be formed.

[0249] According to one or more embodiments of the present disclosure, an auxiliary electrode having high light transmittance may be used to increase light transmittance.

[0250] In one or more embodiments, the auxiliary electrode may be formed as a double layer, and the lower auxiliary electrode in contact with the barrier rib may be designed to contain zinc to prevent or reduce corrosion of the auxiliary electrode.

[0251] Terms such as "substantially," "approximately," and "approximately" are used as relative terms rather than terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that are recognized by those of ordinary skill in the art. They may include the stated values ​​and acceptable ranges of deviation determined by those of ordinary skill in the art, taking into account the limitations and errors associated with the measurement of quantities. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0252] The numerical ranges disclosed herein include and are intended to disclose all subranges of the same numerical precision that fall within the range. For example, a range of "1.0 to 10.0" includes all subranges having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Therefore, the applicant reserves the right to amend this specification (including the claims) to explicitly state any subranges contained within the ranges explicitly listed herein.

[0253] The display device, light emitting element and / or any other related device or component according to the embodiment of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware and hardware. For example, the various components of the light emitting device and / or the light emitting element can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of the light emitting device and / or the light emitting element can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of the device and / or element can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (such as, for example, a random access memory (RAM)). The computer program instructions can also be stored in other non-temporary computer-readable media (such as, for example, a read-only compact disk memory (CD-ROM) or a flash drive). Furthermore, those skilled in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the scope of the embodiments of the present disclosure.

[0254] Although the present disclosure has been described with reference to the preferred embodiments of the present disclosure, it will be understood that the present disclosure should not be limited to these preferred embodiments, and those skilled in the art may make one or more suitable changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the technical scope of the present disclosure is not limited to the detailed description in the specification, but should only be determined with reference to the claims and their equivalents.

Claims

1. A display device, wherein: The display device comprises: Base layer; a pixel defining film on the base layer and having a light emitting opening defined in the pixel defining film; a barrier rib including a first barrier rib layer on the pixel defining film and a second barrier rib layer on the first barrier rib layer, wherein the barrier rib has a barrier rib opening defined therein, the barrier rib opening overlapping the light emitting opening; a light emitting element overlapping the light emitting opening, the light emitting element including a first electrode, a light emitting pattern on the first electrode and configured to emit light, and a second electrode on the light emitting pattern; and an auxiliary electrode, on the second electrode, contacting the barrier rib, The auxiliary electrode comprises: a lower auxiliary electrode on the second electrode, contacting the barrier rib and comprising indium zinc tin oxide; and The upper auxiliary electrode is on the lower auxiliary electrode and includes indium tin oxide.

2. The display device according to claim 1, wherein: The lower auxiliary electrode has a thickness equal to or greater than and equal to or less than The thickness between.

3. The display device according to claim 1, wherein: The upper auxiliary electrode has a thickness equal to or greater than and equal to or less than The thickness between.

4. The display device according to claim 1, wherein: The lower auxiliary electrode is on a first inner surface of the barrier rib opening of the first barrier rib layer and is electrically connected to the barrier rib.

5. The display device according to claim 1, wherein: The upper auxiliary electrode does not contact the first barrier rib layer.

6. The display device according to claim 1, wherein: The indium zinc tin oxide comprises: an amount of indium atoms substantially the same as the amount of zinc atoms, and The amount of tin atoms is between equal to or greater than 14 at % and equal to or less than 22 at % based on 100 at % of the total amount of the indium zinc tin oxide.

7. The display device according to claim 1, wherein: Based on 100 wt % of the total amount of the indium tin oxide, the indium tin oxide includes 90 wt % of indium oxide and 10 wt % of tin oxide.

8. The display device according to claim 1, wherein: The second barrier rib layer includes a tip portion protruding from the first barrier rib layer toward the barrier rib opening.

9. The display device according to claim 1, wherein: The lower auxiliary electrode and the upper auxiliary electrode each include an amorphous phase.

10. The display device according to claim 1, wherein: The lower auxiliary electrode extends along each of a first inner surface of the first barrier rib layer and a lower surface of the second barrier rib layer.

11. The display device according to claim 1, wherein: The lower auxiliary electrode and the upper auxiliary electrode each have a light transmittance equal to or greater than 90%.

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