Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are disclosed. The display device includes: a first pixel electrode positioned in a first emission area of a substrate; the insulating layer covers the edge of the first pixel electrode; a first light emitting layer on the first pixel electrode and the insulating layer; a first common electrode on the first light emitting layer; a conductive layer disposed on the insulating layer to surround the first emission region; a first bank on the conductive layer; a second bank adjacent to the first emission region on the first bank and including a tip protruding from a side of the first bank; a groove recessed from an upper surface of the second bank to at least a portion of the first bank; a first organic pattern; and a first inorganic layer.

Description

Technical Field

[0001] Aspects of embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs. The display device can be a flat panel display device, such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among these flat panel display devices, the light emitting display device includes a light emitting element that enables each pixel of the display panel to emit light itself. Therefore, the light emitting display device can display an image without a backlight unit that provides light to the display panel. Summary of the invention

[0003] According to aspects of an embodiment of the present disclosure, there are provided a display device capable of blocking moisture from penetrating through an organic pattern, an electrode pattern, and a capping pattern on a bank, and a method of manufacturing the display device.

[0004] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure provided below.

[0005] According to one or more embodiments of the present disclosure, a display device includes: a first pixel electrode positioned in a first emission region of a substrate; an insulating layer covering an edge of the first pixel electrode; a first light-emitting layer on the first pixel electrode and the insulating layer; a first common electrode on the first light-emitting layer; a conductive layer arranged on the insulating layer to surround the first emission region; a first embankment on the conductive layer; a second embankment on the first embankment adjacent to the first emission region and including a tip protruding from a side of the first embankment; a groove recessed from an upper surface of the second embankment to at least a portion of the first embankment; a first organic pattern including the same material as the first light-emitting layer, wherein a portion of the first organic pattern is on the second embankment and another portion of the first organic pattern is accommodated in the groove; and a first inorganic layer covering an upper surface of the first common electrode and side surfaces of the first organic pattern arranged on the second embankment and an upper surface of the first organic pattern accommodated in the groove.

[0006] In a plan view, the groove may be spaced apart from the first emission region, with the second bank positioned between the groove and the first emission region.

[0007] The display device may further include a first electrode pattern including the same material as the first common electrode. A portion of the first electrode pattern may be on the first organic pattern on the second bank, and another portion of the first electrode pattern may be on the first organic pattern in the groove.

[0008] The display device may further include: a cover layer on the first common electrode; and a first cover pattern including the same material as the cover layer. A portion of the first cover pattern may be on the first electrode pattern on the second bank, and another portion of the first cover pattern may be on the first electrode pattern in the groove.

[0009] The first inorganic layer may cover side surfaces of the first electrode pattern disposed on the second bank, upper and side surfaces of the first capping pattern disposed on the second bank, and an upper surface of the first capping pattern in the groove.

[0010] The depth of the groove may be greater than the sum of the thickness of the first organic pattern, the thickness of the first electrode pattern, and the thickness of the first capping pattern.

[0011] The display device may further include: a second pixel electrode positioned in the second emission region of the substrate; a second light emitting layer on the second pixel electrode; and a second common electrode on the second light emitting layer.

[0012] Each of the first common electrode and the second common electrode may be in contact with a side surface of the conductive layer and an upper surface of an edge of the conductive layer.

[0013] The first common electrode and the second common electrode may be electrically connected through the conductive layer.

[0014] The display device may further include a second organic pattern, the second organic pattern and the second light emitting layer include the same material. A portion of the second organic pattern may be on the second bank, and another portion of the second organic pattern may be accommodated in the groove. The display device may further include a second electrode pattern, the second electrode pattern and the second common electrode include the same material. A portion of the second electrode pattern may be on the second organic pattern on the second bank, and another portion of the second electrode pattern may be on the second organic pattern in the groove.

[0015] The display device may further include a second inorganic layer covering an upper surface of the second common electrode, side surfaces of the second organic pattern arranged on the second bank, side surfaces of the second electrode pattern arranged on the second bank, and an upper surface of the second electrode pattern received in the groove.

[0016] The groove may penetrate from an upper surface of the second bank to a lower surface of the first bank to expose an upper surface of the conductive layer.

[0017] Another portion of the first organic pattern may be received in the groove to be directly disposed on the conductive layer.

[0018] According to one or more embodiments of the present disclosure, a display device includes: a first pixel electrode positioned in a first emission region of a substrate; an insulating layer covering an edge of the first pixel electrode; a first light-emitting layer on the first pixel electrode and the insulating layer; a first common electrode on the first light-emitting layer; a first embankment arranged on the insulating layer to surround the first emission region; a second embankment arranged on the first embankment to be adjacent to the first emission region and including a tip protruding from a side of the first embankment; a groove recessed from an upper surface of the second embankment to at least a portion of the first embankment; and a first organic pattern including the same material as the first light-emitting layer, wherein a portion of the first organic pattern is on the second embankment and another portion of the first organic pattern is accommodated in the groove.

[0019] The display device may further include a first electrode pattern, the first electrode pattern and the first common electrode including the same material. A portion of the first electrode pattern may be arranged on the first organic pattern on the second bank, and another portion of the first electrode pattern may be arranged on the first electrode pattern accommodated in the groove. The display device may further include a first inorganic layer, the first inorganic layer covering the upper surface of the first common electrode, the side surface of the first organic pattern arranged on the second bank, the side surface of the first electrode pattern arranged on the second bank, and the upper surface of the first electrode pattern accommodated in the groove.

[0020] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes the following steps: forming a first pixel electrode and a second pixel electrode on a substrate; sequentially stacking a sacrificial layer, an insulating layer, a conductive layer, a first dam and a second dam on the first pixel electrode and the second pixel electrode; forming a tip of the second dam protruding from a side of the first dam by etching the second dam, the first dam and the conductive layer; and forming a groove recessed from an upper surface of the second dam to at least a portion of the first dam; exposing the first pixel electrode and the second pixel electrode by etching the insulating layer and the sacrificial layer; and forming a first light-emitting layer on the first pixel electrode, forming a portion of a first organic pattern on the second dam, and forming another portion of the first organic pattern in the groove.

[0021] The method may also include: forming a first common electrode on the first light-emitting layer, forming a portion of the first electrode pattern on the first organic pattern on the second embankment, and forming another portion of the first electrode pattern on the first organic pattern in the groove; and forming a covering layer on the first common electrode, forming a portion of the first covering pattern on the first electrode pattern on the second embankment, and forming another portion of the first covering pattern on the first electrode pattern in the groove.

[0022] The method may also include forming a first inorganic layer, the first inorganic layer covering the upper surface of the covering layer, the side surface of the first organic pattern on the second embankment, the side surface of the first electrode pattern on the second embankment, the upper surface and side surface of the first covering pattern on the second embankment, and the upper surface of the first covering pattern in the groove.

[0023] The method may further include etching the first inorganic layer overlapping the second pixel electrode, the capping layer, the first capping pattern, the first electrode pattern, and the first organic pattern.

[0024] The method may further include forming a second light emitting layer on the second pixel electrode, forming a portion of a second organic pattern on the second bank, and forming another portion of the second organic pattern in the groove.

[0025] In a display device and a method for manufacturing the same according to one or more embodiments, a portion of an organic pattern, a portion of an electrode pattern, and a portion of a covering pattern are formed on a bank, another portion of an organic pattern, another portion of an electrode pattern, and another portion of a covering pattern are formed in a groove in the bank, and a side surface of the organic pattern, a side surface of the electrode pattern, and a side surface of the covering pattern on the bank are covered with an inorganic layer. Thus, moisture is blocked from penetrating through the organic pattern, the electrode pattern, and the covering pattern, thereby improving the reliability of the light-emitting element.

[0026] However, aspects and effects of the present disclosure are not limited to the above contents, and other aspects and effects of the present disclosure will be apparent to those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] These and / or other aspects will become apparent and more easily understood through the following description of the embodiments in conjunction with the accompanying drawings, in which: Figure 1 is a perspective view of a display device according to an embodiment; Figure 2 is a cross-sectional view of a display device according to an embodiment; Figure 3 is a plan view of a display unit of a display device according to an embodiment; Figure 4 is a cross-sectional view showing a pixel of a display device according to an embodiment; Figure 5 yes Figure 4 An enlarged view of area "A1"; Figure 6 is a cross-sectional view showing a pixel of a display device according to an embodiment; Figure 7 yes Figure 6 An enlarged view of area "A2"; Figure 8is a cross-sectional view showing a pixel of a display device according to an embodiment; Fig. 9 yes Figure 8 An enlarged view of area "A3"; Figures 10 to 17 is a cross-sectional view showing a process of manufacturing a display device according to an embodiment; Fig.18 A virtual reality device including a display device according to an embodiment is shown; Fig.19 and Fig. 20 A head mounted display including a display device according to an embodiment is shown; Fig.21 It is shown Figures 18 to 20 A cross-sectional view of a pixel according to an embodiment in a display device of FIG. 1 ; Fig. 22 It is shown Figures 18 to 20 A cross-sectional view of a pixel according to an embodiment in a display device of FIG. Fig.23 It is shown Figures 18 to 20 sectional view of a pixel according to an embodiment in a display device of FIG. DETAILED DESCRIPTION

[0028] In the following description, for the purpose of explanation, some details are set forth in order to provide a thorough understanding of the various embodiments or implementations disclosed. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of devices or methods that adopt one or more of the disclosures disclosed herein. However, it will be apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, structures and devices are shown in block diagram form to avoid unnecessary obscurity of various embodiments. In addition, various embodiments may be different, but not necessarily exclusive or limited disclosure. For example, without departing from the disclosure, the specific shape, configuration and characteristics of the embodiment may be used or implemented in other embodiments.

[0029] Unless otherwise specified, the illustrated embodiments will be understood to provide features of varying details that can be used to implement some of the disclosed methods in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (herein individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the disclosure.

[0030] The use of cross-hatching and / or shading in the drawings may generally be provided to clarify boundaries between adjacent elements. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0031] In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0032] When an element, such as a layer, is referred to as being "on," "connected to," or "bound to" another element or layer, it may be directly on, directly connected to, or directly bound to the other element or layer, or one or more intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bound to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0033] In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and thus can be interpreted in a broad sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0034] For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be understood as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, XZ, etc. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, the first element discussed below may be referred to as the second element.

[0036] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "under" may encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0037] The terms used here are for the purpose of describing specific embodiments and are not intended to be referred to as limitations. Unless the context clearly indicates otherwise, as used herein, the singular forms "one", "one (kind / person)" and "the (said)" are also intended to include plural forms. In addition, when the terms "include", "comprise" and / or its variations are used in this specification, the stated features, integral bodies, steps, operations, elements, components and / or their groups are indicated, but the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups are not excluded. In addition, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than as degree terms, and are used to explain the inherent deviations of the measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0038] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated regional shapes, but rather include shape deviations caused by, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are not necessarily intended to be limiting.

[0039] Some embodiments may be described and illustrated in the accompanying drawings in terms of functional blocks, units, components and / or modules. It will be understood by those skilled in the art that these blocks, units, components and / or modules may be physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units, components and / or modules are implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may be optionally driven by firmware and / or software. It is also contemplated that each block, unit, component and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuits) that perform other functions. In addition, without departing from the scope of the disclosure, each block, unit, component and / or module of some embodiments may be physically separated into two or more interactive and discrete blocks, units, components and / or modules. Furthermore, the blocks, units, components and / or modules of some embodiments may be physically combined into more complex blocks, units, components and / or modules without departing from the scope of the disclosure.

[0040] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and disclosure, and should not be interpreted in an ideal or overly formal sense unless explicitly so defined herein.

[0041] Here, some disclosed embodiments are described in more detail with reference to the accompanying drawings.

[0042] Figure 1 is a perspective view of a display device according to an embodiment.

[0043] Reference Figure 1 , the display device 10 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs). For example, the display device 10 can be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. For another example, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays.

[0044] In an embodiment, the display device 10 may have a planar shape such as or similar to a quadrilateral. For example, the display device 10 may have a planar shape similar to a quadrilateral having short sides in the X-axis direction and long sides in the Y-axis direction. In an embodiment, each corner where the short side extending in the X-axis direction meets the long side extending in the Y-axis direction may be rounded with a curvature (e.g., a predetermined curvature) or may have a right angle. However, the planar shape of the display device 10 is not limited to a quadrilateral shape, but may also have a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0045] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0046] The display panel 100 may include a main area MA and a sub area SBA.

[0047] The main area MA may include a display area DA and a non-display area NDA disposed around the display area DA, the display area DA including pixels displaying an image. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0048] For example, each of the self-luminous elements may include, but is not limited to, at least one of an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, and a micro light emitting diode.

[0049] The non-display area NDA may be an area outside the display area DA. In an embodiment, the non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) supplying a gate signal to a gate line and a fan-out line (not shown) connecting the display driver 200 to the display area DA.

[0050] The sub-area SBA may extend from one side of the main area MA. In an embodiment, the sub-area SBA may include a flexible material that may be bent, folded, curled, etc. For example, when the sub-area SBA is bent, it may overlap with the main area MA in the thickness direction (Z-axis direction). The sub-area SBA may include a display driver 200 and a pad (or "pad") unit connected to the circuit board 300. Alternatively, the sub-area SBA may be omitted, and the display driver 200 and the pad unit may be disposed in the non-display area NDA.

[0051] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to data lines. The display driver 200 may supply power voltages to power lines and supply gate control signals to gate drivers. The display driver 200 may be formed as an integrated circuit and mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in a sub-region SBA and may overlap with the main region MA in a thickness direction (Z-axis direction) by bending of the sub-region SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0052] In an embodiment, the circuit board 300 may be attached to the pad unit of the display panel 100 using an anisotropic conductive film. The leads of the circuit board 300 may be electrically connected to the pad unit of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0053] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit, and sense a capacitance change between the touch electrodes. For example, the touch drive signal may be a pulse signal having a certain frequency (e.g., a predetermined frequency). The touch driver 400 may determine whether an input has been made based on the capacitance change between the touch electrodes, and calculate the coordinates of the input. The touch driver 400 may be formed as an integrated circuit.

[0054] Figure 2 is a cross-sectional view of a display device according to an embodiment.

[0055] Reference Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0056] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, curled, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but the present disclosure is not limited thereto. For example, the substrate SUB may include a glass material or a metal material.

[0057] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 and the data line, and a lead connecting the display driver 200 and the pad unit. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0058] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, gate lines, data lines, and power lines of the pixels of the thin film transistor layer TFTL may be disposed in the display area DA. The gate control lines and fan-out lines of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The leads of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0059] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements and a pixel defining layer defining pixels, each light emitting element including a pixel electrode, a light emitting layer, and a common electrode stacked sequentially to emit light. The light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0060] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. In an embodiment, the light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a certain voltage (e.g., a predetermined voltage) through the thin film transistor of the thin film transistor layer TFTL and the common electrode receives a cathode voltage, holes may move to the organic light-emitting layer through the hole transport layer, and electrons may move to the organic light-emitting layer through the electron transport layer. Then, the holes and electrons may recombine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode, but the present disclosure is not limited thereto.

[0061] As another example, each of the light emitting elements may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0062] The encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer to encapsulate the light emitting element layer EML.

[0063] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for sensing the touch of a user in a capacitive manner and a touch line connecting the touch electrodes and the touch driver 400. For example, the touch sensing unit TSU may sense the touch of a user in a mutual capacitance manner or a self-capacitance manner.

[0064] As another example, the touch sensing unit TSU may be provided on a separate substrate provided on the display unit DU. In this case, the substrate supporting the touch sensing unit TSU may be an encapsulation substrate encapsulating the display unit DU.

[0065] The touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor region overlapping the display area DA. The touch lines of the touch sensing unit TSU may be disposed in a touch peripheral region overlapping the non-display area NDA.

[0066] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer CFL may absorb a portion of light from outside the display device 10, thereby reducing reflected light caused by external light. Therefore, the color filter layer CFL may prevent or substantially prevent color distortion caused by reflection of external light.

[0067] In an embodiment, the color filter layer CFL is directly disposed on the touch sensing unit TSU, so that the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0068] The sub-area SBA of the display panel 100 may extend from one side of the main area MA. The sub-area SBA may include a flexible material that may be bent, folded, curled, etc. For example, when the sub-area SBA is bent, it may overlap the main area MA in the thickness direction (Z-axis direction). The sub-area SBA may include a display driver 200 and a pad unit electrically connected to the circuit board 300.

[0069] The display device 10 may include a curved protection layer BPL protecting the sub-area SBA. The curved protection layer BPL may be disposed on the thin film transistor layer TFTL of the curved sub-area SBA. The curved protection layer BPL may protect the thin film transistor layer TFTL of the curved sub-area SBA and minimize or reduce the tensile stress of the sub-area SBA.

[0070] Figure 3 is a plan view of a display unit of a display device according to an embodiment.

[0071] Reference Figure 3 , the display unit DU may include a display area DA and a non-display area NDA.

[0072] The display area DA is an area for displaying an image, and in an embodiment, may be defined as a central area of ​​the display panel 100. The display area DA may include a plurality of pixels SP, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL. Each of the pixels SP may be defined as a minimum unit for outputting light.

[0073] The gate lines GL may supply the pixels SP with gate signals received from the gate driver 210. The gate lines GL may extend in the X-axis direction and may be spaced apart from each other in the Y-axis direction crossing the X-axis direction.

[0074] The data lines DL may supply the pixels SP with data voltages received from the display driver 200. The data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0075] The power lines VL may supply the pixels SP with a power voltage received from the display driver 200. Here, the power voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, a bias voltage, and a low potential voltage. The power lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0076] In an embodiment, the non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 210, a fan-out line FOL, and a gate control line GCL. The gate driver 210 may generate a plurality of gate signals based on the gate control signal and sequentially supply the gate signals to the gate lines GL according to a set order.

[0077] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the data line DL.

[0078] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply a gate control signal received from the display driver 200 to the gate driver 210.

[0079] The sub area SBA may include the display driver 200 , the display pad area DPA, and first and second touch pad areas TPA1 and TPA2 .

[0080] The display driver 200 may output a signal and a voltage for driving the display panel 100 to the fan-out line FOL. The display driver 200 may supply a data voltage to the data line DL through the fan-out line FOL. The data voltage may be supplied to the pixel SP and may determine the brightness of the pixel SP. The display driver 200 may supply a gate control signal to the gate driver 210 through the gate control line GCL.

[0081] The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be disposed at an edge of the sub-area SBA. The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 using a low resistance high reliability material such as an anisotropic conductive film or a self-assembled anisotropic conductive paste (SAP).

[0082] The display pad area DPA may include a plurality of display pad units DP. In an embodiment, the display pad unit DP may be electrically connected to a graphics system through a circuit board 300. The display pad unit DP may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200.

[0083] The first touch pad area TPA1 may be disposed at one side of the display pad area DPA and may include a plurality of first touch pad units TP1. The first touch pad units TP1 may be electrically connected to a touch driver 400 disposed on the circuit board 300. The first touch pad units TP1 may supply touch driving signals to a plurality of driving electrodes through a plurality of driving lines.

[0084] The second touch pad area TPA2 may be disposed at the other side of the display pad area DPA, and may include a plurality of second touch pad units TP2. The second touch pad unit TP2 may be electrically connected to a touch driver 400 disposed on the circuit board 300. The touch driver 400 may receive a touch sensing signal through a plurality of sensing lines connected to the second touch pad unit TP2, and sense a change in mutual capacitance between the driving electrode and the sensing electrode.

[0085] Figure 4 is a cross-sectional view showing a pixel of a display device according to an embodiment; Figure 5 yes Figure 4 An enlarged view of area "A1".

[0086] Reference Figure 4 and Figure 5 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0087] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, curled, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but the present disclosure is not limited thereto. As another example, the substrate SUB may include a glass material or a metal material.

[0088] In an embodiment, the thin film transistor layer TFTL may include a first buffer layer BF1, a light blocking layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0089] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer that may prevent or substantially prevent penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked.

[0090] The light blocking layers BML may be disposed on the first buffer layer BF1. For example, each of the light blocking layers BML may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. As another example, each of the light blocking layers BML may be an organic layer including a black pigment.

[0091] The second buffer layer BF2 may be disposed on the first buffer layer BF1 and the light blocking layer BML. The second buffer layer BF2 may include an inorganic layer that may prevent or substantially prevent penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic layers alternately stacked.

[0092] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of the pixel. For example, each of the thin film transistors TFT may be a driving transistor or a switching transistor of the pixel circuit. Each of the thin film transistors TFT may include a semiconductor region ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0093] The semiconductor region ACT, the source electrode SE, and the drain electrode DE may be disposed on the second buffer layer BF2. The semiconductor region ACT, the source electrode SE, and the drain electrode DE may overlap the light blocking layer BML in the thickness direction. The semiconductor region ACT may overlap the gate electrode GE in the thickness direction and may be insulated from the gate electrode GE by the gate insulating layer GI. The source electrode SE and the drain electrode DE may be formed of a conductive material of the semiconductor region ACT.

[0094] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor region ACT with the gate insulating layer GI interposed therebetween.

[0095] The gate insulating layer GI may be disposed on the semiconductor region ACT, the source electrode SE, the drain electrode DE, and the second buffer layer BF2. The gate insulating layer GI may insulate the semiconductor region ACT from the gate electrode GE.

[0096] A first interlayer insulating layer ILD1 may be disposed on the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may insulate the gate electrode GE from the capacitor electrode CPE.

[0097] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in a thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0098] The second interlayer insulating layer ILD2 may be disposed on the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may insulate the capacitor electrode CPE from the first connection electrode CNE1.

[0099] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole disposed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0100] The first passivation layer PAS1 may be disposed on the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may insulate the first connection electrode CNE1 from the second connection electrode CNE2.

[0101] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the first pixel electrode AE1 of the first light emitting element ED1. The second connection electrode CNE2 may be inserted into a contact hole disposed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0102] The second passivation layer PAS2 may be disposed on the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may insulate the second connection electrode CNE2 from the first pixel electrode AE1.

[0103] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include first, second, and third light emitting elements ED1, ED2, and ED3, a residual pattern RP, a first insulating layer IL1, an etching control layer EST, a capping layer CAP, a conductive layer MTL, a bank BNK, first, second, and third organic patterns ELP1, ELP2, and ELP3, first, second, and third electrode patterns CEP1, CEP2, and CEP3, first, second, and third capping patterns CLP1, CLP2, and CLP3, and first, second, and third inorganic layers TL1, TL2, and TL3.

[0104] The display device 10 may include a plurality of pixels arranged along a plurality of rows and a plurality of columns in the display area DA. The pixels may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 defined by a bank BNK or a pixel defining layer, respectively, and light having a peak wavelength (e.g., a predetermined peak wavelength) may be emitted through the first emission area EA1, the second emission area EA2, and the third emission area EA3. Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be an area where light generated by a light emitting element of the display device 10 is emitted to the outside of the display device 10.

[0105] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit light having a peak wavelength (e.g., a predetermined peak wavelength) to the outside of the display device 10. The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. For example, the light of the first color may be red light having a peak wavelength of about 610nm to 650nm, the light of the second color may be green light having a peak wavelength of about 510nm to 550nm, and the light of the third color may be blue light having a peak wavelength of about 440nm to 480nm. However, the present disclosure is not limited thereto.

[0106] In an embodiment, for example, the area of ​​the third emission region EA3 may be greater than the area of ​​the first emission region EA1, and the area of ​​the first emission region EA1 may be greater than the area of ​​the second emission region EA2. However, the present disclosure is not limited thereto. As another example, the area of ​​the first emission region EA1, the area of ​​the second emission region EA2, and the area of ​​the third emission region EA3 may be substantially the same.

[0107] The first light emitting element ED1 may be disposed on the thin film transistor layer TFTL in the first emission area EA1. The first light emitting element ED1 may include a first pixel electrode AE1, a first light emitting layer EL1, and a first common electrode CE1. The second light emitting element ED2 may be disposed on the thin film transistor layer TFTL in the second emission area EA2. The second light emitting element ED2 may include a second pixel electrode AE2, a second light emitting layer EL2, and a second common electrode CE2. The third light emitting element ED3 may be disposed on the thin film transistor layer TFTL in the third emission area EA3. The third light emitting element ED3 may include a third pixel electrode AE3, a third light emitting layer EL3, and a third common electrode CE3.

[0108] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed on the second passivation layer PAS2. Each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be insulated from each other by the first insulating layer IL1. For example, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and lanthanum (La). As another example, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). As another example, the first pixel electrode AE1 , the second pixel electrode AE2 , and the third pixel electrode AE3 may have a stack structure of ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0109] The residual pattern RP may be disposed on an edge of each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. Due to the residual pattern RP, the first insulating layer IL1 may not directly contact an upper surface of each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The residual pattern RP may serve as a sacrificial layer SFL (see FIG. 1 ) on each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 that is removed in a process of manufacturing the display device 10. Fig.10 ) is formed as a result.

[0110] The first insulating layer IL1 may be disposed on the second passivation layer PAS2 and the residual pattern RP. The first insulating layer IL1 may cover the edges of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 and the residual pattern RP, and may partially expose the upper surfaces of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. For example, the first insulating layer IL1 may expose the first pixel electrode AE1 in the first emission area EA1, and the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1. In an embodiment, the first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0111] The etching control layer EST may be disposed on the first insulating layer IL1. The etching control layer EST may be used as an etching stopper. The etching control layer EST may protect the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 during the process of etching the bank BNK and the conductive layer MTL. Optionally, the etching control layer EST may be omitted.

[0112] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be organic light-emitting layers made of organic materials, and may be formed on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, respectively, through a deposition process. For example, in the deposition process of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, the organic material may be deposited in a direction inclined relative to the upper surface of the substrate SUB.

[0113] The first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1 in the first emission area EA1. A portion of the first light emitting layer EL1 may fill the space around the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1 (e.g., surrounded by the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1), and another portion of the first light emitting layer EL1 may cover the side surface of the etching control layer EST, the upper surface of the edge of the etching control layer EST, and the side surface of the first insulating layer IL1. The second light emitting layer EL2 may be directly disposed on the second pixel electrode AE2 in the second emission area EA2. A portion of the second light emitting layer EL2 may fill the space around the second pixel electrode AE2, the residual pattern RP, and the first insulating layer IL1 (e.g., surrounded by the second pixel electrode AE2, the residual pattern RP, and the first insulating layer IL1), and another portion of the second light emitting layer EL2 may cover the side surface of the etching control layer EST, the upper surface of the edge of the etching control layer EST, and the side surface of the first insulating layer IL1. The third light emitting layer EL3 may be directly disposed on the third pixel electrode AE3 in the third emission area EA3. A portion of the third light-emitting layer EL3 may fill the space around (e.g., surrounded by) the third pixel electrode AE3, the residual pattern RP, and the first insulating layer IL1, and another portion of the third light-emitting layer EL3 may cover the side surface of the etching control layer EST, the upper surface of the edge of the etching control layer EST, and the side surface of the first insulating layer IL1.

[0114] The first common electrode CE1 may be disposed on the first light emitting layer EL1, the second common electrode CE2 may be disposed on the second light emitting layer EL2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may include a transparent conductive material and may transmit light generated from the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may contact the side surface of the conductive layer MTL and the upper surface of the edge of the conductive layer MTL. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be electrically connected through the conductive layer MTL. For example, the first common electrode CE1 may receive a common voltage, a cathode voltage, or a low potential voltage.

[0115] The first pixel electrode AE1 may receive a voltage corresponding to the data voltage from the thin film transistor TFT, and the first common electrode CE1 may receive a common voltage, a cathode voltage, or a low potential voltage. In this case, a potential difference is formed between the first pixel electrode AE1 and the first common electrode CE1, so that holes may move to the first light emitting layer EL1 through the hole transport layer, and electrons may move to the first light emitting layer EL1 through the electron transport layer. Therefore, the first light emitting layer EL1 may emit light.

[0116] The cover layer CAP may be disposed on the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 in the first emission area EA1, the second emission area EA2, and the third emission area EA3. In an embodiment, the cover layer CAP may include an inorganic insulating material and may cover the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3. The cover layer CAP may prevent or substantially prevent the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 from being damaged by external air. For example, the cover layer CAP may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0117] The conductive layer MTL may be disposed on the etching control layer EST and may overlap the bank BNK. In an embodiment, the conductive layer MTL may surround the first emission area EA1, the second emission area EA2, and the third emission area EA3 in a plan view. In an embodiment, the conductive layer MTL may include a metal material having high conductivity. For example, the conductive layer MTL may include, but is not limited to, aluminum (Al). Therefore, the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be electrically connected through the conductive layer MTL.

[0118] The bank BNK may be disposed on the conductive layer MTL to define the first, second, and third emission regions EA1, EA2, and EA3. In an embodiment, the bank BNK may surround the first, second, and third emission regions EA1, EA2, and EA3 in a plan view. In an embodiment, the bank BNK may include a first bank BNK1 and a second bank BNK2.

[0119] The first bank BNK1 may be disposed on the conductive layer MTL, and the second bank BNK2 may be disposed on the first bank BNK1. A side surface of the first bank BNK1 may be recessed inward from a side surface of the second bank BNK2. Since a side surface of the second bank BNK2 protrudes from a side surface of the first bank BNK1 toward the first emission area EA1, the second bank BNK2 may include a protruding tip. Therefore, an undercut structure may be formed under each tip of the second bank BNK2. In an embodiment, the thickness of the first bank BNK1 may be greater than the thickness of the second bank BNK2.

[0120] In an embodiment, the first bank BNK1 and the second bank BNK2 may include different metal materials. The etching rate of the first bank BNK1 and the etching rate of the second bank BNK2 may be different from each other. For example, in a wet etching process, the etching rate of the first bank BNK1 may be greater than the etching rate of the second bank BNK2, and in the process of forming the first emission area EA1, the second emission area EA2, and the third emission area EA3, the first bank BNK1 may be etched more than the second bank BNK2. Therefore, the side shapes of the first bank BNK1 and the second bank BNK2 may be determined by the difference in etching rate between the first bank BNK1 and the second bank BNK2. The first bank BNK1 may include a metal material having high conductivity, and the second bank BNK2 may include a material having low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second bank BNK2 may include titanium (Ti). However, the present disclosure is not limited thereto.

[0121] The first bank BNK1 and the second bank BNK2 may include a groove GRV recessed from the upper surface of the bank BNK. The groove GRV may penetrate from the second bank BNK2 to a portion of the first bank BNK1. In a plan view, the groove GRV may be spaced apart from the first emission area EA1, the second emission area EA2, and the third emission area EA3, and the second bank BNK2 is between the groove GRV and the first emission area EA1, the second emission area EA2, and the third emission area EA3. The groove GRV may accommodate the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, and the first covering pattern CLP1, the second covering pattern CLP2, and the third covering pattern CLP3. For example, the depth of the groove GRV may be greater than the sum of the thickness of the first organic pattern ELP1, the thickness of the first electrode pattern CEP1, and the thickness of the first covering pattern CLP1, but is not limited thereto.

[0122] The embankment BNK may form the first emission area EA1, the second emission area EA2, and the third emission area EA3 through a mask process, and the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be formed in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. When the mask process is performed, a structure for supporting the mask may be required, and an excessively wide non-display area NDA may be required to control the dispersion of the mask process. Therefore, if the mask process is minimized, the structure for supporting the mask may be omitted, and the area of ​​the non-display area NDA for dispersion control may be minimized or reduced.

[0123] In an embodiment, the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may be formed by a deposition and etching process instead of a mask process. In an embodiment, the first bank BNK1 and the second bank BNK2 may include different metal materials, and each inner wall of the bank BNK may have a tip structure. In the display device 10, different layers may be formed separately in the first emission area EA1, the second emission area EA2, and the third emission area EA3 by a deposition process. For example, the first light emitting layer EL1 and the first organic pattern ELP1 may be deposited using the same organic material in a deposition process without a mask, and may be cut and separated by a tip formed on the inner wall of the bank BNK. The first light emitting layer EL1 may be disposed in the first emission area EA1, and the first organic pattern ELP1 may be disposed on the bank BNK adjacent to the first emission area EA1.

[0124] In an embodiment, an organic material for forming the first light emitting layer EL1 may be deposited on the entire surface of the display device 10, and the organic material of the first light emitting layer EL1 deposited in the second emission area EA2 and the third emission area EA3 may be removed. In an embodiment, an organic material for forming the second light emitting layer EL2 may be deposited on the entire surface of the display device 10, and the organic material of the second light emitting layer EL2 deposited in the first emission area EA1 and the third emission area EA3 may be removed. In an embodiment, an organic material for forming the third light emitting layer EL3 may be deposited on the entire surface of the display device 10, and the organic material of the third light emitting layer EL3 deposited in the first emission area EA1 and the second emission area EA2 may be removed. Therefore, in the display device 10, different organic materials may be formed in the first emission area EA1, the second emission area EA2, and the third emission area EA3 by deposition and etching processes without using a mask process. The display device 10 can reduce manufacturing costs by omitting unnecessary processes, and can minimize or reduce the area of ​​the non-display area NDA.

[0125] In an embodiment, the first organic pattern ELP1 may include the same organic material as the first light emitting layer EL1. A portion of the first organic pattern ELP1 may be disposed on the second bank BNK2 adjacent to the first emission region EA1, and another portion of the first organic pattern ELP1 may be accommodated in the groove GRV. In an embodiment, the first light emitting layer EL1 and the first organic pattern ELP1 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the first organic pattern ELP1 may be disposed on the second bank BNK2 in an area adjacent to the first emission region EA1.

[0126] In an embodiment, the first electrode pattern CEP1 may include the same metal material as the first common electrode CE1 and may be disposed on the first organic pattern ELP1. A portion of the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 on the second bank BNK2, and another portion of the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in the groove GRV. In an embodiment, the first common electrode CE1 and the first electrode pattern CEP1 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in an area adjacent to the first emission area EA1.

[0127] In an embodiment, the first capping pattern CLP1 may include the same inorganic material as the capping layer CAP and may be disposed on the first electrode pattern CEP1. A portion of the first capping pattern CLP1 may be disposed on the first electrode pattern CEP1 on the second bank BNK2, and another portion of the first capping pattern CLP1 may be disposed on the first electrode pattern CEP1 in the groove GRV. In an embodiment, the capping layer CAP and the first capping pattern CLP1 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the first capping pattern CLP1 may be disposed on the first electrode pattern CEP1 in an area adjacent to the first emission area EA1.

[0128] The first inorganic layer TL1 may be disposed on the first capping pattern CLP1 and the capping layer CAP of the first emission area EA1. The first inorganic layer TL1 may cover the upper surface of the capping layer CAP in the first emission area EA1. The first inorganic layer TL1 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the first organic pattern ELP1 disposed on the second bank BNK2, the side surface of the first electrode pattern CEP1, and the upper surface and the side surface of the first capping pattern CLP1. The first inorganic layer TL1 may cover the upper surface of the first capping pattern CLP1 in the groove GRV. The first inorganic layer TL1 may include an inorganic material to prevent or substantially prevent oxygen or moisture from penetrating into the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. For example, the first inorganic layer TL1 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0129] The display device 10 may accommodate a portion of the first organic pattern ELP1, a portion of the first electrode pattern CEP1, and a portion of the first covering pattern CLP1 by including a groove GRV, and the first inorganic layer TL1 may cover the side surface of the first organic pattern ELP1 disposed on the second bank BNK2, the side surface of the first electrode pattern CEP1, and the side surface of the first covering pattern CLP1. The first inorganic layer TL1 may not cover the side surface of the first organic pattern ELP1, the side surface of the first electrode pattern CEP1, and the side surface of the first covering pattern CLP1 accommodated in the groove GRV, but may block moisture from penetrating through the first organic pattern ELP1, the first electrode pattern CEP1, and the first covering pattern CLP1 accommodated in the groove GRV through the groove GRV, and may not affect the first light emitting element ED1. Therefore, the display device 10 may block the moisture penetration path through the first organic pattern ELP1, the first electrode pattern CEP1, and the first covering pattern CLP1, and may improve the reliability of the first light emitting element ED1.

[0130] In an embodiment, the second organic pattern ELP2 may include the same organic material as the second light emitting layer EL2. A portion of the second organic pattern ELP2 may be disposed on the second bank BNK2 adjacent to the second emission area EA2, and another portion of the second organic pattern ELP2 may be accommodated in the groove GRV. In an embodiment, the second light emitting layer EL2 and the second organic pattern ELP2 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the second organic pattern ELP2 may be disposed on the second bank BNK2 in an area adjacent to the second emission area EA2.

[0131] In an embodiment, the second electrode pattern CEP2 may include the same metal material as the second common electrode CE2 and may be disposed on the second organic pattern ELP2. A portion of the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 on the second bank BNK2, and another portion of the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 in the groove GRV. In an embodiment, the second common electrode CE2 and the second electrode pattern CEP2 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 in an area adjacent to the second emission area EA2.

[0132] In an embodiment, the second cover pattern CLP2 may include the same inorganic material as the cover layer CAP and may be disposed on the second electrode pattern CEP2. A portion of the second cover pattern CLP2 may be disposed on the second electrode pattern CEP2 on the second bank BNK2, and another portion of the second cover pattern CLP2 may be disposed on the second electrode pattern CEP2 in the groove GRV. In an embodiment, the cover layer CAP and the second cover pattern CLP2 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the second cover pattern CLP2 may be disposed on the second electrode pattern CEP2 in an area adjacent to the second emission area EA2.

[0133] The second inorganic layer TL2 may be disposed on the second capping pattern CLP2 and the capping layer CAP of the second emission area EA2. The second inorganic layer TL2 may cover the upper surface of the capping layer CAP in the second emission area EA2. The second inorganic layer TL2 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the second organic pattern ELP2 disposed on the second bank BNK2, the side surface of the second electrode pattern CEP2, and the upper surface and the side surface of the second capping pattern CLP2. The second inorganic layer TL2 may cover the upper surface of the second capping pattern CLP2 in the groove GRV. The second inorganic layer TL2 may include an inorganic material to prevent or substantially prevent oxygen or moisture from penetrating into the second light emitting element ED2. The second inorganic layer TL2 may be an inorganic encapsulation layer. For example, the second inorganic layer TL2 may be made of at least one of the materials described as examples with respect to the first inorganic layer TL1.

[0134] The display device 10 may accommodate a portion of the second organic pattern ELP2, a portion of the second electrode pattern CEP2, and a portion of the second covering pattern CLP2 by including a groove GRV, and the second inorganic layer TL2 may cover the side surface of the second organic pattern ELP2 disposed on the second embankment BNK2, the side surface of the second electrode pattern CEP2, and the side surface of the second covering pattern CLP2. The second inorganic layer TL2 may not cover the side surface of the second organic pattern ELP2, the side surface of the second electrode pattern CEP2, and the side surface of the second covering pattern CLP2 accommodated in the groove GRV, but may block moisture from penetrating through the second organic pattern ELP2, the second electrode pattern CEP2, and the second covering pattern CLP2 accommodated in the groove GRV through the groove GRV, and may not affect the second light-emitting element ED2. Therefore, the display device 10 may block the moisture penetration path through the second organic pattern ELP2, the second electrode pattern CEP2, and the second covering pattern CLP2, and may improve the reliability of the second light-emitting element ED2.

[0135] In an embodiment, the third organic pattern ELP3 may include the same organic material as the third light emitting layer EL3. A portion of the third organic pattern ELP3 may be disposed on the second bank BNK2 adjacent to the third emission area EA3, and another portion of the third organic pattern ELP3 may be accommodated in the groove GRV. In an embodiment, the third light emitting layer EL3 and the third organic pattern ELP3 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the third organic pattern ELP3 may be disposed on the second bank BNK2 in an area adjacent to the third emission area EA3.

[0136] In an embodiment, the third electrode pattern CEP3 may include the same metal material as the third common electrode CE3 and may be disposed on the third organic pattern ELP3. A portion of the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 on the second bank BNK2, and another portion of the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 in the groove GRV. In an embodiment, the third common electrode CE3 and the third electrode pattern CEP3 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 in an area adjacent to the third emission area EA3.

[0137] In an embodiment, the third cover pattern CLP3 may include the same inorganic material as the cover layer CAP and may be disposed on the third electrode pattern CEP3. A portion of the third cover pattern CLP3 may be disposed on the third electrode pattern CEP3 on the second bank BNK2, and another portion of the third cover pattern CLP3 may be disposed on the third electrode pattern CEP3 in the groove GRV. In an embodiment, the cover layer CAP and the third cover pattern CLP3 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the third cover pattern CLP3 may be disposed on the third electrode pattern CEP3 in an area adjacent to the third emission area EA3.

[0138] The third inorganic layer TL3 may be disposed on the third capping pattern CLP3 and the capping layer CAP of the third emission area EA3. The third inorganic layer TL3 may cover the upper surface of the capping layer CAP in the third emission area EA3. The third inorganic layer TL3 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third organic pattern ELP3 disposed on the second bank BNK2, the side surface of the third electrode pattern CEP3, and the upper surface and the side surface of the third capping pattern CLP3. The third inorganic layer TL3 may cover the upper surface of the third capping pattern CLP3 in the groove GRV. The third inorganic layer TL3 may include an inorganic material to prevent or substantially prevent oxygen or moisture from penetrating into the third light emitting element ED3. The third inorganic layer TL3 may be an inorganic encapsulation layer. For example, the third inorganic layer TL3 may be made of at least one of the materials described as examples of the first inorganic layer TL1.

[0139] The display device 10 may accommodate a portion of the third organic pattern ELP3, a portion of the third electrode pattern CEP3, and a portion of the third covering pattern CLP3 by including a groove GRV, and the third inorganic layer TL3 may cover the side surface of the third organic pattern ELP3 disposed on the second embankment BNK2, the side surface of the third electrode pattern CEP3, and the side surface of the third covering pattern CLP3. The third inorganic layer TL3 may not cover the side surfaces of the third organic pattern ELP3, the third electrode pattern CEP3, and the third covering pattern CLP3 accommodated in the groove GRV, but may block moisture from penetrating through the third organic pattern ELP3, the third electrode pattern CEP3, and the third covering pattern CLP3 accommodated in the groove GRV through the groove GRV, and may not affect the third light emitting element ED3. Therefore, the display device 10 may block the moisture penetration path through the third organic pattern ELP3, the third electrode pattern CEP3, and the third covering pattern CLP3, and may improve the reliability of the third light emitting element ED3.

[0140] The encapsulation layer TFEL may be disposed on the first to third inorganic layers TL1 , TL2 , and TL3 to cover the light emitting element layer EML. The encapsulation layer TFEL may include first to third encapsulation layers TFE1 to TFE3.

[0141] The first encapsulation layer TFE1 may be disposed on the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3. The first encapsulation layer TFE1 may include an inorganic material to prevent or substantially prevent oxygen or moisture from penetrating into the light emitting element layer EML. For example, the first encapsulation layer TFE1 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0142] The second encapsulation layer TFE2 may be disposed on the first encapsulation layer TFE1 to flatten the top of the light emitting element layer EML. The second encapsulation layer TFE2 may include an organic material to protect the light emitting element layer EML from foreign matter such as dust. For example, the second encapsulation layer TFE2 may include an organic material such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The second encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0143] The third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2. The third encapsulation layer TFE3 may include an inorganic material to prevent or substantially prevent oxygen or moisture from penetrating into the light emitting element layer EML. For example, the third encapsulation layer TFE3 may be made of at least one of the materials described as an example of the first encapsulation layer TFE1.

[0144] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a third buffer layer BF3, a bridge electrode BRG, a second insulating layer IL2, a touch electrode TE, and a third insulating layer IL3.

[0145] The third buffer layer BF3 may be disposed on the encapsulation layer TFEL. The third buffer layer BF3 may have an insulating function and an optical function. The third buffer layer BF3 may include at least one inorganic layer. Optionally, the third buffer layer BF3 may be omitted.

[0146] The bridge electrode BRG may be disposed on the third buffer layer BF3. The bridge electrode BRG may be disposed at a different layer from the touch electrode TE, and may electrically connect adjacent touch electrodes TE.

[0147] The second insulating layer IL2 may be disposed on the bridge electrode BRG and the third buffer layer BF3. The second insulating layer IL2 may have an insulating function and an optical function. For example, the second insulating layer IL2 may include but is not limited to at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0148] The touch electrode TE may be disposed on the second insulating layer IL2. The touch electrode TE may include a driving electrode and a sensing electrode, and may sense changes in mutual capacitance between the driving electrode and the sensing electrode. In an embodiment, the touch electrode TE may not overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3. Each of the touch electrodes TE may be a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and indium tin oxide (ITO / APC / ITO).

[0149] The third insulating layer IL3 may be disposed on the touch electrode TE and the second insulating layer IL2. The third insulating layer IL3 may have an insulating function and an optical function. The third insulating layer IL3 may be made of at least one of the materials described as examples of the second insulating layer IL2.

[0150] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a light blocking member BM, first, second, and third color filters CF1, CF2, and CF3, and a planarization layer OC.

[0151] The light blocking member BM may be disposed on the third insulating layer IL3 around the first optical region OPT1, the second optical region OPT2, and the third optical region OPT3 (for example, may be disposed on the third insulating layer IL3 to surround the first optical region OPT1 to the third optical region OPT3). The light blocking member BM may overlap the touch electrode TE. The light blocking member BM may include a light absorbing material to prevent or substantially prevent reflection of light. For example, the light blocking member BM may include an inorganic black pigment, an organic black pigment, or an organic blue pigment. The inorganic black pigment may be carbon black or a metal oxide such as titanium black, the organic black pigment may include at least one of lactam black, perylene black, and aniline black, and the organic blue pigment may be CI pigment blue. However, the present disclosure is not limited thereto. The light blocking member BM may prevent or substantially prevent color mixing by preventing or substantially preventing visible light from intruding between the first emission region EA1, the second emission region EA2, and the third emission region EA3, thereby improving the color gamut of the display device 10.

[0152] The first, second, and third color filters CF1, CF2, and CF3 may be disposed on the third insulating layer IL3 to correspond to the first, second, and third emission regions EA1, EA2, and EA3, respectively.

[0153] The first color filter CF1 may be disposed on the third insulating layer IL3 in the first emission area EA1. In an embodiment, in a plan view, the first color filter CF1 may be surrounded by the light blocking member BM. The edge of the first color filter CF1 may partially cover the upper surface of the light blocking member BM, but the present disclosure is not limited thereto. The first color filter CF1 may selectively transmit light of a first color (e.g., red light) and block or absorb light of a second color (e.g., green light) and light of a third color (e.g., blue light). For example, the first color filter CF1 may be a red color filter and may include a red colorant.

[0154] The second color filter CF2 may be disposed on the third insulating layer IL3 in the second emission area EA2. In an embodiment, in a plan view, the second color filter CF2 may be surrounded by the light blocking member BM. The edge of the second color filter CF2 may partially cover the upper surface of the light blocking member BM, but the present disclosure is not limited thereto. The second color filter CF2 may selectively transmit light of a second color (e.g., green light) and block or absorb light of a first color (e.g., red light) and light of a third color (e.g., blue light). For example, the second color filter CF2 may be a green color filter and may include a green colorant.

[0155] The third color filter CF3 may be disposed on the third insulating layer IL3 in the third emission area EA3. In an embodiment, in a plan view, the third color filter CF3 may be surrounded by the light blocking member BM. The edge of the third color filter CF3 may partially cover the upper surface of the light blocking member BM, but the present disclosure is not limited thereto. The third color filter CF3 may selectively transmit light of a third color (e.g., blue light) and block or absorb light of a first color (e.g., red light) and light of a second color (e.g., green light). For example, the third color filter CF3 may be a blue color filter and may include a blue colorant.

[0156] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can absorb a portion of light from outside the display device 10, thereby reducing reflected light caused by the external light. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent or substantially prevent color distortion caused by reflection of external light.

[0157] A planarization layer OC may be disposed on the light blocking member BM and the first, second, and third color filters CF1, CF2, and CF3. The planarization layer OC may planarize the top of the color filter layer CFL. For example, the planarization layer OC may include an organic insulating material.

[0158] Figure 6 is a cross-sectional view showing a pixel of a display device according to an embodiment; and Figure 7 yes Figure 6 Magnified view of area "A2". Figure 6 and Figure 7 The display device 10 and Figure 4 and Figure 5 The display device 10 of FIG. 1 is different in that the configuration of the groove GRV is different. The same elements as those described above may be briefly described or may not be described.

[0159] Reference Figure 6 and Figure 7 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0160] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include first, second, and third light emitting elements ED1, ED2, and ED3, a residual pattern RP, a first insulating layer IL1, an etching control layer EST, a capping layer CAP, a conductive layer MTL, a bank BNK, first, second, and third organic patterns ELP1, ELP2, and ELP3, first, second, and third electrode patterns CEP1, CEP2, and CEP3, first, second, and third capping patterns CLP1, CLP2, and CLP3, and first, second, and third inorganic layers TL1, TL2, and TL3.

[0161] The conductive layer MTL may be disposed on the first insulating layer IL1 and may overlap the bank BNK. In an embodiment, the conductive layer MTL may surround the first emission area EA1, the second emission area EA2, and the third emission area EA3 in a plan view. In an embodiment, the conductive layer MTL may include a metal material having high conductivity. For example, the conductive layer MTL may include aluminum (Al), but is not limited thereto. Therefore, the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be electrically connected through the conductive layer MTL.

[0162] The bank BNK may be disposed on the conductive layer MTL to define the first, second, and third emission regions EA1, EA2, and EA3. In an embodiment, the bank BNK may surround the first, second, and third emission regions EA1, EA2, and EA3 in a plan view. The bank BNK may include a first bank BNK1 and a second bank BNK2.

[0163] The first bank BNK1 and the second bank BNK2 may include a groove GRV recessed from the upper surface of the bank BNK. The groove GRV may penetrate from the upper surface of the second bank BNK2 to the lower surface of the first bank BNK1 to expose the upper surface of the conductive layer MTL. In a plan view, the groove GRV may be spaced apart from the first emission area EA1, the second emission area EA2, and the third emission area EA3, and the second bank BNK2 is between the groove GRV and the first emission area EA1, the second emission area EA2, and the third emission area EA3. The groove GRV may accommodate the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, and the first covering pattern CLP1, the second covering pattern CLP2, and the third covering pattern CLP3. For example, the depth of the groove GRV may be greater than the sum of the thickness of the first organic pattern ELP1, the thickness of the first electrode pattern CEP1, and the thickness of the first covering pattern CLP1, but is not limited thereto.

[0164] In an embodiment, the first organic pattern ELP1 may include the same organic material as the first light emitting layer EL1. A portion of the first organic pattern ELP1 may be disposed on the second bank BNK2 adjacent to the first emission region EA1, and another portion of the first organic pattern ELP1 may be accommodated in the groove GRV to be directly disposed on the conductive layer MTL. In an embodiment, the first light emitting layer EL1 and the first organic pattern ELP1 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the first organic pattern ELP1 may be disposed on the second bank BNK2 in an area adjacent to the first emission region EA1.

[0165] The display device 10 may accommodate a portion of the first organic pattern ELP1, a portion of the first electrode pattern CEP1, and a portion of the first cover pattern CLP1 by including a groove GRV, and the first inorganic layer TL1 may cover the side surface of the first organic pattern ELP1 disposed on the second bank BNK2, the side surface of the first electrode pattern CEP1, and the side surface of the first cover pattern CLP1. In an embodiment, the first inorganic layer TL1 may not cover the side surface of the first organic pattern ELP1, the side surface of the first electrode pattern CEP1, and the side surface of the first cover pattern CLP1 accommodated in the groove GRV, but may block moisture from penetrating through the first organic pattern ELP1, the first electrode pattern CEP1, and the first cover pattern CLP1 accommodated in the groove GRV through the groove GRV, and may not affect the first light emitting element ED1. Therefore, the display device 10 may block the moisture penetration path through the first organic pattern ELP1, the first electrode pattern CEP1, and the first cover pattern CLP1, and may improve the reliability of the first light emitting element ED1.

[0166] In an embodiment, the second organic pattern ELP2 may include the same organic material as the second light emitting layer EL2. A portion of the second organic pattern ELP2 may be disposed on the second bank BNK2 adjacent to the second emission area EA2, and another portion of the second organic pattern ELP2 may be accommodated in the groove GRV and may be directly disposed on the conductive layer MTL. In an embodiment, the second light emitting layer EL2 and the second organic pattern ELP2 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the second organic pattern ELP2 may be disposed on the second bank BNK2 in an area adjacent to the second emission area EA2.

[0167] The display device 10 may accommodate a portion of the second organic pattern ELP2, a portion of the second electrode pattern CEP2, and a portion of the second covering pattern CLP2 by including a groove GRV, and the second inorganic layer TL2 may cover the side surface of the second organic pattern ELP2 disposed on the second bank BNK2, the side surface of the second electrode pattern CEP2, and the side surface of the second covering pattern CLP2. In an embodiment, the second inorganic layer TL2 may not cover the side surface of the second organic pattern ELP2, the side surface of the second electrode pattern CEP2, and the side surface of the second covering pattern CLP2 accommodated in the groove GRV, but may block moisture from penetrating through the second organic pattern ELP2, the second electrode pattern CEP2, and the second covering pattern CLP2 accommodated in the groove GRV through the groove GRV, and may not affect the second light emitting element ED2. Therefore, the display device 10 may block the moisture penetration path through the second organic pattern ELP2, the second electrode pattern CEP2, and the second covering pattern CLP2, and may improve the reliability of the second light emitting element ED2.

[0168] In an embodiment, the third organic pattern ELP3 may include the same organic material as the third light emitting layer EL3. A portion of the third organic pattern ELP3 may be disposed on the second bank BNK2 adjacent to the third emission area EA3, and another portion of the third organic pattern ELP3 may be accommodated in the groove GRV and may be directly disposed on the conductive layer MTL. In an embodiment, the third light emitting layer EL3 and the third organic pattern ELP3 may be deposited in the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the third organic pattern ELP3 may be disposed on the second bank BNK2 in an area adjacent to the third emission area EA3.

[0169] The display device 10 may accommodate a portion of the third organic pattern ELP3, a portion of the third electrode pattern CEP3, and a portion of the third covering pattern CLP3 by including a groove GRV, and the third inorganic layer TL3 may cover the side surface of the third organic pattern ELP3 disposed on the second bank BNK2, the side surface of the third electrode pattern CEP3, and the side surface of the third covering pattern CLP3. In an embodiment, the third inorganic layer TL3 may not cover the side surface of the third organic pattern ELP3, the side surface of the third electrode pattern CEP3, and the side surface of the third covering pattern CLP3 accommodated in the groove GRV, but may block moisture from penetrating through the third organic pattern ELP3, the third electrode pattern CEP3, and the third covering pattern CLP3 accommodated in the groove GRV through the groove GRV, and may not affect the third light emitting element ED3. Therefore, the display device 10 may block the moisture penetration path through the third organic pattern ELP3, the third electrode pattern CEP3, and the third covering pattern CLP3, and may improve the reliability of the third light emitting element ED3.

[0170] Figure 8 is a cross-sectional view showing a pixel of a display device according to an embodiment; and Fig. 9 yes Figure 8 An enlarged view of area "A3" is shown in FIG. Figure 8 and Fig. 9 The display device 10 is a display device in which the conductive layer MTL is omitted. Figure 4 and Figure 5 The same elements as those described above may be briefly described or may not be described.

[0171] Reference Figure 8 and Fig. 9 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0172] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include first, second, and third light emitting elements ED1, ED2, and ED3, a residual pattern RP, a first insulating layer IL1, an etching control layer EST, a capping layer CAP, a bank BNK, first, second, and third organic patterns ELP1, ELP2, and ELP3, first, second, and third electrode patterns CEP1, CEP2, and CEP3, first, second, and third capping patterns CLP1, CLP2, and CLP3, and first, second, and third inorganic layers TL1, TL2, and TL3.

[0173] The bank BNK may be disposed on the etching control layer EST to define the first, second, and third emission regions EA1, EA2, and EA3. In an embodiment, the bank BNK may surround the first, second, and third emission regions EA1, EA2, and EA3 in a plan view. The bank BNK may include a first bank BNK1 and a second bank BNK2.

[0174] The first bank BNK1 may be disposed on the etching control layer EST, and the second bank BNK2 may be disposed on the first bank BNK1. A side surface of the first bank BNK1 may be recessed inward from a side surface of the second bank BNK2. In an embodiment, a side surface of the second bank BNK2 may protrude from a side surface of the first bank BNK1 toward the first emission region EA1, and the second bank BNK2 may include a protruding tip. Therefore, an undercut structure may be formed under each tip of the second bank BNK2. The thickness of the first bank BNK1 may be greater than the thickness of the second bank BNK2.

[0175] The first bank BNK1 and the second bank BNK2 may include a groove GRV recessed from the upper surface of the bank BNK. The groove GRV may penetrate from the second bank BNK2 to a portion of the first bank BNK1. In a plan view, the groove GRV may be spaced apart from the first emission area EA1, the second emission area EA2, and the third emission area EA3, and the second bank BNK2 is between the groove GRV and the first emission area EA1, the second emission area EA2, and the third emission area EA3. The groove GRV may accommodate the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, and the first covering pattern CLP1, the second covering pattern CLP2, and the third covering pattern CLP3. For example, the depth of the groove GRV may be greater than the sum of the thickness of the first organic pattern ELP1, the thickness of the first electrode pattern CEP1, and the thickness of the first covering pattern CLP1, but is not limited thereto.

[0176] The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may contact the side surface of the first bank BNK1 and may be electrically connected to each other through the first bank BNK1. For example, the first common electrode CE1 may receive a common voltage, a cathode voltage, or a low potential voltage.

[0177] Figures 10 to 17 is a cross-sectional view illustrating a process of manufacturing a display device according to an embodiment.

[0178] exist Fig.10In the embodiment, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other on the thin film transistor layer TFTL. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and lanthanum (La). For another example, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). As another example, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may have a stacked structure of ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0179] A sacrificial layer SFL may be disposed on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The sacrificial layer SFL may be disposed between the upper surfaces of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 and the first insulating layer IL1. In an embodiment, the sacrificial layer SFL may include an oxide semiconductor. For example, the sacrificial layer SFL may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium zinc oxide (IZO).

[0180] A first insulating layer IL1 may be disposed on the thin film transistor layer TFTL and the sacrificial layer SFL. The first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include but is not limited to at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0181] An etching control layer EST may be disposed on the first insulating layer IL1. The etching control layer EST may be used as an etching stopper. Alternatively, the etching control layer EST may be omitted.

[0182] A conductive layer MTL may be disposed on the etching control layer EST. In an embodiment, the conductive layer MTL may include a metal material having high conductivity. For example, the conductive layer MTL may include, but is not limited to, aluminum (Al).

[0183] A first bank BNK1 may be disposed on the conductive layer MTL, and a second bank BNK2 may be disposed on the first bank BNK1. The thickness of the first bank BNK1 may be greater than the thickness of the second bank BNK2. In an embodiment, the first bank BNK1 may include a metal material having high conductivity, and the second bank BNK2 may include a material having low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second bank BNK2 may include titanium (Ti). However, the present disclosure is not limited thereto.

[0184] exist Fig.11 In the embodiment, the second bank BNK2, the first bank BNK1 and the conductive layer MTL may be sequentially etched to form a plurality of holes. The hole may overlap with the first emission area EA1, the second emission area EA2 and the third emission area EA3. The conductive layer MTL and the first bank BNK1 and the second bank BNK2 may be etched by performing at least one of a dry etching process and a wet etching process. In the process of etching the bank BNK and the conductive layer MTL, the etching control layer EST may protect the first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3. The first bank BNK1 and the second bank BNK2 may include different metal materials, and the etching rates of the first bank BNK1 and the second bank BNK2 may be different from each other. The etching rate of the first bank BNK1 may be higher than the etching rate of the second bank BNK2, and the first bank BNK1 may be etched more than the second bank BNK2. Therefore, the side shapes of the first bank BNK1 and the second bank BNK2 may be determined by the difference in etching rates between the first bank BNK1 and the second bank BNK2. The second bank BNK2 may include a tip protruding from the first bank BNK1 toward the hole. A side surface of the first bank BNK1 may be recessed inward from a side surface of the second bank BNK2. An undercut structure may be formed under each tip of the second bank BNK2. A thickness of the first bank BNK1 may be greater than a thickness of the second bank BNK2.

[0185] For example, the upper surface of the bank BNK may be recessed to form the groove GRV. The groove GRV may penetrate from the second bank BNK2 to a portion of the first bank BNK1. In a plan view, the groove GRV may be spaced apart from the first, second, and third emission regions EA1, EA2, and EA3, and the second bank BNK2 is between the groove GRV and the first, second, and third emission regions EA1, EA2, and EA3.

[0186] As another example, the groove GRV may penetrate from the upper surface of the second bank BNK2 to the lower surface of the first bank BNK1 to expose the upper surface of the conductive layer MTL.

[0187] The etching control layer EST, the first insulating layer IL1, and the sacrificial layer SFL may be etched by performing at least one of a dry etching process and a wet etching process. Since the etching control layer EST, the first insulating layer IL1, and the sacrificial layer SFL are etched, at least a portion of the upper surface of each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be exposed. In a plan view, the sacrificial layer SFL may be etched more than the first insulating layer IL1. When the sacrificial layer SFL is etched, the residual pattern RP may remain between the first insulating layer IL1 and the first pixel electrode AE1. Therefore, the side surface of the residual pattern RP may be recessed inward from the side surface of the first insulating layer IL1.

[0188] exist Fig.12 In the embodiment, the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1 in the first emission area EA1. A portion of the first light emitting layer EL1 may fill a space surrounded by the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1, and another portion of the first light emitting layer EL1 may cover a side surface of the etching control layer EST, an upper surface of an edge of the etching control layer EST, and a side surface of the first insulating layer IL1.

[0189] In an embodiment, an organic material for forming the first light emitting layer EL1 and the first organic pattern ELP1 may be deposited on the entire surface of the display device 10. In an embodiment, the first light emitting layer EL1 and the first organic pattern ELP1 may be deposited in the same process, and the first light emitting layer EL1 and the first organic pattern ELP1 may be cut and separated by the tip of the second bank BNK2. A portion of the first organic pattern ELP1 may be disposed on the second bank BNK2 adjacent to the first emission area EA1, and another portion of the first organic pattern ELP1 may be accommodated in the groove GRV. The first organic pattern ELP1 may be directly disposed on the second pixel electrode AE2 in the second emission area EA2, and may be directly disposed on the third pixel electrode AE3 in the third emission area EA3.

[0190] The first common electrode CE1 may be directly disposed on the first light emitting layer EL1 in the first emission region EA1. The first common electrode CE1 may contact the side surface of the conductive layer MTL and the upper surface of the edge of the conductive layer MTL. The first common electrode CE1 may include a transparent conductive material and may transmit light generated from the first light emitting layer EL1. Therefore, the first light emitting element ED1 may be disposed in a hole formed by the bank BNK and may emit light through the first emission region EA1.

[0191] In an embodiment, a metal material for forming the first common electrode CE1 and the first electrode pattern CEP1 may be deposited on the entire surface of the display device 10. A portion of the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 on the second bank BNK2, and another portion of the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in the groove GRV. In an embodiment, the first common electrode CE1 and the first electrode pattern CEP1 may be deposited in the same process, and the first common electrode CE1 and the first electrode pattern CEP1 may be cut and separated by the tip of the second bank BNK2. The first electrode pattern CEP1 may be directly disposed on the first organic pattern ELP1 in each of the second emission area EA2 and the third emission area EA3. Therefore, the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in an area other than the first emission area EA1.

[0192] A capping layer CAP may be disposed on the first common electrode CE1 in the first emission area EA1. The capping layer CAP may include an inorganic insulating material and may cover the first light emitting element ED1. The capping layer CAP may prevent or substantially prevent the first light emitting element ED1 from being damaged by external air. For example, the capping layer CAP may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0193] In an embodiment, an inorganic material for forming a capping layer CAP and a first capping pattern CLP1 may be deposited on the entire surface of the display device 10. A portion of the first capping pattern CLP1 may be disposed on the first electrode pattern CEP1 on the second bank BNK2, and another portion of the first capping pattern CLP1 may be disposed on the first electrode pattern CEP1 in the groove GRV. In an embodiment, the capping layer CAP and the first capping pattern CLP1 may be deposited in the same process, and the capping layer CAP and the first capping pattern CLP1 may be cut and separated by a tip of the second bank BNK2. The first capping pattern CLP1 may be disposed on the first electrode pattern CEP1 in each of the second emission area EA2 and the third emission area EA3. Therefore, the first capping pattern CLP1 may be disposed on the first electrode pattern CEP1 in an area other than the first emission area EA1.

[0194] In an embodiment, an inorganic material for forming the first inorganic layer TL1 may be deposited on the entire surface of the display device 10. The first inorganic layer TL1 may cover the upper surface of the capping layer CAP in the first emission area EA1, and may cover the upper surface of the first capping pattern CLP1 in the second emission area EA2 and the third emission area EA3. The first inorganic layer TL1 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the first organic pattern ELP1 disposed on the second bank BNK2, the side surface of the first electrode pattern CEP1, and the upper surface and the side surface of the first capping pattern CLP1. The first inorganic layer TL1 may cover the upper surface of the first capping pattern CLP1 in the groove GRV. The first inorganic layer TL1 may include an inorganic material to prevent or substantially prevent oxygen or moisture from penetrating into the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. For example, the first inorganic layer TL1 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0195] exist Fig.13 In the embodiment, the first inorganic layer TL1, the first cover pattern CLP1, the first electrode pattern CEP1, and the first organic pattern ELP1 that are not disposed in the first emission area EA1 and the area adjacent to the first emission area EA1 may be etched by an etching process. For example, the first inorganic layer TL1, the first cover pattern CLP1, the first electrode pattern CEP1, and the first organic pattern ELP1 may be etched by performing at least one of a dry etching process and a wet etching process. Therefore, the second pixel electrode AE2 may be exposed in the second emission area EA2, and the third pixel electrode AE3 may be exposed in the third emission area EA3.

[0196] exist Fig.14 In the embodiment, the second light emitting layer EL2 may be directly disposed on the second pixel electrode AE2 in the second emission area EA2. A portion of the second light emitting layer EL2 may fill a space surrounded by the second pixel electrode AE2, the residual pattern RP, and the first insulating layer IL1, and another portion of the second light emitting layer EL2 may cover a side surface of the etching control layer EST, an upper surface of an edge of the etching control layer EST, and a side surface of the first insulating layer IL1.

[0197] In an embodiment, an organic material for forming the second light emitting layer EL2 and the second organic pattern ELP2 may be deposited on the entire surface of the display device 10. In an embodiment, the second light emitting layer EL2 and the second organic pattern ELP2 may be deposited in the same process, and the second light emitting layer EL2 and the second organic pattern ELP2 may be cut and separated by the tip of the second bank BNK2. A portion of the second organic pattern ELP2 may be disposed on the second bank BNK2 adjacent to the second emission area EA2, and another portion of the second organic pattern ELP2 may be accommodated in the groove GRV. The second organic pattern ELP2 may be directly disposed on the third pixel electrode AE3 in the third emission area EA3.

[0198] The second common electrode CE2 may be directly disposed on the second light emitting layer EL2 in the second emission region EA2. The second common electrode CE2 may contact the side surface of the conductive layer MTL and the upper surface of the edge of the conductive layer MTL. The second common electrode CE2 may include a transparent conductive material and may transmit light generated from the second light emitting layer EL2. Therefore, the second light emitting element ED2 may be disposed in a hole formed by the bank BNK and may emit light through the second emission region EA2.

[0199] In an embodiment, a metal material for forming the second common electrode CE2 and the second electrode pattern CEP2 may be deposited on the entire surface of the display device 10. A portion of the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 on the second embankment BNK2, and another portion of the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 in the groove GRV. In an embodiment, the second common electrode CE2 and the second electrode pattern CEP2 may be deposited in the same process, and the second common electrode CE2 and the second electrode pattern CEP2 may be cut and separated by the tip of the second embankment BNK2. The second electrode pattern CEP2 may be directly disposed on the second organic pattern ELP2 in each of the first emission area EA1 and the third emission area EA3. Therefore, the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 in an area other than the second emission area EA2.

[0200] A capping layer CAP may be disposed on the second common electrode CE2 in the second emission area EA2. The capping layer CAP may include an inorganic insulating material and may cover the second light emitting element ED2. The capping layer CAP may prevent or substantially prevent the second light emitting element ED2 from being damaged by external air.

[0201] In an embodiment, an inorganic material for forming a capping layer CAP and a second capping pattern CLP2 may be deposited on the entire surface of the display device 10. A portion of the second capping pattern CLP2 may be disposed on the second electrode pattern CEP2 on the second bank BNK2, and another portion of the second capping pattern CLP2 may be disposed on the second electrode pattern CEP2 in the groove GRV. In an embodiment, the capping layer CAP and the second capping pattern CLP2 may be deposited in the same process, and the capping layer CAP and the second capping pattern CLP2 may be cut and separated by the tip of the second bank BNK2. The second capping pattern CLP2 may be disposed on the second electrode pattern CEP2 in each of the first emission area EA1 and the third emission area EA3. Therefore, the second capping pattern CLP2 may be disposed on the second electrode pattern CEP2 in an area other than the second emission area EA2.

[0202] In an embodiment, an inorganic material for forming a second inorganic layer TL2 may be deposited on the entire surface of the display device 10. The second inorganic layer TL2 may cover the upper surface of the capping layer CAP in the second emission area EA2, and may cover the upper surface of the second capping pattern CLP2 in the first emission area EA1 and the third emission area EA3. The second inorganic layer TL2 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the second organic pattern ELP2 disposed on the second bank BNK2, the side surface of the second electrode pattern CEP2, and the upper surface and the side surface of the second capping pattern CLP2. The second inorganic layer TL2 may cover the upper surface of the second capping pattern CLP2 in the groove GRV. The second inorganic layer TL2 may include an inorganic material to prevent or substantially prevent oxygen or moisture from penetrating into the second light emitting element ED2. The second inorganic layer TL2 may be an inorganic encapsulation layer. For example, the second inorganic layer TL2 may be formed of at least one of the materials described as examples of the first inorganic layer TL1.

[0203] exist Fig.15 In the embodiment, the second inorganic layer TL2, the second cover pattern CLP2, the second electrode pattern CEP2, and the second organic pattern ELP2 that are not disposed in the second emission area EA2 and the area adjacent to the second emission area EA2 may be etched by an etching process. For example, the second inorganic layer TL2, the second cover pattern CLP2, the second electrode pattern CEP2, and the second organic pattern ELP2 may be etched by at least one of a dry etching process and a wet etching process. Therefore, the third pixel electrode AE3 may be exposed in the third emission area EA3.

[0204] exist Fig.16In the embodiment, the third light emitting layer EL3 may be directly disposed on the third pixel electrode AE3 in the third emission area EA3. A portion of the third light emitting layer EL3 may fill a space surrounded by the third pixel electrode AE3, the residual pattern RP, and the first insulating layer IL1, and another portion of the third light emitting layer EL3 may cover a side surface of the etching control layer EST, an upper surface of an edge of the etching control layer EST, and a side surface of the first insulating layer IL1.

[0205] In an embodiment, an organic material for forming the third light emitting layer EL3 and the third organic pattern ELP3 may be deposited on the entire surface of the display device 10. In an embodiment, the third light emitting layer EL3 and the third organic pattern ELP3 may be deposited in the same process, and the third light emitting layer EL3 and the third organic pattern ELP3 may be cut and separated by the tip of the second bank BNK2. A portion of the third organic pattern ELP3 may be disposed on the second bank BNK2 adjacent to the third emission area EA3, and another portion of the third organic pattern ELP3 may be accommodated in the groove GRV.

[0206] The third common electrode CE3 may be directly disposed on the third light emitting layer EL3 in the third emission region EA3. The third common electrode CE3 may contact the side surface of the conductive layer MTL and the upper surface of the edge of the conductive layer MTL. The third common electrode CE3 may include a transparent conductive material and may transmit light generated from the third light emitting layer EL3. Therefore, the third light emitting element ED3 may be disposed in a hole formed by the bank BNK and may emit light through the third emission region EA3.

[0207] In an embodiment, a metal material for forming the third common electrode CE3 and the third electrode pattern CEP3 may be deposited on the entire surface of the display device 10. A portion of the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 on the second embankment BNK2, and another portion of the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 in the groove GRV. In an embodiment, the third common electrode CE3 and the third electrode pattern CEP3 may be deposited in the same process, and the third common electrode CE3 and the third electrode pattern CEP3 may be cut and separated by the tip of the second embankment BNK2. The third electrode pattern CEP3 may be directly disposed on the third organic pattern ELP3 in each of the first emission area EA1 and the second emission area EA2. Therefore, the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 in an area other than the third emission area EA3.

[0208] A capping layer CAP may be disposed on the third common electrode CE3 in the third emission area EA3. The capping layer CAP may include an inorganic insulating material and may cover the third light emitting element ED3. The capping layer CAP may prevent or substantially prevent the third light emitting element ED3 from being damaged by external air.

[0209] In an embodiment, an inorganic material for forming a capping layer CAP and a third capping pattern CLP3 may be deposited on the entire surface of the display device 10. A portion of the third capping pattern CLP3 may be disposed on the third electrode pattern CEP3 on the second bank BNK2, and another portion of the third capping pattern CLP3 may be disposed on the third electrode pattern CEP3 in the groove GRV. In an embodiment, the capping layer CAP and the third capping pattern CLP3 may be deposited in the same process, and the capping layer CAP and the third capping pattern CLP3 may be cut and separated by the tip of the second bank BNK2. The third capping pattern CLP3 may be disposed on the third electrode pattern CEP3 in each of the first emission area EA1 and the second emission area EA2. Therefore, the third capping pattern CLP3 may be disposed on the third electrode pattern CEP3 in an area other than the third emission area EA3.

[0210] In an embodiment, an inorganic material for forming a third inorganic layer TL3 may be deposited on the entire surface of the display device 10. The third inorganic layer TL3 may cover the upper surface of the capping layer CAP in the third emission area EA3, and may cover the upper surface of the third capping pattern CLP3 in the first emission area EA1 and the second emission area EA2. The third inorganic layer TL3 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third organic pattern ELP3 disposed on the second bank BNK2, the side surface of the third electrode pattern CEP3, and the upper surface and the side surface of the third capping pattern CLP3. The third inorganic layer TL3 may cover the upper surface of the third capping pattern CLP3 in the groove GRV. The third inorganic layer TL3 may include an inorganic material to prevent or substantially prevent oxygen or moisture from penetrating into the third light emitting element ED3. The third inorganic layer TL3 may be an inorganic encapsulation layer. For example, the third inorganic layer TL3 may be made of at least one of the materials described as an example of the first inorganic layer TL1.

[0211] exist Fig.17In the embodiment, the third inorganic layer TL3, the third cover pattern CLP3, the third electrode pattern CEP3, and the third organic pattern ELP3 that are not disposed in the third emission area EA3 and the area adjacent to the third emission area EA3 may be etched by an etching process. For example, the third inorganic layer TL3, the third cover pattern CLP3, the third electrode pattern CEP3, and the third organic pattern ELP3 may be etched by performing at least one of a dry etching process and a wet etching process.

[0212] Fig.18 A virtual reality device including a display device according to an embodiment is shown. Fig.18 The display device 10_1 may include the Figures 1 to 9 Any one of the display devices 10 of the embodiments.

[0213] Reference Fig.18 In an embodiment, the virtual reality device 1 may be a glasses-type display. The virtual reality device 1 may include a display device 10_1, a left lens 10a, a right lens 10b, a support frame 20, glasses frame legs 30a and 30b, a reflective member 40, and a display device housing 50.

[0214] In another embodiment, the virtual reality device 1 may be applied to a head mounted display including a head strap that can be worn on the head in place of the glasses frame legs 30a and 30b. Fig.18 The virtual reality device 1 shown in FIG. 1 may be applied to various other electronic devices in various forms.

[0215] The display device housing 50 may house the display device 10_1 and the reflective member 40. The image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the right eye of the user through the right lens 10b. Therefore, the user may view the virtual reality image displayed on the display device 10_1 through the right eye.

[0216] The display device housing 50 may be disposed at the right end of the support frame 20. However, the position of the display device housing 50 is not limited thereto. For example, the display device housing 50 may be disposed at the left end of the support frame 20. In this case, the image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the user's left eye through the left lens 10a. Therefore, the user may view the virtual reality image displayed on the display device 10_1 through the left eye.

[0217] As another example, the display device housing 50 may be provided at both the left and right ends of the support frame 20. In this case, the user may view the virtual reality image displayed on the display device 10_1 through both the left eye and the right eye.

[0218] Fig.19 and Fig. 20 A head mounted display including a display device according to an embodiment is shown. Fig.19 and Fig. 20 The display device 10_2 may include the Figures 1 to 9 Any one of the display devices 10 of the embodiments.

[0219] Reference Fig.19 and Fig. 20 , the display device 10_2 may be applied to a head mounted display (HMD). The first display device 1100 may provide an image to the right eye of the user, and the second display device 1200 may provide an image to the left eye of the user.

[0220] The first lens array 1310 may be disposed between the first display device 1100 and the housing cover 1700. The first lens array 1310 may include a plurality of lenses 1311. The lenses 1311 may include convex lenses convex toward the housing cover 1700.

[0221] The second lens array 1410 may be disposed between the second display device 1200 and the housing cover 1700. The second lens array 1410 may include a plurality of lenses 1411. The lenses 1411 may include convex lenses convex toward the housing cover 1700.

[0222] The display panel housing 1600 may accommodate the first display device 1100, the second display device 1200, the first lens array 1310, and the second lens array 1410. One surface of the display panel housing 1600 may be open to accommodate the first display device 1100, the second display device 1200, the first lens array 1310, and the second lens array 1410.

[0223] The housing cover 1700 may cover the open surface of the display panel housing 1600. The housing cover 1700 may include a first opening 1710 on which the left eye of the user is placed and a second opening 1720 on which the right eye of the user is placed. For example, the first opening 1710 and the second opening 1720 may be formed in a square shape, but the shapes of the first opening 1710 and the second opening 1720 are not limited thereto. As another example, the first opening 1710 and the second opening 1720 may be formed in a circular shape or an elliptical shape. As another example, the first opening 1710 and the second opening 1720 may be integrated to form one opening.

[0224] The second opening 1720 may be aligned with the first display device 1100 and the first lens array 1310, and the first opening 1710 may be aligned with the second display device 1200 and the second lens array 1410. Therefore, the user may view the image of the first display device 1100 magnified as a virtual image by the first lens array 1310 through the second opening 1720, and may view the image of the second display device 1200 magnified as a virtual image by the second lens array 1410 through the first opening 1710.

[0225] In an embodiment, the headband 1800 can fix the display panel housing 1600 to the user's head so that the first opening 1710 and the second opening 1720 of the housing cover 1700 are placed on the user's left eye and right eye, respectively. The headband 1800 can be connected to the upper surface, the left surface, and the right surface of the display panel housing 1600.

[0226] Fig.21 It is shown Figures 18 to 20 sectional view of a pixel according to an embodiment in a display device of FIG. Fig.21 The display device may include Figure 4 The same elements as those described above may be briefly described or may not be described.

[0227] Reference Fig.21 , the display panel 100 may include a semiconductor backplane SBP, an emission backplane EBP, a light emitting element layer EML, and an encapsulation layer TFEL.

[0228] The semiconductor back plate SBP may include a semiconductor substrate SSUB, first to third semiconductor insulating layers SIL1 to SIL3 , and contact terminals CTE.

[0229] In an embodiment, the semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type impurity. A plurality of well regions WA may be provided in the upper surface of the semiconductor substrate SSUB. The well region WA may be a region doped with a second type impurity different from the first type impurity. For example, the first type impurity may be a p-type impurity, and the second type impurity may be an n-type impurity. As another example, the first type impurity may be an n-type impurity, and the second type impurity may be a p-type impurity.

[0230] The semiconductor substrate SSUB may include a plurality of pixel transistors PTR. Each of the pixel transistors PTR may include a well region WA, a source region SCA, a drain region DRA, a channel region CH, a first lightly doped impurity region LDD1, a second lightly doped impurity region LDD2, a bottom insulating layer BIL, a gate electrode GE, and a side insulating layer FIL.

[0231] The well area WA may be disposed in an upper portion of the semiconductor substrate SSUB. The well area WA may accommodate the source area SCA, the drain area DRA, the channel area CH, the first lightly doped impurity area LDD1, and the second lightly doped impurity area LDD2.

[0232] The source region SCA may correspond to the source electrode of the pixel transistor PTR, and the drain region DRA may correspond to the drain electrode of the pixel transistor PTR. Each of the source region SCA and the drain region DRA may be doped with first type impurities. The source region SCA may be disposed on one side of the gate electrode GE, and the drain region DRA may be disposed on the other side of the gate electrode GE.

[0233] The channel region CH may be disposed between the source region SCA and the drain region DRA. The bottom insulating layer BIL may be disposed on the channel region CH to insulate the channel region CH from the gate electrode GE. The gate electrode GE may be disposed on the bottom insulating layer BIL. The gate electrode GE may overlap the channel region CH and the well region WA in the thickness direction. The side insulating layer FIL may be disposed on the side surface of the gate electrode GE and the upper surface of the bottom insulating layer BIL.

[0234] The first lightly doped impurity region LDD1 may be disposed between the channel region CH and the source region SCA, and the second lightly doped impurity region LDD2 may be disposed between the channel region CH and the drain region DRA. Due to the bottom insulating layer BIL, the first lightly doped impurity region LDD1 may have an impurity concentration lower than that of the source region SCA. Due to the bottom insulating layer BIL, the second lightly doped impurity region LDD2 may have an impurity concentration lower than that of the drain region DRA. The distance between the source region SCA and the drain region DRA may be increased by the first lightly doped impurity region LDD1 and the second lightly doped impurity region LDD2. Therefore, the length of the channel region CH of the pixel transistor PTR may be increased, thereby preventing or substantially preventing perforation and hot carrier phenomena caused by a short channel.

[0235] The first semiconductor insulating layer SIL1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SIL1 may include, but is not limited to, silicon carbonitride (SiCN) or silicon oxide (SiO x (0<x≤2)) based inorganic materials.

[0236] The second semiconductor insulating layer SIL2 may be disposed on the first semiconductor insulating layer SIL1. The second semiconductor insulating layer SIL2 may include, but is not limited to, silicon oxide (SiO x ) based inorganic materials.

[0237] The contact terminal CTE may be disposed on the second semiconductor insulating layer SIL2. Each of the contact terminals CTE may be connected to any one of the gate electrode GE, the source region SCA, and the drain region DRA of the pixel transistor PTR through a hole penetrating the first semiconductor insulating layer SIL1 and the second semiconductor insulating layer SIL2. In an embodiment, the contact terminal CTE may include at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd).

[0238] The third semiconductor insulating layer SIL3 may be disposed on the side surface of each of the contact terminals CTE. The upper surface of each of the contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SIL3. The third semiconductor insulating layer SIL3 may include, but is not limited to, silicon oxide (SiO x ) based inorganic materials.

[0239] In an embodiment, the emission backplane EBP may include first to eighth metal layers MTL1 to MTL8 , first to eighth vias VIA1 to VIA8 , and first to ninth interlayer insulating layers ILD1 to ILD9 .

[0240] The first metal layer MTL1 to the eighth metal layer MTL8 may be electrically connected to the contact terminal CTE exposed in the semiconductor backplane SBP to form each pixel circuit. For example, the semiconductor backplane SBP may include a plurality of pixel transistors PTR, and the emission backplane EBP may include a connection electrode connecting the pixel transistors PTR and at least one capacitor connected to each of the pixel transistors PTR. The emission backplane EBP may electrically connect the pixel circuit to the first light emitting element ED1.

[0241] The first interlayer insulating layer ILD1 may be disposed on the semiconductor backplane SBP. The first via VIA1 may penetrate the first interlayer insulating layer ILD1 and may be connected to the contact terminal CTE exposed in the semiconductor backplane SBP. The first metal layer MTL1 may be disposed on the first interlayer insulating layer ILD1 and may be connected to the first via VIA1.

[0242] The second interlayer insulating layer ILD2 may be disposed on the first interlayer insulating layer ILD1 and the first metal layer MTL1. The second via VIA2 may penetrate the second interlayer insulating layer ILD2 and may be connected to the first metal layer MTL1. The second metal layer MTL2 may be disposed on the second interlayer insulating layer ILD2 and may be connected to the second via VIA2.

[0243] The third interlayer insulating layer ILD3 may be disposed on the second interlayer insulating layer ILD2 and the second metal layer MTL2. The third via VIA3 may penetrate the third interlayer insulating layer ILD3 and may be connected to the second metal layer MTL2. The third metal layer MTL3 may be disposed on the third interlayer insulating layer ILD3 and may be connected to the third via VIA3.

[0244] The fourth interlayer insulating layer ILD4 may be disposed on the third interlayer insulating layer ILD3 and the third metal layer MTL3. The fourth via VIA4 may penetrate the fourth interlayer insulating layer ILD4 and may be connected to the third metal layer MTL3. The fourth metal layer MTL4 may be disposed on the fourth interlayer insulating layer ILD4 and may be connected to the fourth via VIA4.

[0245] The fifth interlayer insulating layer ILD5 may be disposed on the fourth interlayer insulating layer ILD4 and the fourth metal layer MTL4. The fifth via VIA5 may penetrate the fifth interlayer insulating layer ILD5 and may be connected to the fourth metal layer MTL4. The fifth metal layer MTL5 may be disposed on the fifth interlayer insulating layer ILD5 and may be connected to the fifth via VIA5.

[0246] The sixth interlayer insulating layer ILD6 may be disposed on the fifth interlayer insulating layer ILD5 and the fifth metal layer MTL5. The sixth via VIA6 may penetrate the sixth interlayer insulating layer ILD6 and may be connected to the fifth metal layer MTL5. The sixth metal layer MTL6 may be disposed on the sixth interlayer insulating layer ILD6 and may be connected to the sixth via VIA6.

[0247] The seventh interlayer insulating layer ILD7 may be disposed on the sixth interlayer insulating layer ILD6 and the sixth metal layer MTL6. The seventh via VIA7 may penetrate the seventh interlayer insulating layer ILD7 and may be connected to the sixth metal layer MTL6. The seventh metal layer MTL7 may be disposed on the seventh interlayer insulating layer ILD7 and may be connected to the seventh via VIA7.

[0248] The eighth interlayer insulating layer ILD8 may be disposed on the seventh interlayer insulating layer ILD7 and the seventh metal layer MTL7. The eighth via VIA8 may penetrate the eighth interlayer insulating layer ILD8 and may be connected to the seventh metal layer MTL7. The eighth metal layer MTL8 may be disposed on the eighth interlayer insulating layer ILD8 and may be connected to the eighth via VIA8. The ninth interlayer insulating layer ILD9 may be disposed on the eighth interlayer insulating layer ILD8 and the eighth metal layer MTL8.

[0249] In an embodiment, the first to eighth metal layers MTL1 to MTL8 and the first to eighth vias VIA1 to VIA8 may include substantially the same material. In an embodiment, the first to eighth metal layers MTL1 to MTL8 and the first to eighth vias VIA1 to VIA8 may include at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). Each of the first to ninth interlayer insulating layers ILD1 to ILD9 may include, but is not limited to, silicon oxide (SiO x ) based inorganic materials.

[0250] The thickness of the first metal layer MTL1, the thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6 may be greater than each of the thickness of the first via VIA1, the thickness of the second via VIA2, the thickness of the third via VIA3, the thickness of the fourth via VIA4, the thickness of the fifth via VIA5, and the thickness of the sixth via VIA6. The thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6 may be greater than the thickness of the first metal layer MTL1. The thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6 may be substantially the same. For example, the thickness of the first metal layer MTL1 can be about 1360Å, the thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5 and the thickness of the sixth metal layer MTL6 can all be about 1440Å, the thickness of the first via VIA1, the thickness of the second via VIA2, the thickness of the third via VIA3, the thickness of the fourth via VIA4, the thickness of the fifth via VIA5 and the thickness of the sixth via VIA6 can all be about 1150Å.

[0251] The thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may be greater than each of the thickness of the first metal layer MTL1, the thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6. The thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may be greater than each of the thickness of the seventh via VIA7 and the thickness of the eighth via VIA8. The thickness of the seventh via VIA7 and the thickness of the eighth via VIA8 may be greater than each of the thickness of the first via VIA1, the thickness of the second via VIA2, the thickness of the third via VIA3, the thickness of the fourth via VIA4, the thickness of the fifth via VIA5, and the thickness of the sixth via VIA6. The thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may be substantially the same. For example, the thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may be approximately 9000Å. For example, the thickness of the seventh via VIA7 and the thickness of the eighth via VIA8 may both be about 6000 Å.

[0252] As the resolution increases, the display device 10 can include a large number of pixels SP in a relatively small area. The emission backplane EBP including the first metal layer MTL1 to the eighth metal layer MTL8 can realize the connection electrode connecting the pixel transistor PTR and at least one capacitor connected to each of the pixel transistors PTR, thereby realizing a pixel circuit with a relatively small area. Therefore, the light emitting element layer EML can be formed on a silicon wafer (Si wafer) including the semiconductor backplane SBP and the emission backplane EBP, and the display device 10 can achieve ultra-high resolution image quality.

[0253] Fig. 22 It is shown Figures 18 to 20 sectional view of a pixel according to an embodiment in a display device of FIG. Fig. 22 The display device may include Fig.21 The semiconductor backplane SBP and the emitter backplane EBP may include Figure 6 Therefore, the light emitting element layer EML and the encapsulation layer TFEL will be omitted. Fig. 22 Further description of the display device.

[0254] Fig.23 It is shown Figures 18 to 20 sectional view of a pixel according to an embodiment in a display device of FIG. Fig.23 The display device may include Fig.21 The semiconductor backplane SBP and the emitter backplane EBP may include Figure 8 Therefore, the light emitting element layer EML and the encapsulation layer TFEL will be omitted. Fig.23 Further description of the display device.

Claims

1. A display device, comprising: a first pixel electrode positioned in a first emission region of the substrate; an insulating layer, covering an edge of the first pixel electrode; a first light emitting layer, on the first pixel electrode and the insulating layer; a first common electrode, on the first light-emitting layer; a conductive layer, arranged on the insulating layer to surround the first emitting region; a first bank on the conductive layer; a second bank adjacent to the first emission region on the first bank and including a tip protruding from a side of the first bank; a groove recessed from an upper surface of the second bank to at least a portion of the first bank; a first organic pattern including the same material as the first light emitting layer, wherein a portion of the first organic pattern is on the second bank and another portion of the first organic pattern is received in the groove; as well as A first inorganic layer covers an upper surface of the first common electrode and side surfaces of the first organic pattern disposed on the second bank and an upper surface of the first organic pattern received in the groove.

2. The display device according to claim 1, wherein: In a plan view, the groove is spaced apart from the first emission region, and the second bank is positioned between the groove and the first emission region.

3. The display device according to claim 1, further comprising: a first electrode pattern comprising the same material as the first common electrode, Part of the first electrode pattern is on the first organic pattern on the second bank, and another part of the first electrode pattern is on the first organic pattern in the groove.

4. The display device according to claim 3, further comprising: a covering layer, on the first common electrode; as well as a first covering pattern comprising the same material as the covering layer, Part of the first covering pattern is on the first electrode pattern on the second bank, and another part of the first covering pattern is on the first electrode pattern in the groove.

5. The display device according to claim 4, wherein: The first inorganic layer covers a side surface of the first electrode pattern on the second bank, an upper surface and a side surface of the first capping pattern disposed on the second bank, and an upper surface of the first capping pattern in the groove.

6. The display device according to claim 4, wherein: A depth of the groove is greater than a sum of a thickness of the first organic pattern, a thickness of the first electrode pattern, and a thickness of the first capping pattern.

7. The display device according to claim 1, further comprising: a second pixel electrode positioned in a second emission region of the substrate; a second light emitting layer, on the second pixel electrode; as well as A second common electrode is on the second light-emitting layer.

8. The display device according to claim 7, wherein: Each of the first common electrode and the second common electrode contacts a side surface of the conductive layer and an upper surface of an edge of the conductive layer.

9. The display device according to claim 7, wherein: The first common electrode and the second common electrode are electrically connected through the conductive layer.

10. The display device according to claim 7, further comprising: a second organic pattern including the same material as the second light emitting layer, wherein a portion of the second organic pattern is on the second bank and another portion of the second organic pattern is received in the groove; and A second electrode pattern includes the same material as the second common electrode, wherein a portion of the second electrode pattern is on the second organic pattern on the second bank, and another portion of the second electrode pattern is on the second organic pattern in the groove.

11. The display device according to claim 10, further comprising a second inorganic layer, wherein the second inorganic layer covers an upper surface of the second common electrode, a side surface of the second organic pattern arranged on the second embankment, a side surface of the second electrode pattern arranged on the second embankment, and an upper surface of the second electrode pattern accommodated in the groove.

12. The display device according to claim 1, wherein: The groove penetrates from the upper surface of the second bank to a lower surface of the first bank to expose an upper surface of the conductive layer.

13. The display device according to claim 12, wherein: The other portion of the first organic pattern is received in the groove to be directly disposed on the conductive layer.

14. A display device, comprising: a first pixel electrode positioned in a first emission region of the substrate; an insulating layer, covering an edge of the first pixel electrode; a first light emitting layer, on the first pixel electrode and the insulating layer; a first common electrode, on the first light-emitting layer; a first bank arranged on the insulating layer to surround the first emission region; a second bank disposed on the first bank to be adjacent to the first emission region and including a tip protruding from a side of the first bank; a groove recessed from an upper surface of the second bank to at least a portion of the first bank; as well as A first organic pattern includes the same material as the first light emitting layer, wherein a portion of the first organic pattern is on the second bank and another portion of the first organic pattern is received in the groove.

15. The display device according to claim 14, further comprising: a first electrode pattern including the same material as the first common electrode, wherein a portion of the first electrode pattern is disposed on the first organic pattern on the second bank, and another portion of the first electrode pattern is disposed on the first electrode pattern received in the groove; and A first inorganic layer covers an upper surface of the first common electrode, side surfaces of the first organic pattern arranged on the second bank, side surfaces of the first electrode pattern arranged on the second bank, and an upper surface of the first electrode pattern accommodated in the groove.

16. A method for manufacturing a display device, the method comprising the following steps: forming a first pixel electrode and a second pixel electrode on a substrate; sequentially stacking a sacrificial layer, an insulating layer, a conductive layer, a first bank and a second bank on the first pixel electrode and the second pixel electrode; forming a tip of the second bank protruding from a side of the first bank by etching the second bank, the first bank, and the conductive layer, and forming a groove recessed from an upper surface of the second bank to at least a portion of the first bank; exposing the first pixel electrode and the second pixel electrode by etching the insulating layer and the sacrificial layer; as well as A first light emitting layer is formed on the first pixel electrode, a portion of a first organic pattern is formed on the second bank, and another portion of the first organic pattern is formed in the groove.

17. The method according to claim 16, further comprising: forming a first common electrode on the first light emitting layer, forming a portion of a first electrode pattern on the first organic pattern on the second bank, and forming another portion of the first electrode pattern on the first organic pattern in the groove; as well as A capping layer is formed on the first common electrode, a portion of a first capping pattern is formed on the first electrode pattern on the second bank, and another portion of the first capping pattern is formed on the first electrode pattern in the groove.

18. The method according to claim 17 further includes forming a first inorganic layer, wherein the first inorganic layer covers an upper surface of the covering layer, a side surface of the first organic pattern on the second embankment, a side surface of the first electrode pattern on the second embankment, an upper surface and a side surface of the first covering pattern on the second embankment, and an upper surface of the first covering pattern in the groove. 19 . The method of claim 18 , further comprising etching the first inorganic layer, the capping layer, the first capping pattern, the first electrode pattern, and the first organic pattern overlapping the second pixel electrode.

20. The method according to claim 19, further comprising: A second light emitting layer is formed on the second pixel electrode, a portion of a second organic pattern is formed on the second bank, and another portion of the second organic pattern is formed in the groove.

Images