Display device

Abstract

One or more embodiments of the present disclosure provide a display device. The display device includes a substrate having a display area and a non-display area, a sub-pixel in the display area, a metal line traversing the non-display area and the display area and extending in the display area to be spaced apart from a light emitting area of the sub-pixel in a plan view, and an auxiliary circuit connected to the metal line in the display area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0120657 filed in the Korean Intellectual Property Office on September 11, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device and a wearable device. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has become increasingly prominent. Therefore, the use of display devices such as liquid crystal display devices, organic light emitting display devices, etc. has been increasing.

[0005] A display device displays an image using pixels. In order to realize augmented reality (AR), virtual reality (VR), and mixed reality (MR), a display device may appropriately have more pixels positioned on a small display surface.

[0006] As the gap between pixels narrows, leakage current through common layers of adjacent pixels may become a problem. Summary of the invention

[0007] The present disclosure provides a display device and a wearable device that can reduce or prevent leakage current through a common layer between adjacent pixels.

[0008] One or more embodiments of the present disclosure provide a display device, comprising: a substrate having a display area and a non-display area, sub-pixels located in the display area, metal lines that cross the non-display area and the display area and extend in the display area to be separated from the light-emitting area of ​​the sub-pixels in a plan view, and auxiliary circuits connected to the metal lines in the display area.

[0009] The sub-pixels and auxiliary circuits may be coupled to a first supply voltage node.

[0010] The auxiliary circuit may include an auxiliary transistor coupled between the metal line and the first power supply voltage node.

[0011] The first electrode and the gate electrode of the auxiliary transistor may be coupled to the first power supply voltage node.

[0012] A second electrode of the auxiliary transistor may be coupled to the metal line and may be configured to receive a reference voltage.

[0013] The subpixel may include: a light emitting element; a first transistor having a gate electrode coupled to a first node, a first electrode coupled to a second node, and a second electrode coupled to an anode of the light emitting element; a second transistor having a gate electrode coupled to a gate line, a first electrode coupled to a data line, and a second electrode coupled to the first node; and a storage capacitor having a first electrode coupled to a first power supply voltage node and a second electrode coupled to the first node.

[0014] The subpixel may also include a third transistor having a gate electrode connected to a second node, a first electrode connected to a first power supply voltage node, and a second electrode connected to the second node; and a fourth transistor having a gate electrode and a first electrode connected to an anode of the light-emitting element and a second electrode configured to receive a reference voltage.

[0015] One or more other embodiments of the present disclosure provide a display device, comprising: a substrate including a display area and a non-display area, a plurality of sub-pixels located in the display area, a plurality of metal lines that traverse the non-display area and the display area and extend in the display area to be spaced apart from light-emitting areas of the plurality of sub-pixels in a plan view, and a plurality of auxiliary circuits each connected to at least one of the plurality of metal lines in the display area.

[0016] The number of auxiliary circuits may be smaller than the number of sub-pixels.

[0017] The metal line may extend in a first direction, wherein, in the display region, a density of the auxiliary circuit increases toward the first direction.

[0018] At least one of the plurality of auxiliary circuits may be coupled to two or more points of the same metal line.

[0019] At least one of the plurality of auxiliary circuits may be coupled to two or more different metal lines.

[0020] The multiple auxiliary circuits may include a first auxiliary circuit and a second auxiliary circuit connected to the same metal wire, wherein the length of the first connecting wire connecting the first auxiliary circuit to one of the multiple metal wires is longer than the length of the second connecting wire connecting the second auxiliary circuit to the one of the multiple metal wires.

[0021] The display device may also include a first metal pad located in the non-display area and connected to the first ends of multiple metal lines, and a second metal pad located in the non-display area and connected to the second ends of the multiple metal lines, wherein the display area is located between the first metal pad and the second metal pad.

[0022] The metal line may be located on a pixel defining layer defining a light emitting area of ​​a sub-pixel in the display area.

[0023] The plurality of metal lines may respectively contact cathodes of the light emitting elements of the plurality of sub-pixels.

[0024] The light emitting element of the sub-pixel may include a first light emitting portion and a second light emitting portion stacked on the first light emitting portion and in contact with a corresponding one of the plurality of metal wires.

[0025] One or more other embodiments of the present disclosure provide a wearable device including a first display panel and a second display panel, wherein the first display panel and the second display panel include: a substrate including a display area and a non-display area, a plurality of sub-pixels located in the display area, a plurality of metal lines that traverse the non-display area and the display area and extend in the display area to be spaced apart from light-emitting areas of the plurality of sub-pixels in a plan view, and a plurality of auxiliary circuits each connected to at least one of the plurality of metal lines in the display area.

[0026] The sub-pixels and auxiliary circuits may be coupled to a first supply voltage node.

[0027] The auxiliary circuit may include an auxiliary transistor coupled between one of the plurality of metal lines and a first power supply voltage node, wherein a first electrode and a gate electrode of the auxiliary transistor are coupled to the first power supply voltage node, and wherein a second electrode of the auxiliary transistor is coupled to one of the plurality of metal lines.

[0028] According to the display device and wearable device of the present disclosure, leakage current through a common layer between adjacent pixels can be reduced or prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A block diagram illustrating one or more embodiments of a display device is shown.

[0030] Figure 2 Shows Figure 1 A top view of one or more embodiments of a display panel.

[0031] Figure 3 A block diagram of a sub-pixel and auxiliary circuitry is shown.

[0032] Figure 4 is a diagram for explaining one or more embodiments of sub-pixels and auxiliary circuits.

[0033] Figure 5 is a diagram for explaining one or more other embodiments of sub-pixels and auxiliary circuits.

[0034] Figure 6 Shows Figure 2 An exploded perspective view of a portion of a display panel.

[0035] Figure 7 A top view showing the relationship between sub-pixels and metal lines.

[0036] Figure 8 A cross-sectional view of one or more embodiments of a light emitting structure is shown.

[0037] Fig. 9 Cross-sectional views of one or more other embodiments of light emitting structures are shown.

[0038] Fig.10 Shown along Figure 7 A cross-sectional view taken along line II'.

[0039] Fig.11 Shows Fig.10 A cross-sectional view of one or more other embodiments of the present invention.

[0040] FIG. 12A to FIG. 12F It is used to explain Figure 2 FIG. 1 is a diagram of other embodiments of a display panel.

[0041] Fig.13 A block diagram of one or more implementations of a display system is shown.

[0042] Fig.14 Shows Fig.13 A perspective view showing an example of application of the display system.

[0043] Fig.15 Shows Fig.14 A head mounted display device worn on a user. DETAILED DESCRIPTION

[0044] By referring to the detailed description and drawings of the embodiments, various aspects of some embodiments of the present disclosure and methods for realizing these aspects can be more easily understood. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey various aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or unnecessary processes, elements and techniques for fully understanding various aspects of the present disclosure for those of ordinary skill in the art can be omitted. Unless otherwise stated, the same reference numerals, characters or combinations thereof represent the same elements throughout the drawings and written descriptions, and therefore their repeated descriptions can be omitted.

[0045] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can", "may" or "may not" when describing the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and alternatives within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various technical interlocks and drives are possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0046] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0047] Various embodiments are described herein with reference to schematic cross-sectional illustrations as embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations caused by, for example, manufacturing techniques and / or tolerances are expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but include deviations in shapes caused by, for example, manufacturing.

[0048] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0049] Spatial relative terms, such as "below", "below", "lower", "lower side", "below", "above", "upper side", etc., can be used in this article for the convenience of explanation, to describe the relationship between an element or feature and another (some) element or feature as shown in the figure. It should be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to also cover the different orientations of the device in use or in operation. For example, if the device in the figure is turned over, the element described as "below", "below" or "below" other elements or features will be subsequently oriented to "above" other elements or features. Therefore, the example terms "below" and "below" can cover both the orientations of above and below. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this indicates that the first part is arranged at the upper side or lower side of the second part, without being limited to its upper side based on the direction of gravity.

[0050] In addition, the phrase "in a plan view" means when observing the object portion from above, and the phrase "in a schematic cross-sectional view" means when observing the schematic cross-section taken by vertically cutting the object portion from the side. The term "overlap" or "overlapping" means that the first object may be located above or below the second object or on the side of the second object, and vice versa. Additionally, the term "overlap" may include stacking, facing or facing, extending on ..., covering or partially covering, or any other suitable term that will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include the meaning of any other suitable corresponding words such as "separated from ... "or "set aside ... "or "offset from ... "and any other suitable corresponding words that will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, although still facing each other, the first object and the second object may be understood to be indirectly opposite to each other.

[0051] It should be understood that when an element, layer, region, or component is referred to as being "formed on," "located on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component can be directly formed on, located on, connected to, or directly coupled to another element, layer, region, or component, or indirectly formed on, located on, connected to, or indirectly coupled to another element, layer, region, or component such that there may be one or more intervening elements, layers, regions, or components. Additionally, this may collectively mean direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it can be directly electrically connected or electrically coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, capacitors, and / or the like. When describing embodiments, unless explicitly described as being directly connected, the statement of connection indicates an electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or is located on another component without intermediate components.

[0052] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the situation that the part is "directly" located "below" another part, but also includes the situation that there is another part between the part and the other part. At the same time, other expressions such as "between...", "directly between..." or "adjacent to" and "directly adjacent to" that describe the relationship between parts can be interpreted similarly. It should be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0053] For the purposes of this disclosure, expressions such as "at least one of..." or "any of..." or "one or more of...", when following a list of elements, modify the entire list of elements, rather than modifying the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X; only Y; only Z; any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ; or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of...", "a plurality of...", "one of...", and other prepositional phrases, when preceding or following a list of elements, modify the entire list of elements, rather than modifying the individual elements in the list.

[0054] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, area, region, layer, part or part from another element, member, component, area, region, layer, part or part. Therefore, the first element, component, area, layer or part described below can be referred to as the second element, component, area, layer or part, without departing from the spirit and scope of the present disclosure. The description of the element as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can also be used to distinguish different categories or groups of elements in this article. For the sake of brevity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0055] In the example, the DR1 axis, the DR2 axis, and / or the DR3 axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted as a broader meaning. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. The same applies to the first, second, and / or third directions.

[0056] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms "a" and "an" as used herein are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It should also be understood that the terms "comprise", "comprising", "have", "having", "include" and "including" when used in this specification specify the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof.

[0057] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as terms of approximation rather than as terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. Taking into account the errors associated with the measurement and the measurement of a specific amount (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the stated values ​​and mean within an acceptable deviation range for a specific value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure".

[0058] In addition, the expression "equal to or the same as..." in the description may mean "substantially equal to or substantially the same as..." That is, it may be the same enough to convince a person skilled in the art that it is the same. Even other expressions may be expressions from which "substantially" is omitted.

[0059] In some embodiments, well-known structures and devices are described in the accompanying drawings in relation to one or more functional blocks (e.g., block diagrams), units and / or modules to avoid making various embodiments unnecessary obscurity. It will be understood by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and optionally, blocks, units and / or modules implemented by microprocessors or other similar hardware can be driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform functions different from those of the dedicated hardware. In addition, in some embodiments, blocks, units and / or modules can be physically separated into two or more separate blocks, units and / or modules that interact with each other without departing from the scope of this disclosure. Additionally, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0060] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having the same meaning as they have in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0061] Figure 1 A block diagram illustrating one or more embodiments of a display device is shown.

[0062] Reference Figure 1 , the display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0063] The display panel 110 includes subpixels SP. The subpixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The subpixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn. Each of m and n may be a natural number greater than 0.

[0064] Each of the sub-pixels SP may include at least one light emitting element configured to generate light. Therefore, the sub-pixels SP may respectively generate light of corresponding colors such as red, green, blue, cyan, magenta, yellow, etc. Two or more of the sub-pixels SP may configure one pixel PXL. For example, Figure 1 As shown in FIG. 1 , three sub-pixels SP may configure one pixel PXL.

[0065] The gate driver 120 is connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with a timing of applying a data signal, and the like.

[0066] The gate driver 120 may be positioned on one side of the display panel 110. However, the embodiment is not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and the drivers may be positioned on one side of the display panel 110 and on the other side of the display panel 110 opposite to the one side, respectively. As described above, according to the embodiment, the gate driver 120 may be positioned around the display panel 110 in various forms.

[0067] The data driver 130 is connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the nth data line DLn. The data driver 130 receives the image data DATA and the data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0068] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first to n-th data lines DL1 to DLn using a voltage from the voltage generator 140. When a gate signal is applied to each of the first to m-th gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the first to n-th data lines DL1 to DLn. Therefore, the corresponding sub-pixel SP may generate light corresponding to the data signal. Thus, an image is displayed on the display panel 110.

[0069] In an implementation, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0070] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated voltages to constituent elements of the display device 100. For example, the voltage generator 140 may be configured to generate a plurality of voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0071] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first power supply voltage VDD and the second power supply voltage VSS may be provided to the sub-pixel SP. The first power supply voltage VDD may have a relatively high voltage level, and the second power supply voltage VSS may have a voltage level lower than the first power supply voltage VDD. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be provided by an external device of the display device 100.

[0072] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation of sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a reference voltage (e.g., a predetermined reference voltage) may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate the reference voltage.

[0073] The controller 150 controls various operations of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling display of the input image data IMG from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0074] The controller 150 may convert the input image data IMG to be suitable for the display device 100 or the display panel 110 to output the image data DATA. In an embodiment, the controller 150 may output the image data DATA by aligning the input image data IMG to be suitable for the arrangement of the sub-pixels SP.

[0075] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted in one integrated circuit. Figure 1As shown in , the data driver 130, the voltage generator 140 and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140 and the controller 150 may be functionally separated components within one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140 and the controller 150 may be provided as a component separated from the driver integrated circuit DIC.

[0076] In some embodiments, the display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense ambient temperature and generate temperature data TEP representing the sensed temperature. In embodiments, the temperature sensor 160 may be adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0077] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control the data signal and the first power supply voltage VDD and the second power supply voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0078] Figure 2 Shows Figure 1 A top view of one or more embodiments of a display panel.

[0079] Reference Figure 2 , as Figure 1 The display panel DP of one or more embodiments of the display panel 110 may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is positioned around the display area DA.

[0080] The display panel DP may include a substrate SUB, sub-pixels SP, an auxiliary circuit AC, a first metal pad JPD1, a second metal pad JPD2, metal lines JHL1 to JHLo, and a pad PD.

[0081] When the display panel DP is used as a display screen for a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, or an augmented reality (AR) device, the display panel DP may be positioned very close to the user's eyes. In this case, sub-pixels SP having a relatively high degree of integration are suitable. In order to increase the degree of integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP may be formed on a substrate SUB which is a silicon substrate. A display device 100 (see FIG. 1 ) including a display panel DP including a substrate SUB which is a silicon substrate Figure 1 ) can be called a silicon-based OLED (OLEDoS) display device.

[0082] The sub-pixels SP are positioned in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix format along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag form along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be positioned as Shape (e.g., RGBG matrix structure, is a registered trademark of Samsung Display Co., Ltd. of South Korea). The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction. Two or more of the plurality of sub-pixels SP may configure one pixel PXL (see Figure 1 ).

[0083] The substrate SUB may include a display area DA and a non-display area NDA. Constituent elements for controlling the sub-pixel SP may be positioned in the non-display area NDA on the substrate SUB. For example, wirings connected to the sub-pixel SP, such as Figure 1 The first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn may be spatially efficiently positioned in the non-display area NDA.

[0084] The first metal pad JPD1 may be positioned in the non-display area NDA. The first metal pad JPD1 may have a substantially rectangular shape including a long side extending in the second direction DR2 and a short side extending in the first direction DR1. The length of the long side may be similar to the length of the display area DA in the second direction DR2. The first metal pad JPD1 may include at least one metal material. For example, the first metal pad JPD1 may include a material having a high resistivity and a melting point, such as molybdenum (Mo), titanium (Ti), or titanium nitride (TiN). The first metal pad JPD1 may be positioned in a direction of the display area DA opposite to the first direction DR1.

[0085] The second metal pad JPD2 may be positioned in the non-display area NDA and may be spaced apart from the first metal pad JPD1 in the first direction DR1. The second metal pad JPD2 may have a substantially rectangular shape including a long side extending in the second direction DR2 and a short side extending in the first direction DR1. The length of the long side may be similar to the length of the display area DA in the second direction DR2. The second metal pad JPD2 may include at least one metal material. For example, the second metal pad JPD2 may include a material having a high resistivity and a melting point, such as molybdenum (Mo), titanium (Ti), or titanium nitride (TiN). The second metal pad JPD2 may be positioned in the first direction DR1 of the display area DA. That is, the display area DA may be positioned between the first metal pad JPD1 and the second metal pad JPD2.

[0086] The metal lines JHL1 to JHLo (o may be an integer greater than 1) may cross the non-display area NDA and the display area DA, and may extend in the display area DA so as not to overlap with the light emitting area of ​​the sub-pixel SP. That is, the metal lines JHL1 to JHLo may extend in the display area DA so as to be spaced apart from the light emitting area of ​​the sub-pixel SP on a plane. The metal lines JHL1 to JHLo may connect the first metal pad JPD1 and the second metal pad JPD2. The metal lines JHL1 to JHLo may be parallel to each other in the second direction DR2. One end of each of the metal lines JHL1 to JHLo may be connected to the first metal pad JPD1, and the other end of the metal lines JHL1 to JHLo may be connected to the second metal pad JPD2. For example, the metal lines JHL1 to JHLo may include a material having a high resistivity and a melting point, such as molybdenum (Mo), titanium (Ti), or titanium nitride (TiN).

[0087] The first metal pad JPD1, the second metal pad JPD2, and the metal lines JHL1 to JHLo may be integrally formed using the same material and process.

[0088] When a power supply voltage is applied to the first metal pad JPD1, heat generation due to Joule heating may occur in the metal lines JHL1 to JHLo. The power supply voltage may include a single pulse, or may include a plurality of pulses. Due to the heat generation, an organic material adjacent to the metal lines JHL1 to JHLo may sublime. Therefore, during operation of the display device 100, leakage current through the organic material may be reduced or prevented.

[0089] However, the voltage of the metal lines JHL1 to JHLo near the second metal pad JPD2 may be lower than that of the metal lines JHL1 to JHLo near the first metal pad JPD1 due to a voltage drop phenomenon (IR drop) occurring during current flow from the first metal pad JPD1 to the second metal pad JPD2.

[0090] In order to compensate for this voltage drop phenomenon, the display device 100 may include an auxiliary circuit AC. The auxiliary circuit AC may be connected to at least one of the metal lines JHL1 to JHLo in the display area DA. When a power supply voltage is applied to the first metal pad JPD1, the auxiliary circuit AC may provide an auxiliary current to the connected metal lines JHL1 to JHLo. Therefore, the voltage drop phenomenon may be compensated.

[0091] The number, position and connection relationship of the auxiliary circuits AC can be set differently. Figure 2 In the embodiment, the number of auxiliary circuits AC may be equal to the number of sub-pixels SP. The auxiliary circuits AC in a row unit may be connected to the same metal line. The density of the auxiliary circuits AC may be constant in the entire display area DA. The number, position, and connection relationship of the auxiliary circuits AC will be referred to later. FIG. 12A to FIG. 12F A more different description is made. During the Joule heating process, a power supply voltage may be provided to the auxiliary circuit AC through at least some of the pads PD.

[0092] A virtual first cutting line SCL1 may extend in the second direction DR2 between the first metal pad JPD1 and the display area DA. The first cutting line SCL1 may cross the metal lines JHL1 to JHLo. A virtual second cutting line SCL2 may extend in the second direction DR2 between the second metal pad JPD2 and the display area DA. The second cutting line SCL2 may cross the metal lines JHL1 to JHLo.

[0093] After the Joule heating process, the display panel DP is cut along the cutting lines SCL1 and SCL2, so that the first metal pads JPD1 and the second metal pads JPD2 may not exist in the final product. In one or more other embodiments, by not cutting the display panel DP along the cutting lines SCL1 and SCL2, the first metal pads JPD1 and the second metal pads JPD2 may exist in the final product.

[0094] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 in the display panel DP may be integrated in the non-display area NDA. In an embodiment, Figure 1 The gate driver 120 may be mounted on the display panel DP and may be positioned in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented as an integrated circuit separated from the display panel DP. In an embodiment, the temperature sensor 160 may be positioned in the non-display area NDA to detect the temperature of the display panel DP.

[0095] The pads PD are positioned in the non-display area NDA on the substrate SUB. At least some of the pads PD may be electrically connected to the sub-pixels SP through wirings. For example, some of the pads PD may be connected to the sub-pixels SP through the first to nth data lines DL1 to DLn.

[0096] The pad PD can connect the display panel DP interface to the display device 100 (see Figure 1 ) other constituent elements. In an embodiment, the pad PD can be used from Figure 1 The driver integrated circuit DIC provides voltages and signals suitable for the operation of constituent elements included in the display panel DP. For example, the first data line DL1 to the nth data line DLn (see Figure 1 ) can be connected to the driver integrated circuit DIC through the pad PD. For example, the driver integrated circuit DIC can receive the first power supply voltage VDD and the second power supply voltage VSS through the pad PD (see Figure 1 For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS (see Figure 1 ) can be sent from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0097] In an embodiment, the circuit board may be electrically connected to the pad PD by using a conductive adhesive member such as an anisotropic conductive film. In this case, the circuit board may be a flexible printed circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit DIC may be mounted on the circuit board to be electrically connected to the pad PD.

[0098] In an embodiment, the display area DA may have various shapes. The display area DA may have a closed loop shape including straight and / or curved sides. For example, the display area DA may have shapes such as polygonal shapes, circular shapes, semicircular shapes, and elliptical shapes.

[0099] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially circular. In an embodiment, the display panel DP may be bendable, foldable, or rollable. In these cases, the display panel DP and / or the substrate SUB may include a material having flexible properties.

[0100] Figure 3 A block diagram of a sub-pixel and auxiliary circuitry is shown.

[0101] Reference Figure 3, among the sub-pixels SP, the sub-pixel SPij positioned in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example. The sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0102] In addition, refer to Figure 3 , the auxiliary circuit AC is shown as an example. The auxiliary circuit AC may be connected between at least one metal line JHLk (k is an integer greater than or equal to 1 and less than or equal to o) among the metal lines JHL1 to JHLo and the first power supply voltage node VDDN. The sub-pixel SPij and the auxiliary circuit AC may be commonly connected to the first power supply voltage node VDDN.

[0103] The light emitting element LD is connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. In this case, the first power supply voltage node VDDN is the transmitting Figure 1 The first power supply voltage node VDD, and the second power supply voltage node VSSN are sent Figure 1 A node of a second power supply voltage VSS.

[0104] The anode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC, and the cathode CE of the light emitting element LD may be connected to the second power supply voltage node VSSN. For example, the anode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0105] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi and the m-th gate line GLm of the first gate line GL1 to the m-th gate line GLm Figure 1 The sub-pixel circuit SPC is configured to control the light emitting element LD according to signals received through the signal lines.

[0106] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. For example, the sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to the gate signal. Based on the voltage stored in the sub-pixel circuit SPC, the light emitting element LD may generate light having a brightness corresponding to the data signal.

[0107] During the Joule heating process, the auxiliary circuit AC may supply an auxiliary current to the metal line JHLk based on the auxiliary voltage applied to the first power supply voltage node VDDN. However, when the display device 100 (see Figure 1) displays an image, the auxiliary circuit AC may not operate. For example, when the display device 100 displays an image, the first power supply voltage VDD (see Figure 1 ) may be blocked by the auxiliary circuit AC. Therefore, the first power supply voltage VDD may not be applied to the metal line JHLk.

[0108] Figure 4 is a diagram for explaining one or more embodiments of sub-pixels and auxiliary circuits.

[0109] Reference Figure 4 The sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD. The sub-pixel circuit SPC may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4 and a storage capacitor Cst.

[0110] In the first transistor T1, the gate electrode may be connected to the first node N1, the first electrode may be connected to the second node N2, and the second electrode may be connected to the anode AE ​​of the light emitting element LD. The first transistor T1 may include sub-transistors T1-1 and T1-2 connected in series. The first transistor T1 may be a driving transistor.

[0111] In the second transistor T2, a gate electrode may be connected to the i-th gate line GLi, a first electrode may be connected to the j-th data line DLj, and a second electrode may be connected to the first node N1. The second transistor T2 may be a switching transistor.

[0112] In the third transistor T3 , a gate electrode may be connected to the second node N2 , a first electrode may be connected to the first power supply voltage node VDDN, and a second electrode may be connected to the second node N2 .

[0113] In the fourth transistor T4, the gate electrode and the first electrode may be connected to the anode AE ​​of the light emitting element LD, and the second electrode may receive the reference voltage GND. The reference voltage GND may be set to be less than the first power supply voltage VDD (see Figure 1 The reference voltage GND can be connected to the second power supply voltage VSS (see Figure 1 In one or more other implementations, the reference voltage GND may be different from the second power supply voltage VSS.

[0114] In the storage capacitor Cst, a first electrode may be connected to the first power supply voltage node VDDN, and a second electrode may be connected to the first node N1.

[0115] The light emitting element LD may include an anode AE, a cathode CE, and a light emitting layer. The light emitting layer may be positioned between the anode AE ​​and the cathode CE.

[0116] When a gate signal of a turn-on level (low level) is applied to the i-th gate line GLi, the second transistor T2 may be turned on. In this case, the data signal applied to the j-th data line DLj may be applied to the first node N1 through the second transistor T2. The storage capacitor Cst may maintain the voltage of the data signal. In response to the voltage of the data signal, the first transistor T1 may determine the amount of driving current flowing from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light emitting element LD may emit light having a brightness corresponding to the amount of the driving current.

[0117] The third transistor T3 and the fourth transistor T4 are diode-connected transistors that can limit the direction of current so that the current does not flow in the reverse direction. In some embodiments, the third transistor T3 and the fourth transistor T4 can be removed from the sub-pixel circuit SPC. When the third transistor T3 is removed, the second node N2 can be directly connected to the first power supply voltage node VDDN.

[0118] The auxiliary circuit AC may include an auxiliary transistor ATR. The auxiliary transistor ATR may be connected between at least one metal wire JHLk among the metal wires JHL1 to JHLo and the first power supply voltage node VDDN. The auxiliary transistor ATR may be connected in a diode manner. The first electrode and the gate electrode of the auxiliary transistor ATR may be connected to the first power supply voltage node VDDN. The second electrode of the auxiliary transistor ATR may be connected to at least one metal wire JHLk among the metal wires JHL1 to JHLo. The second electrode of the auxiliary transistor ATR may receive a reference voltage GND. The reference voltage GND may be the same as the second power supply voltage VSS. In one or more other embodiments, the reference voltage GND may be different from the second power supply voltage VSS. In addition, the reference voltage GND applied to the second electrode of the auxiliary transistor ATR may be the same as or different from the reference voltage GND applied to the second electrode of the fourth transistor T4.

[0119] During the Joule heating process, the auxiliary voltage applied to the first power supply voltage node VDDN may be greater than the voltage of the metal lines JHL1 to JHLo. For example, the difference between the auxiliary voltage and the voltage applied to the metal lines JHL1 to JHLo may be greater than the breakdown voltage of the auxiliary transistor ATR. Therefore, an auxiliary current may flow from the first power supply voltage node VDDN toward the metal lines JHL1 to JHLo, and the auxiliary current may compensate for the voltage drop of the metal lines JHL1 to JHLo.

[0120] On the other hand, when the display device 100 displays an image, the difference between the first power supply voltage VDD of the first power supply voltage node VDDN and the reference voltage GND may be less than the breakdown voltage of the auxiliary transistor ATR. Therefore, the possibility of current flowing in the reverse direction from the first power supply voltage node VDDN toward the metal lines JHL1 to JHLo may be reduced or prevented.

[0121] The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 and the auxiliary transistor ATR may be P-type transistors. Each of the transistors T1, T2, T3, T4, and ATR may be a metal oxide silicon field effect transistor (MOSFET). However, the embodiment is not limited thereto. For example, at least one of the transistors T1, T2, T3, T4, and ATR may be replaced by an N-type transistor.

[0122] In an implementation, the transistors T1 , T2 , T3 , and T4 and the ATR may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0123] Figure 5 is a diagram for explaining one or more other embodiments of sub-pixels and auxiliary circuits.

[0124] Reference Figure 5 The sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD. The sub-pixel circuit SPC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst.

[0125] In the first transistor T1, a gate electrode may be connected to the first node N1, a first electrode may be connected to the first power supply voltage node VDDN, and a second electrode may be connected to the anode AE ​​of the light emitting element LD. The first transistor T1 may be a driving transistor.

[0126] In the second transistor T2, a gate electrode may be connected to the i-th gate line GLi, a first electrode may be connected to the j-th data line DLj, and a second electrode may be connected to the first node N1. The second transistor T2 may be a switching transistor.

[0127] In the storage capacitor Cst, a first electrode may be connected to the first node N1, and a second electrode may be connected to the second electrode of the first transistor T1.

[0128] The light emitting element LD may include an anode AE, a cathode CE, and a light emitting layer. The light emitting layer may be positioned between the anode AE ​​and the cathode CE.

[0129] When a gate signal of a turn-on level (low level) is applied to the i-th gate line GLi, the second transistor T2 may be turned on. In this case, the data signal applied to the j-th data line DLj may be applied to the first node N1 through the second transistor T2. The storage capacitor Cst may maintain the voltage of the data signal. In response to the voltage of the data signal, the first transistor T1 may determine the amount of driving current flowing from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light emitting element LD may emit light having a brightness corresponding to the amount of the driving current.

[0130] Since the configuration and function of the auxiliary circuit AC are similar to Figure 4 The configuration and function are the same as in , so their redundant description will be omitted.

[0131] The first transistor T1 and the second transistor T2 may be N-type transistors. Each of the first transistor T1 and the second transistor T2 may be a MOSFET. However, the embodiment is not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 may be replaced by a P-type transistor.

[0132] In an implementation, the transistors T1 and T2 may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0133] Figure 6 Shows Figure 2 An exploded perspective view of a portion of a display panel.

[0134] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0135] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming a circuit element. For example, the semiconductor material may include silicon, germanium and / or silicon germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. In other embodiments, the substrate SUB may include a glass substrate. In still other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0136] The pixel circuit layer PCL is positioned on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern positioned between the insulating layers. The conductive pattern of the pixel circuit layer PCL may be used as at least some of circuit elements, wiring, etc. The conductive pattern may include copper, but the embodiment is not limited thereto.

[0137] The circuit element may include a sub-pixel circuit SPC for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see Figure 3 ). The sub-pixel circuit SPC may include a transistor and at least one capacitor. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3 separated by an insulating layer.

[0138] The wiring of the pixel circuit layer PCL may include a signal line connected to each of the sub-pixels SP, for example, a gate line, a light emission control line, and a data line. The wiring may also include a signal line connected to each of the sub-pixels SP. Figure 3 The wiring of the first power supply voltage node VDDN may also include a wiring connected to Figure 3 Wiring of the second power supply voltage node VSSN.

[0139] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0140] The anode AE ​​may be positioned on the pixel circuit layer PCL. The anode AE ​​may contact the circuit element through the pixel circuit layer PCL. The anode AE ​​may include an opaque conductive material capable of reflecting light, but the embodiment is not limited thereto.

[0141] The pixel defining layer PDL is positioned on the anode AE. The pixel defining layer PDL may include (e.g., define) an opening OP exposing a portion of each of the anodes AE. The opening OP of the pixel defining layer PDL may be understood as corresponding to the light emitting areas of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively.

[0142] In an embodiment, the pixel defining layer PDL may include an inorganic material. In this case, the pixel defining layer PDL may include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0143] The light emitting structure EMS may be positioned on the anode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0144] In an embodiment, the light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be positioned entirely on the upper portion of the pixel defining layer PDL. In other words, the light emitting structure EMS may extend across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In this case, at least some of the layers in the light emitting structure EMS may be disconnected, bent, or removed at the boundaries between the sub-pixels SP. However, embodiments are not limited thereto. For example, portions of the light emitting structure EMS corresponding to the sub-pixels SP may be separated from each other, and each of them may be positioned within the opening OP of the pixel defining layer PDL.

[0145] The cathode CE may be positioned on the light emitting structure EMS. The cathode CE may extend across the sub-pixel SP. As such, the cathode CE may be provided as a common electrode for the sub-pixel SP.

[0146] The cathode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode CE may be made of a metal material or a transparent conductive material to have a relatively thin thickness. In an embodiment, the cathode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In other embodiments, the cathode CE may include at least one of silver (Ag), magnesium (Mg), and a mixture thereof. However, the material of the cathode CE is not limited thereto.

[0147] One of the anodes AE, the portion of the light emitting structure EMS overlapping therewith, and the portion of the cathode CE overlapping therewith can be understood as configuring one light emitting element LD (see Figure 3 ). In other words, each of the light emitting elements of the sub-pixel SP may include an anode AE, a portion of the light emitting structure EMS overlapping therewith, and a portion of the cathode CE overlapping therewith. In each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, holes injected from the anode AE ​​and electrons injected from the cathode CE are transferred to the light emitting layer of the light emitting structure EMS to form excitons, and when the excitons transition from an excited state to a ground state, light may be generated. The brightness of the light may be determined according to the amount of current flowing through the light emitting layer. According to the configuration of the light emitting layer, the wavelength range of the generated light may be determined.

[0148] The encapsulation layer TFE is positioned on the cathode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to reduce or prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL. In an embodiment, the encapsulation layer TFE may include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic film may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ). For example, the organic film may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene (BCB). However, the materials of the organic film and the inorganic film of the encapsulation layer TFE are not limited thereto.

[0149] The encapsulation layer TFE may also include aluminum oxide (AlO x ) to improve the encapsulation efficiency of the encapsulation layer TFE. The film containing aluminum oxide may be positioned on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or the lower surface of the encapsulation layer TFE facing the light emitting element layer LDL.

[0150] The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited thereto. The encapsulation layer TFE may further include a thin film made of at least one of various materials suitable for improving encapsulation efficiency.

[0151] The optical function layer OFL is positioned on the device encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0152] The color filter layer CFL is positioned between the encapsulation layer TFE and the lens array LA. The color filter layer CFL is configured to selectively output light within a wavelength range corresponding to each sub-pixel SP or light of a color corresponding to each sub-pixel SP by filtering light emitted from the light emitting structure EMS. The color filter layer CFL includes color filters CF corresponding to the sub-pixels SP, and each of the color filters CF is permeable to light within a wavelength range corresponding to the sub-pixel SP. For example, the color filter CF corresponding to the first sub-pixel SP1 is permeable to red light, the color filter CF corresponding to the second sub-pixel SP2 is permeable to green light, and the color filter CF corresponding to the third sub-pixel SP3 is permeable to blue light. At least some of the color filters CF may be omitted according to the light emitted from the light emitting structure EMS of each sub-pixel SP.

[0153] The lens array LA is positioned on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the sub-pixels SP, respectively. Each of the lenses LS may improve light output efficiency by outputting light emitted from the light emitting structure EMS in an intended path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylate material. However, the material of the lens LS is not limited thereto.

[0154] In an embodiment, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be displaced in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel defining layer PDL. For example, in the central area of ​​the display area DA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be aligned or overlapped with the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central area of ​​the display area DA, the opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the area of ​​the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be displaced from the center of the corresponding opening OP of the pixel defining layer PDL in the plane direction. For example, in the area of ​​the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, in the center of the display area DA, light emitted from the light emitting structure EMS can be effectively output in the normal direction of the display surface. Light emitted from the light emitting structure EMS outside the display area DA can be effectively output in a direction inclined at an angle (e.g., a predetermined angle) relative to the normal direction of the display surface.

[0155] The outer coating layer OC may be positioned on the lens array LA. The outer coating layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS and / or the pixel circuit layer PCL. The outer coating layer OC may include various materials suitable for protecting its lower layer from foreign matter such as dust and moisture. For example, the outer coating layer OC may include at least one of an inorganic insulating film and an organic insulating film. For example, the outer coating layer OC may include an epoxy resin, but the embodiment is not limited thereto. The outer coating layer OC may have a refractive index lower than that of the lens array LA.

[0156] The cover window CW may be positioned on the outer coating layer OC. The cover window CW is configured to protect its lower layer. The cover window CW may have a refractive index higher than that of the outer coating layer OC. The cover window CW may include glass, but embodiments are not limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect components positioned thereunder. In other embodiments, the cover window CW may be omitted.

[0157] Figure 7 A top view showing the relationship between sub-pixels and metal lines.

[0158] Reference Figure 7 , a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged in the first direction DR1 are shown as examples. The first sub-pixel SP1 may include a first light emitting area EMA1 and a non-light emitting area NEA around the first light emitting area EMA1. The second sub-pixel SP2 may include a second light emitting area EMA2 and a non-light emitting area NEA around the second light emitting area EMA2. The third sub-pixel SP3 may include a third light emitting area EMA3 and a non-light emitting area NEA around the third light emitting area EMA3.

[0159] The first light emitting area EMA1 may be a region where the light emitting structure EMS (see Figure 6 ) is an area where light is emitted from a portion of the light emitting structure EMS corresponding to the first sub-pixel SP1. The second light emitting area EMA2 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third light emitting area EMA3 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. Figure 6 As described above, each light emitting region may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 .

[0160] exist Figure 7 In the figure, the light emitting areas EMA1, EMA2 and EMA3 are shown as hexagonal shapes, but the light emitting areas EMA1, EMA2 and EMA3 can be configured into other polygonal shapes including quadrilateral shapes. On the other hand, the light emitting areas EMA1, EMA2 and EMA3 can be configured into circular or elliptical shapes. In addition, the shapes and areas of different light emitting areas EMA1, EMA2 and EMA3 can be different.

[0161] The metal lines JHLk and JHL(k+1) extend in the first direction DR1 (eg, in a zigzag manner) and may have a shape surrounding the corresponding light emitting areas EMA1, EMA2, and EMA3. For example, the metal lines JHLk and JHL(k+1) may extend in the first direction DR1 and may extend in a zigzag shape.

[0162] However, since the metal lines JHLk and JHL(k+1) are not connected to each other in the display area DA, there may be regions POI1 and POI2 that are not covered by the metal lines JHLk and JHL(k+1) between the adjacent light emitting areas EMA1, EMA2, and EMA3. However, two or more metal lines JHLk and JHL(k+1) may be positioned adjacent to each other with a minimum gap in the regions POI1 and POI2. The organic material present in the regions POI1 and POI2 that do not overlap with the metal lines JHLk and JHL(k+1) may sublime due to heat generated from the two adjacent metal lines JHLk and JHL(k+1), and thus leakage current through the organic material may be reduced or prevented.

[0163] Figure 8 A cross-sectional view of one or more embodiments of a light emitting structure is shown.

[0164] Reference Figure 8 , the light emitting structure EMS may have a series structure in which the first light emitting part EU1 and the second light emitting part EU2 are stacked.

[0165] Each of the first light emitting portion EU1 and the second light emitting portion EU2 may include a light emitting layer that generates light according to a current applied thereto. The first light emitting portion EU1 may include a first light emitting layer EML1, a first electron transport portion ETU1, and a first hole transport portion HTU1. The first light emitting layer EML1 may be positioned between the first electron transport portion ETU1 and the first hole transport portion HTU1. The second light emitting portion EU2 may include a second light emitting layer EML2, a second electron transport portion ETU2, and a second hole transport portion HTU2. The second light emitting layer EML2 may be positioned between the second electron transport portion ETU2 and the second hole transport portion HTU2.

[0166] Each of the first and second hole transport units HTU1 and HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. The first and second hole transport units HTU1 and HTU2 may have the same configuration or different configurations.

[0167] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and a hole blocking layer as needed. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration or different configurations.

[0168] A connection layer that may be provided in the form of a charge generation layer CGL may be positioned between the first light emitting portion EU1 and the second light emitting portion EU2 to connect them to each other. In an embodiment, the charge generation layer CGL may have a stacked structure of a p-doped layer and an n-doped layer. For example, the p-doped layer may include a p-type dopant such as HAT-CN, TCNQ, and / or NDP-9, and the n-doped layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, embodiments are not limited thereto.

[0169] In an embodiment, the first light emitting layer EML1 and the second light emitting layer EML2 may generate light of different colors. Light emitted from each of the first light emitting layer EML1 and the second light emitting layer EML2 may be mixed to be recognized as white light. For example, the first light emitting layer EML1 may generate blue light, and the second light emitting layer EML2 may generate yellow light. In an embodiment, the second light emitting layer EML2 may include a structure in which a first sub-light emitting layer configured to generate red light and a second sub-light emitting layer configured to generate green light are stacked. Red light and green light may be mixed to provide yellow light. In this case, an intermediate layer configured to perform a function of transporting holes and / or reducing or preventing the transport of electrons may be further positioned between the first sub-light emitting layer and the second sub-light emitting layer.

[0170] In other embodiments, the first light emitting layer EML1 and the second light emitting layer EML2 may generate light of the same color.

[0171] In an embodiment, the light emitting structure EMS may be formed by a vacuum deposition method, an inkjet printing method, etc., but the embodiment is not limited thereto.

[0172] Fig. 9 Cross-sectional views of one or more other embodiments of light emitting structures are shown.

[0173] Reference Fig. 9 , the light emitting structure EMS' may have a series structure in which the first to third light emitting parts EU1' to EU3' are stacked.

[0174] Each of the first to third light-emitting parts EU1' to EU3' may include a light-emitting layer that generates light according to a current applied thereto. The first light-emitting part EU1' may include a first light-emitting layer EML1', a first electron transport part ETU1', and a first hole transport part HTU1'. The first light-emitting layer EML1' may be positioned between the first electron transport part ETU1' and the first hole transport part HTU1'. The second light-emitting part EU2' may include a second light-emitting layer EML2', a second electron transport part ETU2', and a second hole transport part HTU2'. The second light-emitting layer EML2' may be positioned between the second electron transport part ETU2' and the second hole transport part HTU2'. The third light-emitting part EU3' may include a third light-emitting layer EML3', a third electron transport part ETU3', and a third hole transport part HTU3'. The third light-emitting layer EML3' may be positioned between the third electron transport part ETU3' and the third hole transport part HTU3'.

[0175] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. as needed. The first to third hole transport units HTU1' to HTU3' may have the same configuration or different configurations.

[0176] Each of the first to third electron transport units ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and a hole blocking layer as needed. The first to third electron transport units ETU1' to ETU3' may have the same configuration or different configurations.

[0177] A first charge generation layer CGL1' is positioned between the first light emitting portion EU1' and the second light emitting portion EU2'. A second charge generation layer CGL2' is positioned between the second light emitting portion EU2' and the third light emitting portion EU3'.

[0178] In an embodiment, the first light emitting layer EML1', the second light emitting layer EML2', and the third light emitting layer EML3' may generate light of different colors. Light emitted from each of the first light emitting layer EML1', the second light emitting layer EML2', and the third light emitting layer EML3' may be mixed to be viewed as white light. For example, the first light emitting layer EML1' may generate blue light, the second light emitting layer EML2' may generate green light, and the third light emitting layer EML3' may generate red light.

[0179] In other embodiments, two or more of the first light emitting layer EML1 ′, the second light emitting layer EML2 ′, and the third light emitting layer EML3 ′ may generate light of the same color.

[0180] and Figure 8 and Fig. 9 Unlike the example shown in FIG. 1 , each light emitting structure EMS of each sub-pixel SP may include one light emitting portion. In this case, the light emitting structures EMS of each sub-pixel SP may include different sub-pixels SP1, SP2, and SP3 adjacent to each other (see FIG. 1 ). Figure 6 ) may be configured to emit light of different colors. For example, the light emitting portion of the first sub-pixel SP1 may emit red light, the light emitting portion of the second sub-pixel SP2 may emit green light, and the light emitting portion of the third sub-pixel SP3 may emit blue light. In this case, the light emitting portions of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are separated from each other, and each of them may be positioned at an opening OP of the pixel defining layer PDL (see Figure 6 In this case, the color filters CF1 to CF3 (see Fig.10 ) at least some of ).

[0181] Fig.10 Shown along Figure 7 A cross-sectional view taken along line II'.

[0182] Reference Fig.10 , providing a substrate SUB and a pixel circuit layer PCL positioned on the substrate SUB.

[0183] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon germanium.

[0184] The pixel circuit layer PCL is positioned on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include a circuit element for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit SPC (see Figure 3 ), the transistor T_SP2 of the second sub-pixel SP2 may be one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 may be one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 6 , for clear and concise description, one of the transistors of each sub-pixel SP is shown, and the remaining circuit elements are omitted.

[0185] The transistor T_SP1 of the first subpixel SP1 may include a source area SRA, a drain area DRA, and a gate electrode GE.

[0186] The source region SRA and the drain region DRA may be positioned in the substrate SUB. A well WL formed by an ion implantation process is positioned in the substrate SUB, and the source region SRA and the drain region DRA may be spaced apart from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0187] The gate electrode GE overlaps the channel region between the source region SRA and the drain region DRA and may be positioned in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0188] The layers included in the pixel circuit layer PCL include insulating layers and conductive patterns positioned between the insulating layers. The conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA through a drain connection portion DRC penetrating one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA through a source connection portion SRC penetrating one or more insulating layers.

[0189] Since the gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to other circuit elements and / or wirings, the transistor T_SP1 of the first subpixel SP1 may be provided as one of the transistors of the first subpixel SP1.

[0190] Each of the transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 may be configured similarly to the transistor T_SP1 of the first sub-pixel SP1. Figure 4 ) may be configured similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0191] Thus, the substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 and an auxiliary transistor ATR of the auxiliary circuit AC. On the other hand, in one or more other embodiments, the auxiliary transistor ATR may be positioned at another layer in the third direction DR3 based on the transistors T_SP1, T_SP2, and T_SP3 of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0192] A via layer VIAL is positioned on the pixel circuit layer PCL. The via layer VIAL covers the pixel circuit layer PCL and may have an overall flat surface. The via layer VIAL is configured to flatten the steps on the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiOx ), silicon nitride (SiN x ) and at least one of silicon carbon nitride (SiCN), but the embodiment is not limited thereto.

[0193] The light emitting element layer LDL is positioned on the via layer VIAL and may include first, second and third reflective electrodes RE1, RE2 and RE3, a planarization layer PLNL, first, second and third anodes AE1, AE2 and AE3, a pixel defining layer PDL, a light emitting structure EMS and a cathode CE.

[0194] The first reflective electrode RE1, the second reflective electrode RE2 and the third reflective electrode RE3 are respectively positioned in the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 on the via layer VIAL. Each of the first reflective electrode RE1, the second reflective electrode RE2 and the third reflective electrode RE3 can contact the circuit elements positioned in the pixel circuit layer PCL through the via hole penetrating the via layer VIAL.

[0195] The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may be used as a total reflector that reflects light emitted from the light emitting structure EMS toward the display surface (or the cover window CW). The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may include a metal material suitable for reflecting light. The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom, but the embodiment is not limited thereto.

[0196] In an embodiment, a connection electrode may be positioned below each of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The connection electrode may improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connection electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), and / or the like, but the embodiment is not limited thereto. In an embodiment, the corresponding reflective electrode may be positioned between multiple layers of the connection electrode.

[0197] A buffer pattern BFP may be positioned below at least one of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The buffer pattern BFP may include an inorganic material such as silicon carbon nitride, but the embodiment is not limited thereto. Due to the arrangement of the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 may be adjusted. For example, the buffer pattern BFP may be positioned between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0198] The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may be used as a total reflective mirror, and the cathode CE may be used as a half reflective mirror. The light emitted from the light emitting layer of the light emitting structure EMS may be at least partially amplified by reciprocating between the reflective electrode and the cathode CE, and the amplified light may be output through the cathode CE. In this way, the distance between each reflective electrode and the cathode CE may be understood as the resonance distance of the light emitted from the light emitting layer of the corresponding light emitting structure EMS.

[0199] Due to the presence of the buffer pattern BFP, the first subpixel SP1 may have a resonance distance shorter than the resonance distances of other subpixels. The resonance distance adjusted in this manner may allow light within a corresponding wavelength range (e.g., red) to be effectively and efficiently amplified. Therefore, the first subpixel SP1 may effectively and efficiently output light within the corresponding wavelength range.

[0200] exist Fig.10 , the buffer pattern BFP is shown as being provided in the first sub-pixel SP1 and not provided in the second sub-pixel SP2 and the third sub-pixel SP3, but the embodiment is not limited thereto. The buffer pattern may also be provided in at least one of the second sub-pixel SP2 and the third sub-pixel SP3, so that the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3 may be adjusted. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may correspond to red, green, and blue, respectively, and the distance between the first reflective electrode RE1 and the cathode CE may be smaller than the distance between the second reflective electrode RE2 and the cathode CE. In addition, the distance between the second reflective electrode RE2 and the cathode CE may be smaller than the distance between the third reflective electrode RE3 and the cathode CE.

[0201] In order to flatten the steps between the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3, the planarization layer PLNL may be positioned on the via layer VIAL and the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The planarization layer PLNL may completely cover the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 and the via layer VIAL, and may have a flat surface. In an embodiment, the planarization layer PLNL may be omitted.

[0202] The first anode AE1, the second anode AE2, and the third anode AE3 respectively overlapping the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 are positioned on the planarization layer PLNL. When viewed in the third direction DR3, the first anode AE1, the second anode AE2, and the third anode AE3 may have the same Figure 7 The first anode AE1, the second anode AE2, and the third anode AE3 are connected to the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3, respectively. The first anode AE1 may be connected to the first reflective electrode RE1 through a first through hole VIA1 penetrating the planarization layer PLNL. The second anode AE2 may be connected to the second reflective electrode RE2 through a second through hole VIA2 penetrating the planarization layer PLNL. The third anode AE3 may be connected to the third reflective electrode RE3 through a third through hole VIA3 penetrating the planarization layer PLNL.

[0203] In an embodiment, the first anode AE1, the second anode AE2, and the third anode AE3 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the materials of the first anode AE1, the second anode AE2 and the third anode AE3 are not limited thereto. For example, the first anode AE1, the second anode AE2 and the third anode AE3 may include titanium nitride.

[0204] In an embodiment, an insulating layer for adjusting the height of one or more of the first anode AE1, the second anode AE2, and the third anode AE3 may be further provided. The insulating layer may be positioned between at least one of the first anode AE1, the second anode AE2, and the third anode AE3 and the corresponding reflective electrode. In this case, the planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may correspond to red, green, and blue, respectively, and the distance between the first anode AE1 and the cathode CE may be smaller than the distance between the second anode AE2 and the cathode CE. In addition, the distance between the second anode AE2 and the cathode CE may be smaller than the distance between the third anode AE3 and the cathode CE. The pixel defining layer PDL is positioned on the first anode AE1, the second anode AE2, and the third anode AE3 and the portion of the planarization layer PLNL. The pixel defining layer PDL may include an opening OP that exposes a portion of each of the first anode AE1, the second anode AE2, and the third anode AE3. The opening OP of the pixel defining layer PDL may define a light emitting area for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Thus, the pixel definition layer PDL can be Figure 7 The non-luminous area NEA is positioned to define Figure 7 The first light emitting area EMA1, the second light emitting area EMA2 and the third light emitting area EMA3.

[0205] In an embodiment, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the pixel defining layer PDL may include first to third inorganic insulating layers sequentially stacked, and each of the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon oxynitride. However, the embodiment is not limited thereto. The first to third inorganic insulating layers may have a stepped cross-section in a region adjacent to the opening OP.

[0206] A metal line JHLk may be provided in a boundary area BDA between adjacent sub-pixels SP. The metal lines JHL1, JHL2, JHL3, . . . , JHLLo including the metal line JHLk (see Figure 2 ) can be positioned on the pixel defining layer PDL.

[0207] Each of the metal lines JHL1 to JHLo including the metal line JHLk may contact the cathode CE of the light emitting element of the sub-pixel SP in the display area DA. For example, the metal lines JHL1 to JHLo may sublimate a portion of the light emitting structure EMS positioned nearby by dissipating heat generated by Joule heating after the light emitting structure EMS is stacked. Figure 8 In the case of the light emitting structure EMS, since the Joule heating process occurs after the first light emitting portion EU1, the charge generation layer CGL, and the second light emitting portion EU2 are all stacked, the light emitting structure EMS may not remain on the metal line JHLk. Fig. 9 In the case of the light emitting structure EMS', since the Joule heating process is performed after the first light emitting unit EU1', the first charge generation layer CGL1', the second light emitting unit EU2', the second charge generation layer CGL2', and the third light emitting unit EU3' are all stacked, the light emitting structure EMS' may not remain on the metal wire JHLk. Therefore, leakage current through the portion of the light emitting structure EMS cut off by the metal wires JHL1 to JHLo may be reduced or prevented. The metal wires JHL1 to JHLo may be exposed to the outside of the light emitting structure EMS and may contact the cathode CE deposited subsequently. In this case, as Figure 2 As shown in , the reference voltage GND may be the same as the second power supply voltage VSS.

[0208] The light emitting structure EMS may be positioned on the anode AE ​​exposed by the opening OP of the pixel defining layer PDL. In an embodiment, the light emitting structure EMS may be formed by a process such as vacuum deposition, inkjet printing, etc. The light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be positioned entirely across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. As described above, the light emitting structure EMS may be at least partially cut off by the metal line JHLk in the boundary area BDA. Therefore, when the display panel DP (see Figure 2 ), current leaking from each of the first to third subpixels SP1, SP2, and SP3 to adjacent subpixels through the layers included in the light emitting structure EMS can be reduced. Therefore, the first to third light emitting elements LD1 to LD3 can operate with relatively high reliability.

[0209] The cathode CE may be positioned on the light emitting structure EMS. The cathode CE may be commonly provided for the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The cathode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0210] The first anode AE1, the portion of the light emitting structure EMS overlapping with the first anode AE1, and the portion of the cathode CE overlapping with the first anode AE1 may be configured with the first light emitting element LD1. The second anode AE2, the portion of the light emitting structure EMS overlapping with the second anode AE2, and the portion of the cathode CE overlapping with the second anode AE2 may be configured with the second light emitting element LD2. The third anode AE3, the portion of the light emitting structure EMS overlapping with the third anode AE3, and the portion of the cathode CE overlapping with the third anode AE3 may be configured with the third light emitting element LD3.

[0211] The encapsulation layer TFE is positioned on the cathode CE. The encapsulation layer TFE can reduce or prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL.

[0212] The optical functional layer OFL is positioned on the encapsulation layer TFE. In an embodiment, the optical functional layer OFL may be attached to the encapsulation layer TFE through an adhesive layer APL. For example, the optical functional layer OFL may be manufactured separately so as to be attached to the encapsulation layer TFE through an adhesive layer APL. The adhesive layer APL may also perform the function of protecting the lower layer including the encapsulation layer TFE.

[0213] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, respectively. The first to third color filters CF1 to CF3 may transmit light within different wavelength ranges. For example, the first to third color filters CF1 to CF3 may transmit red light, green light, and blue light, respectively.

[0214] In an embodiment, the first to third color filters CF1 to CF3 may partially overlap in the boundary area BDA. In other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0215] The lens array LA is positioned on the color filter layer CFL. The lens array LA may include a first lens LS1, a second lens LS2, and a third lens LS3 corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. The first lens LS1, the second lens LS2, and the third lens LS3 may improve light output efficiency by outputting light emitted from the first light emitting element LD1 to the third light emitting element LD3 along a desired path, respectively.

[0216] Fig.11 Shows Fig.10 A cross-sectional view of one or more other embodiments of the present invention.

[0217] Fig.11The luminous structure EMS and Fig.10 The light emitting structure EMS of FIG. 1 is different in that a portion of the light emitting structure EMS remains on the metal line JHLk. That is, the metal lines JHL1 to JHLo (see FIG. 1 ) including the metal line JHLk Figure 2 ) may not contact the display area DA (see Figure 2 ) in the sub-pixel SP (see Figure 2 )'s cathode CE of the light-emitting element.

[0218] For example, in the first light emitting unit EU1 and the charge generation layer CGL (see Figure 8 ) is stacked on the metal wire JHLk, the heat generated by Joule heating in the metal wire JHLk is dissipated, thereby sublimating the first light-emitting unit EU1 and a portion of the charge generation layer CGL positioned nearby. Thereafter, the second light-emitting unit EU2 (see Figure 8 In this case, the metal wire JHLk may contact the remaining second light emitting unit EU2.

[0219] For another example, in the first light emitting unit EU1', the first charge generation layer CGL1', the second light emitting unit EU2' and the second charge generation layer CGL2' (see Fig. 9 ) is stacked on the metal wire JHLk, the first light emitting unit EU1', the first charge generation layer CGL1', the second light emitting unit EU2' and part of the second charge generation layer CGL2' can be sublimated by dissipating the heat generated by Joule heating in the metal wire JHLk. Thereafter, the third light emitting unit EU3' (see Fig. 9 In this case, the metal wire JHLk may contact the remaining third light emitting unit EU3'.

[0220] Since the highly conductive charge generation layer CGL, the first charge generation layer CGL1 ′, or the second charge generation layer CGL2 ′ may be sublimated, leakage current may be reduced or prevented even if part of the light emitting structure EMS remains.

[0221] FIG. 12A to FIG. 12F It is used to explain Figure 2 FIG. 1 is a diagram of other embodiments of a display panel.

[0222] Reference Fig. 12A , the number of auxiliary circuits AC of the display panel DPa may be less than the number of sub-pixels SP.

[0223] The number of appropriate auxiliary circuits AC may vary depending on the design of the display panel DPa. For example, as a result of measuring the voltage drop of the metal lines JHL1 to JHLo of the display panel DPa, the number of auxiliary circuits AC may be reduced because the voltage drop is not large.

[0224] Reference Fig. 12B , the number of the auxiliary circuits AC of the display panel DPb may be less than the number of the sub-pixels SP. In this case, in the display area DA, the density of the auxiliary circuits AC may increase in the first direction DR1 which is the extension direction of the metal lines JHL1 to JHLo.

[0225] A greater voltage drop may occur at a portion of the metal lines JHL1 to JHLo close to the second metal pad JPD2 than at a portion of the metal lines JHL1 to JHLo close to the first metal pad JPD1 to which the power supply voltage is applied. Therefore, by centrally positioning the auxiliary circuit AC near the second metal pad JPD2, the voltages of the respective portions of the metal lines JHL1 to JHLo may be made uniform.

[0226] Reference Fig. 12C Display panel DPc and Fig.12D In the display panel DPd, at least one of the auxiliary circuits AC may be connected to two or more points of the same metal line. Fig. 12C In the embodiment, when the auxiliary current supplied from the auxiliary circuit AC is sufficient, the number of the auxiliary circuit AC can be reduced. Fig.12D In this embodiment, the voltage drop can be compensated for more uniformly, and even when a failure occurs in any auxiliary circuit AC, the auxiliary current can be stably supplied from the adjacent auxiliary circuit AC.

[0227] Reference Fig.12E In the display panel DPe, the auxiliary circuit AC may include a first auxiliary circuit AC1 and a second auxiliary circuit AC2 connected to the same metal line JHL1, JHL2, JHL3, ... or JHLo. The length of the first connection line CNL1 connecting the first auxiliary circuit AC1 and the metal line JHL1, JHL2, JHL3, ... or JHLo may be longer than the length of the second connection line CNL2 connecting the second auxiliary circuit AC2 and the metal line JHL1, JHL2, JHL3, ... or JHLo.

[0228] In this case, the second auxiliary circuit AC2 may be positioned in the first direction DR1 of the first auxiliary circuit AC1. Portions of the metal lines JHL1 to JHLo close to the first metal pad JPD1 to which the power supply voltage is applied may have a voltage drop smaller than a voltage drop of portions of the metal lines JHL1 to JHLo close to the second metal pad JPD2. By configuring the first connection line CNL1 to be relatively long near the first metal pad JPD1 in which a relatively small voltage drop occurs, power received by the metal lines JHL1 to JHLo from the first auxiliary circuit AC1 may be reduced. Therefore, the voltage drop amount of a portion of the first connection line CNL1 of the metal lines JHL1 to JHLo connected to the first auxiliary circuit AC1 may be the same as the voltage drop amount of a portion of the second connection line CNL2 of the metal lines JHL1 to JHLo connected to the second auxiliary circuit AC2.

[0229] Reference Fig.12F In the display panel DPf, at least one of the auxiliary circuits AC may be connected to two or more different metal lines. For example, the auxiliary circuit AC may be connected to two adjacent metal lines JHL1 and JHL2 in the second direction DR2. When the auxiliary current supplied from the auxiliary circuit AC is sufficient, the number of the auxiliary circuits AC may be reduced.

[0230] The embodiments of the present disclosure are not subject to Figure 2 and FIG. 12A to FIG. 12F limitations on the implementation methods. Figure 2 and FIG. 12A to FIG. 12F The embodiments may be combined with each other.

[0231] Fig.13 A block diagram of one or more implementations of a display system is shown.

[0232] Reference Fig.13 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220 .

[0233] The processor 1100 can perform various tasks and calculations. In an embodiment, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 through a bus system and control other components of the display system 1000.

[0234] exist Fig.13 , the display system 1000 is shown to include a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1, and connected to the second display device 1220 through a second channel CH2.

[0235] Through the first channel CH1, the processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 In this case, the first image data IMG1 and the first control signal CTRL1 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0236] The processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 through the second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0237] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, and an ultra mobile personal computer (UMPC). In addition, the display system 1000 may include at least one of a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0238] Fig.14 Shows Fig.13 A perspective view showing an example of application of the display system.

[0239] Reference Fig.14 , Fig.13 The display system 1000 may be applied to a head mounted display device 2000. The head mounted display device 2000 may be a wearable electronic device that can be worn on the head of a user.

[0240] The head-mounted display device 2000 may include a head-mounted band 2100 and a display device housing 2200. The head-mounted band 2100 may be connected to the display device housing 2200. The head-mounted band 2100 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper part of the user's head. However, the embodiment is not limited thereto. For example, the head-mounted band 2100 may be implemented in the form of a glasses frame, a helmet, etc.

[0241] The display device receiving case 2200 can receive Fig.13 The first display device 1210 and the second display device 1220. The display device receiving case 2200 may further receive Fig.13 Processor 1100.

[0242] Fig.15 Shows Fig.14 A head mounted display device worn on a user.

[0243] Reference Fig.15 , the first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 are positioned in the head mounted display device 2000. The head mounted display device 2000 may further include one or more lenses LLNS and RLNS.

[0244] In the display device receiving container 2200, the right eye lens RLNS may be positioned between the first display panel DP1 and the right eye of the user. In the display device receiving container 2200, the left eye lens LLNS may be positioned between the second display panel DP2 and the left eye of the user.

[0245] The image output from the first display panel DP1 may be displayed to the right eye of the user through the right eye lens RLNS. The right eye lens RLNS may refract light from the first display panel DP1 to guide it to the right eye of the user. The right eye lens RLNS may perform an optical function to adjust the viewing distance between the first display panel DP1 and the right eye of the user.

[0246] The image output from the second display panel DP2 may be displayed to the left eye of the user through the left eye lens LLNS. The left eye lens LLNS may refract the light from the second display panel DP2 to guide it to the left eye of the user. The left eye lens LLNS may perform an optical function to adjust the viewing distance between the second display panel DP2 and the left eye of the user.

[0247] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. In this case, each display panel outputs an image corresponding to a sub-region of the multi-channel lens, and the output image may pass through the sub-region and be viewed by a user.

[0248] Although the present disclosure has been described in conjunction with what are currently considered to be practical embodiments, it should be understood that the present disclosure is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the attached claims. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent embodiments of the present disclosure are possible. Therefore, the true technical protection scope of the present disclosure must be determined based on the technical spirit of the attached claims, and its functional equivalents will be included therein.

Claims

1. A display device, comprising: A substrate having a display area and a non-display area; A sub-pixel, wherein the sub-pixel is located in the display area; a metal line that crosses the non-display area and the display area and extends in the display area to be spaced apart from the light emitting area of ​​the sub-pixel in a plan view; as well as An auxiliary circuit is connected to the metal line in the display area.

2. The display device according to claim 1, wherein: The sub-pixel and the auxiliary circuit are coupled to a first supply voltage node.

3. The display device according to claim 2, wherein: The auxiliary circuit includes an auxiliary transistor coupled between the metal line and the first power supply voltage node.

4. The display device according to claim 3, wherein: A first electrode and a gate electrode of the auxiliary transistor are coupled to the first power supply voltage node, and The second electrode of the auxiliary transistor is coupled to the metal line and configured to receive a reference voltage.

5. A display device, comprising: A substrate, the substrate comprising a display area and a non-display area; A plurality of sub-pixels, wherein the plurality of sub-pixels are located in the display area; a plurality of metal lines that cross the non-display area and the display area and extend in the display area to be spaced apart from the light emitting areas of the plurality of sub-pixels in a plan view; as well as A plurality of auxiliary circuits are each coupled to at least one of the plurality of metal lines in the display area.

6. The display device according to claim 5, wherein: The number of the auxiliary circuits is less than the number of the sub-pixels.

7. The display device according to claim 6, wherein: The metal wire extends in a first direction, and Wherein, in the display area, the density of the auxiliary circuits increases toward the first direction.

8. The display device according to claim 5, wherein: At least one of the plurality of auxiliary circuits is coupled to two or more points of the same metal line.

9. The display device according to claim 5, wherein: At least one of the plurality of auxiliary circuits is coupled to two or more different metal lines.

10. The display device according to claim 5, wherein: The plurality of auxiliary circuits include a first auxiliary circuit and a second auxiliary circuit, the first auxiliary circuit and the second auxiliary circuit being coupled to the same metal line, and The length of the first connection line connecting the first auxiliary circuit and one of the plurality of metal lines is longer than the length of the second connection line connecting the second auxiliary circuit and the one of the plurality of metal lines.

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