Preparation method of coplanar resonant cavity coupled with Josephson junction

Abstract

The invention provides a preparation method of a coplanar resonant cavity coupled with Josephson junctions. The preparation method comprises the following steps: forming a first laminated structure comprising a first niobium layer, an aluminum-aluminum oxide layer and a second niobium layer on the surface of a substrate; forming a first mask on the surface of the second niobium layer to define a Josephson junction region, and performing pre-protection, etching and anodic oxidation on a part outside the Josephson junction region; removing the second niobium layer outside the first mask and the Josephson junction area, and corroding the aluminum-aluminum oxide layer through an alkaline developing solution so as to expose the first niobium layer under the condition that the first niobium layer is not damaged; defining a resonant cavity region and a bottom electrode region on two sides of the Josephson junction region on the surface of the first niobium layer, and removing the first niobium layer; and sequentially depositing an insulating layer and a lead layer on the surface of the second laminated structure in the Josephson junction region and the resonant cavity region, and depositing a resistance layer in the bottom electrode region.

Description

Technical Field

[0001] The present disclosure relates to the technical field of superconducting quantum devices, and in particular to a method for preparing a coplanar resonant cavity coupled with a Josephson junction. Background Art

[0002] The Josephson junction with a three-layer film structure based on niobium film / aluminum-aluminum oxide mixed film / niobium film (Nb / Al-AlOx / Nb) has been applied to a variety of superconducting quantum devices, such as ultrafast single flux quantum (SFQ), superconducting quantum interference device (SQUID), kinetic inductance detector (KID) and quantum bits, due to its advantages such as high chemical stability, good superconducting properties and controllable current density. It is also an important component of future quantum computers.

[0003] However, when applying the Josephson junction of the Nb / Al-AlOx / Nb three-layer film structure to related application devices, such as SQUID microwave multiplexing (μMux) readout technology and the radio frequency superconducting quantum interference device (RF-SQUID) resonant cavity that provides a constant magnetic flux bias for quantum bits, it is necessary not only to ensure that the Josephson junction has good consistency, but also to have high requirements on the resonant cavity quality factor of the related application devices.

[0004] In the traditional method of preparing Josephson junction, the etching process of the upper niobium film and aluminum oxide outside the junction area will cause damage to the underlying niobium film, resulting in poor surface roughness of the underlying Nb film, thereby reducing the quality factor of the resonant cavity.

[0005] Therefore, under the premise of ensuring the quality of the Nb / Al-AlOx / Nb Josephson junction, improving the quality of the resonant cavity is one of the keys to ensuring the quality of superconducting quantum devices. Summary of the invention

[0006] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present disclosure provides a method for preparing a coplanar resonant cavity coupled with a Josephson junction, comprising:

[0007] Providing a substrate, and forming a first stacked structure on a surface of the substrate, wherein the first stacked structure includes a first niobium layer, an aluminum-aluminum oxide layer, and a second niobium layer in sequence in a direction away from the substrate;

[0008] forming a patterned first mask on the surface of the second niobium layer to define a Josephson junction region, and pre-protecting and etching a portion outside the Josephson junction region through the first mask;

[0009] Performing anodization to form a second stacked structure in the Josephson junction region, the second stacked structure comprising niobium oxide, aluminum oxide, and niobium oxide;

[0010] After removing the first mask, etching the second niobium layer outside the Josephson junction region to expose the aluminum-aluminum oxide layer outside the Josephson junction region, and corroding the aluminum-aluminum oxide layer by an alkaline developer to expose the first niobium layer without damaging the first niobium layer;

[0011] forming a patterned second mask on the surface of the first niobium layer to respectively define a resonant cavity region and a bottom electrode region located on both sides of the Josephson junction region and remove the first niobium layer;

[0012] An insulating layer is deposited on the surface of the second stacked structure in the Josephson junction region and the resonant cavity region, a wire layer is deposited on the surface of the insulating layer, and a resistor layer is deposited in the bottom electrode region.

[0013] According to an embodiment of the present disclosure, the operation of etching the aluminum-aluminum oxide layer by an alkaline developer includes:

[0014] The alkaline developer is mixed with deionized water and dropped onto the aluminum-aluminum oxide layer outside the Josephson junction area. The aluminum-aluminum oxide layer outside the Josephson junction area forms a complex with the alkaline developer through shaking, and the aluminum-aluminum oxide layer outside the Josephson junction area is washed away.

[0015] According to an embodiment of the present disclosure, the alkaline developer is a potassium hydroxide solution with a mass concentration of 5%.

[0016] According to an embodiment of the present disclosure, the thickness of the first niobium layer is greater than 30 nm, the thickness of the second niobium layer is greater than 30 nm, and the thickness of the aluminum-aluminum oxide layer is 2-20 nm; the stresses of the first niobium layer and the second niobium layer are respectively -300~200 MPa, the roughnesses are respectively less than 3 nm, the residual resistivities are respectively greater than or equal to 3.5, and the transition temperatures are respectively greater than or equal to 9K.

[0017] According to an embodiment of the present disclosure, during the anodization process, the electrolyte is a mixed solution of ammonium pentaborate, ethylene glycol and deionized water.

[0018] According to an embodiment of the present disclosure, the first mask and the second mask are positive photoresists.

[0019] According to an embodiment of the present disclosure, a method for depositing an insulating layer includes:

[0020] A patterned third mask is formed in the Josephson junction region and the resonant cavity region to define the insulating layer region, wherein the third mask is a negative photoresist, wherein the insulating layer region includes a through hole region, the through hole region includes a junction region through hole and a cavity region through hole, the junction region through hole is located on the second niobium layer in the Josephson junction region, and the cavity region through hole is located on the insulating layer in the resonant cavity region;

[0021] Silicon dioxide is deposited in the insulating layer region to form an insulating layer.

[0022] According to an embodiment of the present disclosure, the preparation of the conductor layer includes:

[0023] Niobium is deposited on the surface of the insulating layer in the Josephson junction region and the resonant cavity region to form a wire layer, and the wire layer wraps the insulating layer in the Josephson junction region and the resonant cavity region.

[0024] According to an embodiment of the present disclosure, the method for preparing the conductor layer further includes:

[0025] Before depositing the wire layer, a radio frequency source is used to pre-treat the surfaces of the Josephson junction region and the resonant cavity region to remove the insulating layer on the surface of the first niobium layer.

[0026] According to an embodiment of the present disclosure, a method for preparing a resistance layer includes: pre-depositing titanium as an adhesion layer in a bottom electrode region, and then depositing palladium on the adhesion layer to form a resistance layer.

[0027] According to the embodiments of the present disclosure, the core advantage of the preparation method is to use developer etching technology to accurately remove the aluminum-aluminum oxide layer (Al-AlOx layer) while finely controlling the surface roughness of the underlying second niobium layer. This step ensures that the second niobium layer of the resonant cavity has low roughness, thereby reducing energy scattering and loss, and directly improving the quality factor of the resonant cavity. At the same time, by pre-protecting the resonant cavity area, unnecessary damage to the area during subsequent processing is effectively prevented. This protective measure helps to maintain the integrity and cleanliness of the resonant cavity structure and reduce the adverse effects of impurities or defects introduced during the processing on the performance of the resonant cavity. High-quality resonant cavities not only enhance the stability and sensitivity of quantum bits, but also optimize signal transmission and coupling efficiency, providing a more reliable and efficient platform for quantum computing and quantum information processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a flow chart of a method for preparing a coplanar resonant cavity coupled with a Josephson junction in an embodiment of the present disclosure;

[0029] Figure 2 is a schematic cross-sectional structure diagram of a first stacked structure formed on a substrate surface in an embodiment of the present disclosure;

[0030] Figure 3 is a schematic cross-sectional structure diagram of a first mask patterned on the surface of the second niobium layer in an embodiment of the present disclosure;

[0031] Figure 4 is a schematic diagram of the cross-sectional structure of the second niobium layer exposed in the Josephson junction region after etching in the embodiment of the present disclosure;

[0032] Figure 5 is a schematic cross-sectional structure diagram of a second stacked structure formed in a Josephson junction region in an embodiment of the present disclosure;

[0033] Figure 6 is a schematic cross-sectional structure diagram of the second stacked structure after debonding in the embodiment of the present disclosure;

[0034] Figure 7 is a schematic cross-sectional structure diagram of the protection of the second stacked structure in the embodiment of the present disclosure;

[0035] Figure 8 is a schematic diagram of the cross-sectional structure after etching the second niobium layer outside the Josephson junction region in the embodiment of the present disclosure;

[0036] Fig. 9 is a schematic diagram of the cross-sectional structure of the aluminum-aluminum oxide layer after being etched by an alkaline developer in an embodiment of the present disclosure;

[0037] Fig.10 is a schematic diagram of the cross-sectional structure of a Josephson junction in an embodiment of the present disclosure;

[0038] Fig.11 is a schematic cross-sectional structure diagram of a second mask patterned on the surface of the first niobium layer in an embodiment of the present disclosure;

[0039] Fig.12 is a schematic diagram of the cross-sectional structure of the embodiment of the present disclosure in which the first niobium layer exposed in the resonant cavity region and the bottom electrode region is removed;

[0040] Fig.13 is a schematic diagram of the cross-sectional structure after the second mask is removed in the embodiment of the present disclosure;

[0041] Fig.14 is a schematic cross-sectional structure diagram of an insulating layer deposited on the surface of the second stacked structure in the Josephson junction region and the resonant cavity region in an embodiment of the present disclosure;

[0042] Fig.15 is a schematic cross-sectional structure diagram of depositing a conductor layer on the surface of an insulating layer in an embodiment of the present disclosure;

[0043] Fig.16 It is a schematic diagram of the cross-sectional structure of depositing a resistance layer in the bottom electrode region in an embodiment of the present disclosure.

[0044] In the drawings of this disclosure, the meanings of the reference numerals are:

[0045] 1-substrate; 2-first niobium layer; 3-aluminum-aluminum oxide layer; 4-second niobium layer; 5-photoresist mask structure; 6-niobium oxide; 7-aluminum oxide; 8-insulating layer; 9-conductor layer; 10-resistor layer. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0047] The endpoints and any values ​​of the ranges disclosed in this disclosure are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically disclosed in this disclosure.

[0048] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0049] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0050] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. If the full text involves descriptions such as "first", "second", etc., the descriptions such as "first", "second", etc. are only used to distinguish similar objects, and cannot be understood as indicating or implying their relative importance, order of precedence, or implicitly indicating the number of technical features indicated. It should be understood that the data described by "first", "second", etc. can be interchangeable under appropriate circumstances.

[0051] In order to make the purpose, technical solution and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them.

[0052] Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. The shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual size, proportion, and actual positional relationship. In addition, in the present disclosure, any reference symbol between brackets should not be constructed as a limitation to the present disclosure.

[0053] Similarly, in order to simplify the present disclosure and help understand one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. The description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0054] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this disclosure.

[0055] In the process of implementing the present disclosure, it was found that, under the premise of ensuring a high-quality Josephson junction, the present disclosure ensured the roughness of the bottom second niobium layer 4 by pre-protecting the resonant cavity area and etching the aluminum-aluminum oxide layer 3 (Al-AlOx) on the surface of the second niobium layer 4 with a developer, thereby providing a prerequisite for the preparation of a high-quality factor resonant cavity.

[0056] Figure 1 It is a flow chart of a method for preparing a coplanar resonant cavity coupled with a Josephson junction in an embodiment of the present disclosure.

[0057] The present disclosure provides a method for preparing a coplanar resonant cavity coupled with a Josephson junction, such as Figure 1 As shown, the following steps S101 to S106 are included:

[0058] Figure 2 It is a schematic cross-sectional structure diagram of a first stacked structure formed on the surface of a substrate in an embodiment of the present disclosure.

[0059] Step S101: Provide a substrate 1, such as Figure 2 As shown, a first stacked structure is formed on the surface of the substrate 1 , wherein the first stacked structure includes a first niobium layer 2 , an aluminum-aluminum oxide layer 3 and a second niobium layer 4 in sequence along a direction away from the substrate 1 .

[0060] Figure 3 is a schematic cross-sectional structure diagram of a first mask patterned on the surface of the second niobium layer 4 in an embodiment of the present disclosure; Figure 4 FIG. 4 is a schematic diagram of the cross-sectional structure of the second niobium layer 4 exposed in the Josephson junction region after etching in the embodiment of the present disclosure.

[0061] Step S102: Figure 3 As shown, a patterned first mask is formed on the surface of the second niobium layer 4 to define the Josephson junction region, and the portion outside the Josephson junction region is pre-protected by the first mask, as shown in FIG. Figure 4 As shown, the second niobium layer 4 is etched.

[0062] Figure 5 is a schematic cross-sectional structure diagram of a second stacked structure formed in a Josephson junction region in an embodiment of the present disclosure; Figure 6 It is a schematic diagram of the cross-sectional structure of the second stacked structure after debonding in the embodiment of the present disclosure.

[0063] Step S103: performing anodization to form a second stacked structure in the Josephson junction region, such as Figure 5 , 6 As shown, the second stacked structure includes niobium oxide 6 , aluminum oxide 7 , and niobium oxide 6 .

[0064] Figure 7 is a schematic cross-sectional structure diagram of the protection of the second stacked structure in the embodiment of the present disclosure; Figure 8 is a schematic diagram of the cross-sectional structure after etching the second niobium layer 4 outside the Josephson junction region in the embodiment of the present disclosure; Fig. 9 is a schematic diagram of the cross-sectional structure of the aluminum-aluminum oxide layer 3 after being etched by an alkaline developer in the embodiment of the present disclosure; Fig.10 Schematic diagram of the cross-sectional structure of the Josephson junction in the embodiment of the present disclosure.

[0065] Step S104: Figure 7 As shown, after removing the first mask, the second stacked structure is protected by a positive photoresist method, as shown in FIG. Figure 8 As shown, the second niobium layer 4 outside the Josephson junction region is etched to expose the aluminum-aluminum oxide layer 3 outside the Josephson junction region, as shown in FIG. Fig. 9 As shown, the aluminum-aluminum oxide layer 3 is etched by an alkaline developer to expose the first niobium layer 2 without damaging the first niobium layer 2. Fig.10 As shown, a Josephson junction of a Nb / Al-AlOx / Nb three-layer film structure is formed.

[0066] Fig.11 is a schematic cross-sectional structure diagram of a second mask patterned on the surface of the first niobium layer 2 in an embodiment of the present disclosure; Fig.12 It is a schematic diagram of the cross-sectional structure of the embodiment of the present disclosure after removing the exposed first niobium layer 2 in the resonant cavity region and the bottom electrode region.

[0067] Step S105: Fig.11 As shown, a patterned second mask is formed on the surface of the first niobium layer 2 to define the resonant cavity region and the bottom electrode region located on both sides of the Josephson junction region, respectively. Fig.12As shown, the first niobium layer 2 is removed.

[0068] Fig.13 is a schematic diagram of the cross-sectional structure after the second mask is removed in the embodiment of the present disclosure; Fig.14 is a schematic cross-sectional structure diagram of depositing an insulating layer 8 on the surface of the second stacked structure in the Josephson junction region and the resonant cavity region in the embodiment of the present disclosure; Fig.15 is a schematic cross-sectional structure diagram of depositing a conductor layer 9 on the surface of an insulating layer 8 in an embodiment of the present disclosure; Fig.16 Schematic diagram of the cross-sectional structure of depositing the resistance layer 10 in the bottom electrode region in the embodiment of the present disclosure.

[0069] Step S106: Remove the second mask, the structure of which is as follows Fig.13 as shown; Fig.14 As shown, an insulating layer 8 is deposited on the surface of the second stacked structure in the Josephson junction region and the resonant cavity region, as shown in FIG. Fig.15 As shown, a conductor layer 9 is deposited on the surface of the insulating layer 8, as shown in FIG. Fig.16 As shown, a resistive layer 10 is deposited in the bottom electrode region.

[0070] According to the embodiments of the present disclosure, the core advantage of the preparation method is to use alkaline developer etching technology to accurately remove the aluminum-aluminum oxide layer 3 (Al-AlOx layer), while finely controlling the surface roughness of the underlying second niobium layer 4. This step ensures the roughness of the second niobium layer 4 of the resonant cavity, thereby reducing energy scattering and loss, and directly improving the quality factor of the resonant cavity. At the same time, by pre-protecting the resonant cavity area, unnecessary damage to the area during subsequent processing is effectively prevented. This protective measure helps to maintain the integrity and cleanliness of the resonant cavity structure and reduce the adverse effects of impurities or defects introduced during the processing on the performance of the resonant cavity. High-quality resonant cavities not only enhance the stability and sensitivity of quantum bits, but also optimize signal transmission and coupling efficiency, providing a more reliable and efficient platform for quantum computing and quantum information processing.

[0071] In some specific embodiments, a high-resistance silicon material with a resistivity of not less than 10000Ω·cm may be selected for the substrate 1. At the same time, in order to minimize the influence of silicon oxide on the resonant cavity parameters on the surface of the substrate 1, before depositing the first stacked structure, the oxide layer on the surface of the substrate 1 is removed by hydrofluoric acid or buffered oxide etchant (BOE), and then rinsed with deionized water, dried, and baked.

[0072] According to the embodiments of the present disclosure, the thickness of the first niobium layer 2 is 50-400 nm or more, the thickness of the second niobium layer 4 is 50-400 nm or more, and the thickness of the aluminum-aluminum oxide layer is 2-20 nm; the stress of the first niobium layer 2 and the second niobium layer 4 are respectively -300-200 MPa, the roughness is less than 3 nm, the residual resistivity is respectively greater than or equal to 3.5, and the transition temperature is respectively greater than or equal to 9 K.

[0073] In some specific embodiments, in step S101, magnetron sputtering is used to deposit the first niobium layer 2, the aluminum-aluminum oxide layer 3 and the second niobium layer 4 respectively. The thin film deposition is carried out in the main chamber, and the aluminum-aluminum oxide layer oxidation is carried out in the sample chamber (loadlock). The first niobium layer 2 and the second niobium layer 4 are deposited using a four-inch target, wherein the deposition power is 600-900W and the gas pressure is 3.5-5.5mT. The aluminum-aluminum oxide layer is deposited using a three-inch target, wherein the deposition power is 150-200W and the gas pressure is 3.5-5.5mT. The thickness of the deposited first niobium layer 2 is more than 30nm, and the thickness of the aluminum-aluminum oxide layer is: 2-20nm. At the same time, because the current density (a) satisfies the following relationship (1) with the oxidation gas pressure (p) and time (t):

[0074] (P×t)-a, formula (1)

[0075] By adjusting the corresponding oxidation time and gas pressure, the current density meets the device requirements. The thickness of the second niobium layer 4 is more than 30nm. During the deposition process, the stress of the first niobium layer 2 and the second niobium layer 4 is adjusted by adjusting the gas pressure and power, so that the film performance finally meets the stress of -300~200 MPa, the roughness is less than 3nm, the residual resistivity is not less than 3.5, and the transition temperature is not less than 9k.

[0076] In some specific embodiments, in step S102, the operation of forming a patterned first mask on the surface of the second niobium layer 4 includes: performing corresponding operations such as coating, photolithography, development, and baking on the surface of the second niobium layer 4 to define the Josephson junction area and the resonant cavity area. The purpose of pre-protection of the resonant cavity area is to prevent niobium oxide 6 from being introduced by the subsequent anodization process, thereby affecting the resonant cavity quality factor. Among them, the photoresist in the first mask uses positive photoresist, and the photolithography can use ultraviolet contact exposure, laser direct writing and other exposure methods.

[0077] According to the embodiments of the present disclosure, by pre-protecting the resonant cavity region, unnecessary damage to the region during subsequent processing is effectively prevented. This protective measure helps maintain the integrity and cleanliness of the resonant cavity structure and reduces the adverse effects of impurities or defects introduced during processing on the resonant cavity performance.

[0078] In some specific embodiments, in step S102, the operation of etching the second niobium layer 4 includes: using reactive ion etching (RIE) and inductively coupled plasma (ICP) etching technology to etch the second niobium layer 4. At the same time, an end point detection mark is used to determine the etching degree of the second niobium layer 4 through the change of the end point detection etching curve. In order to ensure complete etching, the second niobium layer 4 is generally overetched by 10-15%.

[0079] According to an embodiment of the present disclosure, during the anodization process in step S103, the electrolyte is a mixed solution of ammonium pentaborate, ethylene glycol and deionized water.

[0080] According to the embodiment of the present disclosure, after etching is completed, the first stacked structure is anodized to repair the damage caused by the Nb etching process. The degree of oxidation depends on the degree of damage during the etching process of the second niobium layer 4. The more the second niobium layer 4 is overetched, the greater the degree of oxidation.

[0081] In some specific embodiments, in step S104, the operation of etching the second niobium layer 4 outside the Josephson junction region includes: using reactive ion etching (RIE) and inductively coupled plasma (ICP) etching technology to etch the second niobium layer 4. At the same time, an end point detection mark is used to determine the etching degree of the second niobium layer 4 through the change of the end point detection etching curve. In order to ensure complete etching, the second niobium layer 4 is generally overetched by 10-15%.

[0082] According to an embodiment of the present disclosure, in step S104, the operation of corroding the aluminum-aluminum oxide layer 3 by using an alkaline developer includes: mixing the alkaline developer and deionized water in a volume ratio of 1:4, and dropping the mixture onto the aluminum-aluminum oxide layer 3 outside the Josephson junction region, and oscillating the aluminum-aluminum oxide layer outside the Josephson junction region to form a complex with the alkaline developer, and then washing and removing the aluminum-aluminum oxide layer outside the Josephson junction region.

[0083] According to the embodiment of the present disclosure, the aluminum-aluminum oxide layer 3 (Al-AlOx) on the surface of the second niobium layer 4 is etched with a developer, so that the surface roughness of the bottom second niobium layer 4 can be precisely controlled and improved. Lower surface roughness helps to reduce scattering losses in the resonant cavity, thereby improving the quality factor (Q value) of the resonant cavity. The improvement of the quality factor means that the resonant cavity can store energy more efficiently and reduce energy dissipation, which is crucial to improving the sensitivity and stability of quantum devices.

[0084] According to an embodiment of the present disclosure, the alkaline developer is a potassium hydroxide solution with a mass concentration of 5%.

[0085] In some specific embodiments, in step S105, the operation of forming a patterned second mask on the surface of the first niobium layer 2 includes: performing photoresist protection on the Josephson junction region, wherein the area of ​​the protection region is larger than the area of ​​the junction region, so as to prevent the subsequent etching process from damaging the junction region. The photoresist is a positive photoresist, and the photolithography can be performed by ultraviolet contact exposure, laser direct writing and other exposure methods.

[0086] In some specific embodiments, in step S105, the operation of removing the first niobium layer 2 includes: using reactive ion etching (RIE) and inductively coupled plasma (ICP) etching technology to etch the first niobium layer 2. At the same time, an endpoint detection mark is used to determine the etching degree of the first niobium layer 2 by changing the endpoint detection etching curve.

[0087] According to an embodiment of the present disclosure, the first mask and the second mask are positive photoresists.

[0088] In some specific embodiments, the method for removing the first mask and the second mask is: ultrasonically cleaning and removing the glue using acetone, isopropyl alcohol, and deionized water in sequence, and drying.

[0089] According to an embodiment of the present disclosure, a method for depositing the insulating layer 8 includes:

[0090] A patterned third mask is formed in the Josephson junction region and the resonant cavity region to define the insulating layer 8 region, wherein the third mask is a negative photoresist, wherein the insulating layer 8 region includes a through hole region, the through hole region includes a junction region through hole and a cavity region through hole, the junction region through hole is located on the second niobium layer 4 in the Josephson junction region, and the cavity region through hole is located on the insulating layer 8 in the resonant cavity region;

[0091] Silicon dioxide is deposited in the insulating layer 8 region to form the insulating layer 8 .

[0092] According to the embodiment of the present disclosure, in order to avoid the degradation of the surface roughness of the first niobium layer 2 due to subsequent etching, which leads to a reduction in the quality factor of the resonant cavity, the third mask uses a reverse photoresist, and a stripping process is subsequently used. The photolithography can use ultraviolet contact exposure, laser direct writing and other exposure methods.

[0093] In some specific embodiments, thermal evaporation is used to deposit silicon dioxide to form the insulating layer 8, so as to facilitate subsequent peeling. The peeling is performed by acetone, isopropyl alcohol, deionized water, ultrasonic treatment and drying.

[0094] According to an embodiment of the present disclosure, the preparation of the wire layer 9 includes:

[0095] Niobium is deposited on the surface of the insulating layer 8 in the Josephson junction region and the resonant cavity region to form a wire layer 9, and the wire layer 9 wraps the insulating layer 8 in the Josephson junction region and the resonant cavity region.

[0096] According to an embodiment of the present disclosure, the method for preparing the wire layer 9 further includes:

[0097] Before depositing the wire layer 9 , a radio frequency source is used to pre-treat the surface of the Josephson junction region and the resonant cavity region to remove the insulating layer 8 on the surface of the first niobium layer 2 .

[0098] According to the embodiment of the present disclosure, before the deposition of the wire layer 9, the surface of the Josephson junction region and the resonant cavity region is pre-treated by a radio frequency source to remove silicon oxide on the surface of the first niobium layer 2 to make it more conductive. The stripping is performed by ultrasonic treatment with acetone, isopropyl alcohol, and deionized water and drying.

[0099] According to an embodiment of the present disclosure, the method for preparing the resistance layer 10 includes: pre-depositing titanium as an adhesion layer in the bottom electrode region, and then depositing palladium on the adhesion layer to form the resistance layer 10 .

[0100] In some specific embodiments, before the resistance layer 10 is deposited, a radio frequency source is used to pre-treat the surface of the sample to remove silicon oxide on the surface of the first niobium layer 2 to make it more conductive. Before the resistance layer 10 PdAu is deposited, a layer of adhesion layer Ti is pre-deposited to make it better connected. The peeling is carried out by ultrasonic treatment with acetone, isopropyl alcohol, and deionized water and then drying.

[0101] According to the embodiments of the present disclosure, the method for preparing the coplanar resonant cavity coupled with the Josephson junction proposed in the present disclosure effectively improves the preparation quality of the coplanar resonant cavity coupled with the Josephson junction through a series of innovative process steps, and provides strong support for the development of quantum computing and quantum information processing. The process steps adopted are relatively simple and easy to control, and have high process compatibility and scalability. This means that it can be applied on different quantum chip platforms and provide technical support for the preparation of larger-scale and more complex quantum circuits in the future.

[0102] It should be noted that the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, other embodiments obtained by ordinary technicians in the field without creative work are all within the scope of protection of the present disclosure.

[0103] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a coplanar resonant cavity coupled with a Josephson junction, comprising: Providing a substrate, and forming a first stacked structure on a surface of the substrate, wherein the first stacked structure includes, in a direction away from the substrate, a first niobium layer, an aluminum-aluminum oxide layer, and a second niobium layer in sequence; forming a patterned first mask on the surface of the second niobium layer to define a Josephson junction region, and pre-protecting and etching a portion outside the Josephson junction region through the first mask; Performing anodization to form a second stacked structure in the Josephson junction region, wherein the second stacked structure includes niobium oxide, aluminum oxide, and niobium oxide; After removing the first mask, etching the second niobium layer outside the Josephson junction region to expose the aluminum-aluminum oxide layer outside the Josephson junction region, and corroding the aluminum-aluminum oxide layer with an alkaline developer to expose the first niobium layer without damaging the first niobium layer; forming a patterned second mask on the surface of the first niobium layer to respectively define a resonant cavity region and a bottom electrode region located on both sides of the Josephson junction region and remove the first niobium layer; An insulating layer is deposited on the surface of the second stacked structure in the Josephson junction region and the resonant cavity region, a wire layer is deposited on the surface of the insulating layer, and a resistor layer is deposited in the bottom electrode region.

2. The preparation method according to claim 1, wherein The operation of etching the aluminum-aluminum oxide layer by an alkaline developer comprises: The alkaline developer is mixed with deionized water, and the mixture is dropped onto the aluminum-aluminum oxide layer outside the Josephson junction region. The aluminum-aluminum oxide layer outside the Josephson junction region forms a complex with the alkaline developer by shaking, and the aluminum-aluminum oxide layer outside the Josephson junction region is washed away.

3. The preparation method according to claim 2, wherein The alkaline developer is a potassium hydroxide solution with a mass concentration of 5%.

4. The preparation method according to claim 1, wherein The thickness of the first niobium layer is greater than 30 nm, the thickness of the second niobium layer is greater than 30 nm, and the thickness of the aluminum-aluminum oxide layer is 2-20 nm; the stresses of the first niobium layer and the second niobium layer are respectively -300~200 MPa, the roughness is less than 3 nm, the residual resistivity is respectively greater than or equal to 3.5, and the transition temperature is respectively greater than or equal to 9K.

5. The preparation method according to claim 1, wherein In the anodizing process, the electrolyte is a mixed solution of ammonium pentaborate, ethylene glycol and deionized water.

6. The preparation method according to claim 1, wherein The first mask and the second mask are positive photoresists.

7. The preparation method according to claim 1, wherein The insulating layer deposition method comprises: A patterned third mask is formed in the Josephson junction region and the resonant cavity region to define an insulating layer region, wherein the third mask is a negative photoresist, wherein the insulating layer region includes a through hole region, the through hole region includes a junction region through hole and a cavity region through hole, the junction region through hole is located on the second niobium layer in the Josephson junction region, and the cavity region through hole is located on the insulating layer in the resonant cavity region; Silicon dioxide is deposited in the insulating layer region to form an insulating layer.

8. The preparation method according to claim 1, wherein The preparation of the conductor layer comprises: Niobium is deposited on the surface of the insulating layer in the Josephson junction region and the resonant cavity region to form the wire layer, and the wire layer wraps the insulating layer in the Josephson junction region and the resonant cavity region.

9. The preparation method according to claim 8, wherein: The method for preparing the conductor layer further comprises: Before depositing the wire layer, a radio frequency source is used to pre-treat the surfaces of the Josephson junction region and the resonant cavity region to remove the insulating layer on the surface of the first niobium layer.

10. The preparation method according to claim 1, wherein: The method for preparing the resistance layer comprises: pre-depositing titanium as an adhesion layer in the bottom electrode region, and then depositing palladium on the adhesion layer to form a resistance layer.

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