Preparation method of coplanar resonant cavity coupled with Josephson junction

Abstract

The present disclosure provides a method for preparing a coplanar resonant cavity coupled with a Josephson junction, comprising: forming a first stacked structure comprising a first niobium layer, an aluminum-aluminum oxide layer, and a second niobium layer on a substrate surface; forming a first mask on the surface of the second niobium layer to define a Josephson junction region, pre-protecting the portion outside the Josephson junction region, etching, and anodizing the portion; removing the first mask and the second niobium layer outside the Josephson junction region, and etching the aluminum-aluminum oxide layer with an alkaline developer to expose the first niobium layer without damaging the first niobium layer; defining a resonant cavity region and a bottom electrode region on both sides of the Josephson junction region on the surface of the first niobium layer, and removing the first niobium layer; and sequentially depositing an insulating layer and a conductive layer on the surface of the second stacked structure in the Josephson junction region and in the resonant cavity region, and depositing a resistive layer in the bottom electrode region.

Description

Technical Field

[0001] The present disclosure relates to the technical field of superconducting quantum devices, and in particular to a method for preparing a coplanar resonant cavity coupled with a Josephson junction. Background Art

[0002] The Josephson junction based on a three-layer film structure of niobium film / aluminum aluminum oxide mixed film / niobium film (Nb / Al-AlOx / Nb) has been applied to a variety of superconducting quantum devices, such as ultrafast single flux quantum (SFQ), superconducting quantum interference device (SQUID), kinetic inductance detector (KID) and quantum bits, due to its advantages such as high chemical stability, good superconducting properties and controllable current density. It is also an important component of future quantum computers.

[0003] However, when applying the Josephson junction with a Nb / Al-AlOx / Nb three-layer film structure to related application devices, such as SQUID microwave multiplexing (μMux) readout technology and the radio frequency superconducting quantum interference device (RF-SQUID) resonant cavity that provides a constant magnetic flux bias for quantum bits, it is necessary not only to ensure that the Josephson junction has good consistency, but also to have high requirements for the resonant cavity quality factor of the related application devices.

[0004] In the traditional Josephson junction preparation method, the etching process of the upper niobium film and aluminum oxide outside the junction area will cause damage to the underlying niobium film, resulting in poor surface roughness of the underlying Nb film, thereby reducing the quality factor of the resonant cavity.

[0005] Therefore, under the premise of ensuring the quality of the Nb / Al-AlOx / Nb Josephson junction, improving the quality of the resonant cavity is one of the keys to ensuring the quality of superconducting quantum devices. Summary of the Invention

[0006] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present disclosure provides a method for preparing a coplanar resonant cavity coupled with a Josephson junction, comprising:

[0007] Providing a substrate, and forming a first stacked structure on a surface of the substrate, wherein the first stacked structure includes, in a direction away from the substrate, a first niobium layer, an aluminum-aluminum oxide layer, and a second niobium layer in sequence;

[0008] forming a patterned first mask on the surface of the second niobium layer to define a Josephson junction region, and pre-protecting and etching a portion outside the Josephson junction region through the first mask;

[0009] performing anodization to form a second stacked structure in the Josephson junction region, the second stacked structure comprising niobium oxide, aluminum oxide, and niobium oxide;

[0010] After removing the first mask, etching the second niobium layer outside the Josephson junction region to expose the aluminum-aluminum oxide layer outside the Josephson junction region, and etching the aluminum-aluminum oxide layer with an alkaline developer to expose the first niobium layer without damaging the first niobium layer;

[0011] forming a patterned second mask on the surface of the first niobium layer to respectively define a resonant cavity region and a bottom electrode region located on both sides of the Josephson junction region and remove the first niobium layer;

[0012] An insulating layer is deposited on the surface of the second stacked structure in the Josephson junction region and the resonant cavity region, a wire layer is deposited on the surface of the insulating layer, and a resistor layer is deposited in the bottom electrode region.

[0013] According to an embodiment of the present disclosure, the operation of etching the aluminum-aluminum oxide layer by using an alkaline developer includes:

[0014] An alkaline developer is mixed with deionized water and added dropwise to the aluminum-aluminum oxide layer outside the Josephson junction area. The aluminum-aluminum oxide layer outside the Josephson junction area forms a complex with the alkaline developer by shaking, and the aluminum-aluminum oxide layer outside the Josephson junction area is washed away.

[0015] According to an embodiment of the present disclosure, the alkaline developer is a potassium hydroxide solution with a mass concentration of 5%.

[0016] According to an embodiment of the present disclosure, the thickness of the first niobium layer is greater than 30 nm, the thickness of the second niobium layer is greater than 30 nm, and the thickness of the aluminum-aluminum oxide layer is 2-20 nm. The stress of the first niobium layer and the second niobium layer are respectively -300~200 MPa, the roughness is less than 3 nm, the residual resistivity is greater than or equal to 3.5, and the transition temperature is greater than or equal to 9 K.

[0017] According to an embodiment of the present disclosure, during the anodization process, the electrolyte is a mixed solution of ammonium pentaborate, ethylene glycol, and deionized water.

[0018] According to an embodiment of the present disclosure, the first mask and the second mask are positive photoresists.

[0019] According to an embodiment of the present disclosure, a method for depositing an insulating layer includes:

[0020] A patterned third mask is formed in the Josephson junction region and the resonant cavity region to define an insulating layer region, wherein the third mask is a negative photoresist, wherein the insulating layer region includes a through-hole region, the through-hole region includes a junction region through-hole and a cavity region through-hole, the junction region through-hole is located on the second niobium layer in the Josephson junction region, and the cavity region through-hole is located on the insulating layer in the resonant cavity region;

[0021] Silicon dioxide is deposited in the insulating layer region to form an insulating layer.

[0022] According to an embodiment of the present disclosure, the preparation of the conductive line layer includes:

[0023] Niobium is deposited on the surface of the insulating layer in the Josephson junction region and the resonant cavity region to form a wire layer, and the wire layer wraps the insulating layer in the Josephson junction region and the resonant cavity region.

[0024] According to an embodiment of the present disclosure, the method for preparing the conductive line layer further includes:

[0025] Before depositing the wire layer, a radio frequency source is used to pre-treat the surfaces of the Josephson junction region and the resonant cavity region to remove the insulating layer on the surface of the first niobium layer.

[0026] According to an embodiment of the present disclosure, a method for preparing a resistance layer includes: pre-depositing titanium as an adhesion layer in a bottom electrode region, and then depositing palladium and gold on the adhesion layer to form a resistance layer.

[0027] According to the embodiments of the present disclosure, the core advantage of this preparation method lies in the use of developer etching technology to precisely remove the aluminum-aluminum oxide layer (Al-AlOx layer), while also carefully controlling the surface roughness of the underlying second niobium layer. This step ensures low roughness in the second niobium layer of the resonant cavity, thereby reducing energy scattering and loss, directly improving the quality factor of the resonant cavity. Furthermore, by pre-protecting the resonant cavity area, unnecessary damage to this area during subsequent processing is effectively prevented. This protective measure helps maintain the integrity and cleanliness of the resonant cavity structure and reduces the adverse effects of impurities or defects introduced during processing on the resonant cavity performance. A high-quality resonant cavity not only enhances the stability and sensitivity of the qubit but also optimizes signal transmission and coupling efficiency, providing a more reliable and efficient platform for quantum computing and quantum information processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a flow chart of a method for preparing a coplanar resonant cavity coupled with a Josephson junction in an embodiment of the present disclosure;

[0029] Figure 2 is a schematic cross-sectional structural diagram of a first stacked structure formed on a substrate surface in an embodiment of the present disclosure;

[0030] Figure 3 is a schematic cross-sectional structural diagram of a first mask patterned on the surface of the second niobium layer in an embodiment of the present disclosure;

[0031] Figure 4 is a schematic cross-sectional structure diagram of the second niobium layer exposed in the Josephson junction region after etching in an embodiment of the present disclosure;

[0032] Figure 5 is a schematic cross-sectional structural diagram of a second stacked structure formed in a Josephson junction region in an embodiment of the present disclosure;

[0033] Figure 6 is a schematic cross-sectional structural diagram of the second stacked structure after debonding in an embodiment of the present disclosure;

[0034] Figure 7 is a schematic cross-sectional structural diagram of the protection of the second stacked structure in an embodiment of the present disclosure;

[0035] Figure 8 is a schematic diagram of the cross-sectional structure after etching the second niobium layer outside the Josephson junction region in the embodiment of the present disclosure;

[0036] Figure 9 is a schematic diagram of the cross-sectional structure of the aluminum-aluminum oxide layer after being etched by an alkaline developer in an embodiment of the present disclosure;

[0037] Figure 10 is a schematic diagram of the cross-sectional structure of a Josephson junction in an embodiment of the present disclosure;

[0038] Figure 11 is a schematic cross-sectional structural diagram of a second mask patterned on the surface of the first niobium layer in an embodiment of the present disclosure;

[0039] Figure 12 is a schematic diagram of the cross-sectional structure of the embodiment of the present disclosure after removing the first niobium layer exposed in the resonant cavity region and the bottom electrode region;

[0040] Figure 13 is a schematic diagram of the cross-sectional structure after the second mask is removed in the embodiment of the present disclosure;

[0041] Figure 14 is a schematic cross-sectional view of an insulating layer deposited on the surface of the second stacked structure in the Josephson junction region and the resonant cavity region in an embodiment of the present disclosure;

[0042] Figure 15 is a schematic cross-sectional structural diagram of depositing a conductor layer on the surface of an insulating layer in an embodiment of the present disclosure;

[0043] Figure 16 It is a schematic cross-sectional structure diagram of depositing a resistance layer in the bottom electrode region in an embodiment of the present disclosure.

[0044] In the drawings of this disclosure, the meanings of the reference numerals are:

[0045] 1-substrate; 2-first niobium layer; 3-aluminum-aluminum oxide layer; 4-second niobium layer; 5-photoresist mask structure; 6-niobium oxide; 7-aluminum oxide; 8-insulating layer; 9-conductor layer; 10-resistor layer. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0047] The endpoints of the ranges and any values ​​disclosed in this disclosure are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed in this disclosure.

[0048] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0049] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0050] It should be noted that, unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by persons of ordinary skill in the art to which this disclosure belongs. Where references to "first," "second," or the like are used throughout this disclosure, such references are intended solely to distinguish similar objects and should not be construed as indicating or implying their relative importance, order of precedence, or implicitly specifying the quantity of the technical features being referred to. References to "first," "second," or the like should be understood to be interchangeable where appropriate.

[0051] To make the purpose, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them.

[0052] Throughout the drawings, identical elements are represented by identical or similar reference numerals. Conventional structures or configurations are omitted where they may cause confusion in understanding the present disclosure. Furthermore, the shapes, sizes, and positional relationships of the components in the drawings do not reflect actual size, proportion, or actual positional relationships. Furthermore, any reference symbols placed between parentheses in this disclosure should not be construed as limiting the present disclosure.

[0053] Similarly, in order to streamline the present disclosure and aid in understanding one or more of the various disclosed aspects, in the above description of exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. Descriptions with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" and the like mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in an appropriate manner.

[0054] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this disclosure.

[0055] During the implementation of the present disclosure, it was found that, while ensuring a high-quality Josephson junction, the present disclosure ensured the roughness of the underlying second niobium layer 4 by pre-protecting the resonant cavity region and simultaneously etching the aluminum-aluminum oxide layer 3 (Al-AlOx) on the surface of the second niobium layer 4 with a developer, thereby providing a prerequisite for the preparation of a high-quality factor resonant cavity.

[0056] Figure 1 It is a flow chart of a method for preparing a coplanar resonant cavity coupled with a Josephson junction in an embodiment of the present disclosure.

[0057] The present disclosure provides a method for preparing a coplanar resonant cavity coupled with a Josephson junction, such as Figure 1 As shown, the following steps S101 to S106 are included:

[0058] Figure 2 It is a schematic cross-sectional structural diagram of a first stacked structure formed on the substrate surface in an embodiment of the present disclosure.

[0059] Step S101: Provide a substrate 1, such as Figure 2 As shown, a first stacked structure is formed on the surface of the substrate 1 , wherein the first stacked structure includes a first niobium layer 2 , an aluminum-aluminum oxide layer 3 and a second niobium layer 4 in sequence along a direction away from the substrate 1 .

[0060] Figure 3 is a schematic cross-sectional structure diagram of a first mask patterned on the surface of the second niobium layer 4 in an embodiment of the present disclosure; Figure 4 FIG. 4 is a schematic cross-sectional structural diagram of the second niobium layer 4 exposed in the Josephson junction region after etching in an embodiment of the present disclosure.

[0061] Step S102: Figure 3 As shown, a patterned first mask is formed on the surface of the second niobium layer 4 to define the Josephson junction region, and the portion outside the Josephson junction region is pre-protected by the first mask, as shown in FIG. Figure 4 As shown, the second niobium layer 4 is etched.

[0062] Figure 5 is a schematic cross-sectional structural diagram of a second stacked structure formed in a Josephson junction region in an embodiment of the present disclosure; Figure 6 It is a schematic diagram of the cross-sectional structure of the second stacked structure after debonding in the embodiment of the present disclosure.

[0063] Step S103: performing anodization to form a second stacked structure in the Josephson junction region, such as Figure 5 、 6 As shown, the second stacked structure includes niobium oxide 6, aluminum oxide 7, and niobium oxide 6.

[0064] Figure 7 is a schematic cross-sectional structural diagram of the protection of the second stacked structure in an embodiment of the present disclosure; Figure 8 is a schematic diagram of the cross-sectional structure after etching the second niobium layer 4 outside the Josephson junction region in the embodiment of the present disclosure; Figure 9 is a schematic diagram of the cross-sectional structure of the aluminum-aluminum oxide layer 3 after being etched by an alkaline developer in an embodiment of the present disclosure; Figure 10 Schematic diagram of the cross-sectional structure of the Josephson junction in the embodiment of the present disclosure.

[0065] Step S104: Figure 7 As shown, after removing the first mask, the second stacked structure is protected by a positive photoresist method, as shown in FIG. Figure 8 As shown, the second niobium layer 4 outside the Josephson junction region is etched to expose the aluminum-aluminum oxide layer 3 outside the Josephson junction region, as shown in FIG. Figure 9 As shown, the aluminum-aluminum oxide layer 3 is etched by an alkaline developer to expose the first niobium layer 2 without damaging the first niobium layer 2. Figure 10 As shown, a Josephson junction of a Nb / Al-AlOx / Nb three-layer film structure is formed.

[0066] Figure 11 is a schematic cross-sectional structural diagram of a second mask patterned on the surface of the first niobium layer 2 in an embodiment of the present disclosure; Figure 12 3 is a schematic diagram of the cross-sectional structure of the embodiment of the present disclosure after removing the exposed first niobium layer 2 in the resonant cavity region and the bottom electrode region.

[0067] Step S105: Figure 11 As shown, a patterned second mask is formed on the surface of the first niobium layer 2 to define the resonant cavity region and the bottom electrode region on both sides of the Josephson junction region, as shown in FIG. Figure 12As shown, the first niobium layer 2 is removed.

[0068] Figure 13 is a schematic diagram of the cross-sectional structure after the second mask is removed in the embodiment of the present disclosure; Figure 14 is a schematic cross-sectional structural diagram of an insulating layer 8 deposited on the surface of the second stacked structure in the Josephson junction region and the resonant cavity region in an embodiment of the present disclosure; Figure 15 1 is a schematic cross-sectional view of a conductive line layer 9 deposited on the surface of an insulating layer 8 in an embodiment of the present disclosure; Figure 16 1 is a schematic cross-sectional view of the resistive layer 10 deposited in the bottom electrode region in an embodiment of the present disclosure.

[0069] Step S106: Remove the second mask, the structure of which is as follows Figure 13 As shown; Figure 14 As shown, an insulating layer 8 is deposited on the surface of the second stacked structure in the Josephson junction region and the resonant cavity region, as shown in FIG. Figure 15 As shown, a conductor layer 9 is deposited on the surface of the insulating layer 8, as shown in FIG. Figure 16 As shown, a resistive layer 10 is deposited in the bottom electrode region.

[0070] According to the embodiments of the present disclosure, the core advantage of this preparation method lies in the precise removal of the aluminum-aluminum oxide layer 3 (Al-AlOx layer) using an alkaline developer etching technique, while also meticulously controlling the surface roughness of the underlying second niobium layer 4. This step ensures the roughness of the second niobium layer 4 within the resonant cavity, thereby reducing energy scattering and loss, directly improving the quality factor of the resonant cavity. Furthermore, by pre-protecting the resonant cavity region, unnecessary damage to this area during subsequent processing is effectively prevented. This protective measure helps maintain the integrity and cleanliness of the resonant cavity structure, minimizing the adverse effects of impurities or defects introduced during processing on the resonant cavity performance. The high-quality resonant cavity not only enhances the stability and sensitivity of the qubit but also optimizes signal transmission and coupling efficiency, providing a more reliable and efficient platform for quantum computing and quantum information processing.

[0071] In some specific embodiments, substrate 1 may be made of a high-resistance silicon material with a resistivity of no less than 10,000 Ω·cm. Furthermore, to minimize the impact of silicon oxide on the resonant cavity parameters, prior to depositing the first stacked structure, the oxide layer on the surface of substrate 1 is removed using hydrofluoric acid or a buffered oxide etchant (BOE), followed by rinsing with deionized water, drying, and baking.

[0072] According to the embodiments of the present disclosure, the thickness of the first niobium layer 2 is greater than 50-400 nm, the thickness of the second niobium layer 4 is greater than 50-400 nm, and the thickness of the aluminum-aluminum oxide layer is 2-20 nm. The stress of the first niobium layer 2 and the second niobium layer 4 are respectively -300-200 MPa, the roughness is less than 3 nm, the residual resistivity is greater than or equal to 3.5, and the transition temperature is greater than or equal to 9 K.

[0073] In some specific embodiments, in step S101, magnetron sputtering is used to deposit the first niobium layer 2, the aluminum-aluminum oxide layer 3, and the second niobium layer 4, respectively. The thin film deposition is carried out in the main chamber, and the aluminum-aluminum oxide layer oxidation is carried out in the sample chamber (loadlock). The first niobium layer 2 and the second niobium layer 4 are deposited using a four-inch target, wherein the deposition power is 600-900W and the gas pressure is 3.5-5.5mT. The aluminum-aluminum oxide layer is deposited using a three-inch target, wherein the deposition power is 150-200W and the gas pressure is 3.5-5.5mT. In this way, the thickness of the deposited first niobium layer 2 is more than 30nm, and the thickness of the aluminum-aluminum oxide layer is: 2-20nm. At the same time, because the current density (a) satisfies the following relationship (1) with the oxidation gas pressure (p) and time (t):

[0074] (P×t)-a, formula (1)

[0075] By adjusting the oxidation time and pressure, the current density meets the device requirements. The thickness of the second niobium layer 4 is at least 30nm. During the deposition process, the stress of the first and second niobium layers 2 and 4 is adjusted by adjusting the pressure and power, ultimately achieving film properties that meet the requirements of a stress range of -300 to 200 MPa, a roughness of less than 3nm, a residual resistivity of no less than 3.5, and a transition temperature of no less than 9K.

[0076] In some specific embodiments, in step S102, forming a patterned first mask on the surface of the second niobium layer 4 includes performing corresponding operations such as photoresist coating, photolithography, development, and baking on the surface of the second niobium layer 4 to define the Josephson junction region and the resonant cavity region. The purpose of pre-protecting the resonant cavity region is to prevent the introduction of niobium oxide 6 during the subsequent anodization process, which could affect the resonant cavity quality factor. The photoresist in the first mask is a positive photoresist, and the photolithography can employ exposure methods such as UV contact exposure and laser direct writing.

[0077] According to the embodiments of the present disclosure, pre-protecting the resonant cavity region effectively prevents unnecessary damage to the region during subsequent processing. This protective measure helps maintain the integrity and cleanliness of the resonant cavity structure and reduces the adverse effects of impurities or defects introduced during processing on the resonant cavity performance.

[0078] In some specific embodiments, in step S102, etching the second niobium layer 4 includes etching the second niobium layer 4 using reactive ion etching (RIE) and inductively coupled plasma (ICP) etching techniques. An endpoint detection marker is also used to determine the etching extent of the second niobium layer 4 based on changes in the endpoint detection etching curve. To ensure complete etching, the second niobium layer 4 is typically overetched by 10-15%.

[0079] According to an embodiment of the present disclosure, during the anodization process in step S103 , the electrolyte is a mixed solution of ammonium pentaborate, ethylene glycol, and deionized water.

[0080] According to an embodiment of the present disclosure, after etching is completed, the first stacked structure is anodized to repair damage caused by the Nb etching process. The degree of oxidation depends on the degree of damage to the second niobium layer 4 during the etching process. The more the second niobium layer 4 is overetched, the greater the degree of oxidation.

[0081] In some specific embodiments, in step S104, etching the second niobium layer 4 outside the Josephson junction region includes etching the second niobium layer 4 using reactive ion etching (RIE) and inductively coupled plasma (ICP) etching techniques. An endpoint detection marker is also used to determine the etching extent of the second niobium layer 4 based on changes in the endpoint detection etching curve. To ensure complete etching, the second niobium layer 4 is typically overetched by 10-15%.

[0082] According to an embodiment of the present disclosure, in step S104, the operation of corroding the aluminum-aluminum oxide layer 3 by using an alkaline developer includes: mixing the alkaline developer and deionized water in a volume ratio of 1:4, adding the mixture dropwise to the aluminum-aluminum oxide layer 3 outside the Josephson junction region, oscillating the aluminum-aluminum oxide layer outside the Josephson junction region to form a complex with the alkaline developer, and rinsing and removing the aluminum-aluminum oxide layer outside the Josephson junction region.

[0083] According to the embodiments of the present disclosure, the aluminum-aluminum oxide layer 3 (Al-AlOx) on the surface of the second niobium layer 4 is etched using a developer solution, allowing the surface roughness of the underlying second niobium layer 4 to be precisely controlled and improved. Lower surface roughness helps reduce scattering losses in the resonant cavity, thereby improving the cavity's quality factor (Q). An improved Q factor means the cavity can more efficiently store energy and reduce energy dissipation, which is crucial for enhancing the sensitivity and stability of quantum devices.

[0084] According to an embodiment of the present disclosure, the alkaline developer is a potassium hydroxide solution with a mass concentration of 5%.

[0085] In some specific embodiments, in step S105, forming a patterned second mask on the surface of the first niobium layer 2 includes applying a photoresist to protect the Josephson junction region, where the protected area is larger than the junction area to prevent damage to the junction region during subsequent etching. The photoresist is a positive photoresist, and the photolithography can employ an exposure method such as UV contact exposure or laser direct writing.

[0086] In some specific embodiments, in step S105, removing the first niobium layer 2 includes etching the first niobium layer 2 using reactive ion etching (RIE) and inductively coupled plasma (ICP) etching techniques. An endpoint detection marker is used to determine the etching extent of the first niobium layer 2 based on changes in the endpoint detection etching curve.

[0087] According to an embodiment of the present disclosure, the first mask and the second mask are positive photoresists.

[0088] In some specific embodiments, the method for removing the adhesive from the first mask and the second mask is: ultrasonically cleaning and removing the adhesive using acetone, isopropyl alcohol, and deionized water in sequence, and then drying.

[0089] According to an embodiment of the present disclosure, a method for depositing the insulating layer 8 includes:

[0090] A patterned third mask is formed in the Josephson junction region and the resonant cavity region to define the insulating layer 8 region. The third mask is a negative photoresist. The insulating layer 8 region includes a through-hole region. The through-hole region includes a junction region through-hole and a cavity region through-hole. The junction region through-hole is located on the second niobium layer 4 in the Josephson junction region, and the cavity region through-hole is located on the insulating layer 8 in the resonant cavity region.

[0091] Silicon dioxide is deposited in the insulating layer 8 region to form the insulating layer 8 .

[0092] According to the embodiment of the present disclosure, to avoid the degradation of the surface roughness of the first niobium layer 2 due to subsequent etching, which would lead to a reduction in the resonant cavity quality factor, the third mask uses a reverse photoresist, and a subsequent lift-off process is used. The photolithography can use exposure methods such as ultraviolet contact exposure and laser direct writing.

[0093] In some specific embodiments, thermal evaporation is used to deposit silicon dioxide to form the insulating layer 8, so as to facilitate subsequent stripping. The stripping is performed using acetone, isopropyl alcohol, deionized water, ultrasonic treatment, and drying.

[0094] According to an embodiment of the present disclosure, the preparation of the wire layer 9 includes:

[0095] Niobium is deposited on the surface of the insulating layer 8 in the Josephson junction region and the resonant cavity region to form a wire layer 9, which wraps the insulating layer 8 in the Josephson junction region and the resonant cavity region.

[0096] According to an embodiment of the present disclosure, the method for preparing the conductive line layer 9 further includes:

[0097] Before depositing the wire layer 9 , a radio frequency source is used to pre-treat the surfaces of the Josephson junction region and the resonant cavity region to remove the insulating layer 8 on the surface of the first niobium layer 2 .

[0098] According to the embodiment of the present disclosure, before the deposition of the conductive layer 9, the surface of the Josephson junction region and the resonant cavity region is pretreated using a radio frequency source to remove silicon oxide from the surface of the first niobium layer 2, thereby improving conductivity. The stripping process is performed using acetone, isopropyl alcohol, and deionized water ultrasonic treatment, followed by drying.

[0099] According to an embodiment of the present disclosure, the method for preparing the resistance layer 10 includes: pre-depositing titanium as an adhesion layer in the bottom electrode region, and then depositing palladium gold on the adhesion layer to form the resistance layer 10 .

[0100] In some specific embodiments, before depositing the resistor layer 10, the sample surface is pretreated using a radio frequency source to remove silicon oxide from the surface of the first niobium layer 2, enhancing conductivity. Before depositing the PdAu layer 10, a Ti adhesion layer is pre-deposited to enhance connectivity. Debonding is performed using acetone, isopropyl alcohol, and deionized water, followed by ultrasonic drying.

[0101] According to the embodiments of the present disclosure, the method for preparing a coplanar resonant cavity coupled with a Josephson junction proposed in this disclosure effectively improves the preparation quality of the coplanar resonant cavity coupled with a Josephson junction through a series of innovative process steps, providing strong support for the development of quantum computing and quantum information processing. The process steps used are relatively simple and easy to control, with high process compatibility and scalability. This means that it can be applied on different quantum chip platforms and provide technical support for the preparation of larger-scale and more complex quantum circuits in the future.

[0102] It should be noted that the embodiments described are only part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, other embodiments obtained by ordinary technicians in this field without making creative work are all within the scope of protection of the present disclosure.

[0103] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for preparing a coplanar resonant cavity coupled with a Josephson junction, comprising: Providing a substrate, and forming a first stacked structure on a surface of the substrate, wherein the first stacked structure includes, in a direction away from the substrate, a first niobium layer, an aluminum-aluminum oxide layer, and a second niobium layer in sequence; forming a patterned first mask on the surface of the second niobium layer to define a Josephson junction region, and pre-protecting and etching a portion outside the Josephson junction region through the first mask; performing anodization to form a second stacked structure in the Josephson junction region, wherein the second stacked structure includes niobium oxide, aluminum oxide, and niobium oxide; After removing the first mask, the second stacked structure is protected by a positive photoresist method, the second niobium layer outside the Josephson junction region is etched to expose the aluminum-aluminum oxide layer outside the Josephson junction region, and the aluminum-aluminum oxide layer is corroded by an alkaline developer to expose the first niobium layer without damaging the first niobium layer. The etching of the aluminum-aluminum oxide layer by the alkaline developer comprises: mixing the alkaline developer with deionized water, adding the mixture dropwise to the aluminum-aluminum oxide layer outside the Josephson junction region, shaking the mixture so that the aluminum-aluminum oxide layer outside the Josephson junction region forms a complex with the alkaline developer, and then rinsing to remove the aluminum-aluminum oxide layer outside the Josephson junction region. forming a patterned second mask on the surface of the first niobium layer to respectively define a resonant cavity region and a bottom electrode region located on both sides of the Josephson junction region and remove the first niobium layer; An insulating layer is deposited on the surface of the second stacked structure in the Josephson junction region and the resonant cavity region, a wire layer is deposited on the surface of the insulating layer, and a resistor layer is deposited in the bottom electrode region.

2. The preparation method according to claim 1, wherein The alkaline developer is a potassium hydroxide solution with a mass concentration of 5%.

3. The preparation method according to claim 1, wherein The thickness of the first niobium layer is greater than 30 nm, the thickness of the second niobium layer is greater than 30 nm, and the thickness of the aluminum-aluminum oxide layer is 2-20 nm. The stress of the first niobium layer and the second niobium layer are respectively -300 to 200 MPa, the roughness is less than 3 nm, the residual resistivity is greater than or equal to 3.5, and the transition temperature is greater than or equal to 9 K.

4. The preparation method according to claim 1, wherein During the anodic oxidation process, the electrolyte is a mixed solution of ammonium pentaborate, ethylene glycol and deionized water.

5. The preparation method according to claim 1, wherein The first mask and the second mask are positive photoresists.

6. The preparation method according to claim 1, wherein The insulating layer deposition method comprises: A patterned third mask is formed in the Josephson junction region and the resonant cavity region to define an insulating layer region, wherein the third mask is a negative photoresist, wherein the insulating layer region includes a through-hole region, the through-hole region includes a junction region through-hole and a cavity region through-hole, the junction region through-hole is located on the second niobium layer in the Josephson junction region, and the cavity region through-hole is located on the insulating layer in the resonant cavity region; Silicon dioxide is deposited in the insulating layer region to form an insulating layer.

7. The preparation method according to claim 1, wherein The preparation of the conductor layer includes: Niobium is deposited on the surface of the insulating layer in the Josephson junction region and the resonant cavity region to form the wire layer, and the wire layer wraps the insulating layer in the Josephson junction region and the resonant cavity region.

8. The preparation method according to claim 7, wherein The method for preparing the conductor layer further comprises: Before depositing the wire layer, a radio frequency source is used to pre-treat the surfaces of the Josephson junction region and the resonant cavity region to remove the insulating layer on the surface of the first niobium layer.

9. The preparation method according to claim 1, wherein The method for preparing the resistance layer includes: pre-depositing titanium as an adhesion layer in the bottom electrode area, and then depositing palladium gold on the adhesion layer to form a resistance layer.

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