Display device, gate driving circuit, shift register unit and driving method thereof

Abstract

The invention discloses a display device, a gate driving circuit, a shift register unit and a driving method thereof. The shift register unit comprises an input sub-circuit (1) used for controlling the potential of a first node (Q (N)) under the potential control of an input control end CR (N-2); the signal output sub-circuit (2) is used for controlling a clock signal end to be disconnected or connected with a corresponding signal output end under the potential control of the first node (Q (N)); and the first control sub-circuit (3) is used for controlling the potential of the first node (Q (N)) under the potential control of the first control signal end (CL).

Description

Display device, gate driving circuit, shift register unit and driving method thereof Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display device, a gate driving circuit, a shift register unit, and a driving method thereof. Background Art

[0002] A gate drive circuit is an important auxiliary circuit in a display device. Existing gate drive circuits include multiple cascaded shift register units. However, this gate drive circuit needs to be improved.

[0003] Summary of the Invention

[0004] The present disclosure aims to provide a display device, a gate driving circuit, a shift register unit and a driving method thereof.

[0005] According to one aspect of the present disclosure, there is provided a shift register unit, comprising:

[0006] an input subcircuit connected to the input control terminal and the first node, and configured to control the potential of the first node under the potential control of the input control terminal;

[0007] a signal output subcircuit connected to the first node and to a plurality of signal output terminals and a plurality of clock signal terminals, wherein the plurality of signal output terminals correspond to the plurality of clock signal terminals; the signal output subcircuit is configured to control the clock signal terminals to be disconnected or connected to the corresponding signal output terminals under the control of the potential of the first node; the plurality of signal output terminals correspondingly output a plurality of output signals, and the plurality of output signals are sequentially shifted;

[0008] A first control subcircuit is connected to a first control signal terminal and the first node, and is used to control the potential of the first node under the potential control of the first control signal terminal; the first control signal terminal is used to output a control signal; in a display frame, the end time of the effective potential interval of the last output signal among the multiple output signals shifted sequentially is greater than or equal to the start time of the effective potential interval of the control signal, and the end time of the effective potential interval of the last output signal among the multiple output signals shifted sequentially is less than the end time of the effective potential interval of the control signal.

[0009] Furthermore, the first control subcircuit includes a first control transistor connected between the first control signal terminal and the first node.

[0010] Furthermore, the first control subcircuit includes a coupling capacitor, a first electrode of the coupling capacitor is connected to the first control signal terminal, and a second electrode of the coupling capacitor is connected to the first node.

[0011] Furthermore, the shift register unit further includes:

[0012] The cascade output sub-circuit is connected to the first node and the cascade output terminal, and is used to control the potential of the cascade output terminal under the control of the potential of the first node.

[0013] Furthermore, the shift register unit further includes:

[0014] a denoising subcircuit, connected to the second node and the reset power supply terminal, and connected to at least one of the cascade output terminal, the first node, and the signal output terminal, and configured to control the reset power supply terminal to be disconnected from or connected to the signal output terminal under the potential control of the second node, and also to control the reset power supply terminal to be disconnected from or connected to the cascade output terminal under the potential control of the second node, and also to control the reset power supply terminal to be disconnected from or connected to the first node under the potential control of the second node.

[0015] Furthermore, the shift register unit further includes:

[0016] The inverting sub-circuit is connected to the first node and the second node, and is used to control the potential of the first node to be opposite to the potential of the second node.

[0017] Furthermore, the shift register unit further includes:

[0018] The first reset sub-circuit is connected to the display reset signal terminal, the reset power terminal and the first node, and is used to control the reset power terminal to be disconnected or connected to the first node under the potential control of the display reset signal terminal.

[0019] Furthermore, the shift register unit further includes:

[0020] The second reset sub-circuit is connected to the global reset signal terminal, the reset power terminal and the first node, and is used to control the reset power terminal to be disconnected or connected to the first node under the potential control of the global reset signal terminal.

[0021] Furthermore, the shift register unit further includes:

[0022] a compensation control subcircuit connected to the input control terminal, the compensation control signal terminal, and the third node, and configured to control the input control terminal to be disconnected from or connected to the third node under the control of the potential of the compensation control signal terminal;

[0023] The compensation output subcircuit is connected to the third node, the fourth node, the clock signal terminal and the first node, and is used to control the clock signal terminal to be disconnected or connected with the fourth node under the potential control of the third node, and is also used to control the fourth node to be disconnected or connected with the first node under the potential control of the clock signal terminal.

[0024] Furthermore, the first control subcircuit further includes a second control transistor, wherein the first electrode and the control electrode of the first control transistor are connected to the first control signal terminal, the first electrode of the second control transistor is connected to the second electrode of the first control transistor, the control electrode of the second control transistor is connected to the first control signal terminal, and the second electrode of the second control transistor is connected to the first node;

[0025] The shift register unit further includes:

[0026] A first anti-leakage transistor, wherein a first electrode of the first anti-leakage transistor is connected to a fixed power supply terminal, a second electrode of the first anti-leakage transistor is connected to a second electrode of the first control transistor, and a control electrode of the first anti-leakage transistor is connected to the first node.

[0027] Further, in a display frame, the effective potential interval of the control signal is located within the effective potential interval of the first node.

[0028] According to one aspect of the present disclosure, a gate driving circuit is provided, comprising the shift register unit.

[0029] According to one aspect of the present disclosure, a display device is provided, comprising the gate driving circuit.

[0030] According to one aspect of the present disclosure, a driving method for a shift register unit is provided. The driving method adopts the shift register unit, and the driving method includes:

[0031] enabling the input sub-circuit to control the potential of the first node under the potential control of the input control terminal;

[0032] The signal output subcircuit controls the clock signal terminal and the corresponding signal output terminal to be disconnected or connected under the potential control of the first node;

[0033] The first control sub-circuit is enabled to control the potential of the first node under the potential control of the first control signal terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic diagram of a shift register unit according to an embodiment of the present disclosure.

[0035] FIG2 is a circuit diagram of a shift register unit according to an embodiment of the present disclosure.

[0036] FIG3 is a schematic diagram of the circuit diagram shown in FIG2 on the left side of the dotted line L1.

[0037] FIG. 4 is a schematic diagram on the right side of the dotted line L1 in the circuit diagram shown in FIG. 2 .

[0038] 5 and 6 are timing diagrams of clock signals and control signals.

[0039] 7 to 10 are partial schematic diagrams of the shift register unit in the embodiment of the present disclosure.

[0040] FIG11 is an operation timing diagram of the gate driving circuit according to an embodiment of the present disclosure.

[0041] FIG12 is a schematic diagram of a simulation of an output signal of a shift register unit according to an embodiment of the present disclosure.

[0042] Explanation of the accompanying symbols: 1. input subcircuit; 2. signal output subcircuit; 3. first control subcircuit; 4. cascade output subcircuit; 5. inverting subcircuit; 6. denoising subcircuit; 7. first reset subcircuit; 8. second reset subcircuit; 9. compensation control subcircuit; 10. compensation output subcircuit; 11. second control subcircuit; M1. first input transistor; M2. second input transistor; M3. first output transistor; M4. second output transistor; M5. third output transistor; M6. fourth output transistor; M7. first control transistor; M8. second control transistor M9, cascade output transistor; M10, third control transistor; M11, first reset transistor; M12, second reset transistor; M13, third reset transistor; M14, fourth reset transistor; M15, first de-noising transistor; M16, second de-noising transistor; M17, third de-noising transistor; M18, fourth de-noising transistor; M19, fifth de-noising transistor; M20, sixth de-noising transistor; M21, seventh de-noising transistor; M22, first inverting transistor; M23, second inverting transistor; M24, third inverting transistor; M36, fourth inverting transistor body tube; M25, first compensation control transistor; M26, second compensation control transistor; M27, first compensation output transistor; M28, second compensation output transistor; M29, third compensation output transistor; M30, second anti-leakage transistor; M31, first anti-leakage transistor; M32, third anti-leakage transistor; M33, first auxiliary transistor; M34, second auxiliary transistor; M35, third auxiliary transistor; C1, first energy storage capacitor; C2, second energy storage capacitor; C3, third energy storage capacitor; C4, coupling capacitor; Q(N), first node; QB, second Node; N1, third node; N2, fourth node; CR(N-2), input control terminal; OE, compensation control signal terminal; CL, first control signal terminal; TRST, global reset signal terminal; CR(N+10), display reset signal terminal; CR(N+2), cascade output terminal; G(N), Nth signal output terminal; G(N+1), (N+1)th signal output terminal; G(N+2), (N+2)th signal output terminal; G(N+3), (N+3)th signal output terminal; CLKE, clock signal terminal; VGL, reset power supply terminal; GVDD, fixed power supply terminal. DETAILED DESCRIPTION

[0043] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0044] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and similar words used in this disclosure and the claims do not denote any order, quantity, or importance, but are simply used to distinguish different components. Similarly, the terms "a" or "an" and similar words do not denote a limitation of quantity, but rather denote the presence of at least one. The terms "plurality" or "several" mean two or more. The terms "include" or "comprising" and similar words mean that the elements or objects preceding the term "include" or "comprising" include the elements or objects listed after the term "include" or "comprising," and their equivalents, and do not exclude other elements or objects. As used in this disclosure and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0045] The transistors used in the present disclosure may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the control electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0046] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0047] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0048] The present disclosure provides a shift register unit for a gate drive circuit. The gate drive circuit may include multiple cascaded shift registers. The gate drive circuit is used in a display device. As shown in Figures 1 to 4, the shift register unit may include an input subcircuit 1, a first control subcircuit 3, and a signal output subcircuit 2, wherein:

[0049] The input subcircuit 1 is connected to the input control terminal CR(N-2) and the first node Q(N), and is used to control the potential of the first node Q(N) under the potential control of the input control terminal CR(N-2). The signal output subcircuit 2 is connected to the first node Q(N) and is connected to multiple signal output terminals [G(N) to G(N+3) in Figure 1] and multiple clock signal terminals (CLKE1 to CLKE4 in Figure 1). The multiple signal output terminals correspond to the multiple clock signal terminals. The signal output subcircuit 2 is used to control the clock signal terminals to disconnect or connect with the corresponding signal output terminals under the potential control of the first node Q(N). As shown in Figures 5 and 6, the multiple clock signal terminals (CLKE1 to CLKE4) output multiple clock signals in a corresponding manner, and the multiple clock signals are shifted sequentially; the multiple signal output terminals [G(N) to G(N+3)] output multiple output signals in a corresponding manner, and the multiple output signals are shifted sequentially. The first control subcircuit 3 is connected to the first control signal terminal CL and the first node Q(N), and is configured to control the potential of the first node Q(N) under the potential control of the first control signal terminal CL. The first control signal terminal CL is configured to output a control signal. As shown in FIG5 and FIG6 , in a display frame, the end time of the effective potential interval T3 of the last output signal among the plurality of sequentially shifted output signals is greater than or equal to the start time of the effective potential interval T2 of the control signal, and the end time of the effective potential interval T3 of the last output signal among the plurality of sequentially shifted output signals is less than the end time of the effective potential interval T2 of the control signal.

[0050] In the shift register unit of the embodiment of the present disclosure, in a display frame, the end time of the effective potential interval T3 of the last output signal among the multiple output signals shifted sequentially is greater than or equal to the start time of the effective potential interval T2 of the control signal, and the end time of the effective potential interval T3 of the last output signal among the multiple output signals shifted sequentially is less than the end time of the effective potential interval T2 of the control signal. Therefore, at the end time of the effective potential interval T3 of the last output signal among the multiple output signals, the potential of the first node Q(N) can be compensated by the control signal to shorten the falling edge time of the signal output by the signal output terminal G(N+3) corresponding to the last clock signal, avoid the generation of GOA horizontal stripes, and improve the display effect.

[0051] The following describes in detail the various parts of the shift register unit according to the embodiment of the present disclosure:

[0052] As shown in Figure 1, the input sub-circuit 1 is connected to the input control terminal CR (N-2) and the first node Q (N), and is used to control the potential of the first node Q (N) under the potential control of the input control terminal CR (N-2). For example, as shown in Figures 2 and 3, the input sub-circuit 1 may include a first input transistor M1 and a second input transistor M2. The control electrode of the first input transistor M1 is connected to the input control terminal CR (N-2), and the first electrode of the first input transistor M1 is connected to the input control terminal CR (N-2). The control electrode of the second input transistor M2 is connected to the input control terminal CR (N-2), the first electrode of the second input transistor M2 is connected to the second electrode of the first input transistor M1, and the second electrode of the second input transistor M2 is connected to the first node Q (N). It should be noted that for the first-stage shift register in the gate drive circuit, since there is no cascaded shift register before the first-stage shift register. The input control terminal CR (N-2) can input a start signal,

[0053] As shown in Figures 2 and 3, the shift register unit of the present disclosure may further include a compensation control subcircuit 9 and a compensation output subcircuit 10. The compensation control subcircuit 9 is connected to the input control terminal CR(N-2), the compensation control signal terminal OE, and the third node N1, and is configured to control the input control terminal CR(N-2) to be disconnected from or connected to the third node N1 under the control of the potential of the compensation control signal terminal OE. The compensation output subcircuit 10 is connected to the third node N1, the fourth node N2, the clock signal terminal CLKA, and the first node Q(N), and is configured to control the clock signal terminal CLKA to be disconnected from or connected to the fourth node N2 under the control of the potential of the third node N1, and is further configured to control the fourth node N2 to be disconnected from or connected to the first node Q(N) under the control of the potential of the clock signal terminal CLKA.

[0054] For example, as shown in Figures 2 and 3, the compensation control subcircuit 9 may include a first compensation control transistor M25 and a second compensation control transistor M26. The control electrode of the first compensation control transistor M25 is connected to the compensation control signal terminal OE, and the first electrode of the first compensation control transistor M25 is connected to the input control terminal CR(N-2). The control electrode of the second compensation control transistor M26 is connected to the compensation control signal terminal OE, the first electrode of the second compensation control transistor M26 is connected to the second electrode of the first compensation control transistor M25, and the second electrode of the second compensation control transistor M26 is connected to the third node N1. In addition, the compensation control subcircuit 9 may further include a third energy storage capacitor C3. The third energy storage capacitor C3 may be connected between the third node N1 and the reset power supply terminal VGL1. In Figures 8, 9, and 10, the first electrode of the first compensation control transistor M25 may be connected to the signal terminal CR(N-4).

[0055] For example, as shown in Figures 2 and 3, the compensation output sub-circuit 10 may include a first compensation output transistor M27, a second compensation output transistor M28, and a third compensation output transistor M29. The control electrode of the first compensation output transistor M27 is connected to the third node N1, the first electrode of the first compensation output transistor M27 is connected to the clock signal terminal CLKA, and the second electrode of the first compensation output transistor M27 is connected to the fourth node N2. The control electrode of the second compensation output transistor M28 is connected to the clock signal terminal CLKA, and the first electrode of the second compensation output transistor M28 is connected to the fourth node N2. The control electrode of the third compensation output transistor M29 is connected to the clock signal terminal CLKA, the first electrode of the third compensation output transistor M29 is connected to the second electrode of the second compensation output transistor M28, and the second electrode of the third compensation output transistor M29 is connected to the first node Q(N).

[0056] As shown in Figures 2 and 4, the signal output subcircuit 2 is connected to the first node Q(N) and is connected to multiple signal output terminals [G(N) to G(N+3)] and multiple clock signal terminals (CLKE1 to CLKE4). The multiple signal output terminals [G(N) to G(N+3)] correspond to the multiple clock signal terminals (CLKE1 to CLKE4). The signal output subcircuit 2 is used to control the clock signal terminals (CLKE1 to CLKE4) to be disconnected or connected to the corresponding signal output terminals [G(N) to G(N+3)] under the potential control of the first node Q(N). The number of the signal output terminals and the clock signal terminals can both be four. The plurality of signal output terminals may include an Nth signal output terminal G(N), an (N+1)th signal output terminal G(N+1), an (N+2)th signal output terminal G(N+2), and an (N+3)th signal output terminal G(N+3). The plurality of clock signal terminals may include a clock signal terminal CLKE1, a clock signal terminal CLKE2, a clock signal terminal CLKE3, and a clock signal terminal CLKE4. The plurality of clock signal terminals correspondingly output a plurality of clock signals, and the plurality of clock signals are sequentially shifted (see FIG5 and FIG6 ), and each clock signal includes a plurality of valid potential intervals T1. For any two adjacent clock signals in the sequentially shifted plurality of clock signals, the plurality of valid potential intervals T1 of one clock signal correspond one-to-one with the plurality of valid potential intervals T1 of the other clock signal, and each valid potential interval T1 overlaps with the corresponding valid potential interval T1, and the duration of the overlapping region may be half the duration of an effective potential interval T1.

[0057] As shown in Figures 2 and 4, the signal output sub-circuit 2 may include a first output transistor M3, a second output transistor M4, a third output transistor M5, and a fourth output transistor M6. The control electrode of the first output transistor M3 is connected to the first node Q(N), the first electrode of the first output transistor M3 is connected to the clock signal terminal CLKE1, and the second electrode of the first output transistor M3 is connected to the Nth signal output terminal G(N). The control electrode of the second output transistor M4 is connected to the first node Q(N), the first electrode of the second output transistor M4 is connected to the clock signal terminal CLKE2, and the second electrode of the second output transistor M4 is connected to the (N+1)th signal output terminal G(N+1). The control electrode of the third output transistor M5 is connected to the first node Q(N), the first electrode of the third output transistor M5 is connected to the clock signal terminal CLKE3, and the second electrode of the third output transistor M5 is connected to the (N+2)th signal output terminal G(N+2). The control electrode of the fourth output transistor M6 is connected to the first node Q(N), the first electrode of the fourth output transistor M6 is connected to the clock signal terminal CLKE4, and the second electrode of the fourth output transistor M6 is connected to the (N+3)th signal output terminal G(N+3). In addition, the signal output sub-circuit 2 may further include multiple first energy storage capacitors C1, each of which is connected between the first node Q(N) and each signal output terminal.

[0058] As shown in Figures 2 and 4, the shift register unit may further include a cascade output subcircuit 4. The cascade output subcircuit 4 is connected to the first node Q(N) and the cascade output terminal CR(N+2), and is used to control the potential of the cascade output terminal CR(N+2) under the potential control of the first node Q(N). For example, the cascade output subcircuit 4 may include a cascade output transistor M9, the control electrode of the cascade output transistor M9 is connected to the first node Q(N), the first electrode of the cascade output transistor M9 is connected to the clock signal terminal CLKD, and the second electrode of the cascade output transistor M9 is connected to the cascade output terminal CR(N+2). In addition, the cascade output subcircuit 4 may further include a second energy storage capacitor C2, which may be connected between the first node Q(N) and the cascade output terminal CR(N+2). In other embodiments of the present disclosure, the cascade output terminal may also be CR(N+4).

[0059] As shown in Figures 2, 3, and 4, the shift register unit of the embodiment of the present disclosure may further include a denoising sub-circuit 6. The denoising sub-circuit 6 is connected to the second node QB and the reset power supply terminals (VGL1, VGL2), and is also connected to at least one of the cascade output terminal CR(N+2), the first node Q(N), and the signal output terminal. The denoising sub-circuit 6 is configured to control the reset power supply terminal VGL2 to be disconnected from or connected to the signal output terminal under the potential control of the second node QB, to control the reset power supply terminal VGL1 to be disconnected from or connected to the cascade output terminal CR(N+2), and to control the reset power supply terminal VGL1 to be disconnected from or connected to the first node Q(N) under the potential control of the second node QB.

[0060] For example, as shown in Figures 3 and 4, the denoising sub-circuit 6 may include a first denoising transistor M15, a second denoising transistor M16, a third denoising transistor M17, a fourth denoising transistor M18, a fifth denoising transistor M19, a sixth denoising transistor M20, and a seventh denoising transistor M21. The control electrode of the first denoising transistor M15 is connected to the second node QB, the first electrode of the first denoising transistor M15 is connected to the reset power supply terminal VGL2, and the second electrode of the first denoising transistor M15 is connected to the Nth signal output terminal G(N). The control electrode of the second denoising transistor M16 is connected to the second node QB, the first electrode of the second denoising transistor M16 is connected to the reset power supply terminal VGL2, and the second electrode of the second denoising transistor M16 is connected to the (N+1)th signal output terminal G(N+1). The control electrode of the third de-noising transistor M17 is connected to the second node QB, the first electrode of the third de-noising transistor M17 is connected to the reset power supply terminal VGL2, and the second electrode of the third de-noising transistor M17 is connected to the (N+2)th signal output terminal G(N+2). The control electrode of the fourth de-noising transistor M18 is connected to the second node QB, the first electrode of the fourth de-noising transistor M18 is connected to the reset power supply terminal VGL2, and the second electrode of the fourth de-noising transistor M18 is connected to the (N+3)th signal output terminal G(N+3). The control electrode of the fifth de-noising transistor M19 is connected to the second node QB, the first electrode of the fifth de-noising transistor M19 is connected to the reset power supply terminal VGL1, and the second electrode of the fifth de-noising transistor M19 is connected to the cascade output terminal CR(N+2). As shown in FIG3 , the control electrode of the sixth de-noising transistor M20 and the control electrode of the seventh de-noising transistor M21 are both connected to the second node QB, the first electrode of the sixth de-noising transistor M20 is connected to the reset power supply terminal VGL1, the first electrode of the seventh de-noising transistor M21 is connected to the second electrode of the sixth de-noising transistor M20, and the second electrode of the seventh de-noising transistor M21 is connected to the first node Q(N).

[0061] As shown in Figures 2 and 3, the shift register unit of the embodiment of the present disclosure may further include an inverting sub-circuit 5. The inverting sub-circuit 5 is used to control the potential of the first node Q(N) to be opposite to the potential of the second node QB. For example, the inverting sub-circuit 5 may include a first inverting transistor M22, a second inverting transistor M23, a third inverting transistor M24, and a fourth inverting transistor M36. The control electrode of the first inverting transistor M22 is connected to the first node Q(N), the first electrode of the first inverting transistor M22 is connected to the reset power supply terminal VGL1, and the second electrode of the first inverting transistor M22 is connected to the second node QB. The control electrode of the second inverting transistor M23 is connected to the input control terminal CR(N-2), the first electrode of the second inverting transistor M23 is connected to the reset power supply terminal VGL1, and the second electrode of the second inverting transistor M23 is connected to the second node QB. The control electrode of the third inverting transistor M24 is connected to the third node N1, the first electrode of the third inverting transistor M24 is connected to the reset power supply terminal VGL1, the control electrode of the fourth inverting transistor M36 is connected to the clock signal terminal CLKA, the first electrode of the fourth inverting transistor M36 is connected to the second electrode of the third inverting transistor M24, and the second electrode of the fourth inverting transistor M36 is connected to the second node QB.

[0062] As shown in Figures 2 and 3, the shift register unit of the embodiment of the present disclosure may further include a first reset sub-circuit 7. The first reset sub-circuit 7 may be connected to the display reset signal terminal CR(N+10), the reset power supply terminal VGL1, and the first node Q(N), and is configured to control the disconnection or connection between the reset power supply terminal VGL and the first node Q(N) under the control of the potential of the display reset signal terminal CR(N+10). The first reset sub-circuit 7 may include a first reset transistor M11 and a second reset transistor M12. The first electrode of the second reset transistor M12 is connected to the reset power supply terminal VGL1, the control electrode of the second reset transistor M12 is connected to the display reset signal terminal CR(N+10), the first electrode of the first reset transistor M11 is connected to the second electrode of the second reset transistor M12, the second electrode of the first reset transistor M11 is connected to the first node Q(N), and the control electrode of the first reset transistor M11 is connected to the display reset signal terminal CR(N+10).

[0063] As shown in Figures 2 and 3, the shift register unit of the embodiment of the present disclosure may further include a second reset sub-circuit 8. The second reset sub-circuit 8 may be connected to the global reset signal terminal TRST, the reset power supply terminal VGL1, and the first node Q(N), and is configured to control the reset power supply terminal VGL1 to be disconnected or connected to the first node Q(N) under the potential control of the global reset signal terminal TRST. The first reset sub-circuit 7 may include a third reset transistor M13 and a fourth reset transistor M14. The first electrode of the fourth reset transistor M14 is connected to the reset power supply terminal VGL1, the control electrode of the fourth reset transistor M14 is connected to the global reset signal terminal TRST, the first electrode of the third reset transistor M13 is connected to the second electrode of the fourth reset transistor M14, the second electrode of the third reset transistor M13 is connected to the first node Q(N), and the control electrode of the third reset transistor M13 is connected to the global reset signal terminal TRST.

[0064] As shown in Figures 7 and 8, the shift register unit of the embodiment of the present disclosure may include a first anti-leakage transistor M31. The first electrode of the first anti-leakage transistor M31 is connected to the fixed power supply terminal GVDD2, the control electrode of the first anti-leakage transistor M31 is connected to the first node Q(N), and the second electrode of the first anti-leakage transistor M31 can be connected to the second electrode of the first input transistor M1. The shift register unit may also include a second anti-leakage transistor M30. The first electrode of the second anti-leakage transistor M30 is connected to the fixed power supply terminal GVDD1, the control electrode of the second anti-leakage transistor M30 is connected to the third node N1, and the second electrode of the second anti-leakage transistor M30 can be connected to the second electrode of the first compensation control transistor M25.

[0065] As shown in Figures 9 and 10, the shift register unit of the embodiment of the present disclosure may include a first anti-leakage transistor M31 and a third anti-leakage transistor M32. The first electrode of the third anti-leakage transistor M32 is connected to the fixed power supply terminal GVDD1, the control electrode of the third anti-leakage transistor M32 is connected to the first node Q(N), the first electrode of the first anti-leakage transistor M31 is connected to the second electrode of the third anti-leakage transistor M32, the control electrode of the first anti-leakage transistor M31 is connected to the first node Q(N), and the second electrode of the first anti-leakage transistor M31 is connected to the first electrode of the first reset transistor M11.

[0066] As shown in Figures 2 and 3, the shift register unit of the embodiment of the present disclosure may further include a first control subcircuit 3. The first control subcircuit 3 is connected to the first control signal terminal CL and the first node Q(N), and is used to control the potential of the first node Q(N) under the potential control of the first control signal terminal CL. The first control signal terminal CL can be connected to the signal output terminal G(N+5). For example, the first control subcircuit 3 may include a first control transistor M7. The first control transistor M7 is connected between the first control signal terminal CL and the first node Q(N). Furthermore, the first control subcircuit 3 may further include a second control transistor M8. The first electrode and control electrode of the first control transistor M7 are connected to the first control signal terminal CL, the first electrode of the second control transistor M8 is connected to the second electrode of the first control transistor M7, the control electrode of the second control transistor M8 is connected to the first control signal terminal CL, and the second electrode of the second control transistor M8 is connected to the first node Q(N). The second electrode of the above-mentioned first anti-leakage transistor M31 can be connected to the second electrode of the first control transistor M7.

[0067] In another embodiment, as shown in Figure 8, the first control subcircuit 3 may include a coupling capacitor C4, wherein a first electrode of the coupling capacitor C4 is connected to the first control signal terminal CL, and a second electrode of the coupling capacitor C4 is connected to the first node Q(N).

[0068] The above-mentioned gate drive circuit may include a plurality of cascaded shift register units. Taking a shift register unit including four signal output terminals as an example, a shift register unit may correspond to four sequentially arranged pixel rows. The first control signal terminal CL may be connected to the signal output terminal G(N+5) of the next-stage shift register. In addition, in a plurality of cascaded shift register units, three sequentially arranged shift register units constitute a shift group. Therefore, a shift group includes 12 signal output terminals, and the 12 signal output terminals correspond to 12 sequentially arranged pixel rows. The 12 signal output terminals correspond to 12 clock signal terminals (CLKE1-CLKE12 in FIG11 ), and the clock signals output by the 12 clock signal terminals are sequentially shifted. Among them, among the 12 sequentially shifted clock signals, the end time of the effective potential interval of the xth clock signal is equal to the start time of the effective potential interval of the (x+2)th clock signal. For example, if the end time of the effective potential interval of the last output signal among the multiple output signals sequentially shifted in a display frame is equal to the start time of the effective potential interval of the control signal, and if the last clock signal is the xth clock signal, then the control signal may be the (x+2)th clock signal. For example, if the end time of the effective potential interval of the last output signal among the multiple output signals sequentially shifted in a display frame is greater than the start time of the effective potential interval of the control signal, and if the last clock signal is the xth clock signal, then the control signal may be the (x+1)th clock signal. Furthermore, in a display frame, the effective potential interval of the control signal may be within the effective potential interval of the first node.

[0069] Figure 12 shows a simulation diagram of the shift register unit. As can be seen from Figure 12, the difference between the falling edge time of the signal output terminal G(3) and the falling edge time of the signal output terminal G(4) of the shift register unit is very small.

[0070] As shown in FIG3 , the shift register unit of the embodiment of the present disclosure may further include a second control subcircuit 11. This second control subcircuit is used to control the potential of the first node Q(N) based on the potential of the fixed power supply terminal GVDD3. The second control subcircuit 11 may include a third control transistor M10. The control electrode and first electrode of the third control transistor M10 are connected to the fixed power supply terminal GVDD3, and the second electrode of the third control transistor M10 is connected to the first node Q(N). In another embodiment, as shown in FIG9 and FIG10 , the second control subcircuit 11 may include the third control transistor M10, a first auxiliary transistor M33, and a second auxiliary transistor M34. Of course, the shift register may also include a third auxiliary transistor M35. The control electrode of the third auxiliary transistor M35 is connected to the first node Q(N), the first electrode of the third auxiliary transistor M35 is connected to the reset power supply terminal VGL3, and the second electrode of the third auxiliary transistor M35 is connected to the control electrode of the third control transistor M10. The first auxiliary transistor M33 and the second auxiliary transistor M34 are connected in series.

[0071] The disclosed embodiments further provide a gate drive circuit, which may include a plurality of cascaded shift registers according to any of the above embodiments.

[0072] The present disclosure also provides a display device, which may include the gate driving circuit of the above embodiment.

[0073] The present disclosure also provides a driving method for a shift register unit. The driving method employs the shift register unit of the above-described embodiment. The driving method may include: causing the input subcircuit 1 to control the potential of the first node Q(N) under the potential control of the input control terminal CR(N-2); causing the signal output subcircuit 2 to control the clock signal terminal and the corresponding signal output terminal to be disconnected or connected under the potential control of the first node Q(N); and causing the first control subcircuit 3 to control the potential of the first node Q(N) under the potential control of the first control signal terminal CL.

[0074] The display device, gate driving circuit, shift register unit and driving method thereof provided in the embodiments of the present disclosure belong to the same inventive concept, and the descriptions of relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0075] The above is merely a preferred embodiment of the present disclosure and does not constitute any form of limitation to the present disclosure. Although the present disclosure has been disclosed as a preferred embodiment as above, it is not intended to limit the present disclosure. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A shift register unit, characterized in that: include: An input subcircuit, connected to the input control terminal and the first node, and configured to control the potential of the first node under the potential control of the input control terminal; a signal output subcircuit connected to the first node and to a plurality of signal output terminals and a plurality of clock signal terminals, wherein the plurality of signal output terminals correspond to the plurality of clock signal terminals; the signal output subcircuit is used to control the clock signal terminals to be disconnected or connected with the corresponding signal output terminals under the potential control of the first node; the plurality of signal output terminals correspond to outputting a plurality of output signals, and the plurality of output signals are sequentially shifted; A first control subcircuit, connected to the first control signal terminal and the first node, and configured to control the potential of the first node under the potential control of the first control signal terminal; The first control signal terminal is used to output a control signal; in a display frame, the end time of the effective potential interval of the last output signal among the multiple output signals shifted sequentially is greater than or equal to the start time of the effective potential interval of the control signal, and the end time of the effective potential interval of the last output signal among the multiple output signals shifted sequentially is less than the end time of the effective potential interval of the control signal.

2. The shift register unit according to claim 1, characterized in that: The first control subcircuit includes a first control transistor connected between the first control signal terminal and the first node.

3. The shift register unit according to claim 1, characterized in that: The first control subcircuit includes a coupling capacitor, a first electrode of the coupling capacitor is connected to the first control signal terminal, and a second electrode of the coupling capacitor is connected to the first node.

4. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: The cascade output subcircuit is connected to the first node and the cascade output terminal, and is used to control the potential of the cascade output terminal under the control of the potential of the first node.

5. The shift register unit according to claim 4, characterized in that: The shift register unit also includes: A denoising subcircuit is connected to the second node and the reset power supply terminal, and is connected to at least one of the cascade output terminal, the first node and the signal output terminal, and is used to control the reset power supply terminal to be disconnected or connected with the signal output terminal under the potential control of the second node, and is also used to control the reset power supply terminal to be disconnected or connected with the cascade output terminal under the potential control of the second node, and is also used to control the reset power supply terminal to be disconnected or connected with the first node under the potential control of the second node.

6. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: The inverting sub-circuit is connected to the first node and the second node, and is used to control the potential of the first node to be opposite to the potential of the second node.

7. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: The first reset subcircuit is connected to the display reset signal terminal, the reset power terminal and the first node, and is used to control the reset power terminal to be disconnected or connected to the first node under the potential control of the display reset signal terminal.

8. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: The second reset subcircuit is connected to the global reset signal terminal, the reset power terminal and the first node, and is used to control the reset power terminal to be disconnected or connected with the first node under the potential control of the global reset signal terminal.

9. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: a compensation control subcircuit connected to the input control terminal, the compensation control signal terminal and the third node, and configured to control the input control terminal to be disconnected or connected to the third node under the potential control of the compensation control signal terminal; The compensation output subcircuit is connected to the third node, the fourth node, the clock signal terminal and the first node, and is used to control the clock signal terminal to be disconnected or connected with the fourth node under the potential control of the third node, and is also used to control the fourth node to be disconnected or connected with the first node under the potential control of the clock signal terminal.

10. The shift register unit according to claim 2, characterized in that: The first control subcircuit further includes a second control transistor, wherein a first electrode and a control electrode of the first control transistor are connected to the first control signal terminal, a first electrode of the second control transistor is connected to a second electrode of the first control transistor, a control electrode of the second control transistor is connected to the first control signal terminal, and a second electrode of the second control transistor is connected to the first node; The shift register unit also includes: A first anti-leakage transistor, wherein a first electrode of the first anti-leakage transistor is connected to a fixed power supply terminal, a second electrode of the first anti-leakage transistor is connected to a second electrode of the first control transistor, and a control electrode of the first anti-leakage transistor is connected to the first node.

11. The shift register unit according to claim 1, characterized in that: In a display frame, the effective potential interval of the control signal is within the effective potential interval of the first node.

12. A gate drive circuit, characterized in that: The invention comprises the shift register unit as claimed in any one of claims 1 to 11.

13. A display device, characterized in that: Includes the gate drive circuit as claimed in claim 12.

14. A driving method of a shift register unit, characterized in that: The driving method adopts the shift register unit according to any one of claims 1 to 11, and the driving method comprises: enabling the input subcircuit to control the potential of the first node under the potential control of the input control terminal; The signal output subcircuit controls the clock signal terminal and the corresponding signal output terminal to be disconnected or connected under the potential control of the first node; The first control subcircuit is enabled to control the potential of the first node under the potential control of the first control signal terminal.

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