Display panel, display device and driving control method

Abstract

The invention discloses a display panel, a display device and a driving control method. The display panel comprises a shift register unit and a plurality of output control signal lines coupled with the shift register unit, the plurality of output control signal lines are arranged between the shifting register units coupled with the output control signal lines and the display area of the display panel; the shift register unit comprises: a shift register (100) configured to output a cascade signal through a cascade output end (OT); the output circuit (200) is coupled with the shifting register (100), the output circuit (200) is configured to control the driving output end (OUT) to output a grid scanning signal according to a signal of an output control signal end (CS) and a signal of a first reference signal end (VREF1), and the output control signal end (CS) is coupled with one output control signal line in the multiple output control signal lines.

Description

Display panel, display device, and drive control method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display device, and a driving control method. Background Art

[0002] With the rapid development of display technology, display panels are showing a trend toward high integration and low cost. Among these technologies, Gate Driver on Array (GOA) technology integrates drive control circuitry onto the array substrate of a display panel to provide scan drive for the display panel. Currently, these drive control circuits typically consist of multiple cascaded shift register units.

[0003] Summary of the Invention

[0004] Some embodiments of the present disclosure provide a display panel including:

[0005] a shift register unit and a plurality of output control signal lines coupled to the shift register unit; the plurality of output control signal lines are arranged between the shift register unit coupled thereto and a display area of ​​the display panel;

[0006] The shift register unit includes:

[0007] The shift register is configured to output a cascade signal through a cascade output terminal;

[0008] An output circuit is coupled to the shift register, and the output circuit is configured to control the output gate scan signal of the driving output terminal according to the signal of the output control signal terminal and the signal of the first reference signal terminal, and the output control signal terminal is coupled to one of the multiple output control signal lines.

[0009] In some possible implementations provided by the present disclosure, the output circuit includes: a first output circuit and a second output circuit;

[0010] The first output circuit is coupled to the cascade output terminal or the first node in the shift register and is configured to transmit the signal from the output control signal terminal to the driving output terminal in response to a signal from the cascade output terminal or the first node;

[0011] The second output circuit is coupled to a second node in the shift register and is configured to transmit the signal from the first reference signal terminal to the driving output terminal in response to a signal at the second node.

[0012] In some possible implementations provided by the present disclosure, the first output circuit includes: a first output transistor;

[0013] The gate of the first output transistor is coupled to the cascade output terminal or the first node, the first electrode of the first output transistor is coupled to the output control signal terminal, and the second electrode of the first output transistor is coupled to the driving output terminal.

[0014] In some possible implementations provided by the present disclosure, the second output circuit includes: a second output transistor;

[0015] A gate of the second output transistor is coupled to the second node, a first electrode of the second output transistor is coupled to the first reference signal terminal, and a second electrode of the second output transistor is coupled to the driving output terminal.

[0016] In some possible implementations provided by the present disclosure, the shift register includes:

[0017] an input sub-circuit configured to provide a signal from an input signal terminal to the third node in response to a signal from a first clock signal terminal;

[0018] a control subcircuit configured to control signals of the first node and the second node, and provide the signal of the third node to the first node or the second node;

[0019] The cascade sub-circuit is configured to enable the cascade output terminal to output the cascade signal in response to signals at the first node and the second node.

[0020] In some possible implementations provided by the present disclosure, the input sub-circuit includes: a first transistor;

[0021] A gate of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the third node.

[0022] In some possible implementations provided by the present disclosure, the control subcircuit includes: a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

[0023] The gate of the second transistor is coupled to the third node, the first electrode of the second transistor is coupled to the first clock signal terminal, and the second electrode of the second transistor is coupled to the fourth node;

[0024] The gate of the third transistor is coupled to the second reference signal terminal, the first electrode of the third transistor is coupled to the fourth node, and the second electrode of the third transistor is coupled to the gate of the fourth transistor;

[0025] A first electrode of the fourth transistor is coupled to the second clock signal terminal, and a second electrode of the fourth transistor is coupled to the first electrode of the fifth transistor;

[0026] The gate of the fifth transistor is coupled to the second clock signal terminal, and the second electrode of the fifth transistor is coupled to the first node;

[0027] The gate of the sixth transistor is coupled to the first clock signal terminal, the first electrode of the sixth transistor is coupled to the input signal terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor;

[0028] The gate of the seventh transistor is coupled to the second reference signal terminal, and the second electrode of the seventh transistor is coupled to the fifth node;

[0029] The gate of the eighth transistor is coupled to the fifth node, the first electrode of the eighth transistor is coupled to the fifth node, and the second electrode of the eighth transistor is coupled to the second node;

[0030] The gate of the ninth transistor is coupled to the first clock signal terminal, the first electrode of the ninth transistor is coupled to the second reference signal terminal, and the second electrode of the ninth transistor is coupled to the gate of the tenth transistor;

[0031] A first electrode of the tenth transistor is coupled to the third reference signal terminal, and a second electrode of the tenth transistor is coupled to the sixth node;

[0032] The gate of the eleventh transistor is coupled to the fifth node, the first electrode of the eleventh transistor is coupled to the sixth node, and the second electrode of the eleventh transistor is coupled to the second clock signal terminal;

[0033] The gate of the twelfth transistor is coupled to the first electrode of the fifteenth transistor, the first electrode of the twelfth transistor is coupled to the first node, and the second electrode of the twelfth transistor is coupled to the fourth reference signal terminal;

[0034] The gate of the thirteenth transistor is coupled to the fifth reference signal terminal, the first electrode of the thirteenth transistor is coupled to the fourth reference signal terminal, and the second electrode of the thirteenth transistor is coupled to the first electrode of the fourteenth transistor;

[0035] The gate of the fourteenth transistor is coupled to the first reference signal terminal, and the second electrode of the fourteenth transistor is coupled to the first electrode of the fifteenth transistor;

[0036] The gate of the fifteenth transistor is coupled to the first reference signal terminal, the first electrode of the fifteenth transistor is coupled to the third node, and the second electrode of the fifteenth transistor is coupled to the second node;

[0037] A first electrode of the first capacitor is coupled to the gate of the fourth transistor, and a second electrode of the first capacitor is coupled to the second electrode of the fourth transistor;

[0038] A first electrode of the second capacitor is coupled to the sixth node, and a second electrode of the second capacitor is coupled to the second electrode of the seventh transistor;

[0039] A first electrode of the third capacitor is coupled to the fourth reference signal terminal, and a second electrode of the third capacitor is coupled to the first node;

[0040] A first electrode of the fourth capacitor is coupled to the cascade output terminal, and a second electrode of the fourth capacitor is coupled to the first reference signal terminal.

[0041] In some possible implementations provided by the present disclosure, the cascade sub-circuit includes: a first cascade transistor and a second cascade transistor;

[0042] The gate of the first cascode transistor is coupled to the first node, the first electrode of the first cascode transistor is coupled to the fourth reference signal terminal, and the second electrode of the first cascode transistor is coupled to the cascode output terminal;

[0043] A gate of the second cascode transistor is coupled to the second node, a first electrode of the second cascode transistor is coupled to the cascode output terminal, and a second electrode of the second cascode transistor is coupled to the first reference signal terminal.

[0044] In some possible implementations provided by the present disclosure, the input sub-circuit includes: a sixteenth transistor and a seventeenth transistor;

[0045] The gate of the sixteenth transistor is coupled to the first clock signal terminal, the first electrode of the sixteenth transistor is coupled to the input signal terminal, and the second electrode of the sixteenth transistor is coupled to the seventh node;

[0046] A gate of the seventeenth transistor is coupled to the first clock signal terminal, a first electrode of the seventeenth transistor is coupled to the seventh node, and a second electrode of the seventeenth transistor is coupled to the third node.

[0047] In some possible implementations provided by the present disclosure, the control subcircuit includes: an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a fifth capacitor, and a sixth capacitor;

[0048] The gate of the eighteenth transistor is coupled to the cascade output terminal, the first electrode of the eighteenth transistor is coupled to the third clock signal terminal, and the second electrode of the eighteenth transistor is coupled to the seventh node;

[0049] The gate of the nineteenth transistor is coupled to the input signal terminal, the first electrode of the nineteenth transistor is coupled to the first reference signal terminal, and the second electrode of the nineteenth transistor is coupled to the second node;

[0050] A gate of the twentieth transistor is coupled to the second node, a first electrode of the twentieth transistor is coupled to the first reference signal terminal, and a second electrode of the twentieth transistor is coupled to the eighth node;

[0051] A gate of the twenty-first transistor is coupled to the second node, a first electrode of the twenty-first transistor is coupled to the eighth node, and a second electrode of the twenty-first transistor is coupled to the third node;

[0052] A gate of the 22nd transistor is coupled to the third node, a first electrode of the 22nd transistor is coupled to the eighth node, and a second electrode of the 22nd transistor is coupled to the sixth reference signal terminal;

[0053] A gate of the twenty-third transistor is coupled to the fourth clock signal terminal, a first electrode of the twenty-third transistor is coupled to the second node, and a second electrode of the twenty-third transistor is coupled to the sixth reference signal terminal;

[0054] A first electrode of the fifth capacitor is coupled to the first reference signal terminal, and a second electrode of the fifth capacitor is coupled to the first electrode of the twenty-third transistor;

[0055] A first electrode of the sixth capacitor is coupled to the cascade output terminal, and a second electrode of the sixth capacitor is coupled to the first node.

[0056] In some possible implementations provided by the present disclosure, the cascade sub-circuit includes: a first cascade transistor and a second cascade transistor;

[0057] The gate of the first cascode transistor is coupled to the first node, the first electrode of the first cascode transistor is coupled to the cascode output terminal, and the second electrode of the first cascode transistor is coupled to the third clock signal terminal;

[0058] The gate of the second cascode transistor is coupled to the second node, the first electrode of the second cascode transistor is coupled to the first reference signal terminal, and the second electrode of the second cascode transistor is coupled to the cascode output terminal;

[0059] In some possible implementations provided by the present disclosure, the control subcircuit includes: a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a seventh capacitor, and an eighth capacitor;

[0060] A gate of the twenty-fourth transistor is coupled to the first clock signal terminal, a first electrode of the twenty-fourth transistor is coupled to the seventh reference signal terminal, and a second electrode of the twenty-fourth transistor is coupled to the second node;

[0061] A gate of the twenty-fifth transistor is coupled to the third node, a first electrode of the twenty-fifth transistor is coupled to the second node, and a second electrode of the twenty-fifth transistor is coupled to the first clock signal terminal;

[0062] A gate of the twenty-sixth transistor is coupled to the second node, a first electrode of the twenty-sixth transistor is coupled to the first reference signal terminal, and a second electrode of the twenty-sixth transistor is coupled to the first electrode of the twenty-seventh transistor;

[0063] A gate of the twenty-seventh transistor is coupled to the third clock signal terminal, and a second electrode of the twenty-seventh transistor is coupled to a first electrode of the twenty-eighth transistor;

[0064] a gate of the twenty-eighth transistor coupled to the seventh reference signal terminal, a first electrode of the twenty-eighth transistor coupled to the third node, and a second electrode of the twenty-eighth transistor coupled to the first node;

[0065] A first electrode of the seventh capacitor is coupled to the first reference signal terminal, and a second electrode of the seventh capacitor is coupled to the first node;

[0066] A first electrode of the eighth capacitor is coupled to the cascade output terminal, and a second electrode of the eighth capacitor is coupled to the first node.

[0067] In some possible implementations provided by the present disclosure, the control subcircuit further includes: a twenty-eighth transistor;

[0068] A first electrode of the 28th transistor is coupled to the second electrode of the fifth transistor, a second electrode of the 28th transistor is coupled to the first node, and a gate of the 28th transistor is coupled to the first reference signal terminal.

[0069] Some embodiments of the present disclosure provide a display panel including:

[0070] A base substrate, comprising a display area and a non-display area;

[0071] The display area includes:

[0072] multiple sub-pixels;

[0073] a plurality of scan lines, wherein a row of the sub-pixels in the plurality of sub-pixels is correspondingly coupled to at least one of the scan lines;

[0074] The non-display area includes:

[0075] The gate driving circuit includes a plurality of the shift register units mentioned above, wherein a driving output end of each of the plurality of shift register units is correspondingly coupled to at least one of the plurality of scan lines.

[0076] In some possible implementations provided by the present disclosure, the present invention further includes: a plurality of output control signal lines coupled to the gate drive circuit; the extension direction of the plurality of output control signal lines is the same as the arrangement direction of the plurality of shift register units.

[0077] In some possible implementations provided by the present disclosure, the plurality of output control signal lines are arranged between the gate driving circuit coupled thereto and the display area.

[0078] In some possible implementations provided by the present disclosure, in two adjacent shift register units among the plurality of shift register units, the input signal terminal of the next shift register unit is coupled to the cascade output terminal of the previous shift register unit;

[0079] The multiple output control signal lines include: a first output control signal line and a second output control signal line; the first output control signal line is coupled to the output control signal end of the odd-numbered shift register unit, and the second output control signal line is coupled to the output control signal end of the even-numbered shift register unit.

[0080] In some possible implementations provided by the present disclosure, in two adjacent shift register units among the plurality of shift register units, the input signal terminal of the next shift register unit is coupled to the cascade output terminal of the previous shift register unit;

[0081] The multiple output control signal lines include: a first output control signal line and a second output control signal line; every eight adjacent shift register units in a number of the shift register units constitute a shift register unit group; the first output control signal line is coupled to the output control signal end of the shift register unit in the odd-numbered shift register unit group, and the second output control signal line is coupled to the output control signal end of the shift register unit in the even-numbered shift register unit group.

[0082] In some possible implementations provided by the present disclosure, the present invention further includes: a plurality of output control auxiliary signal lines; a first insulating layer is provided between the plurality of output control auxiliary signal lines and the plurality of output control signal lines;

[0083] The plurality of output control auxiliary signal lines correspond one-to-one to the plurality of output control signal lines, and the corresponding output control auxiliary signal lines and output control signal lines are coupled to each other through first vias penetrating the first insulating layer.

[0084] In some possible implementations provided by the present disclosure, the present invention further includes: a plurality of clock signal lines coupled to the gate drive circuit; the extension direction of the plurality of clock signal lines is the same as the arrangement direction of the plurality of shift register units.

[0085] In some possible implementations provided by the present disclosure, the plurality of clock signal lines are arranged on a side of the gate driving circuit coupled thereto that is away from the display area.

[0086] In some possible implementations provided by the present disclosure, the plurality of output control signal lines are disposed between the orthographic projections of the plurality of clock signal lines on the base substrate and the display area.

[0087] In some possible implementations provided by the present disclosure, the gate driving circuit is disposed between the orthographic projections of the plurality of clock signal lines on the base substrate and the orthographic projections of the plurality of output control signal lines on the base substrate.

[0088] The orthographic projections of the plurality of output control signal lines on the base substrate are arranged between the orthographic projections of the gate driving circuit on the base substrate and the display area.

[0089] In some possible implementations provided by the present disclosure, the orthographic projection of the first output transistor on the base substrate is located between the orthographic projection of the first cascode transistor on the base substrate and the display area.

[0090] In some possible implementations provided by the present disclosure, a width of a channel of the first output transistor is greater than a width of a channel of the first cascode transistor.

[0091] In some possible implementations provided by the present disclosure, a width of a channel of the first output transistor is not less than 100 um.

[0092] In some possible implementations provided by the present disclosure, the width of the channel of the first cascade transistor is no greater than 60 um.

[0093] In some possible implementations provided by the present disclosure, an orthographic projection of the second output transistor on the base substrate is located between an orthographic projection of the second cascode transistor on the base substrate and the display area.

[0094] In some possible implementations provided by the present disclosure, a width of a channel of the second output transistor is greater than a width of a channel of the second cascode transistor.

[0095] In some possible implementations provided by the present disclosure, a width of a channel of the second output transistor is not less than 100 um.

[0096] In some possible implementations provided by the present disclosure, the width of the channel of the second cascode transistor is no greater than 60 um.

[0097] Some embodiments of the present disclosure provide a display device including:

[0098] The above-mentioned display panel;

[0099] a drive control circuit coupled to the display panel and configured to, when determining to adopt a full-screen drive mode, input a first output control signal to the output control signal terminals of the plurality of shift register units, so that the plurality of shift register units sequentially output gate scan signals to drive the scan lines row by row;

[0100] When it is determined to adopt the local driving mode, a second output control signal is input to the output control signal terminals of the plurality of shift register units, so that some of the plurality of shift register units output gate scanning signals in sequence, and the remaining shift register units output invalid scanning signals.

[0101] Some embodiments of the present disclosure provide a drive control method, including:

[0102] When it is determined to adopt the full-screen driving mode, inputting a first output control signal to the output control signal terminals of the plurality of shift register units, so that the plurality of shift register units sequentially output gate scanning signals and drive the scanning lines row by row;

[0103] When it is determined to adopt the local driving mode, a second output control signal is input to the output control signal terminal of the multiple shift register units, so that some of the multiple shift register units output gate scanning signals in sequence, and the remaining shift register units output invalid scanning signals to drive some of the scan lines.

[0104] In some possible implementations provided by the present disclosure, the first output control signal is a fixed voltage signal with a first level.

[0105] In some possible implementations provided by the present disclosure, the second output control signal includes a fixed voltage signal portion having a first level and a fixed voltage signal portion having a second level, the fixed voltage signal portion having the first level is input into some of the shift register units, and the fixed voltage signal portion having the second level is input into the remaining shift register units.

[0106] In some possible implementations provided by the present disclosure, the first output control signal is a clock signal.

[0107] In some possible implementations provided by the present disclosure, the second output control signal includes a clock signal portion and a fixed voltage signal portion having a first level;

[0108] The clock signal portion of the second output control signal is input to some of the shift register units, and the fixed voltage signal portion having the first level is input to the remaining shift register units.

[0109] In some possible implementations provided in the present disclosure, the pulse width of the input signal at the input signal end of the shift register unit is 18H, the pulse width of the cascade signal output by the cascade signal end of the shift register unit is 18H, the pulse width of the gate scan signal output by the driving output end of the shift register unit is 18H, and the cascade signal and the effective gate scan signal output by the shift register unit of the next level among the multiple shift register units are shifted 2H behind the cascade signal and the effective gate scan signal output by the shift register unit of the previous level. BRIEF DESCRIPTION OF THE DRAWINGS

[0110] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0111] FIG1 is a schematic diagram of some structures of a shift register unit provided by an embodiment of the present disclosure;

[0112] FIG2 is another schematic diagram of the structure of the shift register unit provided by the embodiment of the present disclosure;

[0113] FIG3 is a schematic diagram of some structures of a display panel provided by an embodiment of the present disclosure;

[0114] FIG4 is a schematic diagram of some structures of a display device provided by an embodiment of the present disclosure;

[0115] FIG5 is a flow chart of a drive control method provided by an embodiment of the present disclosure;

[0116] FIG6 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0117] FIG7 is another signal timing diagram provided by an embodiment of the present disclosure;

[0118] FIG8 is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0119] FIG9 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0120] FIG10 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0121] FIG11 is a schematic diagram of some further structures of a shift register unit provided by an embodiment of the present disclosure;

[0122] FIG12 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0123] FIG13 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0124] FIG14 is a schematic diagram of the layout structure of a shift register unit provided in an embodiment of the present disclosure;

[0125] FIG15 is a schematic diagram of the layout structure of the semiconductor layer provided in an embodiment of the present disclosure;

[0126] FIG16 is a schematic diagram of the layout structure of the gate conductive layer provided in an embodiment of the present disclosure;

[0127] FIG17 is a schematic diagram of the layout structure of the capacitor electrode layer provided in an embodiment of the present disclosure;

[0128] FIG18 is a schematic diagram of the layout structure of the cascade routing layer provided in an embodiment of the present disclosure;

[0129] FIG19 is a schematic diagram of the layout structure of the transmission wiring layer provided in an embodiment of the present disclosure;

[0130] FIG20 is a schematic diagram of the layout structure of the auxiliary routing layer provided in an embodiment of the present disclosure;

[0131] FIG21 is another schematic diagram of the structure of the shift register unit provided by the embodiment of the present disclosure;

[0132] FIG22 is a schematic diagram of some structures of a display device provided by an embodiment of the present disclosure;

[0133] FIG23 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0134] FIG24 is a further signal timing diagram provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0135] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of this specification, as detailed in the appended claims.

[0136] The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. Unless otherwise defined, technical or scientific terms used in this specification should have the same ordinary meaning as those having ordinary skill in the art to which this application belongs. The terms "first," "second," and similar terms used in this specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather indicate the presence of one. "Multiple" or "several" means two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are used for convenience only and are not intended to limit the scope of the present disclosure to a specific location or spatial orientation. Terms such as "include" or "comprising" mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0137] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used in this specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0138] The present disclosure provides a shift register unit, as shown in FIG1 , comprising:

[0139] The shift register 100 is configured to output a cascade signal through a cascade output terminal OT;

[0140] The output circuit 200 is coupled to the shift register 100 . The output circuit 200 is configured to control the driving output terminal OUT to output a gate scanning signal according to the signal of the output control signal terminal CS and the signal of the first reference signal terminal VREF1 .

[0141] Embodiments of the present disclosure provide a shift register unit that outputs a cascade signal and controls a gate scanning signal at a driver output terminal in an output circuit by controlling a signal at an output control signal terminal. When this shift register unit is applied to a display panel, the signal at the output control signal terminal can be controlled to scan any area of ​​the display panel, thereby flexibly adjusting the refresh rate of different areas, saving power, and reducing losses.

[0142] In some embodiments of the present disclosure, as shown in Figure 2, the output circuit 200 includes: a first output circuit 210 and a second output circuit 220; wherein the first output circuit 210 is coupled to the first node N1 in the shift register 100, and is configured to transmit the signal from the output control signal terminal CS to the driving output terminal OUT in response to the signal of the first node N1; the second output circuit 220 is coupled to the second node N2 in the shift register 100, and is configured to transmit the signal from the first reference signal terminal VREF1 to the driving output terminal OUT in response to the signal of the second node N2.

[0143] In some embodiments of the present disclosure, as shown in Figure 2, the first output circuit 210 includes: a first output transistor T1; wherein the gate of the first output transistor T1 is coupled to the first node N1, the first electrode of the first output transistor T1 is coupled to the output control signal terminal CS, and the second electrode of the first output transistor T1 is coupled to the drive output terminal OUT.

[0144] In some embodiments of the present disclosure, as shown in Figure 2, the second output circuit 220 includes: a second output transistor T2; wherein the gate of the second output transistor T2 is coupled to the second node N2, the first electrode of the second output transistor T2 is coupled to the first reference signal terminal VREF1, and the second electrode of the second output transistor T2 is coupled to the driving output terminal OUT.

[0145] Alternatively, the first output circuit may be coupled to the cascade output terminal in the shift register, and the first output circuit is configured to transmit the signal from the output control signal terminal to the driver output terminal in response to a signal at the cascade output terminal. In this regard, the gate of the first output transistor is coupled to the cascade output terminal in the shift register.

[0146] In the disclosed embodiments, coupling the gate of the first output transistor to the first node provides a better technical effect than coupling the gate of the first output transistor to the cascade output terminal of the shift register. Taking FIG2 as an example, the gate of the first output transistor T1 is coupled to the first node N1, and the voltage at which the driven output terminal OUT can output a low-level signal is VGL. If the gate of the first output transistor is coupled to the cascade output terminal of the shift register, since the voltage at which the cascade output terminal can output a low-level signal can only be VGL, the voltage at which the driven output terminal OUT can output a low-level signal can only be VGL-Vth.

[0147] In some embodiments of the present disclosure, as shown in FIG2 , the shift register 100 includes: an input sub-circuit 110 configured to provide a signal from an input signal terminal IN to a third node N3 in response to a signal from a first clock signal terminal CK1 ;

[0148] The control sub-circuit 120 is configured to control the signals of the first node N1 and the second node N2, and provide the signal of the third node N3 to the first node N1 or the second node N2;

[0149] The cascade sub-circuit 130 is configured to enable the cascade output terminal OT to output a cascade signal in response to signals at the first node N1 and the second node N2.

[0150] In some embodiments of the present disclosure, as shown in FIG2 , the input sub-circuit 110 includes: a first transistor M1; wherein a gate of the first transistor M1 is coupled to the first clock signal terminal CK1, a first electrode of the first transistor M1 is coupled to the input signal terminal IN, and a second electrode of the first transistor M1 is coupled to a third node N3.

[0151] In some embodiments of the present disclosure, as shown in FIG2 , the control subcircuit 120 includes: a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4;

[0152] The gate of the second transistor M2 is coupled to the third node N3, the first electrode of the second transistor M2 is coupled to the first clock signal terminal CK1, and the second electrode of the second transistor M2 is coupled to the fourth node N4; the gate of the third transistor M3 is coupled to the second reference signal terminal VREF2, the first electrode of the third transistor M3 is coupled to the fourth node N4, and the second electrode of the third transistor M3 is coupled to the gate of the fourth transistor M4; the first electrode of the fourth transistor M4 is coupled to the second clock signal terminal CK2, and the second electrode of the fourth transistor M4 is coupled to the first electrode of the fifth transistor M5; the gate of the fifth transistor M5 is coupled to the second clock signal terminal CK2, and the second electrode of the fifth transistor M5 is coupled to the first node N1; the sixth transistor The gate of the transistor M6 is coupled to the first clock signal terminal CK1, the first electrode of the sixth transistor M6 is coupled to the input signal terminal IN, and the second electrode of the sixth transistor M6 is coupled to the first electrode of the seventh transistor M7; the gate of the seventh transistor M7 is coupled to the second reference signal terminal VREF2, and the second electrode of the seventh transistor M7 is coupled to the fifth node N5; the gate of the eighth transistor M8 is coupled to the fifth node N5, the first electrode of the eighth transistor M8 is coupled to the fifth node N5, and the second electrode of the eighth transistor M8 is coupled to the second node N2; the gate of the ninth transistor M9 is coupled to the first clock signal terminal CK1, the first electrode of the ninth transistor M9 is coupled to the second reference signal terminal VREF2, and the second electrode of the ninth transistor M9 is coupled to the tenth transistor The gate of the body transistor M10 is coupled; the first electrode of the tenth transistor M10 is coupled to the third reference signal terminal VREF3, and the second electrode of the tenth transistor M10 is coupled to the sixth node N6; the gate of the eleventh transistor M11 is coupled to the fifth node N5, the first electrode of the eleventh transistor M11 is coupled to the sixth node N6, and the second electrode of the eleventh transistor M11 is coupled to the second clock signal terminal CK2; the gate of the twelfth transistor M12 is coupled to the first electrode of the fifteenth transistor M15, the first electrode of the twelfth transistor M12 is coupled to the first node N1, and the second electrode of the twelfth transistor M12 is coupled to the fourth reference signal terminal VREF4; the gate of the thirteenth transistor M13 is coupled to the fifth reference signal terminal VREF5, A first electrode of the thirteenth transistor M13 is coupled to the fourth reference signal terminal VREF4, and a second electrode of the thirteenth transistor M13 is coupled to a first electrode of the fourteenth transistor M14; a gate of the fourteenth transistor M14 is coupled to the first reference signal terminal VREF1, and a second electrode of the fourteenth transistor M14 is coupled to a first electrode of the fifteenth transistor M15; a gate of the fifteenth transistor M15 is coupled to the first reference signal terminal VREF1, a first electrode of the fifteenth transistor M15 is coupled to the third node N3, and a second electrode of the fifteenth transistor M15 is coupled to the second node N2; a first electrode of the first capacitor C1 is coupled to the gate of the fourth transistor M4, and a second electrode of the first capacitor C1 is coupled to the second electrode of the fourth transistor M4;A first electrode of the second capacitor C2 is coupled to the sixth node N6, and a second electrode of the second capacitor C2 is coupled to the second electrode of the seventh transistor M7. A first electrode of the third capacitor C3 is coupled to the fourth reference signal terminal VREF4, and a second electrode of the third capacitor C3 is coupled to the first node N1. A first electrode of the fourth capacitor C4 is coupled to the cascade output terminal OT, and a second electrode of the fourth capacitor C4 is coupled to the first reference signal terminal VREF1.

[0153] In some embodiments of the present disclosure, as shown in FIG2 , the cascade sub-circuit 130 includes: a first cascade transistor T3 and a second cascade transistor T4; wherein, a gate of the first cascade transistor T3 is coupled to the first node N1, a first electrode of the first cascade transistor T3 is coupled to the fourth reference signal terminal VREF4, and a second electrode of the first cascade transistor T3 is coupled to the cascade output terminal OT; a gate of the second cascade transistor T4 is coupled to the second node N2, a first electrode of the second cascade transistor T4 is coupled to the cascade output terminal OT, and a second electrode of the second cascade transistor T4 is coupled to the first reference signal terminal VREF1.

[0154] In some embodiments of the present disclosure, as shown in FIG21 , the control sub-circuit 120 further includes: a twenty-eighth transistor M28 ;

[0155] A first electrode of the twenty-eighth transistor M28 is coupled to the second electrode of the fifth transistor M5 , a second electrode of the twenty-eighth transistor M28 is coupled to the first node N1 , and a gate of the twenty-eighth transistor M28 is coupled to the first reference signal terminal VREF1 .

[0156] Exemplarily, the effective pulse signal of the cascade signal outputted from the cascade output terminal may be a high-level signal, the effective pulse signal of the gate scan signal outputted from the driver output terminal may be a high-level signal, the effective pulse signal of the first reference signal outputted from the first reference signal terminal may be a low-level signal, the effective pulse signal of the second reference signal outputted from the second reference signal terminal may be a low-level signal, the effective pulse signal of the third reference signal outputted from the third reference signal terminal may be a high-level signal, and the effective pulse signal of the fourth reference signal outputted from the fourth reference signal terminal may be a high-level signal. Alternatively, the effective pulse signal of the cascade signal outputted from the cascade output terminal may be a low-level signal, the effective pulse signal of the gate scan signal outputted from the driver output terminal may be a low-level signal, the effective pulse signal of the first reference signal outputted from the first reference signal terminal may be a high-level signal, the effective pulse signal of the second reference signal outputted from the second reference signal terminal may be a high-level signal, the effective pulse signal of the third reference signal outputted from the third reference signal terminal may be a low-level signal, and the effective pulse signal of the fourth reference signal outputted from the fourth reference signal terminal may be a low-level signal.

[0157] For example, to reduce the manufacturing process, all transistors can be P-type transistors; alternatively, all transistors can be N-type transistors, which is not limited here. Furthermore, N-type transistors are turned on by a high-level signal and turned off by a low-level signal; P-type transistors are turned off by a high-level signal and turned on by a low-level signal.

[0158] It should be noted that the transistors mentioned in the above embodiments of the present disclosure may be thin film transistors (TFTs) or metal oxide semiconductor field effect transistors (MOSs), without limitation. In specific implementations, depending on the transistor type and input signal, the first electrode of the transistor may be used as its source and the second electrode as its drain; or the first electrode may be used as its drain and the second electrode as its source, without making any specific distinction here.

[0159] The present disclosure provides a display panel, as shown in FIG3 , including:

[0160] The base substrate 1000 includes a display area AA and a non-display area BB;

[0161] Display area AA includes:

[0162] a plurality of sub-pixels SPX;

[0163] A plurality of scanning lines GA, wherein a row of sub-pixels SPX in the plurality of sub-pixels SPX is correspondingly coupled to at least one scanning line GA in the plurality of scanning lines GA;

[0164] The non-display area BB includes:

[0165] The gate drive circuit 10 includes the above-mentioned shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8 in FIG3 ), wherein a driving output terminal OUT of each of the plurality of shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8 in FIG3 ) is correspondingly coupled to at least one scan line GA among the plurality of scan lines GA.

[0166] In some embodiments of the present disclosure, as shown in FIG3 , the display panel further includes: a plurality of output control signal lines (e.g., CS-1 and CS-2 in FIG3 ) coupled to the shift register unit in the gate drive circuit 10. The output control signal terminal of a shift register unit is coupled to one of the plurality of output control signal lines. Furthermore, the extension direction of the plurality of output control signal lines (e.g., CS-1 and CS-2 in FIG3 ) is the same as the arrangement direction of the plurality of shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8 in FIG3 ). Exemplarily, the extension direction of the plurality of output control signal lines (e.g., CS-1 and CS-2 in FIG3 ) is the second direction F2, and the arrangement direction of the plurality of shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8 in FIG3 ) is also the second direction F2. Wherein, F1 in FIG3 is the first direction.

[0167] In some embodiments of the present disclosure, as shown in FIG. 3 , a plurality of output control signal lines (eg, CS- 1 and CS- 2 in FIG. 3 ) are disposed between the gate driving circuit 10 coupled thereto and the display area AA.

[0168] In some embodiments of the present disclosure, as shown in Figure 3, in two adjacent shift register units among a plurality of shift register units (for example, SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8 in Figure 3), the input signal terminal IN of the next shift register unit is coupled to the cascade output terminal OT of the previous shift register unit; it should be noted that the input signal terminal IN of the first shift register unit SR1 among the plurality of shift register units (for example, SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8 in Figure 3) is coupled to the frame start signal line stv.

[0169] In some embodiments of the present disclosure, as shown in FIG3 , a plurality of output control signal lines (e.g., CS-1 and CS-2 in FIG3 ) include: a first output control signal line CS-1 and a second output control signal line CS-2; the first output control signal line CS-1 is coupled to the output control signal terminal CS of the odd-numbered shift register units, and the second output control signal line CS-2 is coupled to the output control signal terminal CS of the even-numbered shift register units. Exemplarily, the first output control signal line CS-1 is coupled to the output control signal terminals CS of the shift register units SR1, SR3, SR5, and SR7; and the second output control signal line CS-2 is coupled to the output control signal terminals CS of the shift register units SR2, SR4, SR6, and SR8.

[0170] In some embodiments of the present disclosure, as shown in FIG22 , a plurality of output control signal lines (e.g., CS-1 and CS-2 in FIG3 ) include: a first output control signal line CS-1 and a second output control signal line CS-2; every eight adjacent shift register units in a plurality of shift register units constitute a shift register unit group; the first output control signal line CS-1 is coupled to the output control signal terminal CS of the shift register units in the odd-numbered shift register unit group, and the second output control signal line CS-2 is coupled to the output control signal terminal CS of the shift register units in the even-numbered shift register unit group. Exemplarily, the first output control signal line CS-1 is coupled to the output control signal terminal CS of the shift register units SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8; and the second output control signal line CS-2 is coupled to the output control signal terminal CS of the shift register units SR9, SR10, SR11, SR12, SR13, SR14, SR15, and SR16.

[0171] In some embodiments of the present disclosure, as shown in Figure 3, the display panel also includes: multiple clock signal lines (for example, clk1 and clk2 in Figure 3) coupled to the gate drive circuit; the extension direction of the multiple clock signal lines (for example, clk1 and clk2 in Figure 3) is the same as the arrangement direction of the multiple shift register units.

[0172] In some embodiments of the present disclosure, as shown in Figure 3, there are multiple output control auxiliary signal lines; there is a first insulating layer between the multiple output control auxiliary signal lines and the multiple output control signal lines; the multiple output control auxiliary signal lines correspond one-to-one to the multiple output control signal lines, and the corresponding output control auxiliary signal lines and the output control signal lines are coupled to each other through a first via penetrating the first insulating layer.

[0173] In some embodiments of the present disclosure, as shown in Figures 14 to 20 , the following are sequentially provided on a substrate: a semiconductor layer 010, a gate conductive layer 020, a capacitor electrode layer 030, a cascade routing layer 040, a signal transmission routing layer 050, and an auxiliary routing layer 060. Furthermore, an insulating layer is provided between each adjacent layer of the semiconductor layer 010, the gate conductive layer 020, the capacitor electrode layer 030, the cascade routing layer 040, the signal transmission routing layer 050, and the auxiliary routing layer 060. Furthermore, two layers that need to be coupled are coupled to each other via vias penetrating the insulating layer.

[0174] Illustratively, semiconductor layer 010 includes the active layer of each of the aforementioned transistors. The semiconductor layer can be patterned using a semiconductor material. The semiconductor layer can be used to form the active layers of the aforementioned multiple transistors. Illustratively, the semiconductor layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be conductive regions formed by doping with n-type or p-type impurities.

[0175] Exemplarily, the gate conductive layer 020 includes the gate and scan line of each of the above transistors, wherein the gate of some transistors is reused as a plate of the above capacitor.

[0176] Exemplarily, the capacitor electrode layer 030 includes the other electrode plate of each of the above capacitors. The two electrodes with facing areas form the above capacitors.

[0177] Exemplarily, the cascade wiring layer 040 includes cascade wirings for coupling the input signal terminal IN of the next shift register unit with the cascade output terminal OT of the previous shift register unit.

[0178] Exemplarily, the signal transmission wiring layer 050 includes a clock signal line, an output control signal line, and a source and a drain in each of the above transistors.

[0179] Exemplarily, the auxiliary wiring layer 060 includes output control auxiliary signal lines SC- 1 and SC- 2 and other reference signal lines.

[0180] In some embodiments of the present disclosure, as shown in FIG14 , a plurality of clock signal lines clk1 and clk2 are disposed on a side of the gate driving circuit coupled thereto that is away from the display area.

[0181] In some embodiments of the present disclosure, as shown in Figure 14, the orthographic projections of multiple output control signal lines (such as CS-1 and CS-2) on the substrate are set between the orthographic projections of multiple clock signal lines (such as clk1 and clk2) on the substrate and the display area.

[0182] In some embodiments of the present disclosure, as shown in Figure 14, the orthographic projection of the shift register 100 on the substrate is arranged between the orthographic projection of multiple clock signal lines (such as clk1, clk2) on the substrate and the orthographic projection of multiple output control signal lines (such as CS-1, CS-2) on the substrate, and the orthographic projection of multiple output control signal lines (such as CS-1, CS-2) on the substrate is arranged between the orthographic projection of the shift register 100 on the substrate and the display area.

[0183] In some embodiments of the present disclosure, as shown in FIG14 , the orthographic projection of the first output transistor on the base substrate is located between the orthographic projection of the first cascode transistor on the base substrate and the display area.

[0184] In some embodiments of the present disclosure, as shown in FIG. 14 , the width of the channel of the first output transistor φI_{tilde over (T)} and φI_{tilde over (T)} is greater than the width of the channel of the first cascode transistor φI_{tilde over (T)}.

[0185] In some embodiments of the present disclosure, a width of a channel of the first output transistor is not less than 100 um.

[0186] In some embodiments of the present disclosure, the width of the channel of the first cascode transistor is no greater than 60 um.

[0187] In some embodiments of the present disclosure, as shown in FIG14 , the orthographic projection of the second output transistor on the base substrate is located between the orthographic projection of the second cascode transistor on the base substrate and the display area.

[0188] In some embodiments of the present disclosure, as shown in FIG. 14 , the width of the channel of the second output transistor is greater than the width of the channel of the second cascode transistor.

[0189] In some embodiments of the present disclosure, a width of a channel of the second output transistor is not less than 100 um.

[0190] In some embodiments of the present disclosure, the width of the channel of the second cascode transistor is no greater than 60 um.

[0191] An embodiment of the present disclosure provides a display device, as shown in FIG4 , comprising: the display panel described above;

[0192] The drive control circuit 11 is coupled to the display panel and is configured to input a first output control signal to an output control signal terminal CS of a plurality of shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8 in FIG4 ) when determining to adopt the full-screen drive mode, so that the plurality of shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8 in FIG4 ) sequentially output gate scan signals to drive the scan lines row by row;

[0193] When it is determined to adopt the local driving mode, a second output control signal is input to the output control signal terminals CS of the plurality of shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8 in FIG4 ), so that some of the plurality of shift register units sequentially output gate scan signals, and the remaining shift register units output invalid scan signals. For example, the second output control signal is input to the output control signal terminals CS of the plurality of shift register units SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8, so that the shift register units SR1, SR2, SR6, SR7, and SR8 sequentially output gate scan signals, and the remaining shift register units SR3, SR4, and SR5 output invalid scan signals.

[0194] Exemplarily, the gate scanning signal is a high-level signal, and the invalid scanning signal is a low-level signal, or the gate scanning signal is a low-level signal, and the invalid scanning signal is a high-level signal, which is not limited here.

[0195] The embodiment of the present disclosure provides a drive control method, as shown in FIG5 , including:

[0196] S100, when it is determined to adopt the full-screen driving mode, inputting a first output control signal to the output control signal terminals of the plurality of shift register units, so that the plurality of shift register units sequentially output gate scanning signals and drive the scanning lines row by row;

[0197] S200. When it is determined to adopt the local driving mode, a second output control signal is input to the output control signal terminals of the plurality of shift register units, so that some of the plurality of shift register units output gate scanning signals in sequence, and the remaining shift register units output invalid scanning signals to drive some scanning lines.

[0198] In some embodiments of the present disclosure, as shown in Figure 6, the first output control signal cs1 is a fixed voltage signal having a first level V1. Exemplarily, the fixed voltage signal of the first level V1 is a high level, or the fixed voltage signal of the first level V1 is a low level, which is not limited here.

[0199] For example, in full-screen drive mode, the first output control signal cs1 is input to the output control signal terminals of the plurality of shift register units via the first output control signal line CS-1 and the second output control signal line CS-2. A timing diagram of the gate scan signals out1 to out8 applied to scan lines (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8 in FIG. 4 ) is shown in FIG. 6 .

[0200] As shown in FIG6 , in represents the input signal of the input signal terminal IN, ck1 represents the first clock signal of the first clock signal terminal CK1, ck2 represents the second clock signal of the second clock signal terminal CK2, cs1 represents the first output control signal of the output control signal terminal CS, ot1 represents the cascade signal of the cascade signal terminal OT in the first shift register unit SR1, ot2 represents the cascade signal of the cascade signal terminal OT in the second shift register unit SR2, ot3 represents the cascade signal of the cascade signal terminal OT in the third shift register unit SR3, ot4 represents the cascade signal of the cascade signal terminal OT in the fourth shift register unit SR4, ot5 represents the cascade signal of the cascade signal terminal OT in the fifth shift register unit SR5, ot6 represents the cascade signal of the cascade signal terminal OT in the sixth shift register unit SR6, ot7 represents the cascade signal of the cascade signal terminal OT in the seventh shift register unit SR7, and o t8 represents the cascade signal of the cascade signal terminal OT in the eighth shift register unit SR8, out1 represents the gate scan signal of the drive output terminal OUT in the first shift register unit SR1, out2 represents the gate scan signal of the drive output terminal OUT in the second shift register unit SR2, out3 represents the gate scan signal of the drive output terminal OUT in the third shift register unit SR3, out4 represents the gate scan signal of the drive output terminal OUT in the fourth shift register unit SR4, out5 represents the gate scan signal of the drive output terminal OUT in the fifth shift register unit SR5, out6 represents the gate scan signal of the drive output terminal OUT in the sixth shift register unit SR6, out7 represents the gate scan signal of the drive output terminal OUT in the seventh shift register unit SR7, and out8 represents the gate scan signal of the drive output terminal OUT in the eighth shift register unit SR8.

[0201] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG. 2 as an example and combining it with the signal timing diagram shown in FIG. 6 .

[0202] As shown in Figure 2, all transistors are P-type transistors, the effective pulse signal of the first reference signal output by the first reference signal terminal VREF1 is a low-level signal, the effective pulse signal of the second reference signal output by the second reference signal terminal VREF2 is a low-level signal, the effective pulse signal of the third reference signal output by the third reference signal terminal VREF3 is a high-level signal, the effective pulse signal of the fourth reference signal output by the fourth reference signal terminal VREF4 is a high-level signal, the effective pulse signal of the fifth reference signal output by the fifth reference signal terminal VREF5 is a high-level signal, and the fixed voltage signal of the first level V1 of the first output control signal cs1 is a high-level signal.

[0203] Since the gates of the third transistor M3 and the seventh transistor M7 are both coupled to the second reference voltage signal terminal VREF2, which receives a low-level signal, and the gates of the fourteenth transistor M14 and the fifteenth transistor M15 are both coupled to the first reference voltage signal terminal VREF1, which receives a low-level signal, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, and the fifteenth transistor M15 are normally on. Since the gate of the thirteenth transistor M13 is coupled to the fifth reference voltage signal terminal VREF5, which receives a high-level signal, the thirteenth transistor M13 is normally off. For ease of description, the following will not further analyze the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 at any given moment.

[0204] In the first phase H1, the input signal in provides a high level, the first clock signal ck1 provides a low level, and the second clock signal ck2 provides a high level. The first transistor M1 is turned on by the low level of the first clock signal ck1 and supplies the high level of the input signal in to the third node N3. The second transistor M2 is turned off by the high level of the third node N3. The twelfth transistor M12 is turned off by the high level of the third node N3. The fifteenth transistor M15 supplies the high level of the third node N3 to the second node N2, turning off the second cascode transistor T4 and the second output transistor T2. The ninth transistor M9 is turned on by the low level of the first clock signal ck1 and supplies the low level of the second reference signal terminal VREF2 to the fourth node N4. The tenth transistor M10 is turned on by the low level of the fourth node N4 and supplies the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate of the fourth transistor M4, turning on the fourth transistor M4. The fourth transistor M4 supplies the high level of the second clock signal ck2 to the first electrode of the fifth transistor M5, turning off the fifth transistor M5 under the control of the high level of the second clock signal ck2. The first cascode transistor T3 and the first output transistor T1 are then turned off. The sixth transistor M6 is turned on under the control of the low level of the first clock signal ck1. The sixth transistor M6 and the seventh transistor M7 supply the high level of the input signal in to the fifth node N5. The eighth transistor M8 and the eleventh transistor M11 are then turned off under the control of the high level of the fifth node N5. The cascade signal output by the cascade signal terminal OT remains at a low level, and the gate scan signal output by the driver output terminal OUT remains at a low level.

[0205] In the second phase H2, the input signal in provides a low level, the first clock signal ck1 provides a high level, and the second clock signal ck2 provides a low level. The first transistor M1 is turned off by the high level of the first clock signal ck1, the third node N3 remains at a high level, and the second transistor M2 is turned off by the high level of the third node N3. The twelfth transistor M12 is turned off by the high level of the third node N3. The fifteenth transistor M15 provides the high level of the third node N3 to the second node N2, turning off the second cascode transistor T4 and the second output transistor T2. The ninth transistor M9 is turned off by the high level of the first clock signal ck1, the fourth node N4 remains at a low level, and the tenth transistor M10 is turned on by the low level of the fourth node N4. The tenth transistor M10 provides the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate of the fourth transistor M4, turning on the fourth transistor M4. The fourth transistor M4 supplies the low level of the second clock signal ck2 to the first electrode of the fifth transistor M5. The fifth transistor M5 is turned on by the low level of the second clock signal ck2. The fifth transistor M5 supplies the low level of the first electrode to the first node N1, turning on the first cascode transistor T3 and the first output transistor T1 by the low level of the first node N1. The first cascode transistor T3 supplies the high level of the fourth reference signal terminal VREF4 to the cascode signal terminal OT. The first output transistor T1 supplies the high level of the first output control signal cs1 of the output control signal terminal CS to the driver output terminal OUT. The sixth transistor M6 is turned off by the high level of the first clock signal ck1. The fifth node N5 remains high, turning off the eighth transistor M8 and the eleventh transistor M11 by the high level of the fifth node N5. The cascode signal output from the cascode signal terminal OT remains low, and the gate scan signal output from the driver output terminal OUT remains low. The cascade signal outputted by the cascade signal terminal OT is at a high level, and the gate scanning signal outputted by the driving output terminal OUT is at a high level.

[0206] In the third phase H3, the input signal in provides a low level, the first clock signal ck1 provides a low level, and the second clock signal ck2 provides a high level. The first transistor M1 is turned on by the low level of the first clock signal ck1 and supplies the low level of the input signal in to the third node N3. The second transistor M2 is turned on by the low level of the third node N3 and supplies the low level of the first clock signal ck1 to the fourth node N4. The twelfth transistor M12 is turned on by the low level of the third node N3 and supplies the high level of the fourth reference signal terminal VREF4 to the first node N1. The first cascode transistor T3 and the first output transistor T1 are then turned off. The fifteenth transistor M15 provides the low level of the third node N3 to the second node N2, and the second cascode transistor T4 and the second output transistor T2 are turned on under the control of the low level of the second node N2. The second cascode transistor T4 provides the low level of the first reference signal terminal VREF1 to the cascode signal terminal OT, and the second output transistor T2 provides the low level of the first reference signal terminal VREF1 to the driving output terminal OUT. The ninth transistor M9 is turned on under the control of the low level of the first clock signal ck1, and the ninth transistor M9 provides the low level of the second reference signal terminal VREF2 to the fourth node N4. The tenth transistor M10 is turned on under the control of the low level of the fourth node N4, and the tenth transistor M10 provides the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate of the fourth transistor M4, turning on the fourth transistor M4. The fourth transistor M4 supplies the high level of the second clock signal ck2 to the first electrode of the fifth transistor M5. The fifth transistor M5 is turned off under the control of the high level of the second clock signal ck2. The first cascode transistor T3 and the first output transistor T1 are turned off under the control of the high level of the first node N1. The sixth transistor M6 is turned on under the control of the low level of the first clock signal ck1. The sixth transistor M6 and the seventh transistor M7 supply the low level of the input signal in to the fifth node N5. The eighth transistor M8 and the eleventh transistor M11 are turned on under the control of the low level of the fifth node N5. The eighth transistor M8 supplies the low level of the fifth node N5 to the second node N2, and the eleventh transistor M11 supplies the high level of the second clock signal ck2 to the sixth node N6. The cascade signal outputted by the cascade signal terminal OT remains at a low level, and the gate scan signal outputted by the driver output terminal OUT remains at a low level. The cascade signal outputted by the cascade signal terminal OT is at a low level, and the gate scanning signal outputted by the driving output terminal OUT is at a low level.

[0207] In the subsequent time period, the shift register unit will repeat the working process of the above-mentioned stages H1 to H3.

[0208] In some embodiments of the present disclosure, as shown in Figure 7, the second output control signal cs2 includes a fixed voltage signal portion with a first level V1 and a fixed voltage signal portion with a second level V2, the fixed voltage signal portion with the first level V1 is input to part of the shift register units, and the fixed voltage signal portion with the second level V2 is input to the remaining shift register units.

[0209] Exemplarily, the fixed voltage signal portion of the first level V1 of the second output control signal cs2 is input into the shift register units SR1, SR2, SR6, SR7, and SR8, and the fixed voltage signal portion of the second level V2 of the second output control signal cs2 is input into the shift register units SR3, SR4, and SR5.

[0210] Illustratively, in the local drive mode, the second output control signal cs2 is input to the output control signal terminals of the plurality of shift register units via the first output control signal line CS-1 and the second output control signal line CS-2. A timing diagram of the gate scan signals out1 to out8 applied to scan lines (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8 in FIG. 4 ) is shown in FIG. 7 .

[0211] As shown in FIG7 , in represents the input signal of the input signal terminal IN, ck1 represents the first clock signal of the first clock signal terminal CK1, ck2 represents the second clock signal of the second clock signal terminal CK2, cs2 represents the second output control signal of the output control signal terminal CS, ot1 represents the cascade signal of the cascade signal terminal OT in the first shift register unit SR1, ot2 represents the cascade signal of the cascade signal terminal OT in the second shift register unit SR2, ot3 represents the cascade signal of the cascade signal terminal OT in the third shift register unit SR3, ot4 represents the cascade signal of the cascade signal terminal OT in the fourth shift register unit SR4, ot5 represents the cascade signal of the cascade signal terminal OT in the fifth shift register unit SR5, ot6 represents the cascade signal of the cascade signal terminal OT in the sixth shift register unit SR6, ot7 represents the cascade signal of the cascade signal terminal OT in the seventh shift register unit SR7, and o t8 represents the cascade signal of the cascade signal terminal OT in the eighth shift register unit SR8, out1 represents the gate scan signal of the drive output terminal OUT in the first shift register unit SR1, out2 represents the gate scan signal of the drive output terminal OUT in the second shift register unit SR2, out3 represents the gate scan signal of the drive output terminal OUT in the third shift register unit SR3, out4 represents the gate scan signal of the drive output terminal OUT in the fourth shift register unit SR4, out5 represents the gate scan signal of the drive output terminal OUT in the fifth shift register unit SR5, out6 represents the gate scan signal of the drive output terminal OUT in the sixth shift register unit SR6, out7 represents the gate scan signal of the drive output terminal OUT in the seventh shift register unit SR7, and out8 represents the gate scan signal of the drive output terminal OUT in the eighth shift register unit SR8.

[0212] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG. 2 as an example and combining it with the signal timing diagram shown in FIG. 7 .

[0213] As shown in Figure 2, all transistors are P-type transistors, the effective pulse signal of the first reference signal output by the first reference signal terminal VREF1 is a low-level signal, the effective pulse signal of the second reference signal output by the second reference signal terminal VREF2 is a low-level signal, the effective pulse signal of the third reference signal output by the third reference signal terminal VREF3 is a high-level signal, the effective pulse signal of the fourth reference signal output by the fourth reference signal terminal VREF4 is a high-level signal, the effective pulse signal of the fifth reference signal output by the fifth reference signal terminal VREF5 is a high-level signal, and the second output control signal cs2 has a fixed voltage signal portion of the first level V1 that is a high-level signal, and a fixed voltage signal portion of the second level V2 that is a low-level signal.

[0214] Since the gates of the third transistor M3 and the seventh transistor M7 are both coupled to the second reference voltage signal terminal VREF2, which receives a low-level signal, and the gates of the fourteenth transistor M14 and the fifteenth transistor M15 are both coupled to the first reference voltage signal terminal VREF1, which receives a low-level signal, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, and the fifteenth transistor M15 are normally on. Since the gate of the thirteenth transistor M13 is coupled to the fifth reference voltage signal terminal VREF5, which receives a high-level signal, the thirteenth transistor M13 is normally off. For ease of description, the following will not further analyze the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 at any given moment.

[0215] In the first phase H1, the input signal in provides a high level, the first clock signal ck1 provides a low level, and the second clock signal ck2 provides a high level. The first transistor M1 is turned on by the low level of the first clock signal ck1 and supplies the high level of the input signal in to the third node N3. The second transistor M2 is turned off by the high level of the third node N3. The twelfth transistor M12 is turned off by the high level of the third node N3. The fifteenth transistor M15 supplies the high level of the third node N3 to the second node N2, turning off the second cascode transistor T4 and the second output transistor T2. The ninth transistor M9 is turned on by the low level of the first clock signal ck1 and supplies the low level of the second reference signal terminal VREF2 to the fourth node N4. The tenth transistor M10 is turned on by the low level of the fourth node N4 and supplies the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate of the fourth transistor M4, turning on the fourth transistor M4. The fourth transistor M4 supplies the high level of the second clock signal ck2 to the first electrode of the fifth transistor M5, turning off the fifth transistor M5 under the control of the high level of the second clock signal ck2. The first cascode transistor T3 and the first output transistor T1 are then turned off. The sixth transistor M6 is turned on under the control of the low level of the first clock signal ck1. The sixth transistor M6 and the seventh transistor M7 supply the high level of the input signal in to the fifth node N5. The eighth transistor M8 and the eleventh transistor M11 are then turned off under the control of the high level of the fifth node N5. The cascade signal output by the cascade signal terminal OT remains at a low level, and the gate scan signal output by the driver output terminal OUT remains at a low level.

[0216] In the second phase H2, the input signal in provides a low level, the first clock signal ck1 provides a high level, and the second clock signal ck2 provides a low level. The first transistor M1 is turned off by the high level of the first clock signal ck1, the third node N3 remains at a high level, and the second transistor M2 is turned off by the high level of the third node N3. The twelfth transistor M12 is turned off by the high level of the third node N3. The fifteenth transistor M15 provides the high level of the third node N3 to the second node N2, turning off the second cascode transistor T4 and the second output transistor T2. The ninth transistor M9 is turned off by the high level of the first clock signal ck1, the fourth node N4 remains at a low level, and the tenth transistor M10 is turned on by the low level of the fourth node N4. The tenth transistor M10 provides the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate of the fourth transistor M4, turning on the fourth transistor M4. The fourth transistor M4 supplies the low level of the second clock signal ck2 to the first electrode of the fifth transistor M5. The fifth transistor M5 is turned on by the low level of the second clock signal ck2. The fifth transistor M5 supplies the low level of the first electrode to the first node N1, turning on the first cascode transistor T3 and the first output transistor T1 by the low level of the first node N1. The first cascode transistor T3 supplies the high level of the fourth reference signal terminal VREF4 to the cascode signal terminal OT. The first output transistor T1 supplies the high level of the first output control signal cs1 from the output control signal terminal CS to the driver output terminal OUT. The sixth transistor M6 is turned off by the high level of the first clock signal ck1. The fifth node N5 remains high, turning off the eighth transistor M8 and the eleventh transistor M11 by the high level of the fifth node N5. The cascode signal output from the cascode signal terminal OT remains low, and the gate scan signal output from the driver output terminal OUT remains low. The cascade signal outputted by the cascade signal terminal OT is at a high level, and the gate scanning signal outputted by the driving output terminal OUT is at a high level.

[0217] In the third phase H3, the input signal in provides a low level, the first clock signal ck1 provides a low level, and the second clock signal ck2 provides a high level. The first transistor M1 is turned on by the low level of the first clock signal ck1 and supplies the low level of the input signal in to the third node N3. The second transistor M2 is turned on by the low level of the third node N3 and supplies the low level of the first clock signal ck1 to the fourth node N4. The twelfth transistor M12 is turned on by the low level of the third node N3 and supplies the high level of the fourth reference signal terminal VREF4 to the first node N1. The first cascode transistor T3 and the first output transistor T1 are then turned off. The fifteenth transistor M15 provides the low level of the third node N3 to the second node N2, and the second cascode transistor T4 and the second output transistor T2 are turned on under the control of the low level of the second node N2. The second cascode transistor T4 provides the low level of the first reference signal terminal VREF1 to the cascode signal terminal OT, and the second output transistor T2 provides the low level of the first reference signal terminal VREF1 to the driving output terminal OUT. The ninth transistor M9 is turned on under the control of the low level of the first clock signal ck1, and the ninth transistor M9 provides the low level of the second reference signal terminal VREF2 to the fourth node N4. The tenth transistor M10 is turned on under the control of the low level of the fourth node N4, and the tenth transistor M10 provides the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate of the fourth transistor M4, turning on the fourth transistor M4. The fourth transistor M4 supplies the high level of the second clock signal ck2 to the first electrode of the fifth transistor M5. The fifth transistor M5 is turned off under the control of the high level of the second clock signal ck2. The first cascode transistor T3 and the first output transistor T1 are turned off under the control of the high level of the first node N1. The sixth transistor M6 is turned on under the control of the low level of the first clock signal ck1. The sixth transistor M6 and the seventh transistor M7 supply the low level of the input signal in to the fifth node N5. The eighth transistor M8 and the eleventh transistor M11 are turned on under the control of the low level of the fifth node N5. The eighth transistor M8 supplies the low level of the fifth node N5 to the second node N2, and the eleventh transistor M11 supplies the high level of the second clock signal ck2 to the sixth node N6. The cascade signal outputted by the cascade signal terminal OT remains at a low level, and the gate scan signal outputted by the driver output terminal OUT remains at a low level. The cascade signal outputted by the cascade signal terminal OT is at a low level, and the gate scanning signal outputted by the driving output terminal OUT is at a low level.

[0218] In the subsequent time period, the shift register unit will repeat the working process of the above-mentioned stages H1 to H3.

[0219] In the embodiment of the present disclosure, the signal at the output control signal terminal is controlled to control the gate scanning signal at the driving output terminal in the output circuit, thereby controlling any area of ​​the display panel to be scanned, and controlling any area of ​​the display panel not to be scanned, thereby saving power consumption and reducing losses.

[0220] The present disclosure also provides another structural diagram of a shift register unit, as shown in Figure 8, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0221] In other embodiments of the present disclosure, as shown in Figure 8, the input sub-circuit 110 includes: a sixteenth transistor M16 and a seventeenth transistor M17; wherein, the gate of the sixteenth transistor M16 is coupled to the first clock signal terminal CK1, the first electrode of the sixteenth transistor M16 is coupled to the input signal terminal IN, and the second electrode of the sixteenth transistor M16 is coupled to the seventh node N7; the gate of the seventeenth transistor M17 is coupled to the first clock signal terminal CK1, the first electrode of the seventeenth transistor M17 is coupled to the seventh node N7, and the second electrode of the seventeenth transistor M17 is coupled to the third node N3.

[0222] In some other embodiments of the present disclosure, as shown in FIG8 , the control subcircuit 120 includes: an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a fifth capacitor C5, and a sixth capacitor C6; wherein a gate of the eighteenth transistor M18 is coupled to the cascade output terminal OT, a first electrode of the eighteenth transistor M18 is coupled to the third clock signal terminal CK3, and a second electrode of the eighteenth transistor M18 is coupled to the seventh node N7; a gate of the nineteenth transistor M19 is coupled to the input signal terminal IN, a first electrode of the nineteenth transistor M19 is coupled to the first reference signal terminal VREF1, and a second electrode of the nineteenth transistor M19 is coupled to the second node N2; a gate of the twentieth transistor M20 is coupled to the second node N2, a first electrode of the twentieth transistor M20 is coupled to the first reference signal terminal VREF1, and a second electrode of the twentieth transistor M20 is coupled to the eighth node N8 a gate of the twenty-first transistor M21 is coupled to the second node N2, a first electrode of the twenty-first transistor M21 is coupled to the eighth node N8, and a second electrode of the twenty-first transistor M21 is coupled to the third node N3; a gate of the twenty-second transistor M22 is coupled to the third node N3, a first electrode of the twenty-second transistor M22 is coupled to the eighth node N8, and a second electrode of the twenty-second transistor M22 is coupled to the sixth reference signal terminal VREF6; a gate of the twenty-third transistor M23 is coupled to the fourth clock signal terminal CK4, a first electrode of the twenty-third transistor M23 is coupled to the second node N2, and a second electrode of the twenty-third transistor M23 is coupled to the sixth reference signal terminal VREF6; a first electrode of the fifth capacitor C5 is coupled to the first reference signal terminal VREF1, and a second electrode of the fifth capacitor C5 is coupled to the first electrode of the twenty-third transistor M23; a first electrode of the sixth capacitor C6 is coupled to the cascade output terminal OT, and a second electrode of the sixth capacitor C6 is coupled to the first node N1.

[0223] In other embodiments of the present disclosure, as shown in Figure 8, the cascade sub-circuit 130 includes: a first cascade transistor T3 and a second cascade transistor T4; wherein, the gate of the first cascade transistor T3 is coupled to the first node N1, the first electrode of the first cascade transistor T3 is coupled to the cascade output terminal OT, and the second electrode of the first cascade transistor T3 is coupled to the third clock signal terminal CK3; the gate of the second cascade transistor T4 is coupled to the second node N2, the first electrode of the second cascade transistor T4 is coupled to the first reference signal terminal VREF1, and the second electrode of the second cascade transistor T4 is coupled to the cascade output terminal OT.

[0224] In some other embodiments of the present disclosure, as shown in FIG9 , the first output control signals cs- 1 and cs- 2 are clock signals.

[0225] For example, in full-screen drive mode, first output control signals CS-1 and CS-2 are input to the output control signal terminals of the plurality of shift register units via first and second output control signal lines CS-1 and CS-2, respectively. A timing diagram of gate scan signals out1 through out8 applied to scan lines (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8 in FIG. 4 ) is shown in FIG. 9 .

[0226] As shown in FIG9 , in represents the input signal of the input signal terminal IN, ck1 represents the first clock signal of the first clock signal terminal CK1, ck3 represents the third clock signal of the third clock signal terminal CK3, ck4 represents the fourth clock signal of the fourth clock signal terminal CK4, cs-1 represents the first output control signal on the first output control signal line CS-1, cs-2 represents the first output control signal on the second output control signal line CS-2, out1 represents the gate scan signal of the drive output terminal OUT in the first shift register unit SR1, and out2 represents the gate scan signal of the drive output terminal OUT in the second shift register unit SR2. Scanning signal, out3 represents the gate scanning signal of the driving output terminal OUT in the third shift register unit SR3, out4 represents the gate scanning signal of the driving output terminal OUT in the fourth shift register unit SR4, out5 represents the gate scanning signal of the driving output terminal OUT in the fifth shift register unit SR5, out6 represents the gate scanning signal of the driving output terminal OUT in the sixth shift register unit SR6, out7 represents the gate scanning signal of the driving output terminal OUT in the seventh shift register unit SR7, and out8 represents the gate scanning signal of the driving output terminal OUT in the eighth shift register unit SR8.

[0227] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG8 as an example and combining it with the signal timing diagram shown in FIG9 .

[0228] As shown in FIG8 , an example is given in which all transistors are P-type transistors, the valid pulse signal of the first reference signal outputted by the first reference signal terminal VREF1 is a high-level signal, and the valid pulse signal of the sixth reference signal outputted by the sixth reference signal terminal VREF6 is a low-level signal.

[0229] In the first phase H1, the input signal in provides a low level, the first clock signal ck1 provides a low level, the third clock signal ck3 provides a high level, the fourth clock signal ck4 provides a high level, the first output control signal cs-1 on the first output control signal line CS-1 provides a low level, and the first output control signal cs-2 on the second output control signal line CS-2 provides a high level. The sixteenth transistor M16 is turned on by the low level of the first clock signal ck1 and supplies the low level of the input signal in to the seventh node N7. The seventeenth transistor M17 is turned on by the low level of the first clock signal ck1 and supplies the low level of the seventh node N7 to the third node N3 and the first node N1. The twenty-second transistor M22 is turned on by the low level of the third node N3 and supplies the low level of the sixth reference signal terminal VREF6 to the eighth node N8. The nineteenth transistor M19 is turned on by the low level of the input signal in and provides the high level of the first reference signal terminal VREF1 to the second node N2. The twentieth transistor M20 is turned off by the high level of the second node N2. The twenty-first transistor M21 is turned off by the high level of the second node N2. The twenty-third transistor M23 is turned off by the high level of the fourth clock signal ck4. The second cascode transistor T4 and the second output transistor T2 are turned off by the high level of the second node N2. The first cascode transistor T3 and the first output transistor T1 are turned on by the low level of the first node N1. The first cascode transistor T3 provides the high level of the third clock signal ck3 to the cascode signal terminal OT, and the first output transistor T1 provides the high level signal on the output control signal terminal CS to the driver output terminal OUT. The eighteenth transistor M18 is turned off by the high level of the cascode signal. The cascode signal output by the cascode signal terminal OT is then high, and the gate scan signal output by the driver output terminal OUT is then high.

[0230] In the second phase H2, the input signal in is high, the first clock signal ck1 is high, the third clock signal ck3 is low, and the fourth clock signal ck4 is high. The first output control signal cs-1 on the first output control signal line CS-1 is high, and the first output control signal cs-2 on the second output control signal line CS-2 is low. The sixteenth transistor M16 is turned off by the high level of the first clock signal ck1, and the seventh node N7 remains low. The seventeenth transistor M17 is turned off by the high level of the first clock signal ck1, and the third node N3 and the first node N1 remain low. The twenty-second transistor M22 is turned on by the low level of the third node N3, and provides the low level of the sixth reference signal terminal VREF6 to the eighth node N8. The nineteenth transistor M19 is turned off by the high level of the input signal in, and the second node N2 remains high. The twentieth transistor M20 is turned off by the high level of the second node N2. The twenty-first transistor M21 is turned off by the high level of the second node N2. The twenty-third transistor M23 is turned off under the control of the high level of the fourth clock signal ck4. The second cascode transistor T4 and the second output transistor T2 are turned off under the control of the high level of the second node N2. The first cascode transistor T3 and the first output transistor T1 are turned on under the control of the low level of the first node N1. The first cascode transistor T3 provides the low level of the third clock signal ck3 to the cascode signal terminal OT, and the first output transistor T1 provides the low level signal on the output control signal terminal CS to the driver output terminal OUT. The eighteenth transistor M18 is turned on under the control of the low level of the cascode signal. The eighteenth transistor M18 provides the low level of the third clock signal ck3 to the seventh node N7. The cascode signal output by the cascode signal terminal OT is low, and the gate scan signal output by the driver output terminal OUT is low.

[0231] In the third phase H3, the input signal in is high, the first clock signal ck1 is high, the third clock signal ck3 is high, the fourth clock signal ck4 is low, the first output control signal cs-1 on the first output control signal line CS-1 is low, and the first output control signal cs-2 on the second output control signal line CS-2 is high. The sixteenth transistor M16 is turned off by the high level of the first clock signal ck1, and the seventh node N7 remains low. The seventeenth transistor M17 is turned off by the high level of the first clock signal ck1, and the third node N3 and the first node N1 remain low. The twenty-second transistor M22 is turned on by the low level of the third node N3, and provides the low level of the sixth reference signal terminal VREF6 to the eighth node N8. The nineteenth transistor M19 is turned off by the high level of the input signal in, and the second node N2 remains high. The twentieth transistor M20 is turned off by the high level of the second node N2. The twenty-first transistor M21 is turned off by the high level of the second node N2. The twenty-third transistor M23 is turned on by the low level of the fourth clock signal ck4. The second cascode transistor T4 and the second output transistor T2 are turned on by the low level of the second node N2. The second cascode transistor 4 provides the high level of the first reference signal VREF1 to the cascode signal terminal OT, and the second output transistor T2 provides the high level of the first reference signal VREF1 to the driver output terminal OUT. The first cascode transistor T3 and the first output transistor T1 are turned on by the low level of the first node N1. The first cascode transistor T3 provides the high level of the third clock signal ck3 to the cascode signal terminal OT, and the first output transistor T1 provides the high level signal on the output control signal terminal CS to the driver output terminal OUT. The eighteenth transistor M18 is turned off by the high level of the cascode signal. The cascode signal output by the cascode signal terminal OT is high, and the gate scan signal output by the driver output terminal OUT is high.

[0232] In the subsequent time period, the shift register unit will repeat the working process of the above-mentioned stages H1 to H3.

[0233] In other embodiments of the present disclosure, as shown in FIG10 , the second output control signals cs-1′ and cs-2′ include a clock signal portion and a fixed voltage signal portion having a first level V1. The clock signal portion of the second output control signals cs-1′ and cs-2′ is input into some shift register units, while the fixed voltage signal portion having the first level is input into the remaining shift register units. For example, the clock signal portion of the second output control signals cs-1′ and cs-2′ is input into shift register units SR1, SR2, SR6, SR7, and SR8, while the fixed voltage signal portion having the first level V1 is input into shift register units SR3, SR4, and SR5.

[0234] For example, in the local drive mode, the second output control signals cs-1' and cs-2' are input to the output control signal terminals of the plurality of shift register units via the first output control signal line CS-1 and the second output control signal line CS-2, respectively. A timing diagram of the gate scan signals out1 to out8 applied to scan lines (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8 in FIG. 4 ) is shown in FIG. 10 .

[0235] As shown in FIG10 , in represents the input signal of the input signal terminal IN, ck1 represents the first clock signal of the first clock signal terminal CK1, ck3 represents the third clock signal of the third clock signal terminal CK3, ck4 represents the fourth clock signal of the fourth clock signal terminal CK4, cs-1′ represents the second output control signal on the first output control signal line CS-1, cs-2′ represents the second output control signal on the second output control signal line CS-2, out1 represents the gate scan signal of the drive output terminal OUT in the first shift register unit SR1, and out2 represents the gate scan signal of the drive output terminal OUT in the second shift register unit SR2. out3 represents the gate scan signal of the driving output terminal OUT in the third shift register unit SR3, out4 represents the gate scan signal of the driving output terminal OUT in the fourth shift register unit SR4, out5 represents the gate scan signal of the driving output terminal OUT in the fifth shift register unit SR5, out6 represents the gate scan signal of the driving output terminal OUT in the sixth shift register unit SR6, out7 represents the gate scan signal of the driving output terminal OUT in the seventh shift register unit SR7, and out8 represents the gate scan signal of the driving output terminal OUT in the eighth shift register unit SR8.

[0236] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG8 as an example and combining it with the signal timing diagram shown in FIG10 .

[0237] As shown in FIG8 , an example is given in which all transistors are P-type transistors, the valid pulse signal of the first reference signal outputted by the first reference signal terminal VREF1 is a high-level signal, and the valid pulse signal of the sixth reference signal outputted by the sixth reference signal terminal VREF6 is a low-level signal.

[0238] In the first phase H1, the input signal in provides a low level, the first clock signal ck1 provides a low level, the third clock signal ck3 provides a high level, the fourth clock signal ck4 provides a high level, the second output control signal cs-1' on the first output control signal line CS-1 provides a low level, and the second output control signal cs-2' on the second output control signal line CS-2 provides a high level. The sixteenth transistor M16 is turned on by the low level of the first clock signal ck1 and supplies the low level of the input signal in to the seventh node N7. The seventeenth transistor M17 is turned on by the low level of the first clock signal ck1 and supplies the low level of the seventh node N7 to the third node N3 and the first node N1. The twenty-second transistor M22 is turned on by the low level of the third node N3 and supplies the low level of the sixth reference signal terminal VREF6 to the eighth node N8. The nineteenth transistor M19 is turned on by the low level of the input signal in and provides the high level of the first reference signal terminal VREF1 to the second node N2. The twentieth transistor M20 is turned off by the high level of the second node N2. The twenty-first transistor M21 is turned off by the high level of the second node N2. The twenty-third transistor M23 is turned off by the high level of the fourth clock signal ck4. The second cascode transistor T4 and the second output transistor T2 are turned off by the high level of the second node N2. The first cascode transistor T3 and the first output transistor T1 are turned on by the low level of the first node N1. The first cascode transistor T3 provides the high level of the third clock signal ck3 to the cascode signal terminal OT, and the first output transistor T1 provides the high level signal on the output control signal terminal CS to the driver output terminal OUT. The eighteenth transistor M18 is turned off by the high level of the cascode signal. The cascode signal output by the cascode signal terminal OT is then high, and the gate scan signal output by the driver output terminal OUT is then high.

[0239] In the second phase H2, the input signal in is high, the first clock signal ck1 is high, the third clock signal ck3 is low, the fourth clock signal ck4 is high, the second output control signal cs-1' on the first output control signal line CS-1 is high, and the second output control signal cs-2' on the second output control signal line CS-2 is low. The sixteenth transistor M16 is turned off by the high level of the first clock signal ck1, and the seventh node N7 remains low. The seventeenth transistor M17 is turned off by the high level of the first clock signal ck1, and the third node N3 and the first node N1 remain low. The twenty-second transistor M22 is turned on by the low level of the third node N3, and provides the low level of the sixth reference signal terminal VREF6 to the eighth node N8. The nineteenth transistor M19 is turned off by the high level of the input signal in, and the second node N2 remains high. The twentieth transistor M20 is turned off by the high level of the second node N2. The twenty-first transistor M21 is turned off by the high level of the second node N2. The twenty-third transistor M23 is turned off under the control of the high level of the fourth clock signal ck4. The second cascode transistor T4 and the second output transistor T2 are turned off under the control of the high level of the second node N2. The first cascode transistor T3 and the first output transistor T1 are turned on under the control of the low level of the first node N1. The first cascode transistor T3 provides the low level of the third clock signal ck3 to the cascode signal terminal OT, and the first output transistor T1 provides the low level signal on the output control signal terminal CS to the driver output terminal OUT. The eighteenth transistor M18 is turned on under the control of the low level of the cascode signal. The eighteenth transistor M18 provides the low level of the third clock signal ck3 to the seventh node N7. The cascode signal output by the cascode signal terminal OT is low, and the gate scan signal output by the driver output terminal OUT is low.

[0240] In the third phase H3, the input signal in is high, the first clock signal ck1 is high, the third clock signal ck3 is high, the fourth clock signal ck4 is low, the second output control signal cs-1' on the first output control signal line CS-1 is low, and the second output control signal cs-2' on the second output control signal line CS-2 is high. The sixteenth transistor M16 is turned off by the high level of the first clock signal ck1, and the seventh node N7 remains low. The seventeenth transistor M17 is turned off by the high level of the first clock signal ck1, and the third node N3 and the first node N1 remain low. The twenty-second transistor M22 is turned on by the low level of the third node N3, and provides the low level of the sixth reference signal terminal VREF6 to the eighth node N8. The nineteenth transistor M19 is turned off by the high level of the input signal in, and the second node N2 remains high. The twentieth transistor M20 is turned off by the high level of the second node N2. The twenty-first transistor M21 is turned off by the high level of the second node N2. The twenty-third transistor M23 is turned on by the low level of the fourth clock signal ck4. The second cascode transistor T4 and the second output transistor T2 are turned on by the low level of the second node N2. The second cascode transistor 4 provides the high level of the first reference signal VREF1 to the cascode signal terminal OT, and the second output transistor T2 provides the high level of the first reference signal VREF1 to the driver output terminal OUT. The first cascode transistor T3 and the first output transistor T1 are turned on by the low level of the first node N1. The first cascode transistor T3 provides the high level of the third clock signal ck3 to the cascode signal terminal OT, and the first output transistor T1 provides the high level signal on the output control signal terminal CS to the driver output terminal OUT. The eighteenth transistor M18 is turned off by the high level of the cascode signal. The cascode signal output by the cascode signal terminal OT is high, and the gate scan signal output by the driver output terminal OUT is high.

[0241] In the subsequent time period, the shift register unit will repeat the working process of the above-mentioned stages H1 to H3.

[0242] In the embodiment of the present disclosure, the signal at the output control signal terminal is controlled to control the gate scanning signal at the driving output terminal in the output circuit, thereby controlling any area of ​​the display panel to be scanned, and controlling any area of ​​the display panel not to be scanned, thereby saving power consumption and reducing losses.

[0243] The present disclosure also provides another structural diagram of a shift register unit, as shown in Figure 11, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0244] In some further embodiments of the present disclosure, as shown in FIG11 , the first output circuit 210 is coupled to the cascade output terminal OT in the shift register 100 and is configured to transmit a signal from the output control signal terminal CS to the driving output terminal OUT in response to a signal at the cascade output terminal OT;

[0245] In some other embodiments of the present disclosure, as shown in Figure 11, the gate of the first output transistor T1 is coupled to the cascade output terminal OT, the first electrode of the first output transistor T1 is coupled to the output control signal terminal CS, and the second electrode of the first output transistor T1 is coupled to the drive output terminal OUT.

[0246] In some other embodiments of the present disclosure, as shown in FIG11 , the control subcircuit includes: a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-seventh transistor M27, a twenty-eighth transistor M28, a seventh capacitor C7, and an eighth capacitor C8; wherein a gate of the twenty-fourth transistor M24 is coupled to the first clock signal terminal CK1, a first electrode of the twenty-fourth transistor M24 is coupled to the seventh reference signal terminal VREF7, and a second electrode of the twenty-fourth transistor M24 is coupled to the second node N2; a gate of the twenty-fifth transistor M25 is coupled to the third node N3, a first electrode of the twenty-fifth transistor M25 is coupled to the second node N2, and a second electrode of the twenty-fifth transistor M25 is coupled to the first clock signal terminal CK1; a gate of the twenty-sixth transistor M26 is coupled to the second node N2, and a gate of the twenty-sixth transistor M27 is coupled to the second node N3. A first electrode of the transistor M26 is coupled to the first reference signal terminal VREF1, a second electrode of the twenty-sixth transistor M26 is coupled to the first electrode of the twenty-seventh transistor M27; a gate of the twenty-seventh transistor M27 is coupled to the third clock signal terminal CK3, a second electrode of the twenty-seventh transistor M27 is coupled to the first electrode of the twenty-eighth transistor M28; a gate of the twenty-eighth transistor M28 is coupled to the seventh reference signal terminal VREF7, a first electrode of the twenty-eighth transistor M28 is coupled to the third node N3, and a second electrode of the twenty-eighth transistor M28 is coupled to the first node N1; a first electrode of the seventh capacitor C7 is coupled to the first reference signal terminal VREF1, a second electrode of the seventh capacitor C7 is coupled to the first node N1; a first electrode of the eighth capacitor C8 is coupled to the cascade output terminal OT, and a second electrode of the eighth capacitor C8 is coupled to the first node N1.

[0247] In some further embodiments of the present disclosure, as shown in FIG12 , the first output control signals cs- 1 and cs- 2 are clock signals.

[0248] For example, in full-screen drive mode, first output control signals CS-1 and CS-2 are input to the output control signal terminals of the plurality of shift register units via first and second output control signal lines CS-1 and CS-2, respectively. A timing diagram of gate scan signals out1 to out8 applied to scan lines (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8 in FIG. 4 ) is shown in FIG. 12 .

[0249] As shown in FIG12 , in represents the input signal of the input signal terminal IN, ck1 represents the first clock signal of the first clock signal terminal CK1, ck3 represents the third clock signal of the third clock signal terminal CK3, cs-1 represents the first output control signal on the first output control signal line CS-1, cs-2 represents the first output control signal on the second output control signal line CS-2, out1 represents the gate scanning signal of the driving output terminal OUT in the first shift register unit SR1, out2 represents the gate scanning signal of the driving output terminal OUT in the second shift register unit SR2, and out3 represents the gate scanning signal of the first shift register unit SR1. The gate scan signal of the driving output terminal OUT in the three shift register units SR3, out4 represents the gate scan signal of the driving output terminal OUT in the fourth shift register unit SR4, out5 represents the gate scan signal of the driving output terminal OUT in the fifth shift register unit SR5, out6 represents the gate scan signal of the driving output terminal OUT in the sixth shift register unit SR6, out7 represents the gate scan signal of the driving output terminal OUT in the seventh shift register unit SR7, and out8 represents the gate scan signal of the driving output terminal OUT in the eighth shift register unit SR8.

[0250] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG11 as an example and combining it with the signal timing diagram shown in FIG12 .

[0251] As shown in FIG11 , an example is given in which all transistors are P-type transistors, the valid pulse signal of the first reference signal outputted by the first reference signal terminal VREF1 is a high-level signal, and the valid pulse signal of the seventh reference signal outputted by the seventh reference signal terminal VREF7 is a low-level signal.

[0252] Since the twenty-eighth transistor M28 is coupled to the seventh reference signal terminal VREF7 and the seventh reference signal terminal VREF7 inputs a low-level signal, the twenty-eighth transistor M28 is in a normally-on state. For ease of description, the state of the twenty-eighth transistor M28 at any moment will not be analyzed below.

[0253] In the first phase H1, the input signal in provides a low level, the first clock signal ck1 provides a low level, the third clock signal ck3 provides a high level, the first output control signal cs-1 on the first output control signal line CS-1 provides a low level, and the first output control signal cs-2 on the second output control signal line CS-2 provides a high level. The first transistor M1 is turned on by the low level of the first clock signal ck1 and supplies the low level of the input signal in to the third node N3. The twenty-eighth transistor M28 supplies the low level of the third node N3 to the first node N1. The first cascode transistor T3 and the first output transistor T1 are turned on by the low level of the first node N1. The first cascode transistor T3 supplies the high level of the third clock signal ck3 to the cascode signal terminal OT, and the first output transistor T1 supplies the high level signal from the output control signal terminal CS to the driver output terminal OUT. The twenty-fifth transistor M25 is turned on by the low level of the third node N3 and supplies the low level of the first clock signal ck1 to the second node N2. The twenty-fourth transistor M24 is turned on by the low level of the first clock signal ck1 and supplies the low level of the seventh reference signal terminal VREF7 to the second node N2. The twenty-sixth transistor M26 is turned on by the low level of the second node N2 and supplies the high level of the first reference signal terminal VREF1 to the first electrode of the twenty-seventh transistor M27. The twenty-seventh transistor M27 is turned off by the high level of the third clock signal ck3. The second cascode transistor T4 and the second output transistor T2 are turned on by the low level of the second node N2. The second cascode transistor T4 supplies the high level of the first reference signal terminal VREF1 to the cascode signal terminal OT, and the second output transistor T2 supplies the high level of the first reference signal terminal VREF1 to the driver output terminal OUT. The cascode signal output by the cascode signal terminal OT is then high, and the gate scan signal output by the driver output terminal OUT is also high.

[0254] In the second phase H1, the input signal in is high, the first clock signal ck1 is high, the third clock signal ck3 is low, the first output control signal cs-1 on the first output control signal line CS-1 is high, and the first output control signal cs-2 on the second output control signal line CS-2 is low. The first transistor M1 is turned off by the high level of the first clock signal ck1, and the third node N3 remains low. The twenty-eighth transistor M28 provides the low level of the third node N3 to the first node N1. The first cascode transistor T3 and the first output transistor T1 are turned off by the high level of the first node N1. The first cascode transistor T3 provides the low level of the third clock signal ck3 to the cascode signal terminal OT, and the first output transistor T1 provides the low level signal from the output control signal terminal CS to the driver output terminal OUT. The twenty-fourth transistor M24 is turned off by the high level of the first clock signal ck1, and the second node N2 remains low. The twenty-fifth transistor M25 is turned on under the control of the low level of the third node N3. The twenty-fifth transistor M25 provides the high level of the first clock signal ck1 to the second node N2, and the second node N2 is at a high level. The twenty-sixth transistor M26 is turned off under the control of the high level of the second node N2, and the twenty-seventh transistor M27 is turned on under the control of the low level of the third clock signal ck3. The second cascode transistor T4 and the second output transistor T2 are turned off under the control of the high level of the second node N2. The cascade signal output by the cascade signal terminal OT is at a low level, and the gate scan signal output by the driver output terminal OUT is at a low level.

[0255] In the third phase H1, the input signal in is at a high level, the first clock signal ck1 is at a low level, the third clock signal ck3 is at a high level, the first output control signal cs-1 on the first output control signal line CS-1 is at a low level, and the first output control signal cs-2 on the second output control signal line CS-2 is at a high level. The first transistor M1 is turned on by the low level of the first clock signal ck1 and supplies the high level of the input signal in to the third node N3. The twenty-eighth transistor M28 supplies the high level of the third node N3 to the first node N1. The first cascode transistor T3 and the first output transistor T1 are turned off by the high level of the first node N1. The twenty-fifth transistor M25 is turned off by the high level of the third node N3. The twenty-fourth transistor M24 is turned on by the low level of the first clock signal ck1 and supplies the low level of the seventh reference signal terminal VREF7 to the second node N2. The 26th transistor M26 is turned on by the low level control of the second node N2. The 26th transistor M26 provides the high level of the first reference signal terminal VREF1 to the first electrode of the 27th transistor M27. The 27th transistor M27 is turned off by the high level control of the third clock signal ck3. The second cascode transistor T4 and the second output transistor T2 are turned on by the low level control of the second node N2. The second cascode transistor T4 provides the high level of the first reference signal terminal VREF1 to the cascode signal terminal OT. The second output transistor T2 provides the high level of the first reference signal terminal VREF1 to the driver output terminal OUT. The cascode signal output by the cascode signal terminal OT is then at a high level, and the gate scan signal output by the driver output terminal OUT is also at a high level.

[0256] In the subsequent time period, the shift register unit will repeat the working process of the above-mentioned stages H1 to H3.

[0257] In some further embodiments of the present disclosure, as shown in FIG13 , the second output control signals cs-1′ and cs-2′ include a clock signal portion and a fixed voltage signal portion having a first level V1. The clock signal portion of the second output control signals cs-1′ and cs-2′ is input into some shift register units, while the fixed voltage signal portion having the first level is input into the remaining shift register units. Exemplarily, the clock signal portion of the second output control signals cs-1′ and cs-2′ is input into shift register units SR1, SR2, SR6, SR7, and SR8, while the fixed voltage signal portion having the first level V1 is input into shift register units SR3, SR4, and SR5.

[0258] In the subsequent time period, the shift register unit will repeat the working process of the above-mentioned stages H1 to H3.

[0259] For example, in the local drive mode, the second output control signals cs-1' and cs-2' are input to the output control signal terminals of the plurality of shift register units via the first output control signal line CS-1 and the second output control signal line CS-2, respectively. A timing diagram of the gate scan signals out1 to out8 applied to scan lines (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8 in FIG. 4 ) is shown in FIG. 13 .

[0260] As shown in FIG13 , in represents the input signal of the input signal terminal IN, ck1 represents the first clock signal of the first clock signal terminal CK1, ck3 represents the third clock signal of the third clock signal terminal CK3, cs-1′ represents the second output control signal on the first output control signal line CS-1, cs-2′ represents the second output control signal on the second output control signal line CS-2, out1 represents the gate scanning signal of the driving output terminal OUT in the first shift register unit SR1, out2 represents the gate scanning signal of the driving output terminal OUT in the second shift register unit SR2, and out3 represents The gate scan signal of the driving output terminal OUT in the third shift register unit SR3, out4 represents the gate scan signal of the driving output terminal OUT in the fourth shift register unit SR4, out5 represents the gate scan signal of the driving output terminal OUT in the fifth shift register unit SR5, out6 represents the gate scan signal of the driving output terminal OUT in the sixth shift register unit SR6, out7 represents the gate scan signal of the driving output terminal OUT in the seventh shift register unit SR7, and out8 represents the gate scan signal of the driving output terminal OUT in the eighth shift register unit SR8.

[0261] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG11 as an example and combining it with the signal timing diagram shown in FIG13 .

[0262] As shown in FIG11 , an example is given in which all transistors are P-type transistors, the valid pulse signal of the first reference signal outputted by the first reference signal terminal VREF1 is a high-level signal, and the valid pulse signal of the seventh reference signal outputted by the seventh reference signal terminal VREF7 is a low-level signal.

[0263] Since the twenty-eighth transistor M28 is coupled to the seventh reference signal terminal VREF7 and the seventh reference signal terminal VREF7 inputs a low-level signal, the twenty-eighth transistor M28 is in a normally-on state. For ease of description, the state of the twenty-eighth transistor M28 at any moment will not be analyzed below.

[0264] In the first phase H1, the input signal in provides a low level, the first clock signal ck1 provides a low level, the third clock signal ck3 provides a high level, the first output control signal cs-1 on the first output control signal line CS-1 provides a low level, and the first output control signal cs-2 on the second output control signal line CS-2 provides a high level. The first transistor M1 is turned on by the low level of the first clock signal ck1 and supplies the low level of the input signal in to the third node N3. The twenty-eighth transistor M28 supplies the low level of the third node N3 to the first node N1. The first cascode transistor T3 and the first output transistor T1 are turned on by the low level of the first node N1. The first cascode transistor T3 supplies the high level of the third clock signal ck3 to the cascode signal terminal OT, and the first output transistor T1 supplies the high level signal from the output control signal terminal CS to the driver output terminal OUT. The twenty-fifth transistor M25 is turned on by the low level of the third node N3 and supplies the low level of the first clock signal ck1 to the second node N2. The twenty-fourth transistor M24 is turned on in response to the low level of the first clock signal ck1. The twenty-fourth transistor M24 supplies the low level of the seventh reference signal terminal VREF7 to the second node N2. The twenty-sixth transistor M26 is turned on in response to the low level of the second node N2. The twenty-sixth transistor M26 supplies the high level of the first reference signal terminal VREF1 to the first electrode of the twenty-seventh transistor M27. The twenty-seventh transistor M27 is turned off in response to the high level of the third clock signal ck3. The second cascode transistor T4 and the second output transistor T2 are turned on in response to the low level of the second node N2. The second cascode transistor T4 supplies the high level of the first reference signal terminal VREF1 to the cascode signal terminal OT. The second output transistor T2 supplies the high level of the first reference signal terminal VREF1 to the driver output terminal OUT. Consequently, the cascode signal output by the cascode signal terminal OT is high, and the gate scan signal output by the driver output terminal OUT is high.

[0265] In the second phase H1, the input signal in is high, the first clock signal ck1 is high, the third clock signal ck3 is low, the first output control signal cs-1 on the first output control signal line CS-1 is high, and the first output control signal cs-2 on the second output control signal line CS-2 is low. The first transistor M1 is turned off by the high level of the first clock signal ck1, and the third node N3 remains low. The twenty-eighth transistor M28 provides the low level of the third node N3 to the first node N1. The first cascode transistor T3 and the first output transistor T1 are turned off by the high level of the first node N1. The first cascode transistor T3 provides the low level of the third clock signal ck3 to the cascode signal terminal OT, and the first output transistor T1 provides the low level signal from the output control signal terminal CS to the driver output terminal OUT. The twenty-fourth transistor M24 is turned off by the high level of the first clock signal ck1, and the second node N2 remains low. The twenty-fifth transistor M25 is turned on under the control of the low level of the third node N3. The twenty-fifth transistor M25 provides the high level of the first clock signal ck1 to the second node N2, and the second node N2 is at a high level. The twenty-sixth transistor M26 is turned off under the control of the high level of the second node N2, and the twenty-seventh transistor M27 is turned on under the control of the low level of the third clock signal ck3. The second cascode transistor T4 and the second output transistor T2 are turned off under the control of the high level of the second node N2. The cascade signal output by the cascade signal terminal OT is at a low level, and the gate scan signal output by the driver output terminal OUT is at a low level.

[0266] In the third phase H1, the input signal in is at a high level, the first clock signal ck1 is at a low level, the third clock signal ck3 is at a high level, the first output control signal cs-1 on the first output control signal line CS-1 is at a low level, and the first output control signal cs-2 on the second output control signal line CS-2 is at a high level. The first transistor M1 is turned on by the low level of the first clock signal ck1 and supplies the high level of the input signal in to the third node N3. The twenty-eighth transistor M28 supplies the high level of the third node N3 to the first node N1. The first cascode transistor T3 and the first output transistor T1 are turned off by the high level of the first node N1. The twenty-fifth transistor M25 is turned off by the high level of the third node N3. The twenty-fourth transistor M24 is turned on by the low level of the first clock signal ck1 and supplies the low level of the seventh reference signal terminal VREF7 to the second node N2. The 26th transistor M26 is turned on by the low level control of the second node N2. The 26th transistor M26 provides the high level of the first reference signal terminal VREF1 to the first electrode of the 27th transistor M27. The 27th transistor M27 is turned off by the high level control of the third clock signal ck3. The second cascode transistor T4 and the second output transistor T2 are turned on by the low level control of the second node N2. The second cascode transistor T4 provides the high level of the first reference signal terminal VREF1 to the cascode signal terminal OT. The second output transistor T2 provides the high level of the first reference signal terminal VREF1 to the driver output terminal OUT. The cascode signal output by the cascode signal terminal OT is then at a high level, and the gate scan signal output by the driver output terminal OUT is also at a high level.

[0267] In the subsequent time period, the shift register unit will repeat the working process of the above-mentioned stages H1 to H3.

[0268] As shown in FIG6 , in represents the input signal of the input signal terminal IN, ck1 represents the first clock signal of the first clock signal terminal CK1, ck2 represents the second clock signal of the second clock signal terminal CK2, cs1 represents the first output control signal of the output control signal terminal CS, ot1 represents the cascade signal of the cascade signal terminal OT in the first shift register unit SR1, ot2 represents the cascade signal of the cascade signal terminal OT in the second shift register unit SR2, ot3 represents the cascade signal of the cascade signal terminal OT in the third shift register unit SR3, ot4 represents the cascade signal of the cascade signal terminal OT in the fourth shift register unit SR4, ot5 represents the cascade signal of the cascade signal terminal OT in the fifth shift register unit SR5, ot6 represents the cascade signal of the cascade signal terminal OT in the sixth shift register unit SR6, ot7 represents the cascade signal of the cascade signal terminal OT in the seventh shift register unit SR7, and o t8 represents the cascade signal of the cascade signal terminal OT in the eighth shift register unit SR8, out1 represents the gate scan signal of the drive output terminal OUT in the first shift register unit SR1, out2 represents the gate scan signal of the drive output terminal OUT in the second shift register unit SR2, out3 represents the gate scan signal of the drive output terminal OUT in the third shift register unit SR3, out4 represents the gate scan signal of the drive output terminal OUT in the fourth shift register unit SR4, out5 represents the gate scan signal of the drive output terminal OUT in the fifth shift register unit SR5, out6 represents the gate scan signal of the drive output terminal OUT in the sixth shift register unit SR6, out7 represents the gate scan signal of the drive output terminal OUT in the seventh shift register unit SR7, and out8 represents the gate scan signal of the drive output terminal OUT in the eighth shift register unit SR8.

[0269] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG21 as an example and combining it with the signal timing diagram shown in FIG6 .

[0270] As shown in Figure 21, all transistors are P-type transistors, the effective pulse signal of the first reference signal output by the first reference signal terminal VREF1 is a low-level signal, the effective pulse signal of the second reference signal output by the second reference signal terminal VREF2 is a low-level signal, the effective pulse signal of the third reference signal output by the third reference signal terminal VREF3 is a high-level signal, the effective pulse signal of the fourth reference signal output by the fourth reference signal terminal VREF4 is a high-level signal, the effective pulse signal of the fifth reference signal output by the fifth reference signal terminal VREF5 is a high-level signal, and the fixed voltage signal of the first level V1 of the first output control signal cs1 is a high-level signal.

[0271] Since the gates of the third transistor M3 and the seventh transistor M7 are both coupled to the second reference voltage signal terminal VREF2, which receives a low-level signal, and the gates of the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-eighth transistor M28 are all coupled to the first reference voltage signal terminal VREF1, which receives a low-level signal, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-eighth transistor M28 are normally on. Since the gate of the thirteenth transistor M13 is coupled to the fifth reference voltage signal terminal VREF5, which receives a high-level signal, the thirteenth transistor M13 is normally off. For ease of description, the following will not further analyze the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 at any given moment.

[0272] In the first phase H1, the input signal in provides a high level, the first clock signal ck1 provides a low level, and the second clock signal ck2 provides a high level. The first transistor M1 is turned on by the low level of the first clock signal ck1 and supplies the high level of the input signal in to the third node N3. The second transistor M2 is turned off by the high level of the third node N3. The twelfth transistor M12 is turned off by the high level of the third node N3. The fifteenth transistor M15 supplies the high level of the third node N3 to the second node N2, turning off the second cascode transistor T4 and the second output transistor T2. The ninth transistor M9 is turned on by the low level of the first clock signal ck1 and supplies the low level of the second reference signal terminal VREF2 to the fourth node N4. The tenth transistor M10 is turned on by the low level of the fourth node N4 and supplies the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate of the fourth transistor M4, turning on the fourth transistor M4. The fourth transistor M4 supplies the high level of the second clock signal ck2 to the first electrode of the fifth transistor M5, turning off the fifth transistor M5 under the control of the high level of the second clock signal ck2. The first cascode transistor T3 and the first output transistor T1 are then turned off. The sixth transistor M6 is turned on under the control of the low level of the first clock signal ck1. The sixth transistor M6 and the seventh transistor M7 supply the high level of the input signal in to the fifth node N5. The eighth transistor M8 and the eleventh transistor M11 are then turned off under the control of the high level of the fifth node N5. The cascade signal output by the cascade signal terminal OT remains at a low level, and the gate scan signal output by the driver output terminal OUT remains at a low level.

[0273] In the second phase H2, the input signal in provides a low level, the first clock signal ck1 provides a high level, and the second clock signal ck2 provides a low level. The first transistor M1 is turned off by the high level of the first clock signal ck1, the third node N3 remains at a high level, and the second transistor M2 is turned off by the high level of the third node N3. The twelfth transistor M12 is turned off by the high level of the third node N3. The fifteenth transistor M15 provides the high level of the third node N3 to the second node N2, turning off the second cascode transistor T4 and the second output transistor T2. The ninth transistor M9 is turned off by the high level of the first clock signal ck1, the fourth node N4 remains at a low level, and the tenth transistor M10 is turned on by the low level of the fourth node N4. The tenth transistor M10 provides the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate of the fourth transistor M4, turning on the fourth transistor M4. The fourth transistor M4 supplies the low level of the second clock signal ck2 to the first electrode of the fifth transistor M5. The fifth transistor M5 is turned on by the low level of the second clock signal ck2. The fifth transistor M5 supplies the low level of the first electrode to the first node N1, turning on the first cascode transistor T3 and the first output transistor T1 by the low level of the first node N1. The first cascode transistor T3 supplies the high level of the fourth reference signal terminal VREF4 to the cascode signal terminal OT. The first output transistor T1 supplies the high level of the first output control signal cs1 from the output control signal terminal CS to the driver output terminal OUT. The sixth transistor M6 is turned off by the high level of the first clock signal ck1. The fifth node N5 remains high, turning off the eighth transistor M8 and the eleventh transistor M11 by the high level of the fifth node N5. The cascode signal output from the cascode signal terminal OT remains low, and the gate scan signal output from the driver output terminal OUT remains low. The cascade signal outputted by the cascade signal terminal OT is at a high level, and the gate scanning signal outputted by the driving output terminal OUT is at a high level.

[0274] In the third phase H3, the input signal in provides a low level, the first clock signal ck1 provides a low level, and the second clock signal ck2 provides a high level. The first transistor M1 is turned on by the low level of the first clock signal ck1 and supplies the low level of the input signal in to the third node N3. The second transistor M2 is turned on by the low level of the third node N3 and supplies the low level of the first clock signal ck1 to the fourth node N4. The twelfth transistor M12 is turned on by the low level of the third node N3 and supplies the high level of the fourth reference signal terminal VREF4 to the first node N1. The first cascode transistor T3 and the first output transistor T1 are then turned off. The fifteenth transistor M15 provides the low level of the third node N3 to the second node N2, and the second cascode transistor T4 and the second output transistor T2 are turned on under the control of the low level of the second node N2. The second cascode transistor T4 provides the low level of the first reference signal terminal VREF1 to the cascode signal terminal OT, and the second output transistor T2 provides the low level of the first reference signal terminal VREF1 to the driving output terminal OUT. The ninth transistor M9 is turned on under the control of the low level of the first clock signal ck1, and the ninth transistor M9 provides the low level of the second reference signal terminal VREF2 to the fourth node N4. The tenth transistor M10 is turned on under the control of the low level of the fourth node N4, and the tenth transistor M10 provides the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate of the fourth transistor M4, turning on the fourth transistor M4. The fourth transistor M4 supplies the high level of the second clock signal ck2 to the first electrode of the fifth transistor M5. The fifth transistor M5 is turned off under the control of the high level of the second clock signal ck2. The first cascode transistor T3 and the first output transistor T1 are turned off under the control of the high level of the first node N1. The sixth transistor M6 is turned on under the control of the low level of the first clock signal ck1. The sixth transistor M6 and the seventh transistor M7 supply the low level of the input signal in to the fifth node N5. The eighth transistor M8 and the eleventh transistor M11 are turned on under the control of the low level of the fifth node N5. The eighth transistor M8 supplies the low level of the fifth node N5 to the second node N2, and the eleventh transistor M11 supplies the high level of the second clock signal ck2 to the sixth node N6. The cascade signal outputted by the cascade signal terminal OT remains at a low level, and the gate scan signal outputted by the driver output terminal OUT remains at a low level. The cascade signal outputted by the cascade signal terminal OT is at a low level, and the gate scanning signal outputted by the driving output terminal OUT is at a low level.

[0275] In the subsequent time period, the shift register unit will repeat the working process of the above-mentioned stages H1 to H3.

[0276] As shown in Figures 21 and 22, multiple output control signal lines (such as CS-1 and CS-2 in Figure 3) include: a first output control signal line CS-1 and a second output control signal line CS-2; every eight adjacent shift register units in a plurality of shift register units constitute a shift register unit group; the first output control signal line CS-1 is coupled to the output control signal terminal CS of the shift register units in the odd-numbered shift register unit group, and the second output control signal line CS-2 is coupled to the output control signal terminal CS of the shift register units in the even-numbered shift register unit group. Exemplarily, the first output control signal line CS-1 is coupled to the output control signal terminal CS of the shift register units SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8; and the second output control signal line CS-2 is coupled to the output control signal terminal CS of the shift register units SR9, SR10, SR11, SR12, SR13, SR14, SR15, and SR16.in represents the input signal of the input signal terminal IN, ck1 represents the first clock signal of the first clock signal terminal CK1, ck2 represents the second clock signal of the second clock signal terminal CK2, cs1 represents the first output control signal of the output control signal terminal CS, out1 represents the gate scan signal of the driving output terminal OUT in the first shift register unit SR1, out2 represents the gate scan signal of the driving output terminal OUT in the second shift register unit SR2, out3 represents the gate scan signal of the driving output terminal OUT in the third shift register unit SR3, out4 represents the gate scan signal of the driving output terminal OUT in the fourth shift register unit SR4, out5 represents the gate scan signal of the driving output terminal OUT in the fifth shift register unit SR5, out6 represents the gate scan signal of the driving output terminal OUT in the sixth shift register unit SR6, out7 represents the gate scan signal of the driving output terminal OUT in the seventh shift register unit SR7, and out8 represents the gate scan signal of the driving output terminal OUT in the eighth shift register unit SR8. out15 represents the gate scan signal of the drive output terminal OUT in the fifteenth shift register unit SR15, out16 represents the gate scan signal of the drive output terminal OUT in the sixteenth shift register unit SR16, and out17 represents the gate scan signal of the drive output terminal OUT in the seventeenth shift register unit SR17. The pulse width of the input signal in is 18H, the pulse width of a high level segment or a low level segment of each clock signal end is 2H, and the pulse width of the effective gate scan signal output by the driving output end OUT and the effective cascade signal output by the cascade output end OT is 18H.

[0277] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG21 as an example and combining it with the signal timing diagram shown in FIG23 .

[0278] As shown in Figure 21, all transistors are P-type transistors, the effective pulse signal of the first reference signal output by the first reference signal terminal VREF1 is a low-level signal, the effective pulse signal of the second reference signal output by the second reference signal terminal VREF2 is a low-level signal, the effective pulse signal of the third reference signal output by the third reference signal terminal VREF3 is a high-level signal, the effective pulse signal of the fourth reference signal output by the fourth reference signal terminal VREF4 is a high-level signal, the effective pulse signal of the fifth reference signal output by the fifth reference signal terminal VREF5 is a high-level signal, the first output control signal cs-1 is a fixed voltage signal with a first level V1 as a high-level signal, and the first output control signal cs-2 is a fixed voltage signal with a first level V1 as a high-level signal.

[0279] Since the gates of the third transistor M3 and the seventh transistor M7 are both coupled to the second reference voltage signal terminal VREF2, which receives a low-level signal, and the gates of the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-eighth transistor M28 are all coupled to the first reference voltage signal terminal VREF1, which receives a low-level signal, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-eighth transistor M28 are normally on. Since the gate of the thirteenth transistor M13 is coupled to the fifth reference voltage signal terminal VREF5, which receives a high-level signal, the thirteenth transistor M13 is normally off. For ease of description, the following will not further analyze the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 at any given moment.

[0280] In the first phase H1, the input signal in is a low-level signal, and the second clock signal ck2 and the first clock signal ck1 periodically switch between high and low levels. The third node N3 is connected only to the input signal terminal IN, so the third node N3 always remains at a low level. Controlled by the potential of the third node N3, the twelfth transistor M12 is turned on, the third node N3 is connected to the fourth reference signal terminal VREF4, and the third node N3 remains at a high level. Controlled by the potential of the third node N3, the first output transistor T1 and the first cascode transistor T3 are turned off, the fourth reference signal terminal VREF4 is disconnected from the second terminal and the cascode output terminal OT, and the output control signal terminal CS is disconnected from the driver output terminal OUT. Controlled by the potential of the third node N3, the second cascode transistor T4 and the second output transistor T2 are turned on, the first reference signal terminal VREF1 is connected to the cascode output terminal OT, and the first reference signal terminal VREF1 is connected to the driver output terminal OUT. The cascode output terminal OT outputs a low-level signal, and the driver output terminal OUT outputs a low-level signal.

[0281] In the second phase H2, the input signal in is a high-level signal, the second clock signal ck2 provides a high-level signal, and the first clock signal ck1 provides a low-level signal. The first transistor M1 and the sixth transistor M6 are turned on, and the third node N3 remains in a high-level state. Controlled by the potential of the third node N3, the second transistor M2, the twelfth transistor M12, the second cascode transistor T4, and the second output transistor T2 are turned off. The second cascode transistor T4 and the second output transistor T2 are turned off, the first reference signal terminal VREF1 is disconnected from the cascode output terminal OT, and the first reference signal terminal VREF1 is disconnected from the drive output terminal OUT. Controlled by the first clock signal ck1, the ninth transistor M9 is turned on, the second reference signal terminal VREF2 is connected to the fourth node N4, and the fourth node N4 remains low. Controlled by the fourth node N4, the fourth transistor M4 is turned on. Controlled by the second clock signal ck2, the fifth transistor M5 is turned off. The first node N1 remains high, the first cascode transistor T3 and the first output transistor T1 are turned off, the fourth reference signal terminal VREF4 is disconnected from the cascode output terminal OT, and the output signal control terminal CS is disconnected from the driver output terminal OUT. The cascode output terminal OT maintains an output low-level signal, and the driver output terminal OUT maintains an output low-level signal.

[0282] In the third phase H3, the input signal in is a high-level signal, and the second clock signal ck2 and the first clock signal ck1 periodically switch between high and low levels. At the beginning of the third phase H3, the second clock signal ck2 provides a low-level signal, and the first clock signal ck1 provides a high-level signal. At this time, controlled by the first clock signal ck1, the first transistor M1 and the sixth transistor M6 switch between on and off, the third node N3 remains high, the second cascode transistor T4 and the second output transistor T2 are off, the first reference signal terminal VREF1 is disconnected from the cascode output terminal OT, and the first reference signal terminal VREF1 is disconnected from the driver output terminal OUT. Controlled by the third node N3, the second transistor M2 remains off. Controlled by the first clock signal ck1, the ninth transistor M9 switches between on and off, and the fourth node N4 remains low. Controlled by the fourth node N4, the fourth transistor M4 remains on. When the second clock signal ck2 switches to a low level, the fifth transistor M5 turns on, the second clock signal terminal CK2 is connected to the first node N1, and the first node N1 becomes low. The first cascode transistor T3 and the first output transistor T1 are turned on, the fourth reference signal terminal VREF4 is connected to the cascode output terminal OT, and the output signal control terminal CS is connected to the driver output terminal OUT. The cascode output terminal OT outputs a high-level signal, and the driver output terminal OUT outputs a high-level signal. When the second clock signal ck2 switches to a high level, the fifth transistor M5 turns off, and the first node N1 remains low. The first cascode transistor T3 and the first output transistor T1 are turned on, the fourth reference signal terminal VREF4 is connected to the cascode output terminal OT, and the output signal control terminal CS is connected to the driver output terminal OUT. The cascode output terminal OT maintains its output high-level signal, and the driver output terminal OUT maintains its output high-level signal.

[0283] In the fourth phase H4, the input signal in is a low-level signal. The second clock signal ck2 provides a low-level signal, and the first clock signal ck1 provides a high-level signal. At this time, the first transistor M1 and the sixth transistor M6 are turned off, and the third node N3 remains high. The second cascode transistor T4 and the second output transistor T2 are turned off, the first reference signal terminal VREF1 is disconnected from the cascode output terminal OT, and the first reference signal terminal VREF1 is disconnected from the driver output terminal OUT. The fourth node N4 remains low. Controlled by the fourth node N4, the fourth transistor M4 remains on. The second clock signal ck2 is low, the fifth transistor M5 is turned on, the second clock signal ck2 is connected to the first node N1, and the first node N1 becomes low. The first cascode transistor T3 and the first output transistor T1 are turned on, the fourth reference signal terminal VREF4 is connected to the cascode output terminal OT, and the output signal control terminal CS is connected to the driver output terminal OUT. The cascode output terminal OT outputs a high-level signal, and the driver output terminal OUT outputs a high-level signal.

[0284] In the fifth phase H5, the second clock signal ck2 and the first clock signal ck1 periodically switch between high and low levels. In the initial stage of the fifth phase H5, the second clock signal ck2 provides a high-level signal, and the first clock signal ck1 provides a low-level signal. At this time, the first transistor M1 and the sixth transistor M6 are turned on, and the third node N3 is at a low level. Controlled by the potential of the third node N3, the twelfth transistor M12 is turned on, connecting the first node N1 to the fourth reference signal terminal VREF4, and the first node N1 remains at a high level. Controlled by the potential of the first node N1, the first cascode transistor T3 and the first output transistor T1 are turned off, the fourth reference signal terminal VREF4 is disconnected from the cascode output terminal OT, and the output signal control terminal CS is disconnected from the driver output terminal OUT. Controlled by the potential of the third node N3, the second cascode transistor T4 and the second output transistor T2 are turned on, connecting the first reference signal terminal VREF1 to the cascode output terminal OT, and connecting the first reference signal terminal VREF1 to the driver output terminal OUT. The cascode output terminal OT outputs a low-level signal, and the driver output terminal OUT outputs a low-level signal. In the subsequent stage, the third node N3 maintains a level, the cascade output terminal OT maintains outputting a low-level signal, and the driving output terminal OUT maintains outputting a low-level signal.

[0285] The high-level signal output by the cascade output terminal OT is transmitted to the input signal terminal IN of the next cascaded GOA unit, serving as the input signal in of the next cascaded GOA unit. Therefore, the next GOA unit will also proceed to stages H2-H5. The valid gate scan signal output by the drive output terminal OUT of the next GOA unit and the valid cascade signal output by the cascade output terminal OT are shifted 2H after the valid gate scan signal output by the drive output terminal OUT of the previous GOA unit and the valid cascade signal output by the cascade output terminal OT. The high-level signal output by the drive output terminal OUT is the valid gate scan signal. This process continues in this way until full-screen scanning is achieved.

[0286] As shown in Figures 21 and 22, multiple output control signal lines (for example, CS-1 and CS-2 in Figure 3) include: a first output control signal line CS-1 and a second output control signal line CS-2; every eight adjacent shift register units in a plurality of shift register units constitute a shift register unit group; the first output control signal line CS-1 is coupled to the output control signal terminal CS of the shift register unit in the odd-numbered shift register unit group, and the second output control signal line CS-2 is coupled to the output control signal terminal CS of the shift register unit in the even-numbered shift register unit group.Exemplarily, the first output control signal line CS-1 is coupled to the output control signal terminal CS in the shift register units SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8; the second output control signal line CS-2 is coupled to the output control signal terminal CS in the shift register units SR9, SR10, SR11, SR12, SR13, SR14, SR15, and SR16, in represents the input signal of the input signal terminal IN, ck1 represents the first clock signal of the first clock signal terminal CK1, ck2 represents the second clock signal of the second clock signal terminal CK2, and cs1 represents the output control signal terminal CS. The first output control signal of the signal terminal CS, out1 represents the gate scan signal of the driving output terminal OUT in the first shift register unit SR1, out2 represents the gate scan signal of the driving output terminal OUT in the second shift register unit SR2, out3 represents the gate scan signal of the driving output terminal OUT in the third shift register unit SR3, out4 represents the gate scan signal of the driving output terminal OUT in the fourth shift register unit SR4, out5 represents the gate scan signal of the driving output terminal OUT in the fifth shift register unit SR5, out6 represents the gate scan signal of the driving output terminal OUT in the sixth shift register unit SR6 The gate scan signal of the output terminal OUT, out7 represents the gate scan signal of the drive output terminal OUT in the seventh shift register unit SR7, out8 represents the gate scan signal of the drive output terminal OUT in the eighth shift register unit SR8, out9 represents the gate scan signal of the drive output terminal OUT in the ninth shift register unit SR9, out10 represents the gate scan signal of the drive output terminal OUT in the tenth shift register unit SR10, out11 represents the gate scan signal of the drive output terminal OUT in the eleventh shift register unit SR11, and out12 represents the gate scan signal of the drive output terminal OUT in the twelfth shift register unit The gate scan signal of the driving output terminal OUT in SR12, out13 represents the gate scan signal of the driving output terminal OUT in the thirteenth shift register unit SR13, out14 represents the gate scan signal of the driving output terminal OUT in the fourteenth shift register unit SR14, out15 represents the gate scan signal of the driving output terminal OUT in the fifteenth shift register unit SR15, out16 represents the gate scan signal of the driving output terminal OUT in the sixteenth shift register unit SR16, and out17 represents the gate scan signal of the driving output terminal OUT in the seventeenth shift register unit SR17. The pulse width of the input signal in is 18H, the pulse width of a high-level segment or a low-level segment of each clock signal terminal is 2H, and the pulse width of the effective gate scan signal output by the driving output terminal OUT and the effective cascade signal output by the cascade output terminal OT is 18H.

[0287] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG21 as an example and combining it with the signal timing diagram shown in FIG24 .

[0288] As shown in Figure 21, all transistors are P-type transistors, the effective pulse signal of the first reference signal output by the first reference signal terminal VREF1 is a low-level signal, the effective pulse signal of the second reference signal output by the second reference signal terminal VREF2 is a low-level signal, the effective pulse signal of the third reference signal output by the third reference signal terminal VREF3 is a high-level signal, the effective pulse signal of the fourth reference signal output by the fourth reference signal terminal VREF4 is a high-level signal, the effective pulse signal of the fifth reference signal output by the fifth reference signal terminal VREF5 is a high-level signal, the second output control signal cs-1' is a fixed voltage signal with a first level V1 as a high-level signal and a fixed voltage signal with a second level V2 as a low-level signal, and the second output control signal cs-2' is a fixed voltage signal with a first level V1 as a high-level signal and a fixed voltage signal with a second level V2 as a low-level signal.

[0289] Since the gates of the third transistor M3 and the seventh transistor M7 are both coupled to the second reference voltage signal terminal VREF2, which receives a low-level signal, and the gates of the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-eighth transistor M28 are all coupled to the first reference voltage signal terminal VREF1, which receives a low-level signal, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-eighth transistor M28 are normally on. Since the gate of the thirteenth transistor M13 is coupled to the fifth reference voltage signal terminal VREF5, which receives a high-level signal, the thirteenth transistor M13 is normally off. For ease of description, the following will not further analyze the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 at any given moment.

[0290] In the first phase H1, the input signal in is a low-level signal, and the second clock signal ck2 and the first clock signal ck1 periodically switch between high and low levels. The third node N3 is connected only to the input signal terminal IN, so the third node N3 always remains at a low level. Controlled by the potential of the third node N3, the twelfth transistor M12 is turned on, the third node N3 is connected to the fourth reference signal terminal VREF4, and the third node N3 remains at a high level. Controlled by the potential of the third node N3, the first output transistor T1 and the first cascode transistor T3 are turned off, the fourth reference signal terminal VREF4 is disconnected from the second terminal and the cascode output terminal OT, and the output control signal terminal CS is disconnected from the driver output terminal OUT. Controlled by the potential of the third node N3, the second cascode transistor T4 and the second output transistor T2 are turned on, the first reference signal terminal VREF1 is connected to the cascode output terminal OT, and the first reference signal terminal VREF1 is connected to the driver output terminal OUT. The cascode output terminal OT outputs a low-level signal, and the driver output terminal OUT outputs a low-level signal.

[0291] In the second phase H2, the input signal in is a high-level signal, the second clock signal ck2 provides a high-level signal, and the first clock signal ck1 provides a low-level signal. The first transistor M1 and the sixth transistor M6 are turned on, and the third node N3 remains in a high-level state. Controlled by the potential of the third node N3, the second transistor M2, the twelfth transistor M12, the second cascode transistor T4, and the second output transistor T2 are turned off. The second cascode transistor T4 and the second output transistor T2 are turned off, the first reference signal terminal VREF1 is disconnected from the cascode output terminal OT, and the first reference signal terminal VREF1 is disconnected from the drive output terminal OUT. Controlled by the first clock signal ck1, the ninth transistor M9 is turned on, the second reference signal terminal VREF2 is connected to the fourth node N4, and the fourth node N4 remains low. Controlled by the fourth node N4, the fourth transistor M4 is turned on. Controlled by the second clock signal ck2, the fifth transistor M5 is turned off. The first node N1 remains high, the first cascode transistor T3 and the first output transistor T1 are turned off, the fourth reference signal terminal VREF4 is disconnected from the cascode output terminal OT, and the output signal control terminal CS is disconnected from the driver output terminal OUT. The cascode output terminal OT maintains an output low-level signal, and the driver output terminal OUT maintains an output low-level signal.

[0292] In the third phase H3, the input signal in is a high-level signal, and the second clock signal ck2 and the first clock signal ck1 periodically switch between high and low levels. At the beginning of the third phase H3, the second clock signal ck2 provides a low-level signal, and the first clock signal ck1 provides a high-level signal. At this time, controlled by the first clock signal ck1, the first transistor M1 and the sixth transistor M6 switch between on and off, the third node N3 remains high, the second cascode transistor T4 and the second output transistor T2 are off, the first reference signal terminal VREF1 is disconnected from the cascode output terminal OT, and the first reference signal terminal VREF1 is disconnected from the driver output terminal OUT. Controlled by the third node N3, the second transistor M2 remains off. Controlled by the first clock signal ck1, the ninth transistor M9 switches between on and off, and the fourth node N4 remains low. Controlled by the fourth node N4, the fourth transistor M4 remains on. When the second clock signal ck2 switches to a low level, the fifth transistor M5 turns on, the second clock signal terminal CK2 is connected to the first node N1, and the first node N1 becomes low. The first cascode transistor T3 and the first output transistor T1 are turned on, the fourth reference signal terminal VREF4 is connected to the cascode output terminal OT, and the output signal control terminal CS is connected to the driver output terminal OUT. The cascode output terminal OT outputs a high-level signal, and the driver output terminal OUT outputs a high-level signal. When the second clock signal ck2 switches to a high level, the fifth transistor M5 turns off, and the first node N1 remains low. The first cascode transistor T3 and the first output transistor T1 are turned on, the fourth reference signal terminal VREF4 is connected to the cascode output terminal OT, and the output signal control terminal CS is connected to the driver output terminal OUT. The cascode output terminal OT maintains its output high-level signal, and the driver output terminal OUT maintains its output high-level signal.

[0293] In the fourth phase H4, the input signal in is a low-level signal. The second clock signal ck2 provides a low-level signal, and the first clock signal ck1 provides a high-level signal. At this time, the first transistor M1 and the sixth transistor M6 are turned off, and the third node N3 remains high. The second cascode transistor T4 and the second output transistor T2 are turned off, the first reference signal terminal VREF1 is disconnected from the cascode output terminal OT, and the first reference signal terminal VREF1 is disconnected from the driver output terminal OUT. The fourth node N4 remains low. Controlled by the fourth node N4, the fourth transistor M4 remains on. The second clock signal ck2 is low, the fifth transistor M5 is turned on, the second clock signal ck2 is connected to the first node N1, and the first node N1 becomes low. The first cascode transistor T3 and the first output transistor T1 are turned on, the fourth reference signal terminal VREF4 is connected to the cascode output terminal OT, and the output signal control terminal CS is connected to the driver output terminal OUT. The cascode output terminal OT outputs a high-level signal, and the driver output terminal OUT outputs a high-level signal.

[0294] In the fifth phase H5, the second clock signal ck2 and the first clock signal ck1 periodically switch between high and low levels. In the initial stage of the fifth phase H5, the second clock signal ck2 provides a high-level signal, and the first clock signal ck1 provides a low-level signal. At this time, the first transistor M1 and the sixth transistor M6 are turned on, and the third node N3 is at a low level. Controlled by the potential of the third node N3, the twelfth transistor M12 is turned on, connecting the first node N1 to the fourth reference signal terminal VREF4, and the first node N1 remains at a high level. Controlled by the potential of the first node N1, the first cascode transistor T3 and the first output transistor T1 are turned off, the fourth reference signal terminal VREF4 is disconnected from the cascode output terminal OT, and the output signal control terminal CS is disconnected from the driver output terminal OUT. Controlled by the potential of the third node N3, the second cascode transistor T4 and the second output transistor T2 are turned on, connecting the first reference signal terminal VREF1 to the cascode output terminal OT, and connecting the first reference signal terminal VREF1 to the driver output terminal OUT. The cascode output terminal OT outputs a low-level signal, and the driver output terminal OUT outputs a low-level signal. In the subsequent stage, the third node N3 maintains a level, the cascade output terminal OT maintains outputting a low-level signal, and the driving output terminal OUT maintains outputting a low-level signal.

[0295] The high-level signal output from the cascade output terminal OT will be transmitted to the input signal terminal IN of the next GOA unit cascaded with it, as the input signal in of the next GOA unit cascaded with it. Therefore, the next GOA unit will also proceed to stages H2-H5. The valid gate scan signal output from the driving output terminal OUT of the next GOA unit and the valid cascade signal output from the cascade output terminal OT are shifted 2H later than the valid gate scan signal output from the driving output terminal OUT of the previous GOA unit and the valid cascade signal output from the cascade output terminal OT. The high-level signal output from the driving output terminal OUT is a valid gate scan signal. When the first group of shift register unit groups outputs a valid gate scan signal, and the eighth shift register unit SR8 outputs a complete 18H valid gate scan signal, the first output control signal cs-1' changes from a high level V1 to a low level V2, and the subsequent odd-numbered shift register unit groups all output invalid gate scan signals. After the second group of shift register units outputs a valid gate scan signal, and the sixteenth shift register unit SR16 outputs a complete 18H valid gate scan signal, the second output control signal cs-2' changes from a high level V1 to a low level V2, and the shift register unit groups of the even group thereafter all output invalid gate scan signals. At this point, each shift register unit outputs a complete 18H gate scan signal, or outputs a complete 18H invalid scan signal. There will be no situation where a valid gate scan signal is outputted that is less than 18H, thereby ensuring the display quality of the display panel. At the same time, the odd group can adjust the output of the gate scan signal of any odd group with the help of the second output control signal cs-1', and the even group can adjust the output of the gate scan signal of any even group with the help of the second output control signal cs-2'. The two groups work together to achieve adjustment of any area of ​​the display panel, thereby achieving partitioned refresh of the display panel.

[0296] For example, in a display panel with 1024 rows of pixels, there are 512 shift register units, each controlling two rows of pixels. Eight adjacent shift register units form a group, for a total of 64 groups. The output control signal terminals CS of the odd-numbered shift register units are coupled to the first output control signal line CS-1, while the output control signal terminals CS of the even-numbered shift register units are coupled to the second output control signal line CS-2. When the first output control signal line CS-1 and the second output control signal line CS-2 are controlled to output the second output control signal, the shift register units of the first to thirty-second groups output valid gate scan signals every frame within 120 frames, and the shift register units of the thirty-third to sixty-fourth groups output valid gate scan signals every other frame within 120 frames. This allows the display panel's first 512 rows of pixels to be controlled at 120 Hz, while the last 512 rows of pixels to be controlled at 60 Hz, thereby achieving partitioned refresh. Of course, the first output control signal line CS-1 and the second output control signal line CS-2 can also be controlled to output the second output control signal, so that any group outputs a valid gate scan signal or an invalid gate scan signal in any frame to achieve partition refresh of the display panel.

[0297] In the embodiment of the present disclosure, the signal at the output control signal terminal is controlled to control the gate scanning signal at the driving output terminal in the output circuit, thereby controlling any area of ​​the display panel to be scanned, and controlling any area of ​​the display panel not to be scanned, thereby saving power consumption and reducing losses.

[0298] Other embodiments of the present invention will readily occur to those skilled in the art upon consideration of the present invention and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the following claims.

[0299] It should be understood that the present description is not limited to the exact structure that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

[0300] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A display panel, comprising: A shift register unit and a plurality of output control signal lines coupled to the shift register unit; The plurality of output control signal lines are arranged between the shift register unit coupled thereto and the display area of ​​the display panel; The shift register unit comprises: The shift register is configured to output a cascade signal through a cascade output terminal; An output circuit is coupled to the shift register, and the output circuit is configured to control the drive output terminal to output a gate scan signal according to a signal at an output control signal terminal and a signal at a first reference signal terminal, and the output control signal terminal is coupled to one of the multiple output control signal lines.

2. The display panel according to claim 1, wherein: The output circuit comprises: a first output circuit and a second output circuit; The first output circuit is coupled to the cascade output terminal or the first node in the shift register and is configured to transmit the signal from the output control signal terminal to the driving output terminal in response to the signal of the cascade output terminal or the first node; The second output circuit is coupled to a second node in the shift register, and is configured to transmit a signal from the first reference signal terminal to the driving output terminal in response to a signal at the second node.

3. The display panel according to claim 2, wherein: The first output circuit includes: a first output transistor; A gate of the first output transistor is coupled to the cascade output terminal or the first node, a first electrode of the first output transistor is coupled to the output control signal terminal, and a second electrode of the first output transistor is coupled to the driving output terminal.

4. The display panel according to claim 2, wherein: The second output circuit includes: a second output transistor; A gate of the second output transistor is coupled to the second node, a first electrode of the second output transistor is coupled to the first reference signal terminal, and a second electrode of the second output transistor is coupled to the driving output terminal.

5. The display panel according to any one of claims 1 to 4, wherein: The shift register comprises: an input subcircuit configured to provide a signal at an input signal terminal to a third node in response to a signal at the first clock signal terminal; a control subcircuit configured to control signals of the first node and the second node, and provide the signal of the third node to the first node or the second node; The cascade sub-circuit is configured to enable the cascade output terminal to output the cascade signal in response to the signals of the first node and the second node.

6. The display panel according to claim 5, wherein: The input subcircuit comprises: a first transistor; A gate of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the third node.

7. The display panel according to claim 5, wherein: The control subcircuit includes: a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; The gate of the second transistor is coupled to the third node, the first electrode of the second transistor is coupled to the first clock signal terminal, and the second electrode of the second transistor is coupled to the fourth node; The gate of the third transistor is coupled to the second reference signal terminal, the first electrode of the third transistor is coupled to the fourth node, and the second electrode of the third transistor is coupled to the gate of the fourth transistor; A first electrode of the fourth transistor is coupled to the second clock signal terminal, and a second electrode of the fourth transistor is coupled to a first electrode of the fifth transistor; The gate of the fifth transistor is coupled to the second clock signal terminal, and the second electrode of the fifth transistor is coupled to the first node; The gate of the sixth transistor is coupled to the first clock signal terminal, the first electrode of the sixth transistor is coupled to the input signal terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor; The gate of the seventh transistor is coupled to the second reference signal terminal, and the second electrode of the seventh transistor is coupled to the fifth node; The gate of the eighth transistor is coupled to the fifth node, the first electrode of the eighth transistor is coupled to the fifth node, and the second electrode of the eighth transistor is coupled to the second node; The gate of the ninth transistor is coupled to the first clock signal terminal, the first electrode of the ninth transistor is coupled to the second reference signal terminal, and the second electrode of the ninth transistor is coupled to the gate of the tenth transistor; A first electrode of the tenth transistor is coupled to the third reference signal terminal, and a second electrode of the tenth transistor is coupled to the sixth node; The gate of the eleventh transistor is coupled to the fifth node, the first electrode of the eleventh transistor is coupled to the sixth node, and the second electrode of the eleventh transistor is coupled to the second clock signal terminal; The gate of the twelfth transistor is coupled to the first electrode of the fifteenth transistor, the first electrode of the twelfth transistor is coupled to the first node, and the second electrode of the twelfth transistor is coupled to the fourth reference signal terminal; The gate of the thirteenth transistor is coupled to the fifth reference signal terminal, the first electrode of the thirteenth transistor is coupled to the fourth reference signal terminal, and the second electrode of the thirteenth transistor is coupled to the first electrode of the fourteenth transistor; The gate of the fourteenth transistor is coupled to the first reference signal terminal, and the second electrode of the fourteenth transistor is coupled to the first electrode of the fifteenth transistor; The gate of the fifteenth transistor is coupled to the first reference signal terminal, the first electrode of the fifteenth transistor is coupled to the third node, and the second electrode of the fifteenth transistor is coupled to the second node; A first electrode of the first capacitor is coupled to a gate of the fourth transistor, and a second electrode of the first capacitor is coupled to a second electrode of the fourth transistor; A first electrode of the second capacitor is coupled to the sixth node, and a second electrode of the second capacitor is coupled to the second electrode of the seventh transistor; A first electrode of the third capacitor is coupled to the fourth reference signal terminal, and a second electrode of the third capacitor is coupled to the first node; A first electrode of the fourth capacitor is coupled to the cascade output terminal, and a second electrode of the fourth capacitor is coupled to the first reference signal terminal.

8. The display panel according to claim 5, wherein: The cascade subcircuit comprises: a first cascade transistor and a second cascade transistor; The gate of the first cascode transistor is coupled to the first node, the first electrode of the first cascode transistor is coupled to the fourth reference signal terminal, and the second electrode of the first cascode transistor is coupled to the cascode output terminal; A gate of the second cascode transistor is coupled to the second node, a first electrode of the second cascode transistor is coupled to the cascode output terminal, and a second electrode of the second cascode transistor is coupled to the first reference signal terminal.

9. The display panel according to claim 5, wherein: The input sub-circuit comprises: a sixteenth transistor and a seventeenth transistor; The gate of the sixteenth transistor is coupled to the first clock signal terminal, the first electrode of the sixteenth transistor is coupled to the input signal terminal, and the second electrode of the sixteenth transistor is coupled to the seventh node; A gate of the seventeenth transistor is coupled to the first clock signal terminal, a first electrode of the seventeenth transistor is coupled to the seventh node, and a second electrode of the seventeenth transistor is coupled to the third node.

10. The display panel according to claim 5, wherein: The control subcircuit includes: an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a fifth capacitor and a sixth capacitor; The gate of the eighteenth transistor is coupled to the cascade output terminal, and the first electrode of the eighteenth transistor is coupled to The third clock signal terminal is coupled, and the second electrode of the eighteenth transistor is coupled to the seventh node; The gate of the nineteenth transistor is coupled to the input signal terminal, the first electrode of the nineteenth transistor is coupled to the first reference signal terminal, and the second electrode of the nineteenth transistor is coupled to the second node; A gate of the 20th transistor is coupled to the second node, a first electrode of the 20th transistor is coupled to the first reference signal terminal, and a second electrode of the 20th transistor is coupled to the eighth node; A gate of the twenty-first transistor is coupled to the second node, a first electrode of the twenty-first transistor is coupled to the eighth node, and a second electrode of the twenty-first transistor is coupled to the third node; A gate of the 22nd transistor is coupled to the third node, a first electrode of the 22nd transistor is coupled to the eighth node, and a second electrode of the 22nd transistor is coupled to the sixth reference signal terminal; A gate of the twenty-third transistor is coupled to the fourth clock signal terminal, a first electrode of the twenty-third transistor is coupled to the second node, and a second electrode of the twenty-third transistor is coupled to the sixth reference signal terminal; A first electrode of the fifth capacitor is coupled to the first reference signal terminal, and a second electrode of the fifth capacitor is coupled to a first electrode of the twenty-third transistor; A first electrode of the sixth capacitor is coupled to the cascade output terminal, and a second electrode of the sixth capacitor is coupled to the first node.

11. The display panel according to claim 5, wherein: The cascade subcircuit comprises: a first cascade transistor and a second cascade transistor; The gate of the first cascode transistor is coupled to the first node, the first electrode of the first cascode transistor is coupled to the cascode output terminal, and the second electrode of the first cascode transistor is coupled to the third clock signal terminal; A gate of the second cascade transistor is coupled to the second node, a first electrode of the second cascade transistor is coupled to the first reference signal terminal, and a second electrode of the second cascade transistor is coupled to the cascade output terminal.

12. The display panel according to claim 5, wherein: The control subcircuit includes: a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a seventh capacitor and an eighth capacitor; A gate of the 24th transistor is coupled to the first clock signal terminal, a first electrode of the 24th transistor is coupled to the seventh reference signal terminal, and a second electrode of the 24th transistor is coupled to the second node; A gate of the 25th transistor is coupled to the third node, a first electrode of the 25th transistor is coupled to the second node, and a second electrode of the 25th transistor is coupled to the first clock signal terminal; A gate of the 26th transistor is coupled to the second node, a first electrode of the 26th transistor is coupled to the first reference signal terminal, and a second electrode of the 26th transistor is coupled to a first electrode of the 27th transistor; A gate of the twenty-seventh transistor is coupled to the third clock signal terminal, and a second electrode of the twenty-seventh transistor is coupled to a first electrode of the twenty-eighth transistor; A gate of the 28th transistor is coupled to the seventh reference signal terminal, a first electrode of the 28th transistor is coupled to the third node, and a second electrode of the 28th transistor is coupled to the first node; A first electrode of the seventh capacitor is coupled to the first reference signal terminal, and a second electrode of the seventh capacitor is coupled to the first node; A first electrode of the eighth capacitor is coupled to the cascade output terminal, and a second electrode of the eighth capacitor is coupled to the first node.

13. The display panel according to claim 7, wherein: The control subcircuit further includes: a twenty-eighth transistor; A first electrode of the 28th transistor is coupled to a second electrode of the fifth transistor, a second electrode of the 28th transistor is coupled to the first node, and a gate of the 28th transistor is coupled to the first reference signal terminal.

14. A display panel, comprising: A substrate, comprising a display area and a non-display area; The display area includes: Multiple sub-pixels; A plurality of scan lines, wherein a row of the sub-pixels in the plurality of sub-pixels is correspondingly coupled to at least one of the scan lines in the plurality of scan lines; The non-display area includes: A gate driving circuit comprises a plurality of shift register units in a display panel as described in any one of claims 1 to 13, wherein a driving output end of each of the plurality of shift register units is correspondingly coupled to at least one of the plurality of scan lines.

15. The display panel according to claim 14, wherein: It also includes: a plurality of output control signal lines coupled to the gate driving circuit; the extension direction of the plurality of output control signal lines is the same as the arrangement direction of the plurality of shift register units.

16. The display panel according to claim 15, wherein: The plurality of output control signal lines are arranged between the gate driving circuit coupled thereto and the display area.

17. The display panel according to claim 16, wherein: In two adjacent shift register units among the plurality of shift register units, an input signal terminal of a next shift register unit is coupled to a cascade output terminal of a previous shift register unit; The multiple output control signal lines include: a first output control signal line and a second output control signal line; the first output control signal line is coupled to the output control signal end of the odd-numbered shift register unit, and the second output control signal line is coupled to the output control signal end of the even-numbered shift register unit.

18. The display panel according to claim 16, wherein: In two adjacent shift register units among the plurality of shift register units, an input signal terminal of a next shift register unit is coupled to a cascade output terminal of a previous shift register unit; The multiple output control signal lines include: a first output control signal line and a second output control signal line; every eight adjacent shift register units in the plurality of shift register units constitute a shift register unit group; the first output control signal line is coupled to the output control signal end of the shift register unit in the odd-numbered shift register unit group, and the second output control signal line is coupled to the output control signal end of the shift register unit in the even-numbered shift register unit group.

19. The display panel according to claim 15, wherein: Also includes: A plurality of output control auxiliary signal lines; a first insulating layer is provided between the plurality of output control auxiliary signal lines and the plurality of output control signal lines; The plurality of output control auxiliary signal lines correspond to the plurality of output control signal lines one by one, and the output control auxiliary signal lines and the output control signal lines corresponding to each other are coupled to each other through first via holes penetrating the first insulating layer.

20. The display panel according to any one of claims 14 to 19, wherein: Also includes: a plurality of clock signal lines coupled to the gate drive circuit; An extending direction of the plurality of clock signal lines is the same as an arrangement direction of the plurality of shift register units.

21. The display panel according to claim 20, wherein: The plurality of clock signal lines are arranged on a side of the gate driving circuit coupled thereto away from the display area.

22. The display panel according to claim 20, wherein: The orthographic projections of the plurality of output control signal lines on the base substrate are arranged between the orthographic projections of the plurality of clock signal lines on the base substrate and the display area.

23. The display panel according to claim 20, wherein: The orthographic projection of the gate driving circuit on the base substrate is arranged between the orthographic projection of the multiple clock signal lines on the base substrate and the orthographic projection of the multiple output control signal lines on the base substrate, and the orthographic projection of the multiple output control signal lines on the base substrate is arranged between the orthographic projection of the gate driving circuit on the base substrate and the display area.

24. The display panel according to any one of claims 14 to 19, wherein: The orthographic projection of the first output transistor on the base substrate is located between the orthographic projection of the first cascode transistor on the base substrate and the display area.

25. The display panel according to any one of claims 14 to 19, wherein: A width of a channel of the first output transistor is greater than a width of a channel of the first cascode transistor.

26. The display panel according to claim 25, wherein: The width of the channel of the first output transistor is not less than 100 um.

27. The display panel according to claim 25, wherein: The width of the channel of the first cascode transistor is no greater than 60 um.

28. The display panel according to any one of claims 14 to 19, wherein: The orthographic projection of the second output transistor on the base substrate is located between the orthographic projection of the second cascode transistor on the base substrate and the display area.

29. The display panel according to any one of claims 14 to 19, wherein: A width of a channel of the second output transistor is greater than a width of a channel of the second cascode transistor.

30. The display panel according to claim 29, wherein: The width of the channel of the second output transistor is not less than 100 um.

31. The display panel according to claim 29, wherein: The width of the channel of the second cascode transistor is no more than 60 um.

32. A display device comprising: The display panel according to any one of claims 14 to 31; A driving control circuit coupled to the display panel and configured to input a first output control signal to the output control signal terminals of the plurality of shift register units when it is determined to adopt the full-screen driving mode, so that the plurality of shift register units sequentially output gate scanning signals and drive the scanning lines row by row; When it is determined to adopt the local driving mode, a second output control signal is input to the output control signal terminal of the plurality of shift register units, so that some of the plurality of shift register units output gate scanning signals in sequence, and the remaining shift register units output invalid scanning signals.

33. A drive control method, comprising: When it is determined to adopt the full-screen driving mode, inputting a first output control signal to the output control signal terminals of the plurality of shift register units, so that the plurality of shift register units sequentially output gate scanning signals and drive the scanning lines row by row; When it is determined to adopt the local driving mode, a second output control signal is input to the output control signal end of the multiple shift register units, so that some of the multiple shift register units output gate scanning signals in sequence, and the remaining shift register units output invalid scanning signals to drive some of the scanning lines.

34. The driving control method according to claim 33, wherein: The first output control signal is a fixed voltage signal with a first level.

35. The drive control method according to any one of claims 33 or 34, wherein: The second output control signal includes a fixed voltage signal portion having a first level and a fixed voltage signal portion having a second level, the fixed voltage signal portion having the first level is input into some of the shift register units, and the fixed voltage signal portion having the second level is input into the remaining shift register units.

36. The driving control method according to claim 33, wherein: The first output control signal is a clock signal.

37. The drive control method according to claim 33 or 36, wherein: The second output control signal includes a clock signal portion and a fixed voltage signal portion having a first level; The clock signal portion of the second output control signal is input to the part of the shift register units, and the fixed voltage signal portion having the first level is input to the remaining shift register units.

38. The driving control method according to claim 33, wherein: The pulse width of the input signal at the input signal end of the shift register unit is 18H, the pulse width of the cascade signal output from the cascade signal end of the shift register unit is 18H, the pulse width of the gate scan signal output from the driving output end of the shift register unit is 18H, and the cascade signal and the effective gate scan signal output by the shift register unit of the next level among the multiple shift register units are shifted 2H backward than the cascade signal and the effective gate scan signal output by the shift register unit of the previous level.

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