Pixel circuit, array substrate and display panel

Abstract

The invention discloses a pixel circuit, an array substrate and a display panel. The pixel circuit comprises a pixel driving circuit and a binding unit connected with the pixel driving circuit. The binding unit comprises a first binding terminal group and at least one second binding terminal group which are arranged in parallel, and the first binding terminal group and the second binding terminal group are configured to bind a light-emitting device; wherein the first binding terminal group comprises a first terminal and a second terminal, the second binding terminal group comprises a third terminal and a fourth terminal, the first terminal and the third terminal are connected and are both connected with the pixel driving circuit, and the second terminal and the fourth terminal are connected and are both connected with a set voltage signal line.

Description

Pixel circuit, array substrate and display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, an array substrate, and a display panel. Background Art

[0002] Mini LED (Mini Light-Emitting Diode) display devices and Micro LED (Micro Light-Emitting Diode) display devices are display devices composed of a large number of small-sized LED arrays. They have the advantages of high brightness, clear display images and low power consumption, and have good application prospects.

[0003] Since the mass transfer process of Mini LED chips in Mini LED display devices and Micro LED chips in Micro LED display devices is relatively difficult and requires multiple transfers, and the amount of chips transferred each time is very large, the stability and accuracy of the transfer process are very high. Therefore, mass transfer technology has become one of the current research hotspots.

[0004] Summary of the Invention

[0005] In one aspect, a pixel circuit is provided. The pixel circuit includes a pixel driving circuit and a binding unit connected to the pixel driving circuit, the binding unit including a first binding terminal group and at least one second binding terminal group arranged in parallel, the first binding terminal group and the second binding terminal group being configured to bind a light-emitting device; wherein the first binding terminal group includes a first terminal and a second terminal, and the second binding terminal group includes a third terminal and a fourth terminal, the first terminal and the third terminal being connected and both connected to the pixel driving circuit, and the second terminal and the fourth terminal being connected and both connected to a set voltage signal line.

[0006] In some embodiments, the pixel driving circuit is electrically connected to the first voltage signal line, and the set voltage signal line is the second voltage signal line, or the pixel driving circuit is electrically connected to the second voltage signal line, and the set voltage signal line is the first voltage signal line; wherein, the first voltage signal line is configured to transmit a first voltage signal, and the second voltage signal line is configured to transmit a second voltage signal, and the voltage of the first voltage signal is greater than the voltage of the second voltage signal.

[0007] In some embodiments, the pixel circuit also includes an electrostatic protection circuit; the first terminal and the third terminal are connected to a first connection node, and the electrostatic protection circuit is electrically connected to the first connection node; the electrostatic protection circuit includes a first electrostatic protection circuit, and the first electrostatic protection circuit includes a first sub-circuit and a second sub-circuit, the first end of the first sub-circuit and the second end of the second sub-circuit are electrically connected to the first connection point, the second end of the first sub-circuit is also electrically connected to the third voltage signal line, and the first end of the second sub-circuit is also electrically connected to the fourth voltage signal line; the third voltage signal line is configured to transmit a third voltage signal, and the fourth voltage signal line is configured to transmit a fourth voltage signal, and the voltage of the third voltage signal is greater than the voltage of the fourth voltage signal; the first sub-circuit is configured to turn on when an abnormally high voltage appears at the first connection node, so that the first connection point discharges to the third voltage signal line; the second sub-circuit is configured to turn on when an abnormally low voltage appears at the first connection node, so that the fourth voltage signal line charges to the first connection point.

[0008] In some embodiments, the first sub-circuit includes at least one first transistor; the first sub-circuit includes a first transistor, the gate of the first transistor is electrically connected to the second electrode, the first electrode of the first transistor is electrically connected to the first connection point, and the second electrode of the first transistor is electrically connected to the third voltage signal line; or, the first sub-circuit includes at least two first transistors, and the at least two first transistors are connected in series; the gate of each first transistor is electrically connected to the second electrode, the first electrode of the first first transistor of the at least two first transistors is electrically connected to the first connection point, and the second electrode of the last first transistor is electrically connected to the third voltage signal line.

[0009] In some embodiments, the second sub-circuit includes at least one second transistor; the second sub-circuit includes a second transistor, the gate of the second transistor is electrically connected to the second electrode, the first electrode of the second transistor is electrically connected to the fourth voltage signal line, and the second electrode of the second transistor is electrically connected to the first connection point; or, the second sub-circuit includes at least two second transistors, and the at least two second transistors are connected in series; the gate of each second transistor is electrically connected to the second electrode, the first electrode of the first second transistor of the at least two second transistors is electrically connected to the fourth voltage signal line, and the second electrode of the last second transistor is electrically connected to the first connection point.

[0010] In some embodiments, the second terminal and the fourth terminal are connected to a second connection node, and the electrostatic protection circuit is also electrically connected to the second connection node; the electrostatic protection circuit also includes a second electrostatic protection circuit, and the second electrostatic protection circuit includes a third sub-circuit and a fourth sub-circuit, the first end of the third sub-circuit and the second end of the fourth sub-circuit are electrically connected to the second connection point, the second end of the third sub-circuit is also electrically connected to the third voltage signal line, and the first end of the fourth sub-circuit is also electrically connected to the fourth voltage signal line; the third sub-circuit is configured to turn on when an abnormally high voltage appears at the second connection node, so that the second connection point discharges to the third voltage signal line; the fourth sub-circuit is configured to turn on when an abnormally low voltage appears at the second connection node, so that the fourth voltage signal line charges to the second connection point.

[0011] In some embodiments, the third sub-circuit includes at least one third transistor, the third sub-circuit includes a third transistor, the gate of the third transistor is electrically connected to the second electrode, the first electrode of the third transistor is electrically connected to the second connection point, and the second electrode of the third transistor is electrically connected to the third voltage signal line; or, the third sub-circuit includes at least two third transistors, the at least two third transistors are connected in series; the gate of each third transistor is electrically connected to the second electrode, the first electrode of the first third transistor of the at least two third transistors is electrically connected to the second connection point, and the second electrode of the last third transistor is electrically connected to the third voltage signal line.

[0012] In some embodiments, the fourth sub-circuit includes at least one fourth transistor; the fourth sub-circuit includes a fourth transistor, the gate of the fourth transistor is electrically connected to the second electrode, the first electrode of the fourth transistor is electrically connected to the fourth voltage signal line, and the second electrode of the fourth transistor is electrically connected to the second connection point; or, the fourth sub-circuit includes at least two fourth transistors, and the at least two fourth transistors are connected in series; the gate of each fourth transistor is electrically connected to the second electrode, the first electrode of the first fourth transistor of the at least two fourth transistors is electrically connected to the fourth voltage signal line, and the second electrode of the last fourth transistor is electrically connected to the second connection point.

[0013] On the other hand, an array substrate is provided. The array substrate includes a plurality of pixel circuits as described in any of the above embodiments; the array substrate includes a stacked substrate, a semiconductor layer, a first gate layer, a second gate layer, a first source / drain metal layer, a second source / drain metal layer, and a binding layer; the setting voltage signal line is located in the first source / drain metal layer or the second source / drain metal layer; the pixel driving circuit is located in the semiconductor layer, the first gate layer, the second gate layer, and the first source / drain metal layer; the binding unit is located in the binding layer; in a region where at least one pixel circuit is located, the binding layer includes a first binding pattern group and at least one second binding pattern group, the first binding pattern group includes a first binding pattern and a second binding pattern, and the second binding pattern group includes a third binding pattern and a fourth binding pattern; the first binding pattern group serves as the first binding terminal group, and the second binding pattern group serves as the second binding terminal group; the first binding pattern and the third binding pattern are both electrically connected to the pixel driving circuit, and the second binding pattern and the fourth binding pattern are both electrically connected to the setting voltage signal line.

[0014] In some embodiments, the second source-drain metal layer includes a first source-drain pattern group and at least one second source-drain pattern group, the first source-drain pattern group includes a first source-drain pattern and a second source-drain pattern, the second source-drain pattern group includes a third source-drain pattern and a fourth source-drain pattern; the first source-drain pattern is electrically connected to the first binding pattern; the second source-drain pattern is electrically connected to the second binding pattern; the third source-drain pattern is electrically connected to the third binding pattern; the fourth source-drain pattern is electrically connected to the fourth binding pattern; the first source-drain pattern and the third source-drain pattern are both electrically connected to the pixel driving circuit; the third source-drain pattern and the fourth source-drain pattern are both electrically connected to the setting voltage signal line.

[0015] In some embodiments, the first source-drain metal layer includes a first connection line, the first connection line is connected to the pixel driving circuit, and the first connection line is connected to the first source-drain pattern and the third source-drain pattern.

[0016] In some embodiments, the first terminal and the third terminal are connected to a first connection node; the first connection line includes a connection portion located in the middle thereof, the connection portion serves as the first connection node, and the first source and drain pattern group and the second source and drain pattern group have no overlap with the connection portion.

[0017] In some embodiments, the pixel driving circuit includes a driving transistor, the semiconductor layer includes an active layer of the driving transistor, and the first source and drain pattern group and the second source and drain pattern group do not overlap with the active layer of the driving transistor.

[0018] In some embodiments, the pixel circuit also includes an electrostatic protection circuit; the electrostatic protection circuit includes a first transistor and a second transistor; the semiconductor layer includes an active layer of the first transistor and an active layer of the second transistor; the first end of the active layer of the first transistor and the second end of the active layer of the second transistor are close to and connected to each other; the first source and drain metal layer includes a first connection pattern, a second connection pattern and a third connection pattern, and a second connection line; the second end of the active layer of the first transistor is connected to the first connection pattern, and the first connection pattern is connected to the third voltage signal line; the third voltage signal line overlaps with the active layer of the first transistor; the first end of the active layer of the first transistor is connected to the second connection pattern, and the second connection pattern is connected to the gate pattern of the second transistor, and the gate pattern of the second transistor overlaps with the active layer of the second transistor; the first end of the active layer of the second transistor is connected to the third connection pattern, and the third connection pattern is connected to the fourth voltage signal line; the two ends of the second connection line are respectively connected to the first connection line and the second connection pattern.

[0019] In some embodiments, the multiple pixel circuits are arranged in an array; the first gate layer includes multiple third voltage signal lines and multiple fourth voltage signal lines extending along the row direction; each third voltage signal line and fourth voltage signal line is located in the area where a row of pixel circuits is located.

[0020] In another aspect, a display panel is provided, comprising: an array substrate according to any of the above embodiments; and a plurality of light-emitting devices, each of the plurality of light-emitting devices being electrically connected to a first binding terminal group or a second binding terminal group in the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0022] FIG1 is a structural diagram of a display device according to some embodiments;

[0023] FIG2A is a structural diagram of a pixel circuit according to some embodiments;

[0024] FIG2B is a diagram illustrating a binding structure of a light emitting device according to some embodiments;

[0025] FIG3A is a structural diagram of a pixel circuit according to some embodiments;

[0026] FIG3B is a structural diagram of a pixel circuit according to some embodiments;

[0027] FIG3C is a structural diagram of a pixel circuit according to some embodiments;

[0028] FIG4 is a structural diagram of a pixel circuit according to some embodiments;

[0029] FIG5A is a connection structure diagram of a first sub-circuit according to some embodiments;

[0030] FIG5B is another connection structure diagram of the first sub-circuit according to some embodiments;

[0031] FIG5C is another connection structure diagram of the first sub-circuit according to some embodiments;

[0032] FIG6A is a connection structure diagram of a second sub-circuit according to some embodiments;

[0033] FIG6B is another connection structure diagram of the second sub-circuit according to some embodiments;

[0034] FIG6C is another connection structure diagram of the second sub-circuit according to some embodiments;

[0035] FIG7 is a structural diagram of a pixel circuit according to some embodiments;

[0036] FIG8A is a connection structure diagram of a third sub-circuit according to some embodiments;

[0037] FIG8B is another connection structure diagram of the third sub-circuit according to some embodiments;

[0038] FIG8C is another connection structure diagram of the third sub-circuit according to some embodiments;

[0039] FIG9A is a connection structure diagram of a first sub-circuit according to some embodiments;

[0040] FIG9B is another connection structure diagram of the first sub-circuit according to some embodiments;

[0041] FIG9C is another connection structure diagram of the first sub-circuit according to some embodiments;

[0042] FIG10 is a structural diagram of an array substrate according to some embodiments;

[0043] FIG11A is another structural diagram of an array substrate according to some embodiments;

[0044] FIG11B is another structural diagram of an array substrate according to some embodiments;

[0045] FIG11C is another structural diagram of an array substrate according to some embodiments;

[0046] FIG11D is another structural diagram of an array substrate according to some embodiments;

[0047] FIG11E is another structural diagram of an array substrate according to some embodiments;

[0048] FIG11F is another structural diagram of an array substrate according to some embodiments;

[0049] FIG12A is a cross-sectional view of an array substrate according to some embodiments;

[0050] FIG12B is a cross-sectional view of an array substrate according to some embodiments;

[0051] FIG. 13 is a cross-sectional structural diagram of a display panel according to some embodiments. DETAILED DESCRIPTION

[0052] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0053] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0054] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0055] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0056] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0057] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0058] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0059] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0060] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0061] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0062] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0063] Currently, Mini LED (Mini Light-Emitting Diode) and Micro LED (Micro Light-Emitting Diode) display devices typically use a stamping method to transfer light-emitting devices in large quantities. However, this transfer method may result in poor transfer, which seriously affects the quality of display products and reduces the reliability of display panels.

[0064] Based on this, some embodiments of the present disclosure provide a pixel circuit, an array substrate, a display panel and a display device. The pixel circuit can solve the above-mentioned problem of poor transfer by adjusting the internal structure, thereby improving product yield and quality.

[0065] The pixel circuit, array substrate, display panel and display device provided by the present disclosure are introduced below respectively.

[0066] Some embodiments of the present disclosure provide a display device. For example, the display device may be a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, an in-vehicle computer, a wearable display device, etc. The embodiments of the present disclosure do not specifically limit the specific form of the display device. Specifically, as shown in FIG1 , display device 2000 is a mobile phone, and display device 2000 includes a display panel 1000.

[0067] In some embodiments, as shown in FIG2A , the display panel 1000 includes a display area AA (Active Area, also referred to as the effective display area) and a peripheral area BB located on at least one side of the display area AA. The display area AA includes a plurality of sub-pixels P arranged in an array and a plurality of signal lines. A sub-pixel P is the smallest unit used by the display panel 1000 for displaying images. Each sub-pixel P can display a single color, such as red (R), green (G), or blue (B). By adjusting the brightness (grayscale) of sub-pixels P of different colors, multiple colors can be displayed through color combination and superposition, thereby achieving full-color display on the display panel 1000.

[0068] In some embodiments, the sub-pixel P includes an electrically connected pixel circuit 10 and a light-emitting device 20, and the pixel circuit is used to drive the light-emitting device 20 to emit light, wherein the light-emitting device 20 can be a micro organic light-emitting diode (Micro Organic Light-Emitting Diode, Micro OLED), a quantum dot organic light-emitting diode (Quantum Dot Light Emitting Diodes, QLED), a mini light-emitting diode (Mini Light-Emitting Diode, Mini LED) or a micro light-emitting diode (Micro Light-Emitting Diode, Micro LED), etc.

[0069] The display panel 1000 includes an array substrate 100, and a plurality of pixel circuits 10 are provided in the array substrate 100. In some embodiments, light-emitting devices are transferred to the array substrate in bulk using a stamp method and connected to the binding terminals in the pixel circuit to achieve electrical connection between the light-emitting devices and the pixel circuit. As shown in FIG2B , the light-emitting devices are picked up using the bumps on the stamp, and the light-emitting devices are transferred to corresponding positions on the array substrate. After the positive and negative electrodes of the light-emitting devices are bound to the corresponding binding terminals, the stamp is separated. During this process, some light-emitting devices may be poorly transferred. For example, some light-emitting devices may be missing, or some light-emitting devices may have poor structures, or some light-emitting devices may have position deviations, resulting in their positive and negative electrodes not being connected to the corresponding binding terminals or short-circuiting. In this case, the light-emitting devices at the corresponding positions cannot be properly illuminated, affecting the image display.

[0070] The following describes a pixel circuit 10 provided by some embodiments of the present invention. As shown in FIG3A , the pixel circuit 10 includes a pixel driving circuit 1 and a binding unit 2 connected to the pixel driving circuit 1. The binding unit 2 includes a first binding terminal group 21 and at least one second binding terminal group 22 arranged in parallel. The first binding terminal group 21 and the second binding terminal group 22 are configured to bind light-emitting devices. The first binding terminal group 21 includes a first terminal 211 and a second terminal 212, and the second binding terminal group 22 includes a third terminal 221 and a fourth terminal 222. The first terminal 211 and the third terminal 221 are connected and both are connected to the pixel driving circuit 1. The second terminal 212 and the fourth terminal 222 are connected and both are connected to the setting voltage signal line 30.

[0071] It should be noted that the two poles of the light-emitting device are respectively connected to the first terminal 211 and the second terminal 212 in the first binding terminal group 21, and the two poles of the light-emitting device are respectively connected to the third terminal 221 and the fourth terminal 222 of the second binding terminal group 22. There is no restriction on which terminal the positive and negative poles of the light-emitting device are bound to, which is determined according to the specific connection relationship between the pixel circuit and the voltage signal line.

[0072] The above-mentioned setting voltage signal line 30 can transmit a setting voltage signal. The setting voltage is a constant voltage. The setting voltage signal line can be a high-level signal line or a low-level signal line.

[0073] The pixel driving circuit can output a driving current for driving the light emitting device to emit light.

[0074] For example, referring to FIG3A , the binding unit 2 includes a first binding terminal group 21 and a second binding terminal group 22 arranged in parallel. The first binding terminal group 21 and the second binding terminal group 22 are both connected to the pixel driving circuit 1 and the set voltage signal line, and are configured to bind light-emitting devices. In the process of transferring light-emitting devices, if a fault occurs in the process of binding the light-emitting devices with the first binding terminal group 21, resulting in the light-emitting devices at the position of the first binding terminal group 21 not being able to be illuminated, a second transfer is performed at the second binding terminal group 22, and the second binding terminal group 22 is used as a spare binding terminal group to complete the binding of the light-emitting devices, so that the light-emitting devices at the position of the second binding terminal group are normally illuminated, thereby reducing the defective rate generated in the process of mass transfer of light-emitting devices, improving the lighting rate of light-emitting devices, and improving the quality of display products. There is no limit on the number of second binding terminal groups 22.

[0075] In some examples, the first terminal 211 and the third terminal 221 are connected to the first connection node 4, and the second terminal 212 and the fourth terminal 222 are connected to the second connection node 5. When the light-emitting device at the position of the first binding terminal group 21 fails and cannot be illuminated, the connecting leads at the first connection node 4 and the second connection node 5 can be cut off to isolate the first binding terminal group 21 from the pixel circuit, and the light-emitting device at the position of the first binding terminal group 21 does not work, thereby avoiding the abnormal illumination of the light-emitting device affecting the screen display, or the positive and negative poles of the light-emitting device short-circuiting affecting the pixel circuit, ensuring that the light-emitting device at the position of the second binding terminal group can emit light normally, thereby improving the lighting rate of the light-emitting device of the display panel.

[0076] A display panel typically includes a first voltage signal line VDD and a second voltage signal line VSS. The first voltage signal line VDD is configured to transmit a first voltage signal, and the second voltage signal line VSS is configured to transmit a second voltage signal. The voltage of the first voltage signal is greater than the voltage of the second voltage signal. A voltage difference between the positive and negative electrodes of a light-emitting device allows current to flow through the light-emitting device, enabling the light-emitting device to emit light. Based on this principle, the following exemplary embodiments provide different connection methods between the pixel circuit 10 and the voltage signal lines.

[0077] In some embodiments, as shown in FIG. 3B , the pixel driving circuit 1 is electrically connected to the first voltage signal line VDD, and the voltage signal line 30 is set to the second voltage signal line VSS.

[0078] Exemplarily, the voltage signal line 30 is set to the second voltage signal line VSS. That is, the second terminal 212 and the fourth terminal 222 of the binding unit 2 are connected to the second voltage signal line VSS, that is, the second terminal 212 and the fourth terminal 222 receive the second voltage signal. One end of the pixel driving circuit 1 is connected to the first voltage signal line VDD, and the other end is connected to the first terminal 211 and the third terminal 221 of the binding unit 2. The first terminal 211 and the third terminal 221 are configured to bind the positive electrode of their respective corresponding light-emitting devices, and the second terminal 212 and the fourth terminal 222 are configured to bind the negative electrode of their respective corresponding light-emitting devices. In this way, the positive electrode of the light-emitting device is indirectly electrically connected to the first voltage signal line VDD through the pixel driving circuit, and the negative electrode is electrically connected to the second voltage signal line VSS. Under the drive of the pixel driving circuit, the light-emitting device can emit light.

[0079] In some embodiments, as shown in FIG3C , the pixel driving circuit 1 is electrically connected to the second voltage signal line VSS, and the set voltage signal line is the first voltage signal line VDD.

[0080] Exemplarily, the voltage signal line 30 is set to the first voltage signal line VDD. That is, the second terminal 212 and the fourth terminal 222 of the binding unit 2 are connected to the first voltage signal line VDD, that is, the second terminal 212 and the fourth terminal 222 receive the first voltage signal. One end of the pixel driving circuit 1 is electrically connected to the second voltage signal line VSS, and the other end is connected to the first terminal 211 and the third terminal 221 of the binding unit 2. The first terminal 211 and the third terminal 221 are configured to bind the cathode of their respective corresponding light-emitting devices, and the second terminal 212 and the fourth terminal 222 are configured to bind the anode of their respective corresponding light-emitting devices. In this way, the anode of the light-emitting device is electrically connected to the first voltage signal line VDD, and the cathode is indirectly electrically connected to the second voltage signal line VSS through the pixel driving circuit. Under the drive of the pixel driving circuit, the light-emitting device can emit light.

[0081] In some embodiments, the pixel driving circuit 1 in some embodiments of the present disclosure can be a 2T1C, 7T1C, 8T1C or 9T1C circuit, where T represents a transistor, and the number before T represents the number of transistors, C represents a capacitor, and the number before C represents the number of capacitors. For example, 7T1C represents 7 transistors and 1 capacitor.

[0082] The following describes the structure of the corresponding pixel driving circuit 1 when the voltage signal line 30 is set to the second voltage signal line VSS. The pixel driving circuit 1 is only an example.

[0083] In some embodiments, the structure of the pixel driving circuit 1 shown in FIG3B is described. The pixel driving circuit 1 is an equivalent circuit diagram of a 7T1C pixel driving circuit 1. The 7T1C pixel driving circuit 1 may specifically include: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a write transistor T4, a first emission control transistor T5, a second emission control transistor T6, a second reset transistor T7, and a first capacitor Cst1. Signal lines electrically connected to the pixel driving circuit 1 include a reset signal line Reset, a first scan signal line Gate1, a second scan signal line Gate2, a first data signal line Data1, a light emission control signal line EM, a first initialization signal line Vinit1, and a second initialization signal line Vinit2.

[0084] 3B , a gate of the first reset transistor T1 is electrically connected to the reset signal line Reset, a first electrode of the first reset transistor T1 is electrically connected to the first node N1, and a second electrode of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1. The first reset transistor T1 is configured to reset the first node N1 in response to a reset signal received at the reset signal line Reset.

[0085] The gate of the compensation transistor T2 is electrically connected to the first scan signal line Gate1, the first electrode of the compensation transistor T2 is electrically connected to the first node N1, and the second electrode of the compensation transistor T2 is electrically connected to the second node N2. The compensation transistor T2 is configured to perform threshold compensation on the driving transistor T3 in response to the scan signal received at the first scan line Gate1.

[0086] The gate of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to the third node N3, and the second electrode of the driving transistor T3 is electrically connected to the second node N2. The driving transistor T3 is configured to generate a driving current signal.

[0087] The gate of the write transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the write transistor T4 is electrically connected to the third node N3, and the second electrode of the write transistor T4 is electrically connected to the first data signal line Data1. The write transistor T4 is configured to transmit a data signal received on the first data signal line Data1 to the drive transistor T3 in response to the scan signal received on the first scan signal line Gate1.

[0088] The gate of the first emission control transistor T5 is electrically connected to the emission control signal line EM, the first electrode of the first emission control transistor T5 is electrically connected to the first voltage signal line VDD, and the second electrode of the first emission control transistor T5 is electrically connected to the third node N3. The first emission control transistor T5 is configured to transmit a power supply signal received on the first voltage signal line VDD to the driving transistor T3 in response to the emission control signal received on the emission control signal line EM.

[0089] The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM, the first electrode of the second light-emitting control transistor T6 is electrically connected to the second node N2, and the second electrode of the second light-emitting control transistor T6 is electrically connected to the fourth node N4. The second light-emitting control transistor T6 is configured to transmit a driving current signal to the light-emitting device in response to a light-emitting control signal received on the light-emitting control signal line EM, so as to drive the light-emitting device to emit light.

[0090] The gate of the second reset transistor T7 is electrically connected to the second scan signal line Gate2, the first electrode of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and the second electrode of the second reset transistor T7 is electrically connected to the fourth node N4. The second reset transistor T7 is configured to: in response to the scan signal received at the second scan signal line Gate2, transmit the initialization signal received at the second initialization signal line Vinit2 to the light-emitting device to reset the light-emitting device.

[0091] Exemplarily, as shown in FIG. 3B , the first capacitor Cst1 includes a first plate Cst11 and a second plate Cst12 , wherein the first plate Cst11 is electrically connected to the first voltage signal line VDD, and the second plate Cst12 is electrically connected to the first node N1 .

[0092] The first voltage signal line VDD in the pixel driving circuit 1 described above is used to transmit a first voltage signal, such as a high voltage DC signal.

[0093] Exemplarily, the fourth node N4 of the pixel driving circuit 1 is electrically connected to the first terminal 211 and the third terminal 221 of the binding unit 2, the first terminal 211 and the third terminal 221 are configured to bind the positive poles of their respective corresponding light-emitting devices, the second terminal 212 and the fourth terminal 222 are connected to the second voltage signal line VSS, and the second terminal 212 and the fourth terminal 222 are configured to bind the negative poles of their respective corresponding light-emitting devices.

[0094] The following describes the structure of the corresponding pixel driving circuit 1 when the voltage signal line 30 is set to the first voltage signal line VDD. The pixel driving circuit 1 is only an example.

[0095] In some embodiments, the structure of the pixel driving circuit 1 shown in FIG3C is described. The pixel driving circuit 1 is an equivalent circuit diagram of a 2T1C pixel driving circuit 1. The 2T1C pixel driving circuit 1 may include: a data writing transistor T11, a current driving transistor T12, a second capacitor Cst2, a scanning signal line Gate, and a second data signal line Data2.

[0096] For example, as shown in FIG3C , the gate of the data write transistor T11 is electrically connected to the scan signal line Gate, the first electrode of the data write transistor T11 is electrically connected to the second data signal line Data2, and the second electrode of the data write transistor T11 is electrically connected to the fifth node H1. The second capacitor Cst2 includes a first plate Cst21 and a second plate Cst22, wherein the first plate Cst21 is electrically connected to the second voltage signal line VSS, and the second plate Cst22 is electrically connected to the fifth node H1. The gate of the current drive transistor T12 is electrically connected to the fifth node H1, the first electrode of the current drive transistor T12 is electrically connected to the sixth node H2, and the second electrode of the current drive transistor T12 is electrically connected to the second voltage signal line VSS.

[0097] The second voltage signal line VSS in the pixel driving circuit 1 described above is used to transmit a second voltage signal, such as a low-voltage DC signal.

[0098] Exemplarily, the sixth node H2 of the pixel driving circuit 1 is electrically connected to the first terminal 211 and the third terminal 221 of the binding unit 2, the first terminal 211 and the third terminal 221 are configured to bind the negative poles of their respective corresponding light-emitting devices, the second terminal 212 and the fourth terminal 222 are connected to the first voltage signal line VDD, and the second terminal 212 and the fourth terminal 222 are configured to bind the positive poles of their respective corresponding light-emitting devices.

[0099] It should be noted that the first electrode of the transistor disclosed herein is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0100] In the circuit provided by the embodiments of the present disclosure, nodes do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0101] 4 , the pixel circuit 10 further includes an electrostatic protection circuit 3 ; the first terminal 211 and the third terminal 221 are connected to a first connection node 4 , and the electrostatic protection circuit 3 is electrically connected to the first connection node 4 .

[0102] The electrostatic protection circuit 3 includes a first electrostatic protection circuit 31, which includes a first sub-circuit 310 and a second sub-circuit 320. The first end 310a of the first sub-circuit 310 and the second end 320b of the second sub-circuit 320 are electrically connected to a first connection point 330. The second end 310b of the first sub-circuit 310 is also electrically connected to a third voltage signal line VGH, and the first end 320a of the second sub-circuit 320 is also electrically connected to a fourth voltage signal line VGL; the third voltage signal line VGH is configured to transmit a third voltage signal, and the fourth voltage signal line VGL is configured to transmit a fourth voltage signal, and the voltage of the third voltage signal is greater than the voltage of the fourth voltage signal.

[0103] The first sub-circuit 310 is configured to be turned on when an abnormally high voltage appears at the first connection node 4, so that the first connection point 330 discharges to the third voltage signal line VGH; the second sub-circuit 320 is configured to be turned on when an abnormally low voltage appears at the first connection node 4, so that the fourth voltage signal line VGL charges to the first connection point 330.

[0104] It should be noted that the above-mentioned abnormally high voltage refers to the situation in which the voltage at the first connection node 4 is higher than the voltage of the third voltage signal transmitted by the third voltage signal line VGH during the transfer of the light-emitting device. At this time, the abnormally high voltage discharges to the third voltage signal line VGH by turning on the first sub-circuit 310, so that the voltage at the first connection node 4 gradually decreases until the voltage at the first connection point 330 is equal to the voltage transmitted by the third voltage signal line VGH; the abnormally low voltage refers to the situation in which the voltage at the first connection node 4 is lower than the voltage of the fourth voltage signal transmitted by the fourth voltage signal line VGL during the transfer of the light-emitting device. At this time, the abnormally low voltage charges the fourth voltage signal line VGL to the first connection point 330 by turning on the second sub-circuit 320, so that the voltage at the first connection node 4 gradually increases until the voltage at the first connection node 4 is equal to the voltage transmitted by the fourth voltage signal line VGL, thereby ensuring that the voltage at the first connection node 4 is within the normal range, thereby achieving the effect of electrostatic release.

[0105] For example, during the transfer of light-emitting devices, such as by using a stamp, static electricity is easily generated and poorly discharged when the stamp contacts and separates from the display backplane. This static electricity can cause breakdown or damage to electronic components on the display panel. For example, the aforementioned abnormally high or low voltage can cause static electricity breakdown or damage to light-emitting devices, affecting the quality of the display product. By providing an electrostatic protection circuit 3, static electricity can be induced to transfer or release, effectively resolving the breakdown problem caused by static electricity accumulation and improving product yield and quality.

[0106] In some examples, the third voltage signal line VGH and the fourth voltage signal line VGL are distributed throughout the entire display area of ​​the display panel, so that the abnormally high voltage at such a binding terminal point can be discharged to the third voltage signal line VGH within the entire display area, or the abnormally low voltage can be charged and increased through the fourth voltage signal line VGL within the entire display area, thereby achieving rapid charging and discharging and more efficiently solving the problem of poor electrostatic discharge.

[0107] It should be noted that, during the mass transfer of light-emitting devices, the third voltage signal line and the fourth voltage signal line need to be loaded with corresponding voltages to ensure the normal operation of the electrostatic protection circuit. For example, a binding point of the third voltage signal line VGH and the fourth voltage signal line VGL can be set on the array substrate, for example, the binding point is set in the peripheral area of ​​the array substrate, wherein the binding point of the third voltage signal line VGH is electrically connected to the third voltage signal line VGH, and the binding point of the fourth voltage signal line VGL is electrically connected to the fourth voltage signal line VGL. Specifically, the voltage output device is electrically connected to the binding points of the third voltage signal line VGH and the fourth voltage signal line VGL respectively, and outputs corresponding signals (third voltage signal and fourth voltage signal), thereby realizing the transmission of the signal to the third voltage signal line VGH and the fourth voltage signal line VGL, so that the static electricity generated during the mass transfer of light-emitting devices can be released through the third voltage signal line VGH and the fourth voltage signal line VGL.

[0108] Several examples of several first sub-circuits are provided below. The first sub-circuit includes at least one first transistor.

[0109] In some embodiments, as shown in Figure 5A, the first sub-circuit 310 includes a first transistor M1, the gate M13 of the first transistor M1 is electrically connected to the second electrode M12, the first electrode M11 of the first transistor M1 is electrically connected to the first connection point 330, and the second electrode M12 of the first transistor M1 is electrically connected to the third voltage signal line VGH.

[0110] The gate M13 of the first transistor M1 is electrically connected to the second pole M12. At this time, the first transistor M1 can be equivalent to a diode. The first transistor M1 is electrically connected between the first connection point 330 and the third voltage signal line VGH. According to the unidirectional conduction performance of the diode, when the voltage V330 at the first connection point 330 is higher than the voltage Vgh of the third voltage signal line VGH, and the difference between the voltage V330 at the first connection point 330 and the voltage Vgh of the third voltage signal line VGH is greater than or equal to a certain specific voltage value Vf, that is, V330 - Vgh ≥ Vf, the first transistor M1 conducts. That is to say, the abnormal high voltage at the first connection node 4 turns on the first transistor M1, and the first connection point 330 gradually discharges to the third voltage signal line VGH, and the potential of the first connection point 330 gradually decreases, thereby causing the voltage at the first connection node 4 to gradually decrease. When the voltage at the first connection node 4 decreases to less than the sum of the voltage Vgh of the third voltage signal line VGH and Vf, that is, V330 < Vgh + Vf, the first transistor M1 does not meet the conduction condition, and at this time the first transistor M1 is cut off.

[0111] In some embodiments, as shown in FIGS. 5B and 5C, the first sub-circuit 310 includes at least two first transistors M1 connected in series. The gate M13 of each first transistor M1 is electrically connected to the second pole M12. The first pole M11 of the first first transistor M1a among the at least two first transistors M1 is electrically connected to the first connection point 330, and the second pole M12 of the last first transistor M1b is electrically connected to the third voltage signal line VGH.

[0112] Exemplarily, as shown in FIG. 5B, the first sub-circuit 310 shown in FIG. 5B includes two first transistors M1 connected in series. Among them, the gate M13 of each first transistor M1 is electrically connected to its second pole M12. And the two first transistors M1 arranged from bottom to top in FIG. 5B are sequentially called the first first transistor M1a and the last first transistor M1b. The first pole M11 of the first first transistor M1a is electrically connected to the first connection point 330, the second pole M12 of the last first transistor M1b is electrically connected to the third voltage signal line VGH, and the second pole M12 of the first first transistor M1a is electrically connected to the first pole M11 of the last first transistor M1b. The conduction principle of the two first transistors M1 involved in the first sub-circuit 310 all refers to the above description of equivalent the first transistor M1 to a diode, and will not be elaborated here one by one.

[0113] For example, as shown in FIG5C , the first sub-circuit 310 shown in FIG5C includes three first transistors M1 connected in series, wherein the gate M13 of each first transistor M1 is electrically connected to its second electrode M12. The three first transistors M1 arranged from bottom to top in FIG5C are sequentially referred to as the first first transistor M1a, the second first transistor M1c, and the last first transistor M1b. The first electrode M11 of the first first transistor M1a is electrically connected to the first connection point 330, the second electrode M12 of the last first transistor M1b is electrically connected to the third voltage signal line VGH, the second electrode M12 of the first first transistor M1a is electrically connected to the first electrode M11 of the second first transistor M1c, and the second electrode M12 of the second first transistor M1c is electrically connected to the first electrode M11 of the last first transistor M1b. The conduction principle of the three first transistors M1 involved in the first sub-circuit 310 is similar to the above description of the first transistor M1 being equivalent to a diode, and is not further described here.

[0114] The first sub-circuit 310 includes at least two first transistors M1 connected in series, which can improve the discharge efficiency from the first connection point 330 to the third voltage signal line VGH, achieve rapid discharge, and further enhance the anti-static effect.

[0115] Several examples of several second sub-circuits are provided below, where the second sub-circuit includes at least one second transistor.

[0116] In some embodiments, as shown in Figure 6A, the second sub-circuit 320 includes a second transistor M2, the gate M23 of the second transistor M2 is electrically connected to the second electrode M22, the first electrode M21 of the second transistor M2 is electrically connected to the fourth voltage signal line VGL, and the second electrode M22 of the second transistor M2 is electrically connected to the first connection point 330.

[0117] The gate M23 of the second transistor M2 is electrically connected to the second electrode M22. At this time, the second transistor M2 can be equivalent to a diode. The second transistor M2 is electrically connected between the first connection point 330 and the fourth voltage signal line VGL. According to the unidirectional conduction performance of the diode, when the voltage V330 at the first connection point 330 is lower than the voltage Vgl of the fourth voltage signal line VGL, and the difference between the voltage Vgl of the fourth voltage signal line VGL and the voltage V330 of the first connection point 330 is greater than or equal to a specific voltage value Vf, that is, Vgl-V33 When 0≥Vf, the second transistor M2 is turned on, that is, the abnormally low voltage at the first connection node 4 turns on the second transistor M2, and the fourth voltage signal line VGL gradually charges the first connection point 330, and the potential of the first connection point 330 gradually increases, thereby causing the voltage at the first connection node 4 to gradually increase. When the voltage at the first connection node 4 increases to a value greater than the difference between the voltage Vgl of the fourth voltage signal line VGL and Vf, that is, V330>Vgl-Vf, the second transistor M2 does not meet the turn-on condition, and the second transistor M2 is turned off.

[0118] In some embodiments, as shown in Figures 6B and 6C, the second sub-circuit 320 includes at least two second transistors M2 connected in series, the gate M23 of each second transistor M2 is electrically connected to the second electrode M22, the first electrode M21 of the first second transistor M2a of the at least two second transistors M2 is electrically connected to the fourth voltage signal line VGL, and the second electrode M22 of the last second transistor M2b is electrically connected to the first connection point 330.

[0119] For example, referring to FIG6B , the second sub-circuit 320 shown in FIG6B includes two second transistors M2 connected in series, wherein the gate M23 of each second transistor M2 is electrically connected to the second electrode M22, and the two second transistors M2 arranged from bottom to top in FIG6B are referred to as the first second transistor M2a and the last second transistor M2b, respectively. The first electrode M21 of the first second transistor M2a is electrically connected to the fourth voltage signal line VGL, the second electrode M22 of the last second transistor M2b is electrically connected to the first connection point 330, and the second electrode M22 of the first second transistor M2a is electrically connected to the first electrode M21 of the last second transistor M2b. The conduction principle of the two second transistors M2 in series in the second sub-circuit 320 is similar to the above description of the second transistor M2 being equivalent to a diode, and will not be repeated here.

[0120] For example, referring to FIG6C , the second sub-circuit 320 shown in FIG6C includes three second transistors M2 connected in series, wherein the gate M23 of each second transistor M2 is electrically connected to the second electrode M22. The three second transistors M2 arranged from bottom to top in FIG6C are sequentially referred to as a first second transistor M2a, a second second transistor M2c, and a last second transistor M2b. The first electrode M21 of the first second transistor M2a is electrically connected to the fourth voltage signal line VGL, the second electrode M22 of the last second transistor M2b is electrically connected to the first connection point 330, the second electrode M22 of the first second transistor M2a is electrically connected to the first electrode M21 of the second second transistor M2c, and the second electrode M22 of the second second transistor M2c is electrically connected to the first electrode M21 of the last first transistor M1b. The conduction principle of the three second transistors M2 in series in the second sub-circuit 320 and the description of the second transistor M2 as a diode are all referred to above, and are not further described here.

[0121] The second sub-circuit 320 includes at least two second transistors M2 connected in series, which can improve the charging efficiency of the fourth voltage signal line VGL to the first connection point 330, achieve fast charging, and further enhance the anti-static effect.

[0122] In some embodiments, referring to Figure 7, the second terminal 212 and the fourth terminal 222 are connected to the second connection node 5, and the electrostatic protection circuit 3 is electrically connected to the second connection node 5; the electrostatic protection circuit 3 also includes a second electrostatic protection circuit 32, the second electrostatic protection circuit 32 includes a third sub-circuit 350 and a fourth sub-circuit 340, the first end 350a of the third sub-circuit 350 and the second end 340b of the fourth sub-circuit 340 are electrically connected to the second connection point 360, the second end 350b of the third sub-circuit 350 is also electrically connected to the third voltage signal line VGH, and the first end 340a of the fourth sub-circuit 340 is also electrically connected to the fourth voltage signal line VGL; the third sub-circuit 350 is configured to be turned on when an abnormally high voltage appears at the second connection node 5, so that the second connection point 360 discharges to the third voltage signal line VGH; the fourth sub-circuit 340 is configured to be turned on when an abnormally low voltage appears at the second connection node 5, so that the fourth voltage signal line VGL charges to the second connection node 5.

[0123] It should be noted that the above-mentioned abnormally high voltage refers to the situation in which the voltage at the second connection node 5 is higher than the voltage of the third voltage signal transmitted by the third voltage signal line VGH during the transfer of the light-emitting device. At this time, the abnormally high voltage is discharged to the third voltage signal line VGH by turning on the third sub-circuit 350, so that the voltage at the second connection node 5 gradually decreases until the voltage at the second connection point 360 decreases to a value equal to the difference between the voltage transmitted by the third voltage signal line VGH and Vf. The abnormally low voltage refers to the situation in which the voltage at the second connection node 5 is lower than the voltage of the fourth voltage signal transmitted by the fourth voltage signal line VGL during the transfer of the light-emitting device. At this time, the abnormally low voltage is discharged to the second connection point 360 by turning on the fourth sub-circuit 340, so that the fourth voltage signal line VGL charges the second connection point 360, so that the voltage at the second connection node 5 gradually increases until the voltage at the second connection node 5 increases to a value equal to the difference between the voltage transmitted by the fourth voltage signal line VGL and Vf. It can be found that when the electrostatic protection circuit 3 is present, the voltage at the second connection node 5 can be ensured to be within the range of (VGL-Vf) to (VGH+Vf), thereby achieving the effect of electrostatic discharge.

[0124] For example, referring to Figure 3B, when the voltage signal line 30 is set to the second voltage signal line VSS, the second terminal 212 and the fourth terminal 222 of the binding unit 2 are connected to the second voltage signal line VSS to receive the second voltage signal. The second terminal 212 and the fourth terminal 222 are bound to the negative pole of the light-emitting device, that is, the negative pole of the light-emitting device is connected to the second voltage signal line VSS. Under normal circumstances, the second voltage signal is a DC signal, which can be distributed throughout the entire display area. When an abnormal voltage appears in the light-emitting device during the transfer process, the abnormal voltage can be directly transferred and transmitted on the second voltage signal, so that the static electricity generated during the transfer can be gradually eliminated. At this time, the second electrostatic protection circuit 32 can also be omitted, and the static electricity can still be transferred or released, effectively solving the problem of electrostatic breakdown and improving the yield and quality of the product. At the same time, since the second electrostatic protection circuit 32 is not set, the pixel circuit space layout can be saved, so that the pixel density of the display panel is higher and the resolution is higher.

[0125] Several examples of several third sub-circuits are provided below, where the third sub-circuit includes at least one third transistor.

[0126] In some embodiments, as shown in Figure 8A, the third sub-circuit 350 includes a third transistor M3, a gate M33 of the third transistor M3 is electrically connected to the second electrode M32, a first electrode M31 of the third transistor M3 is electrically connected to the second connection point 360, and a second electrode M32 of the third transistor M3 is electrically connected to the third voltage signal line VGH.

[0127] The gate M33 of the third transistor M3 is electrically connected to the second pole M32. At this time, the third transistor M3 can be equivalent to a diode. The third transistor M3 is electrically connected between the second connection point 360 and the third voltage signal line VGH. According to the unidirectional conduction performance of the diode, when the voltage V360 of the second connection point 360 is higher than the voltage Vgh of the third voltage signal line VGH, and the difference between the voltage V360 of the second connection point 360 and the voltage Vgh of the third voltage signal line VGH is greater than or equal to a certain specific voltage value Vf, that is, V360 - Vgh ≥ Vf, the third transistor M3 conducts. That is to say, the abnormal high voltage at the second connection node 5 turns on the third transistor M3, and the second connection point 360 gradually discharges to the third voltage signal line VGH, and the potential of the second connection point 360 gradually decreases, so that the voltage at the second connection node 5 gradually decreases. When the voltage at the second connection node 5 decreases to less than the sum of the voltage Vgh of the third voltage signal line VGH and Vf, that is, V360 < Vgh + Vf, the third transistor M3 does not meet the conduction condition, and at this time the third transistor M3 is cut off.

[0128] In some embodiments, as shown in FIGS. 8B and 8C, the third sub-circuit 350 includes at least two third transistors M3 connected in series. The gate M33 of each third transistor M3 is electrically connected to the second pole M32. The first pole M31 of the first third transistor M3a in the at least two third transistors M3 is electrically connected to the second connection point 360, and the second pole M32 of the last third transistor M3b is electrically connected to the third voltage signal line VGH.

[0129] Exemplarily, as shown in FIG. 8B, the third sub-circuit 350 shown in FIG. 8B includes two third transistors M3 connected in series. Among them, the gate M33 of each third transistor M3 is electrically connected to the second pole M32. The two third transistors M3 arranged from bottom to top in FIG. 8B are sequentially called the first third transistor M3a and the last third transistor M3b. The first pole M31 of the first third transistor M3a is electrically connected to the second connection point 360, and the second pole M32 of the last third transistor M3b is electrically connected to the third voltage signal line VGH. The second pole M32 of the first third transistor M3a is electrically connected to the first pole M31 of the last third transistor M3b. The conduction principle of the two third transistors M3 involved in this third sub-circuit 350 all refers to the description of equivalent the third transistor M3 to a diode above, and will not be elaborated here one by one.

[0130] For example, referring to FIG8C , the third sub-circuit 350 shown in FIG8C includes three third transistors M3 connected in series, wherein the gate M33 of each third transistor M3 is electrically connected to the second electrode M32. The three third transistors M3 arranged from bottom to top in FIG8B are sequentially referred to as a first third transistor M3a, a second third transistor M3c, and a last third transistor M3b. The first electrode M31 of the first third transistor M3a is electrically connected to the second connection point 360, the second electrode M32 of the last third transistor M3b is electrically connected to the third voltage signal line VGH, the second electrode M32 of the first third transistor M3a is electrically connected to the first electrode M31 of the second third transistor M3c, and the second electrode M32 of the second third transistor M3c is electrically connected to the first electrode M31 of the last third transistor M3b. The conduction principle of the three third transistors M3 involved in the third sub-circuit 350 is similar to the above description of the third transistor M3 being equivalent to a diode, and is not further described here.

[0131] The third sub-circuit 350 includes at least two third transistors M3 connected in series, which can improve the discharge efficiency from the second connection point 360 to the third voltage signal line VGH, achieve rapid discharge, and further enhance the anti-static effect.

[0132] Several examples of several fourth sub-circuits are provided below, where the first sub-circuit includes at least one fourth transistor.

[0133] In some embodiments, as shown in Figure 9A, the fourth sub-circuit 340 includes a fourth transistor M4, a gate M43 of the fourth transistor M4 is electrically connected to the second electrode M42, a first electrode M41 of the fourth transistor M4 is electrically connected to the fourth voltage signal line VGL, and a second electrode M42 of the fourth transistor M4 is electrically connected to the second connection point 360.

[0134] The gate M43 of the fourth transistor M4 is electrically connected to the second electrode M42. In this case, the fourth transistor M4 can be equivalent to a diode. The fourth transistor M4 is electrically connected between the second connection point 360 and the fourth voltage signal line VGL. According to the unidirectional conduction performance of the diode, when the voltage of the second connection point 360 is lower than the voltage Vgl of the fourth voltage signal line VGL, and the difference between the voltage Vgl of the fourth voltage signal line VGL and the voltage V360 of the second connection point 360 is greater than or equal to a specific voltage value Vf, that is, Vgl-V360≥ When Vf is reached, the fourth transistor M4 is turned on, that is, the abnormally low voltage at the second connection node 5 turns on the fourth transistor M4, and the fourth voltage signal line VGL gradually charges the second connection point 360. The potential of the second connection point 360 gradually increases, thereby causing the voltage at the second connection node 5 to gradually increase. When the voltage at the second connection node 5 increases to a value greater than the difference between the voltage Vgl of the fourth voltage signal line VGL and Vf, that is, V360>Vgl-Vf, the fourth transistor M4 does not meet the turn-on condition, and the fourth transistor M4 is turned off.

[0135] In some embodiments, referring to Figures 9B and 9C, the fourth sub-circuit 340 includes at least two fourth transistors M4 connected in series, the gate M43 of each fourth transistor M4 is electrically connected to the second electrode M42, the first electrode M41 of the first fourth transistor M4a of the at least two fourth transistors M4 is electrically connected to the fourth voltage signal line VGL, and the second electrode M42 of the last fourth transistor M4b is electrically connected to the second connection point 360.

[0136] For example, as shown in FIG9B , the fourth sub-circuit 340 shown in FIG9B includes two fourth transistors M4 connected in series, wherein a gate M43 of each fourth transistor M4 is electrically connected to a second electrode M42. The two fourth transistors M4 arranged from bottom to top in FIG9B are referred to as a first fourth transistor M4a and a last fourth transistor M4b, respectively. A first electrode M41 of the first fourth transistor M4a is electrically connected to the fourth voltage signal line VGL, a second electrode M42 of the last fourth transistor M4b is electrically connected to the second connection point 360, and the second electrode M42 of the first fourth transistor M4a is electrically connected to a first electrode M41 of the last fourth transistor M4b. The conduction principle of the two fourth transistors M4 connected in series in the fourth sub-circuit 340 is similar to the above description of the fourth transistor M4 being equivalent to a diode, and is not further described here.

[0137] For example, as shown in FIG9C , the fourth sub-circuit 340 shown in FIG9C includes three fourth transistors M4 connected in series, wherein a gate M43 of each fourth transistor M4 is electrically connected to a second electrode M42. The three fourth transistors M4 arranged from bottom to top in FIG9C are sequentially referred to as a first fourth transistor M4a, a second fourth transistor M4c, and a last fourth transistor M4b. A first electrode M41 of the first fourth transistor M4a is electrically connected to the fourth voltage signal line VGL, a second electrode M42 of the last fourth transistor M4b is electrically connected to the second connection point 360, a second electrode M42 of the first fourth transistor M4a is electrically connected to a first electrode M41 of the second fourth transistor M4c, and a second electrode M42 of the second fourth transistor M4c is electrically connected to a first electrode M41 of the last fourth transistor M4b. The conduction principle of the three fourth transistors M4 connected in series in the fourth sub-circuit 340 and the description of the fourth transistor M4 as a diode are all referred to above, and are not further elaborated here.

[0138] The fourth sub-circuit 340 includes at least two fourth transistors M4 connected in series, which can improve the charging efficiency of the fourth voltage signal line VGL to the second connection point 360, achieve fast charging, and further enhance the anti-static effect.

[0139] As shown in Figures 10, 11A to 11E, 12A and 12B, some embodiments of the present disclosure further provide an array substrate 100, including the pixel circuit 10 provided by any of the above embodiments, wherein the array substrate 100 shown in Figures 12A and 12B includes a stacked substrate 101, a semiconductor layer 102, a first gate layer 103, a second gate layer 104, a first source-drain metal layer 105, a second source-drain metal layer 107, and a binding layer 106; these film layers are collectively referred to as functional film layers in the array substrate, each functional film layer has a set pattern, and an insulating layer is arranged between adjacent functional film layers.

[0140] For example, referring to FIG3B and FIG11A , the structure of each functional layer is described using a 7T1C pixel driving circuit as an example: the pixel driving circuit 1 is located in the semiconductor layer 102, the first gate layer 103, the second gate layer 104, and the first source-drain metal layer 105. The semiconductor layer 102 includes an active layer comprising a first reset transistor T1, a compensation transistor T2, a drive transistor T3, a write transistor T4, a first emission control transistor T5, a second emission control transistor T6, and a second reset transistor T7. The material of the semiconductor layer 102 can be, for example, amorphous silicon, low-temperature polysilicon, a metal oxide semiconductor, etc., but is not limited here. Referring to FIG11B , the first gate layer 103 includes multiple signal lines extending along the row direction X, namely a reset signal line Reset, a first scan signal line Gate1, an emission control signal line EM, a second scan signal line Gate2, a third voltage signal line VGH, and a fourth voltage signal line VGL, configured to transmit different signals to the transistors. The first gate layer 103 also includes a second plate Cst12 of a first capacitor Cst1. Referring to Figure 11C , the second gate layer 104 includes a first initialization signal line Vinit1 and a second initialization signal line Vinit2, configured to provide an initialization signal to the transistor. The second gate layer 104 also includes a first plate Cst11 of a first capacitor Cst1. The second plate Cst12 overlaps with the first plate Cst11 to form the first capacitor Cst1. Referring to Figure 11D , the first source / drain metal layer 105 includes a first data signal line Data1 and a first voltage signal line VDD, electrically connected to the transistor and configured to transmit data and voltage signals to the transistor.

[0141] The setting voltage signal line 30 is located in the first source-drain metal layer 105 or the second source-drain metal layer 107. For example, the setting voltage signal line 30 illustrated in Figure 11E is located in the second source-drain metal layer 107; referring to Figures 10 and 12A, the binding unit 2 is located in the binding layer 106; in the area where at least one pixel circuit 10 is located, the binding layer 106 includes a first binding pattern group 20a and at least one second binding pattern group 20b, the first binding pattern group 20a includes a first binding pattern 201 and a second binding pattern 202, and the second binding pattern group 20b includes a third binding pattern 203 and a fourth binding pattern 204; combined with Figure 3A, the first binding pattern group 20a serves as the first binding terminal group 21, and the second binding pattern group 20b serves as the second binding terminal group 22; the first binding pattern 201 and the third binding pattern 203 are both electrically connected to the pixel driving circuit 1, and the second binding pattern 202 and the fourth binding pattern 204 are both electrically connected to the setting voltage signal line 30.

[0142] It should be noted that the voltage signal line 30 described above, when located in the first source / drain metal layer 105, is the first voltage signal line VDD, corresponding to the 2T1C pixel driving circuit shown in FIG3C . The voltage signal line 30, when located in the second source / drain metal layer 107, is the second voltage signal line VSS, corresponding to the 7T1C pixel driving circuit shown in FIG3B . Referring to FIG11E , the array substrate will be described below with the voltage signal line 30 being the second voltage signal line VSS.

[0143] For example, referring to Figures 11A to 11E, 12A and 12B, Figures 11A to 11E are planar structural diagrams of the semiconductor layer 102, the first gate layer 103, the second gate layer 104, the first source-drain metal layer 105 and the second source-drain metal layer 107, respectively. Figure 10 is a plan view of a pixel circuit corresponding to a 7T1C pixel driving circuit, and Figures 12A and 12B are cross-sectional structural diagrams obtained based on Figure 10, respectively.

[0144] As shown in Figure 10, the binding layer 106 includes multiple binding patterns, which are used to connect to the positive or negative electrodes of the light-emitting device. For example, the positive electrode and the negative electrode of the light-emitting device are respectively in contact with the first binding pattern 201 and the second binding pattern 202 in the first binding pattern group 20a, or the positive electrode and the negative electrode of the light-emitting device are respectively in contact with the third binding pattern 203 and the fourth binding pattern 204 in the second binding pattern group 20b to achieve binding.

[0145] In some embodiments, referring to Figure 11F, the second source-drain metal layer 107 includes a first source-drain pattern group 30a and at least one second source-drain pattern group 30b, the first source-drain pattern group 30a includes a first source-drain pattern 301 and a second source-drain pattern 302, and the second source-drain pattern group 30b includes a third source-drain pattern 303 and a fourth source-drain pattern 304; the first source-drain pattern 301 is electrically connected to the first binding pattern 201; the second source-drain pattern 302 is electrically connected to the second binding pattern 202; the third source-drain pattern 303 is electrically connected to the third binding pattern 203; the fourth source-drain pattern 304 is electrically connected to the fourth binding pattern 204; the first source-drain pattern 301 and the third source-drain pattern 303 are both electrically connected to the pixel driving circuit 1; specifically, the first source-drain pattern 301 and the third source-drain pattern 303 are both electrically connected to the fourth node N4 of the pixel driving circuit 1. 11E , the second source-drain pattern 302 and the fourth source-drain pattern 304 are both electrically connected to the setting voltage signal line 30 .

[0146] For example, referring to Figures 10 and 12A, the second source-drain metal layer 107 shown in Figures 10 and 12A includes a first source-drain pattern group 30a and a second source-drain pattern group 30b, wherein the first source-drain pattern group 30a includes a first source-drain pattern 301 and a second source-drain pattern 302, and the second source-drain pattern group 30b includes a third source-drain pattern 303 and a fourth source-drain pattern 304. A first insulating layer 108 is provided between the second source-drain metal layer 107 and the binding layer 106, and the first binding pattern 201, the second binding pattern 202, the third binding pattern 203 and the fourth binding pattern 204 respectively pass through the vias of the insulating layer 108 and are electrically connected to the first source-drain pattern 301, the second source-drain pattern 302, the third source-drain pattern 303 and the fourth source-drain pattern 304 respectively. That is to say, the orthographic projections of the first binding pattern 201 and the first source-drain pattern 301 on the substrate 101 overlap, the orthographic projections of the second binding pattern 202 and the second source-drain pattern 302 on the substrate 101 overlap, the orthographic projections of the third binding pattern 203 and the third source-drain pattern 303 on the substrate 101 overlap, and the orthographic projections of the fourth binding pattern 204 and the fourth source-drain pattern 304 on the substrate 101 overlap.

[0147] It should be noted that the above-mentioned setting voltage signal line 30 is the second voltage signal line VSS, the pixel driving circuit 1 is connected to the first voltage signal line VDD, the first binding pattern 201 and the first source and drain pattern 301 form a first terminal 211, the second binding pattern 202 and the second source and drain pattern 302 form a second terminal 212, the third binding pattern 203 and the third source and drain pattern 303 form a third terminal 221, and the fourth binding pattern 204 and the fourth source and drain pattern 304 form a fourth terminal. The pixel driving circuit 1 transmits a first voltage signal to the first binding pattern 201 and the first source and drain pattern 301, or the third binding pattern 203 and the third source and drain pattern 303, and the setting voltage signal line 30 transmits a second voltage signal to the second binding pattern 202 and the second source and drain pattern 302, or the fourth binding pattern 204 and the fourth source and drain pattern 304.

[0148] In some embodiments, referring to Figure 10, the first source and drain pattern 301 and the third source and drain pattern 303 are connected to the pixel driving circuit 1 as follows: the first source and drain metal layer 105 includes a first connecting line 1051, which is connected to the pixel driving circuit 1. The first connecting line 1051 is also connected to the first source and drain pattern 301 and the third source and drain pattern 303.

[0149] For example, referring to Figures 10 and 11D , the first end of the first connection line 1051 contacts the semiconductor layer via a via extending through the first source / drain metal layer and the semiconductor layer. Specifically, the first connection line 1051 is electrically connected to the connection point (fourth node N4) between the active layer of the second reset transistor T7 and the active layer of the second emission control transistor T6 through the via. Referring to Figures 10 and 11E , and Figures 12A and 12B , a second insulating layer 109 and a planar layer 111 are further provided between the first source / drain metal layer 105 and the second source / drain metal layer 107. The first connection line 1051 is electrically connected to the first source / drain pattern 301 and the third source / drain pattern 303 via a via extending through the second insulating layer 109 and the planar layer 111. The first connection line 1051 is configured to transmit a voltage signal from the pixel driving circuit 1 to the first source / drain pattern 301 and the third source / drain pattern 303.

[0150] In some embodiments, referring to Figure 7, the first terminal 211 and the third terminal 221 are connected to the first connection node 4; as shown in Figure 10, the first connection line 1051 includes a connection portion 10511 located in the middle position thereof, and the connection portion 10511 serves as the first connection node 4, and the first source and drain pattern group 30a and the second source and drain pattern group 30b have no overlap with the connection portion 10511.

[0151] For example, when a failure occurs during the binding process of the light-emitting device, the above-mentioned connection portion 10511 serves as the first connection node 4, and this position can be cut off, so that the first binding terminal group (the first binding pattern group 20a and the first source-drain pattern group 30a) is independent of the pixel driving circuit and the second binding terminal group (the second binding pattern group 20b and the second source-drain pattern group 30b), which is convenient for maintenance.

[0152] In some embodiments, referring to FIG. 11A and FIG. 10 , the pixel driving circuit 1 includes a driving transistor T3 , the semiconductor layer 102 includes an active layer of the driving transistor T3 , and the first source-drain pattern group 30 a and the second source-drain pattern group 30 b do not overlap with the active layer of the driving transistor T3 .

[0153] It should be noted that the first source-drain pattern group 30a and the second source-drain pattern group 30b are used to bind the light-emitting device. Since the light-emitting device may be subjected to high temperature and high pressure processes during the mass transfer process, in order to ensure the stability of the transistor operation, the first source-drain pattern group 30a and the second source-drain pattern group 30b are set to have no overlap with the active layer of the driving transistor T3, thereby ensuring that the light-emitting device and the active layer of the driving transistor T3 do not overlap, avoiding adverse effects on the driving transistor T3 and affecting the normal operation of the pixel circuit.

[0154] In some embodiments, referring to Figure 4, the pixel circuit 10 also includes an electrostatic protection circuit 3; the electrostatic protection circuit 3 includes a first transistor M1 and a second transistor M2; as shown in Figure 11A, the semiconductor layer 102 includes an active layer of the first transistor M1 and an active layer of the second transistor M2; the first end of the active layer of the first transistor M1 and the second end of the active layer of the second transistor M2 are close to and connected to each other; referring to Figures 11B and 11D, the first gate layer 103 includes a third voltage signal line VGH, a fourth voltage signal line VGL, and a gate pattern M2G of the second transistor M2; the first source-drain metal layer 105 includes a first connection pattern 105a, a second connection pattern 105b and a third connection pattern 105c, and a second connection line 1052.

[0155] The second end of the active layer of the first transistor M1 is connected to the first connection pattern 105a, which is in turn connected to the third voltage signal line VGH. For example, the first connection pattern 105a is connected to the second end of the active layer of the first transistor M1 through a via extending through the semiconductor layer 102, and the first connection pattern 105a is connected to the third voltage signal line VGH through a via extending through the first gate layer 103. The third voltage signal line VGH overlaps with the active layer of the first transistor M1, and this overlapping portion serves as the gate of the first transistor M1. This ensures that both the second electrode and the gate of the first transistor M1 are connected to the third voltage signal line VGH.

[0156] The first end of the active layer of the first transistor M1 is connected to the second connection pattern 105b, which is connected to the gate pattern M2G of the second transistor M2. The gate pattern of the second transistor M2 overlaps with the active layer of the second transistor M2. For example, the second connection pattern 105b is connected to the first end of the active layer of the first transistor M1 through a via extending through the semiconductor layer 102. The second connection pattern 105b is also connected to the gate pattern M2G of the second transistor M2 through a via extending through the first gate layer. Thus, the first electrode of the first transistor M1 is connected to the gate of the second transistor M2. The first end of the first transistor M1 and the second end of the second transistor M2 are connected in the semiconductor layer.

[0157] The first end of the active layer of the second transistor M2 is connected to the third connection pattern 105c, and the third connection pattern 105c is connected to the fourth voltage signal line VGL. For example, the third connection pattern 105c is connected to the first end of the active layer of the second transistor M2 through a via hole penetrating the semiconductor layer. The third connection pattern 105c is also connected to the fourth voltage signal line VGL through a via hole penetrating the first gate layer 103, so that the first electrode of the second transistor M2 is connected to the fourth voltage signal line VGL.

[0158] As shown in FIG11D , the two ends of the second connection line 1052 are connected to the first connection line 1051 and the second connection pattern 105b, respectively. In this way, the second connection pattern 105b is equivalent to the first connection point, the first connection line 1051 is equivalent to the first connection node 4, and the first connection point 330 is connected to the first connection node 4 through the second connection line 1052.

[0159] The above describes the film structure of the first electrostatic protection circuit 31 in the electrostatic protection circuit 3 . The film structure of the second electrostatic protection circuit 32 refers to the description of the first electrostatic protection circuit 31 .

[0160] It should be noted that the first end of the active layer of the above-mentioned first transistor M1 is equivalent to the first electrode M11 of the first transistor M1, the second end of the active layer of the first transistor M1 is equivalent to the second electrode M12 of the first transistor M1, the first end of the active layer of the second transistor M2 is equivalent to the first electrode M21 of the second transistor M2, and the second end of the active layer of the second transistor M2 is equivalent to the second electrode M22 of the second transistor M2.

[0161] In some embodiments, a plurality of pixel circuits 10 are arranged in an array; the first gate layer 103 includes a plurality of third voltage signal lines VGH and a plurality of fourth voltage signal lines VGL extending along the row direction X; as shown in FIG10 , each third voltage signal line VGH and each fourth voltage signal line VGL is located in an area where a row of pixel circuits 10 is located.

[0162] It can be understood that a plurality of pixel circuits 10 are provided on the array substrate 100, and the plurality of pixel circuits 10 are arranged in an array. Referring to FIG. 10 , FIG. 10 is a structural diagram of a pixel circuit. As can be seen from FIG. 10 , the third voltage signal line VGH and the fourth voltage signal line VGL extend along the row direction X, and each third voltage signal line VGH and the fourth voltage signal line VGL are located in the area where a row of pixel circuits 10 are located.

[0163] As shown in Figure 13, some embodiments of the present disclosure also provide a display panel 1000, including an array substrate 100 provided in any of the above embodiments and a plurality of light-emitting devices 20, each of the plurality of light-emitting devices 20 is electrically connected to the first binding terminal group 21 or the second binding terminal group 22 in the array substrate 100.

[0164] The display panel 1000 also includes a light-emitting device layer and an encapsulation layer 120. The light-emitting device layer includes a plurality of light-emitting devices 20 and a protective adhesive layer 110. The protective adhesive layer fills the gaps between the plurality of light-emitting devices and covers the surfaces of the light-emitting devices. The first binding terminal group 21 or the second binding terminal group 22 is used to bind the plurality of light-emitting devices 20. FIG13 illustrates a light-emitting device 20 bound to the first binding terminal group 21. The encapsulation layer 120 is disposed on the light-emitting device layer and is configured to protect the light-emitting devices 20, preventing the light-emitting devices 20 from being corroded by water and oxygen, which could cause poor display of the display panel 1000, thereby improving the yield of the display panel 1000.

[0165] The embodiment of the present disclosure does not impose any special restrictions on the specific form of the above display panel. Therefore, the display panel 1000 provided by the present invention has all the beneficial effects of the array substrate 100 provided by any of the above embodiments, which will not be described in detail here.

[0166] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A pixel circuit, comprising: Pixel driving circuit; a binding unit connected to the pixel driving circuit, the binding unit comprising a first binding terminal group and at least one second binding terminal group arranged in parallel, the first binding terminal group and the second binding terminal group being configured to bind the light-emitting device; Among them, the first binding terminal group includes a first terminal and a second terminal, the second binding terminal group includes a third terminal and a fourth terminal, the first terminal and the third terminal are connected and are both connected to the pixel driving circuit, the second terminal and the fourth terminal are connected and are both connected to the set voltage signal line.

2. The pixel circuit according to claim 1, wherein: The pixel driving circuit is electrically connected to the first voltage signal line, the set voltage signal line is the second voltage signal line, or, The pixel driving circuit is electrically connected to the second voltage signal line, and the set voltage signal line is the first voltage signal line; The first voltage signal line is configured to transmit a first voltage signal, the second voltage signal line is configured to transmit a second voltage signal, and the voltage of the first voltage signal is greater than the voltage of the second voltage signal.

3. The pixel circuit according to claim 2, wherein: The pixel circuit also includes an electrostatic protection circuit; The first terminal and the third terminal are connected to a first connection node, and the electrostatic protection circuit is electrically connected to the first connection node; The electrostatic protection circuit comprises a first electrostatic protection circuit, the first electrostatic protection circuit comprises a first subcircuit and a second subcircuit, a first end of the first subcircuit and a second end of the second subcircuit are electrically connected to a first connection point, the second end of the first subcircuit is also electrically connected to a third voltage signal line, and the first end of the second subcircuit is also electrically connected to a fourth voltage signal line; the third voltage signal line is configured to transmit a third voltage signal, the fourth voltage signal line is configured to transmit a fourth voltage signal, and a voltage of the third voltage signal is greater than a voltage of the fourth voltage signal; The first sub-circuit is configured to be turned on when an abnormally high voltage appears at the first connection node, so that the first connection point discharges to the third voltage signal line; the second sub-circuit is configured to be turned on when an abnormally low voltage appears at the first connection node, so that the fourth voltage signal line charges to the first connection point.

4. The pixel circuit according to claim 3, wherein: The first subcircuit includes at least one first transistor; The first sub-circuit includes a first transistor, the gate of the first transistor is electrically connected to the second electrode, the first electrode of the first transistor is electrically connected to the first connection point, and the second electrode of the first transistor is electrically connected to the third voltage signal line; or, The first subcircuit includes at least two first transistors connected in series; each first The gate of the transistor is electrically connected to the second electrode, the first electrode of the first first transistor of the at least two first transistors is electrically connected to the first connection point, and the second electrode of the last first transistor is electrically connected to the third voltage signal line.

5. The pixel circuit according to claim 3 or 4, wherein: The second sub-circuit includes at least one second transistor; The second sub-circuit includes a second transistor, the gate of the second transistor is electrically connected to the second electrode, the first electrode of the second transistor is electrically connected to the fourth voltage signal line, and the second electrode of the second transistor is electrically connected to the first connection point; or, The second sub-circuit includes at least two second transistors, which are connected in series; the gate of each second transistor is electrically connected to the second electrode, the first electrode of the first second transistor of the at least two second transistors is electrically connected to the fourth voltage signal line, and the second electrode of the last second transistor is electrically connected to the first connection point.

6. The pixel circuit according to any one of claims 3 to 5, wherein: The second terminal and the fourth terminal are connected to a second connection node, and the electrostatic protection circuit is also electrically connected to the second connection node; The electrostatic protection circuit further includes a second electrostatic protection circuit, the second electrostatic protection circuit includes a third subcircuit and a fourth subcircuit, the first end of the third subcircuit and the second end of the fourth subcircuit are electrically connected to the second connection point, the second end of the third subcircuit is also electrically connected to the third voltage signal line, and the first end of the fourth subcircuit is also electrically connected to the fourth voltage signal line; The third sub-circuit is configured to be turned on when an abnormally high voltage appears at the second connection node, so that the second connection point discharges to the third voltage signal line; the fourth sub-circuit is configured to be turned on when an abnormally low voltage appears at the second connection node, so that the fourth voltage signal line charges to the second connection point.

7. The pixel circuit according to claim 6, wherein: The third sub-circuit comprises at least one third transistor; The third subcircuit includes a third transistor; the gate of the third transistor is electrically connected to the second electrode, the first electrode of the third transistor is electrically connected to the second connection point, and the second electrode of the third transistor is electrically connected to the third voltage signal line; or, The third subcircuit includes at least two third transistors, which are connected in series; the gate of each third transistor is electrically connected to the second electrode, the first electrode of the first third transistor of the at least two third transistors is electrically connected to the second connection point, and the second electrode of the last third transistor is electrically connected to the third voltage signal line.

8. The pixel circuit according to claim 6 or 7, wherein: The fourth subcircuit comprises at least one fourth transistor; The fourth subcircuit includes a fourth transistor; the gate of the fourth transistor is electrically connected to the second electrode, the first electrode of the fourth transistor is electrically connected to the fourth voltage signal line, and the second electrode of the fourth transistor is electrically connected to the second The connection point is electrically connected; or, The fourth subcircuit includes at least two fourth transistors, which are connected in series; the gate of each fourth transistor is electrically connected to the second electrode, the first electrode of the first fourth transistor of the at least two fourth transistors is electrically connected to the fourth voltage signal line, and the second electrode of the last fourth transistor is electrically connected to the second connection point.

9. An array substrate, comprising a plurality of pixel circuits as described in any one of claims 1 to 8; The array substrate comprises a stacked substrate, a semiconductor layer, a first gate layer, a second gate layer, a first source-drain metal layer, a second source-drain metal layer, and a binding layer; the setting voltage signal line is located in the first source-drain metal layer or the second source-drain metal layer; The pixel driving circuit is located in the semiconductor layer, the first gate layer, the second gate layer, and the first source and drain metal layer; The binding unit is located in the binding layer; in the area where at least one pixel circuit is located, the binding layer includes a first binding pattern group and at least one second binding pattern group, the first binding pattern group includes a first binding pattern and a second binding pattern, and the second binding pattern group includes a third binding pattern and a fourth binding pattern; The first binding pattern group serves as the first binding terminal group, and the second binding pattern group serves as the second binding terminal group; The first binding pattern and the third binding pattern are both electrically connected to the pixel driving circuit, and the second binding pattern and the fourth binding pattern are both electrically connected to the setting voltage signal line.

10. The array substrate according to claim 9, wherein: The second source-drain metal layer includes a first source-drain pattern group and at least one second source-drain pattern group, the first source-drain pattern group includes a first source-drain pattern and a second source-drain pattern, and the second source-drain pattern group includes a third source-drain pattern and a fourth source-drain pattern; The first source-drain pattern is electrically connected to the first binding pattern; the second source-drain pattern is electrically connected to the second binding pattern; the third source-drain pattern is electrically connected to the third binding pattern; the fourth source-drain pattern is electrically connected to the fourth binding pattern; The first source-drain pattern and the third source-drain pattern are both electrically connected to the pixel driving circuit; the third source-drain pattern and the fourth source-drain pattern are both electrically connected to the setting voltage signal line.

11. The array substrate according to claim 10, wherein: The first source-drain metal layer includes a first connection line, the first connection line is connected to the pixel driving circuit, and the first connection line is connected to the first source-drain pattern and the third source-drain pattern.

12. The array substrate according to claim 11, wherein: The first terminal and the third terminal are connected to a first connection node; The first connection line includes a connection portion located in the middle thereof, the connection portion serves as the first connection node, and the first source-drain pattern group and the second source-drain pattern group do not overlap with the connection portion.

13. The array substrate according to any one of claims 10 to 12, wherein: The pixel driving circuit includes a driving transistor, the semiconductor layer includes an active layer of the driving transistor, and the first source-drain pattern group and the second source-drain pattern group do not overlap with the active layer of the driving transistor.

14. The array substrate according to any one of claims 9 to 13, wherein: The pixel circuit further includes an electrostatic protection circuit; the electrostatic protection circuit includes a first transistor and a second transistor; The semiconductor layer includes an active layer of the first transistor and an active layer of the second transistor; a first end of the active layer of the first transistor and a second end of the active layer of the second transistor are close to and connected to each other; The first source-drain metal layer includes a first connection pattern, a second connection pattern, a third connection pattern, and a second connection line; The second end of the active layer of the first transistor is connected to the first connection pattern, and the first connection pattern is connected to the third voltage signal line; the third voltage signal line overlaps with the active layer of the first transistor; The first end of the active layer of the first transistor is connected to the second connection pattern, the second connection pattern is connected to the gate pattern of the second transistor, and the gate pattern of the second transistor overlaps with the active layer of the second transistor; The first end of the active layer of the second transistor is connected to the third connection pattern, and the third connection pattern is connected to the fourth voltage signal line; Two ends of the second connection line are respectively connected to the first connection line and the second connection pattern.

15. The array substrate according to claim 14, wherein: The plurality of pixel circuits are arranged in an array; The first gate layer includes a plurality of third voltage signal lines and a plurality of fourth voltage signal lines extending along a row direction; Each of the third voltage signal line and the fourth voltage signal line is located in an area where a row of pixel circuits is located.

16. A display panel, comprising: The array substrate according to any one of claims 9 to 15; A plurality of light emitting devices, each of which is electrically connected to the first binding terminal group or the second binding terminal group in the array substrate.

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