Shift register unit, gate drive circuit and display device

Abstract

Provided is a shift register unit, comprising: an input circuit (101) which receives a first clock signal and an input signal so as to provide the input signal to a first node under the control of the first clock signal; a first control circuit (102) electrically connected to the first node and the second node and receiving the first clock signal to control the voltage of the second node under the control of the first clock signal and the voltage of the first node; the output circuit (103) is electrically connected with the first node and the output end and is used for receiving a second clock signal so as to provide an output signal to the output end based on the second clock signal under the control of the voltage of the first node; an output voltage control circuit (104) electrically connected to the second node and the output terminal and controlling the voltage of the output signal under the control of the voltage of the second node; and a discharge circuit (105) electrically connected with the first node and the second node and configured to receive a second clock signal to discharge the first node under the control of the second clock signal and the voltage of the second node.

Description

Shift register unit, gate drive circuit and display device Technical Field

[0001] The present application relates to the technical field of electronic circuits, and more particularly, to a shift register unit, a gate driving circuit including the shift register unit, and a display device including the gate driving circuit. Background Art

[0002] Thin-film transistors (TFTs) are commonly used electronic components in various display devices. They are the primary components of both the gate driver circuits that provide gate scanning signals and the pixel circuits that drive each pixel in the display device. Currently, common TFT types include low-temperature polycrystalline (LTPC) TFTs, metal oxide thin-film transistors (MTCs), and amorphous silicon (ASi) TFTs. Each type of TFT has its own advantages and disadvantages. For example, compared to the manufacturing process for amorphous silicon (AS) TFTs, the LTPC TFT manufacturing process adds laser crystallization and ion implantation, converting the amorphous silicon thin film into polycrystalline silicon, significantly improving electron mobility. Using LTPC TFTs as driver elements can increase the brightness of liquid crystal displays (LCDs) and reduce power consumption. Furthermore, their use in organic light-emitting diode (OLED) displays can achieve higher resolution. However, the manufacturing process for displays based on LTPC TFTs is relatively complex, and due to limitations in the laser crystallization process, it is difficult to achieve large-scale displays. Currently, the circuit structure of the gate driver circuit still needs to be simplified, and there is still room for improvement in the operating performance and output signal of the gate driver circuit.

[0003] Summary of the Invention

[0004] An embodiment of the present application proposes a shift register unit, which includes: an input circuit, which is configured to receive a first clock signal and an input signal, so as to provide the input signal to a first node under the control of the first clock signal; a first control circuit, which is electrically connected to the first node and the second node, and is configured to receive the first clock signal, so as to control the voltage of the second node under the control of the first clock signal and the voltage of the first node; an output circuit, which is electrically connected to the first node and the output end, and is configured to receive a second clock signal, so as to provide an output signal to the output end based on the second clock signal under the control of the voltage of the first node; an output voltage control circuit, which is electrically connected to the second node and the output end, so as to control the voltage of the output signal under the control of the voltage of the second node; and a discharge circuit, which is electrically connected to the first node and the second node, and is configured to receive the second clock signal, so as to discharge the first node under the control of the second clock signal and the voltage of the second node.

[0005] According to some embodiments of the present application, the input circuit includes a first transistor, wherein the control terminal of the first transistor is electrically connected to the first clock signal terminal to receive the first clock signal, the first electrode of the first transistor is electrically connected to the input signal terminal to receive the input signal, and the second electrode of the first transistor is electrically connected to the first node.

[0006] According to some embodiments of the present application, the first control circuit includes a second transistor and a third transistor, the control terminal of the second transistor is electrically connected to the first clock signal terminal to receive the first clock signal, the first electrode of the second transistor is electrically connected to the first reference voltage terminal, the second electrode of the second transistor is electrically connected to the second node, the control terminal of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first clock signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0007] According to some embodiments of the present application, the output circuit includes a fourth transistor, the control end of the fourth transistor is electrically connected to the first node, the first pole of the fourth transistor is electrically connected to the second clock signal end to receive the second clock signal, and the second pole of the fourth transistor is electrically connected to the output end.

[0008] According to some embodiments of the present application, the output voltage control circuit includes a fifth transistor, the control terminal of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second reference voltage terminal, and the second electrode of the fifth transistor is electrically connected to the output terminal.

[0009] According to some embodiments of the present application, the discharge circuit includes a sixth transistor and a seventh transistor, wherein the sixth transistor and the seventh transistor are connected in series between the first node and the third reference voltage terminal, the control terminal of the sixth transistor is electrically connected to the second clock signal terminal to receive the second clock signal, and the control terminal of the seventh transistor is electrically connected to the second node.

[0010] According to some embodiments of the present application, the shift register unit further includes a node voltage limiting circuit, which is electrically connected to the first node and the signal input terminal of the output circuit, and the node voltage limiting circuit is configured to limit the amplitude of the voltage of the first node.

[0011] According to some embodiments of the present application, the output circuit includes a fourth transistor, the control terminal of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the second clock signal terminal to receive the second clock signal, the second electrode of the fourth transistor is electrically connected to the output terminal, and the node voltage limiting circuit includes an eighth transistor, the first electrode and the second electrode of the eighth transistor are respectively electrically connected to the first node and the control terminal of the fourth transistor, and the control terminal of the eighth transistor is configured to receive a fourth reference voltage so that the eighth transistor is in an on state.

[0012] According to some embodiments of the present application, the output circuit includes a fourth transistor, the control terminal of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the second clock signal terminal to receive the second clock signal, the second electrode of the fourth transistor is electrically connected to the output terminal, and the node voltage limiting circuit includes a ninth transistor, the first electrode and the control terminal of the ninth transistor are respectively electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the fifth reference voltage terminal to receive the fifth reference voltage.

[0013] According to some embodiments of the present application, the output voltage control circuit further includes a first capacitor electrically connected between the first electrode of the fifth transistor and the control terminal of the fifth transistor.

[0014] According to some embodiments of the present application, the output circuit further includes a second capacitor electrically connected between the output terminal and the control terminal of the fourth transistor.

[0015] According to some embodiments of the present application, the output voltage control circuit also includes a tenth transistor, the first electrode and the second electrode of the tenth transistor are respectively connected to the first node and the control end of the fifth transistor, and the control end of the tenth transistor is configured to receive a sixth reference voltage so that the tenth transistor is in an on state.

[0016] According to some embodiments of the present application, a width-to-length ratio of a channel of the fourth transistor is greater than a width-to-length ratio of a channel of the eighth transistor.

[0017] Another embodiment of the present application provides a gate driving circuit, which includes a plurality of cascaded shift register units as described in any one of the aforementioned embodiments.

[0018] Yet another embodiment of the present application provides a display device, which includes the gate driving circuit described in the above embodiment.

[0019] These and other advantages of the application will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Embodiments of the present application will now be described in more detail and with reference to the accompanying drawings, in which:

[0021] FIG1 is a schematic diagram illustrating a circuit module in a shift register unit according to an embodiment of the present application;

[0022] FIG2 illustrates a schematic diagram of a circuit principle of a shift register unit according to an embodiment of the present application;

[0023] FIG3 illustrates a signal timing diagram for the shift register unit shown in FIG2 ;

[0024] FIG4 illustrates a schematic diagram of a circuit module in a shift register unit according to another embodiment of the present application;

[0025] FIG5 illustrates a schematic diagram of a circuit principle of a shift register unit according to another embodiment of the present application;

[0026] FIG6 illustrates a schematic diagram of a circuit principle of a shift register unit according to another embodiment of the present application;

[0027] FIG7 illustrates a schematic circuit diagram of a shift register unit according to another embodiment of the present application;

[0028] FIG8 illustrates a schematic circuit diagram of a shift register unit according to another embodiment of the present application;

[0029] FIG9 illustrates a schematic circuit diagram of a shift register unit according to another embodiment of the present application;

[0030] FIG10 is a diagram illustrating the time it takes for the level of the output signal of the shift register unit shown in FIG5 or FIG6 to change;

[0031] FIG11 illustrates a schematic circuit diagram of a shift register unit according to yet another embodiment of the present application;

[0032] FIG12 shows voltage waveforms of relevant nodes and waveforms of output signals of the shift register unit of the embodiment shown in FIG9 during operation;

[0033] FIG13 shows voltage waveforms of relevant nodes and waveforms of output signals of the shift register unit of the embodiment shown in FIG11 during operation;

[0034] FIG14 illustrates a plurality of cascaded shift register units in a gate driving circuit according to another embodiment of the present application;

[0035] FIG15 illustrates an example of the layout of the bottom gates of the respective transistors in the shift register unit shown in FIG9 ;

[0036] FIG16 illustrates a partial top view of a shift register unit obtained after a semiconductor layer, a top gate, and a signal connection layer are formed on each bottom gate shown in FIG15 ;

[0037] FIG17 illustrates an example of the layout of the bottom gates of the respective transistors in the shift register unit shown in FIG11 ;

[0038] FIG18 illustrates a partial top view of a shift register unit obtained after a semiconductor layer, a top gate, and a signal connection layer are formed on each bottom gate shown in FIG17 . DETAILED DESCRIPTION

[0039] The following description provides specific details of various embodiments of the present application so that those skilled in the art can fully understand and implement the various embodiments of the present application. In some cases, this application does not illustrate or describe in detail some structures or functions well known in the art to avoid these unnecessary descriptions from obscuring the description of the embodiments of the present application. The technical solutions of the present application can be embodied in many different forms and purposes and should not be limited to the embodiments set forth herein. These embodiments are provided to make the technical solutions of the present application clear and complete, but the embodiments do not limit the scope of protection of this patent application.

[0040] Here, some of the terms involved in the embodiments of the present application are first explained to facilitate understanding by those skilled in the art.

[0041] The “control terminal” mentioned herein refers to the gate of the transistor for receiving the scanning signal. The transistor can be in the on state or the off state under the control of the signal received at its control terminal. The “first pole” mentioned herein refers to one of the two terminals of the transistor except the control terminal, and the “second pole” refers to the other of the two terminals of the transistor except the control terminal. That is, the first pole can be one of the source and drain of the transistor, and the second pole can be the other of the source and drain of the transistor. The “display device” mentioned herein can be an assembled display product with an image display function, or it can be a part of a complete display product, but this part of the component includes the gate drive circuit described in the embodiment of the present application.

[0042] Figure 1 schematically illustrates an exemplary topological structure of a shift register unit according to an embodiment of the present application. As shown in Figure 1 , the shift register unit includes an input circuit 101 , a first control circuit 102 , an output circuit 103 , an output signal control circuit 104 , and a discharge circuit 105 . The input circuit 101 is configured to receive a first clock signal CK1 and an input signal IN, so as to provide the input signal IN to the first node N1 under the control of the first clock signal CK1; the first control circuit 102 is electrically connected to the first node N1 and the second node N2, and is configured to receive the first clock signal CK1, so as to control the voltage of the second node N2 under the control of the first clock signal CK1 and the voltage of the first node N1; the output circuit 103 is electrically connected to the first node N1 and the output end of the shift register unit, and is configured to receive the second clock signal CK2, so as to provide the output signal OUT to the output end based on the second clock signal CK2 under the control of the voltage of the first node N1; the output signal control circuit 104 is electrically connected to the second node N2 and the output end, so as to control the voltage of the output end under the control of the voltage of the second node N2; the discharge circuit 105 is electrically connected to the first node N1 and the second node N2, and is configured to receive the second clock signal CK2, so as to discharge the first node N1 under the control of the second clock signal CK2 and the voltage of the second node N2.

[0043] The shift register unit shown in Figure 1 can receive an input signal IN, a first clock signal CK1 and a second clock signal CK2, and output an output signal OUT with a desired pulse level at the output terminal. The input signal IN can be provided periodically, and accordingly, the output signal OUT with a desired pulse level can be output periodically from the output terminal. In each cycle, the discharge circuit 105 can perform a discharge operation on the first node N1 after outputting the output signal OUT with a desired pulse level at the output terminal and before the next cycle arrives, so as to clear the charge accumulated on the first node and improve the accuracy of controlling the output circuit 103 in the next cycle. The various circuit modules in the shift register unit shown in Figure 1 can be implemented based on metal oxide thin film transistors, and the circuit structure is simple. It can be applied to the gate drive circuit of an organic light emitting diode display device to provide a scanning drive signal for the drive element in the pixel circuit of the organic light emitting diode display device.

[0044] The following further describes an embodiment of the shift register unit through a specific example. FIG2 shows an example of a circuit schematic diagram of the shift register unit. As shown in FIG2 , the input circuit may include a first transistor T1, the control terminal of the first transistor being electrically connected to the first clock signal input terminal to receive the first clock signal CK1, the first electrode of the first transistor T1 being electrically connected to the input signal terminal to receive the input signal IN, and the second electrode of the first transistor T1 being electrically connected to the first node N1. Thus, the first transistor T1 can provide the input signal IN to the first node N1 under the control of the first clock signal CK1. The first control circuit may include a second transistor T2 and a third transistor T3, the control terminal of the second transistor T2 being electrically connected to the first clock signal terminal to receive the first clock signal CK1, the first electrode of the second transistor T2 being electrically connected to the first reference voltage terminal to receive the first reference voltage V1, the second electrode of the second transistor T2 being electrically connected to the second node N2, the control terminal of the third transistor T3 being electrically connected to the first node N1, the first electrode of the third transistor T3 being electrically connected to the first clock signal terminal to receive the first clock signal CK1, and the second electrode of the third transistor T3 being electrically connected to the second node N2. The output circuit includes a fourth transistor T4, the control terminal of which is electrically connected to the first node N1, the first electrode of which is electrically connected to the second clock signal terminal to receive the second clock signal CK2, and the second electrode of which is electrically connected to the output terminal. Thus, under the control of the first node N1, the fourth transistor T4 can output the output signal OUT from the output terminal according to the change of the second clock signal CK2. The output voltage control circuit includes a fifth transistor T5, the control terminal of which is electrically connected to the second node N2, the first electrode of which is electrically connected to the second reference voltage terminal to receive the second reference voltage V2, and the second electrode of which is electrically connected to the output terminal. Therefore, the output voltage control circuit can control the voltage at the output terminal through the fifth transistor so that the output terminal generates a desired pulse signal. The discharge circuit 105 includes a sixth transistor T6 and a seventh transistor T7. As shown in Figure 2, the sixth transistor T6 and the seventh transistor T7 are connected in series between the first node N2 and the third reference voltage terminal. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal to receive the second clock signal CK2, and the control terminal of the seventh transistor is electrically connected to the second node N2. A first electrode of the seventh transistor T7 is electrically connected to the third reference voltage terminal to receive the third reference voltage, a second electrode of the seventh transistor T7 is electrically connected to the first electrode of the sixth transistor T6, and a second electrode of the sixth transistor T6 is electrically connected to the first node N1. Thus, the sixth transistor T6 and the seventh transistor T7 in the discharge circuit can discharge the first node N1 under the control of the second clock signal CK2 and the voltage of the second node N2.

[0045] Next, the operating principle of the shift register unit shown in FIG2 is described in detail using specific examples. FIG3 shows examples of input signals, a first clock signal, and a second clock signal provided to the shift register unit shown in FIG2 , as well as examples of output signals, a voltage at a first node, and a voltage at a second node at an output terminal of the shift register unit. It should be understood that the waveform diagram shown in FIG3 is only used to illustrate the operating principle of the shift register unit shown in FIG2 , and does not represent the actual waveform of the shift register unit shown in FIG2 during operation.

[0046] As shown in Figure 3, the operating cycle of the shift register unit shown in Figure 2 may include four time periods P1 to P4. In this example, the transistors (the first to seventh transistors) in each circuit module shown in Figure 2 are all N-type transistors, the first reference voltage V1 is a high-level signal, and the second reference voltage V2 and the third reference voltage V3 are both low-level signals. During the first time period P1, the input signal IN and the first clock signal CK1 change from a low level to a high level, and the second clock signal CK2 changes from a high level to a low level. Accordingly, the first transistor T1 and the second transistor T2 are turned on, and the voltages at the first node N1 and the second node N2 are both high. As a result, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all turned on, while the second clock signal CK2 and the second reference voltage V2 are both low. Therefore, the output signal OUT at the output terminal remains low. In addition, because the second clock signal CK2 is low, the sixth transistor T6 is turned off, and the voltage at the first node N1 is not affected by the third reference voltage V3. During the second period P2, the input signal IN and the first clock signal CK1 change from a high level to a low level, while the second clock signal CK2 changes from a low level to a high level. Accordingly, the first transistor T1 and the second transistor T2 are both in the off state. Due to the presence of the inter-electrode capacitance of the fourth transistor, the voltage at the first node N1 can remain high. Therefore, the third transistor T3 can remain in the on state, and the voltage at the second node N2 changes from a high level to the level of the first clock signal CK1 (i.e., a low level). This causes the fifth transistor T5 and the seventh transistor T7 to be in the off state, and the fourth transistor T4 can remain in the on state. Therefore, the output signal OUT at the output end of the shift register unit now depends only on the second clock signal CK2. As shown in Figure 3, the output signal OUT changes from a low level to a high level. In addition, since the seventh transistor is in the off state, the voltage at the first node N1 is not affected by the third reference voltage V3. During the third period P3, the input signal IN remains low, the first clock signal CK1 changes from a low level to a high level, and the second clock signal CK2 changes from a high level to a low level. Accordingly, the first transistor T1 and the second transistor T2 are both in the on state, the voltage at the first node N1 changes to a low level, and the voltage at the second node N2 changes to a high level. Therefore, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are in the off state, and the fifth transistor T5 is in the on state. The output signal OUT of the shift register unit now depends on the second reference voltage V2. Therefore, the output signal OUT remains at a low level. The voltage at the first node N1 is not affected by the third reference voltage V3. During the fourth period P4, the input signal IN remains at a low level, the first clock signal CK1 changes from a high level to a low level, and the second clock signal CK2 changes from a low level to a high level.Accordingly, the first transistor T1 and the second transistor T2 are in the off state. Due to the inter-electrode capacitance of the fifth transistor, the second node N2 maintains a high level. The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all in the on state. The first node N1 maintains the previous low level. The fourth transistor T4 and the third transistor T3 are in the off state. The first node N1 forms a path to the third reference voltage terminal via the sixth transistor T6 and the seventh transistor T7. That is, the sixth transistor T6 and the seventh transistor T7 can form a discharge path for the first node N1, so that the charge on the first node N1 is fully discharged, thereby facilitating accurate control of the on and off of the fourth transistor T4 in the next cycle and enhancing the accuracy of the pulse waveform of the obtained output signal. Thus, in a single cycle including the above-mentioned four periods P1 to P4, the shift register unit generates a high-level pulse output signal OUT from its output terminal, as shown in FIG3 . In the embodiment of FIG. 2 , in order to enhance the stability of the second node voltage N2 , the shift register unit further includes a first capacitor C1 electrically connected between the first electrode of the fifth transistor T5 and the second node N2 .

[0047] FIG4 shows a block diagram of a structure of a shift register unit provided according to another embodiment of the present application. In addition to the various circuit modules in the shift register unit shown in FIG1 , the shift register unit shown in FIG4 further includes a node voltage limiting circuit 106, which is electrically connected to the first node N1 and the signal input terminal of the output circuit 103, and the node voltage limiting circuit 106 is configured to limit the amplitude of the voltage of the first node N1. In this embodiment, the node voltage limiting circuit 106 can reduce or avoid the impact of voltage fluctuations (for example, voltage surges) that may occur in the output circuit 103 on the voltage of the first node N1, promote the stability of the voltage of the first node N1, thereby helping to protect the transistor electrically connected to the first node N1, delay the aging of the transistor electrically connected to the first node N1, or reduce the threshold voltage drift of the relevant transistor.

[0048] FIG5 shows a circuit schematic diagram of a shift register unit according to another embodiment of the present application. As shown in FIG5 , the node voltage limiting circuit 106 of the shift register unit includes an eighth transistor T8, and the output circuit includes a fourth transistor T4. The first electrode and the second electrode of the eighth transistor T8 are electrically connected to the first node N1 and the control terminal of the fourth transistor T4, respectively, and the control terminal of the eighth transistor T8 is configured to receive a fourth reference voltage V4 so that the eighth transistor T8 is in a conductive state. The first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal to receive the second clock signal CK2, and the second electrode of the fourth transistor T4 is electrically connected to the output terminal of the shift register unit. For the shift register unit shown in FIG5 , when the shift register unit is in an operating state, the eighth transistor T8 is always in a conductive state. When the eighth transistor T8 is an N-type transistor, the fourth reference voltage V4 is a constant high-level signal.

[0049] Referring back to the embodiment shown in FIG2 , due to the influence of the inter-electrode capacitance of the fourth transistor T4, when the voltage level of the output signal OUT of the shift register unit suddenly increases, the potential of the first node N1 also suddenly increases. This can be detrimental to the third transistor T3, the sixth transistor T6, and the first transistor T1 electrically connected to the first node N1. In particular, the excessively high voltage at the first node N1 may cause the threshold value of the third transistor T3 to shift. In the embodiment of FIG5 , the eighth transistor T8, which is in the on state, can act as a buffer for the voltage of the first node N1. Even if the voltage amplitude of the output signal OUT of the shift register unit suddenly increases, the amplitude of the voltage of the first node N1 is limited, thereby reducing the impact of the output signal of the output circuit on the voltage of the first node N1. Therefore, the first transistor T1, the third transistor T3, and the sixth transistor T6 electrically connected to the first node N1 are protected from the adverse effects of the sudden high voltage.

[0050] FIG6 shows a circuit schematic diagram of a shift register unit according to another embodiment of the present application. As shown in FIG6 , the node voltage limiting circuit 106 in the shift register unit includes a ninth transistor T9. The first electrode and control terminal of the ninth transistor T9 are electrically connected to the first node N1, respectively. The second electrode of the ninth transistor T9 is electrically connected to a fifth reference voltage terminal to receive a fifth reference voltage V5. In this embodiment, when the voltage of the first node N1 suddenly increases due to the output signal of the shift register unit, for example, when the voltage of the first node N1 exceeds the threshold voltage of the ninth transistor T9, the ninth transistor T9 will turn on, thereby pulling the voltage of the first node N1 down to the fifth reference voltage V5. The fifth reference voltage V5 can be a voltage with a constant amplitude, and the amplitude of the fifth reference voltage V5 can be set to be close to the amplitude of the high-level pulse of the input signal IN. Therefore, the node voltage limiting circuit 106 in the embodiment shown in FIG6 can also function to appropriately limit the amplitude of the voltage of the first node N1.

[0051] According to some embodiments of the present application, the output voltage control circuit 104 of the shift register unit further includes a first capacitor C1 electrically connected between the first electrode of the fifth transistor T5 and the control terminal of the fifth transistor T5. As shown in Figures 2, 5, and 6, the first capacitor C1 is connected between the control terminal and the first electrode of the fifth transistor T5, thereby enhancing the stability of the voltage at the first node N2 and facilitating rapid control of the fifth transistor T5.

[0052] As shown in FIG7 , according to another embodiment of the present application, the output circuit of the shift register unit further includes a second capacitor C2 electrically connected between the output terminal of the shift register unit and the control terminal of the fourth transistor T4. The embodiment shown in FIG7 is advantageous for applying the shift register unit to a high-resolution display device because the second capacitor C2 can increase the conduction rate of the fourth transistor T4 in the output circuit, or in other words, can reduce the switching time between the off state and the on state of the fourth transistor T4, thereby enabling the shift register unit to generate a larger output current.

[0053] FIG8 illustrates a circuit schematic diagram of a shift register unit provided according to another embodiment of the present application. Similar to the embodiment shown in FIG7 , in this embodiment, the output circuit of the shift register unit includes a second capacitor C2 connected between the control terminal of the fourth transistor T4 and the output terminal of the shift register unit. At the same time, the shift register unit also includes a node voltage limiting circuit 106, and the fourth transistor T4, the second capacitor C2 and the eighth transistor T8 in the node voltage limiting circuit 106 are electrically connected to the third node N3. In this way, it is beneficial to quickly turn on the fourth transistor T4 in the output circuit, and at the same time, the influence of voltage fluctuations (for example, voltage surges) that may occur in the output circuit 103 on the voltage of the first node N1 is reduced due to the node voltage limiting circuit 106, thereby promoting the stability of the voltage of the first node N1, thereby facilitating the protection of the transistor device electrically connected to the first node N1.

[0054] According to another embodiment of the present application, the output voltage control circuit of the shift register unit further includes a tenth transistor, wherein the first and second electrodes of the tenth transistor are connected to the second node and the control terminal of the fifth transistor, respectively. The control terminal of the tenth transistor is configured to receive a sixth reference voltage to turn the tenth transistor on. FIG9 shows a circuit schematic diagram of the shift register unit according to this embodiment. In the embodiment of FIG9 , the tenth transistor T10 is an N-type metal oxide transistor, and the sixth reference voltage V6 can be a high-level signal with a constant voltage. The tenth transistor T10, the first capacitor C1, and the fifth transistor T5 are collectively connected to the fourth node N4. The tenth transistor T10 can act as a buffer between the second node N2 and the fourth node N4, mitigating or preventing the adverse effects of a sudden voltage change on the voltage of the other node due to a sudden change in the voltage of one of the second node N2 and the fourth node N4. In addition, experimental research has found that the provision of the tenth transistor T10 helps reduce the time it takes for the output signal OUT of the shift register unit to change between different levels. FIG10 schematically illustrates the waveform changes of the output signal OUT of the shift register unit. FIG10 illustrates the time it takes for the level of the output signal of the shift register unit shown in FIG5 or FIG6 to change. As shown in FIG10 , during the actual operation of the shift register unit, the output signal OUT at its output end may not be a regular square wave pulse as shown in FIG3 , but an output signal similar to a trapezoidal pulse as shown in FIG10 . That is, the output signal OUT needs to take a certain amount of time to change from a low level to a high level, and from a high level to a low level. As shown in FIG10 , Ta represents the time it takes for the output signal OUT to change from a low level to a high level, and Tb represents the time it takes for the output signal OUT to change from a high level to a low level. The shorter the time Ta and Tb, the higher the quality of the output signal OUT of the shift register unit. Compared with the shift register unit shown in FIG2 , the shift register unit shown in FIG9 can reduce the time Ta for the output signal OUT to change from a low level to a high level and the time Tb for the output signal OUT to change from a high level to a low level shown in FIG10 by providing the tenth transistor T10 in the output voltage control circuit, thereby improving the quality of the output signal of the shift register unit.

[0055] Figure 11 shows a circuit schematic diagram of a shift register unit provided according to another embodiment of the present application. In this embodiment, the shift register unit includes a node voltage limiting circuit, which includes a ninth transistor T9. The first electrode and control terminal of the ninth transistor T9 are electrically connected to the first node N1, respectively. The second electrode of the ninth transistor T9 is electrically connected to the fifth reference voltage terminal to receive the fifth reference voltage V5. In addition, the output voltage control circuit includes a fifth transistor T5, a tenth transistor T10, and a first capacitor C1. The first electrode and second electrode of the tenth transistor T10 are respectively connected to the second node N2 and the control terminal of the fifth transistor. The control terminal of the tenth transistor T10 receives the sixth reference voltage V6 to keep the tenth transistor T10 in a conductive state. In this embodiment, when the voltage of the first node N1 suddenly increases, the ninth transistor T9 can appropriately limit the voltage amplitude of the first node N1. For example, if the voltage of the first node N1 exceeds the threshold voltage of the ninth transistor T9, the ninth transistor T9 will turn on, thereby pulling the voltage of the first node N1 down to the fifth reference voltage V5. The fifth reference voltage V5 may be a voltage having a constant amplitude, and the amplitude of the fifth reference voltage V5 may be set to be close to the amplitude of the high-level pulse of the input signal IN. Meanwhile, by providing the tenth transistor T10 in the output voltage control circuit, the quality of the output signal of the shift register unit may be improved.

[0056] Next, the differences between the relevant nodes and output signals in the shift register unit described in the different embodiments described above are schematically illustrated with reference to Figures 12 and 13. Figure 12 shows the voltage waveforms of the relevant nodes and the waveforms of the output signals of the shift register unit of the embodiment shown in Figure 9 during operation. Figure 13 shows the voltage waveforms of the relevant nodes and the waveforms of the output signals of the shift register unit of the embodiment shown in Figure 11 during operation. As shown in Figure 12, the input signal, the first clock signal, and the second clock signal provided to the shift register unit are labeled IN, CK1, and CK2, respectively. The waveforms corresponding to SN1 and SN2 in Figure 12 represent the waveforms of the voltages of the first node N1 and the second node N2 in Figure 9, respectively. As can be seen from Figure 12, during the time period corresponding to the high-level pulse of the output signal OUT, the voltage SN1 of the first node N1 experiences a significant sudden increase. This may be due to the impact of the output signal OUT changing from a low level to a high level on the voltage of the first node N1. This sudden increase in the voltage SN1 of the first node N1 may be detrimental to the operating life of the third transistor T3, the sixth transistor T6, and the first transistor T1, and may even cause a shift in the threshold voltage of the third transistor T3. As shown in FIG13 , for the shift register unit shown in FIG11 , due to the presence of the node voltage limiting circuit (ninth transistor T9), the voltage SN1 of the first node N1 remains substantially stable even during the high pulse level of the output signal OUT, and does not experience the voltage surge phenomenon shown in FIG12 . Furthermore, as can be seen from FIG12 and FIG13 , the time it takes for the output signal OUT to switch between the high level and the low level is relatively short, that is, the rising and falling edges of the high-level pulse of the output signal OUT both exhibit a nearly right-angled change trend, and the output signal OUT has a high-quality pulse waveform, which is primarily attributed to the tenth transistor T10 in the output voltage control circuit of the shift register unit.

[0057] The shift register units described in the above embodiments can be applied to display devices, and the output signals generated by the shift register units can be used as scanning signals for pixel circuits in the display devices. Therefore, another embodiment of the present application provides a gate drive circuit, which includes multiple shift register units as described in any of the above embodiments, connected in cascade. The cascade mentioned here refers to multiple shift register units connected in series, and the output signal of the previous shift register unit serves as the input signal of the next shift register unit. Figure 14 schematically shows four cascaded shift register units. Each shift register unit includes an input signal terminal for receiving an input signal IN, an output signal terminal for providing an output signal OUT, a first clock signal input terminal for receiving a first clock signal CK1, and a second clock signal input terminal for receiving a second clock signal CK2. For the sake of simplicity, the reference voltage terminals of the shift register units for receiving various reference voltages are not shown in Figure 14. The first clock signal input terminal and the second clock signal input terminal of each shift register unit can be electrically connected to a first clock signal line CL1 and a second clock signal line CL2, respectively. Although FIG14 shows four cascaded shift register units, the gate drive circuit for a display device may include any number of shift register units, and the embodiments of the present application do not impose any limitation thereto. In addition, although each circuit module in the example circuit diagram of the shift register unit of the present application is implemented with N-type transistors, this does not constitute a limitation on the scope of protection of the present application. Based on the embodiments disclosed in the present application, circuit modules implemented with P-type transistors are obvious variations of the embodiments disclosed in the present application and also fall within the scope of protection of the present patent application.

[0058] Another embodiment of the present application provides a display device, which may include the gate drive circuit described in the above embodiment. As previously discussed herein, the "display device" referred to herein may be a fully assembled display product with image display functionality, or a component within a complete display product. For example, an example display device may include an array substrate for a gate drive circuit, a display panel, and a finished display device shipped for sale.

[0059] In some embodiments, each transistor in the shift register unit described above with reference to the various figures (e.g., the first to tenth transistors) may include a dual-gate transistor, that is, each transistor may include a bottom gate, a top gate, and a semiconductor layer or active layer located between the bottom gate and the top gate. In this way, the performance of the transistor can be adjusted by controlling the voltage applied to the bottom gate, and the transistor is in an on or off state in response to different signals received by its top gate. Figure 15 illustrates an example of the layout of the bottom gates of each transistor in the shift register unit shown in Figure 9. Referring to Figures 9 and 15, the fourth transistor T4 and the fifth transistor T5 include bottom gates GB4 and GB5, respectively, and the bottom gate GB4 of the fourth transistor T4 and the bottom gate GB5 of the fifth transistor T5 are connected to each other. As can be seen from Figure 15, the bottom gate GB4 of the fourth transistor T4 and the bottom gate GB5 of the fifth transistor T5 each include a plurality of elongated electrodes connected to each other, which is conducive to achieving a larger width-to-length ratio for the channels of the fourth transistor T4 and the fifth transistor T5. The bottom gate GB1 of the first transistor T1, the bottom gate GB2 of the second transistor T2, and the bottom gate GB3 of the third transistor T3 are interconnected, and the bottom gate GB6 of the sixth transistor T6, the bottom gate GB7 of the seventh transistor T7, and the bottom gate GB10 of the tenth transistor T10 are interconnected. The lengths of the bottom gates of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are significantly shorter than the bottom gates of the fourth transistor T4 and the fifth transistor T5. The bottom gates of the above-mentioned transistors can be formed on a substrate, which can support the structures required for the normal operation of the various devices of the shift register unit. In some embodiments, after the bottom gates of the various transistors are formed on the substrate, a semiconductor layer (active layer) for each transistor, a top gate for each transistor located on the semiconductor layer, and a signal connection layer on the top gate can be formed on the bottom gate.

[0060] Figure 16 illustrates a partial top view of a shift register cell obtained after forming a semiconductor layer, a top gate, and a signal connection layer on the bottom gates shown in Figure 15. Referring to Figures 9 and 16, the top gates of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are labeled GT1, GT2, GT3, GT4, GT5, GT6, GT7, and GT10, respectively. Figure 16 also shows clock signal lines CKA and CKB for transmitting the first and second clock signals, a reference signal line VGH receiving a constant high voltage, and a reference signal line VGL receiving a constant low voltage. In some embodiments, the reference signal line VGH can transmit the first reference voltage V1 and the sixth reference voltage V6 shown in Figure 9, and the reference signal line VGL can transmit the second reference voltage V2 and the third reference voltage V3 shown in Figure 9. Additional metal electrodes may be formed on the substrate, and the additional metal electrodes may be paired with the top gates of the fourth transistor T4 and the fifth transistor T5, respectively, to form the first capacitor C1 and the second capacitor C2 shown in FIG9 . As can be seen from FIG15 and FIG16 , for each transistor in the shift register unit, the width-to-length ratio of the channel of either the fourth transistor or the fifth transistor is greater than the width-to-length ratio of the channels of the remaining transistors in the shift register unit, thereby enabling the fourth transistor and the fifth transistor to have a higher switching speed, which is beneficial for improving the quality of the output signal of the shift register unit.

[0061] FIG17 illustrates an example of the layout of the bottom gates of the various transistors in the shift register unit shown in FIG11. Referring to FIG11 and FIG17, the fourth transistor T4 and the fifth transistor T5 include bottom gates GB4 and GB5, respectively. The bottom gate GB4 of the fourth transistor T4 and the bottom gate GB5 of the fifth transistor T5 are connected to each other. The bottom gate GB1 of the first transistor T1, the bottom gate GB2 of the second transistor T2, the bottom gate GB3 of the third transistor T3, and the bottom gate GB9 of the ninth transistor are connected to each other. The bottom gate GB6 of the sixth transistor T6, the bottom gate GB7 of the seventh transistor T7, and the bottom gate GB10 of the tenth transistor T10 are connected to each other. The lengths of the bottom gates of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are significantly shorter than the bottom gates of the fourth transistor T4 and the fifth transistor T5.

[0062] Figure 18 illustrates a partial top view of a shift register cell obtained after forming a semiconductor layer, a top gate, and a signal connection layer on the bottom gates shown in Figure 17. Referring to Figures 11 and 18, the top gates of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are labeled GT1, GT2, GT3, GT4, GT5, GT6, GT7, GT9, and GT10, respectively. Figure 18 also shows clock signal lines CKA and CKB for transmitting the first and second clock signals, a reference signal line VGH receiving a constant high voltage, and a reference signal line VGL receiving a constant low voltage. In some embodiments, the reference signal line VGH can transmit the first reference voltage V1, the fifth reference voltage V5, and the sixth reference voltage V6 shown in Figure 11, and the reference signal line VGL can transmit the second reference voltage V2 and the third reference voltage V3 shown in Figure 11. It can be seen from Figures 17 and 18 that for each transistor in the shift register unit, the width-to-length ratio of the channel of any one of the fourth transistor and the fifth transistor is greater than the width-to-length ratio of the channel of the remaining transistors of the shift register unit, so that the fourth transistor and the fifth transistor have a higher switching speed, which is beneficial to improving the quality of the output signal of the shift register unit.

[0063] It will be understood that although the terms first, second, third, etc. may be used herein to describe various devices, elements, components or parts, these devices, elements, components or parts should not be limited by these terms, and only represent the distinction in terms of name. For example, the aforementioned first to seventh sub-package structures are only used to distinguish the names of the sub-package structures in different embodiments of the power amplifier device. In addition, the "electrical connection" mentioned herein includes "direct connection" or "indirect connection". Although the technical solutions of the present application have been described in conjunction with some embodiments, the scope of protection of the present application is not limited to the specific forms set forth herein, and the scope of the present application is defined by the appended claims.

Claims

1. A shift register unit, characterized in that: The shift register unit comprises: an input circuit configured to receive a first clock signal and an input signal to provide the input signal to a first node under control of the first clock signal; a first control circuit electrically connected to the first node and the second node and configured to receive the first clock signal to control the voltage of the second node under the control of the first clock signal and the voltage of the first node; an output circuit electrically connected to the first node and an output terminal and configured to receive a second clock signal to provide an output signal to the output terminal based on the second clock signal under the control of the voltage of the first node; an output voltage control circuit electrically connected to the second node and the output terminal to control the voltage of the output signal under the control of the voltage of the second node; and A discharge circuit is electrically connected to the first node and the second node and is configured to receive the second clock signal to discharge the first node under the control of the second clock signal and the voltage of the second node.

2. The shift register unit according to claim 1, characterized in that: The input circuit includes a first transistor, a control terminal of the first transistor is electrically connected to a first clock signal terminal to receive the first clock signal, a first electrode of the first transistor is electrically connected to an input signal terminal to receive the input signal, and a second electrode of the first transistor is electrically connected to the first node.

3. The shift register unit according to claim 1, characterized in that: The first control circuit includes a second transistor and a third transistor, the control terminal of the second transistor is electrically connected to the first clock signal terminal to receive the first clock signal, the first electrode of the second transistor is electrically connected to the first reference voltage terminal, the second electrode of the second transistor is electrically connected to the second node, the control terminal of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first clock signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

4. The shift register unit according to claim 1, characterized in that: The output circuit includes a fourth transistor, a control terminal of the fourth transistor is electrically connected to the first node, a first electrode of the fourth transistor is electrically connected to a second clock signal terminal to receive the second clock signal, and a second electrode of the fourth transistor is electrically connected to the output terminal.

5. The shift register unit according to claim 1, characterized in that: The output voltage control circuit includes a fifth transistor, a control terminal of the fifth transistor is electrically connected to the second node, a first electrode of the fifth transistor is electrically connected to a second reference voltage terminal, and a second electrode of the fifth transistor is electrically connected to the output terminal.

6. The shift register unit according to claim 1, characterized in that: The discharge circuit includes a sixth transistor and a seventh transistor, the sixth transistor and the seventh transistor are connected in series between the first node and the third reference voltage terminal, the control terminal of the sixth transistor is electrically connected to the second clock signal terminal to receive the second clock signal, and the control terminal of the seventh transistor is electrically connected to the second node.

7. The shift register unit according to claim 1, characterized in that: The shift register unit further includes a node voltage limiting circuit electrically connected to the first node and a signal input terminal of the output circuit, wherein the node voltage limiting circuit is configured to limit the amplitude of the voltage of the first node.

8. The shift register unit according to claim 7, characterized in that: The output circuit includes a fourth transistor, a control terminal of the fourth transistor is electrically connected to the first node, a first electrode of the fourth transistor is electrically connected to a second clock signal terminal to receive the second clock signal, and a second electrode of the fourth transistor is electrically connected to the output terminal, wherein the node voltage limiting circuit includes an eighth transistor, a first electrode and a second electrode of the eighth transistor are electrically connected to the first node and the control terminal of the fourth transistor, respectively, and the control terminal of the eighth transistor is configured to receive a fourth reference voltage so that the eighth transistor is in a conducting state.

9. The shift register unit according to claim 7, characterized in that: The output circuit includes a fourth transistor, a control terminal of the fourth transistor is electrically connected to the first node, a first electrode of the fourth transistor is electrically connected to a second clock signal terminal to receive the second clock signal, and a second electrode of the fourth transistor is electrically connected to the output terminal, wherein the node voltage limiting circuit includes a ninth transistor, a first electrode and a control terminal of the ninth transistor are electrically connected to the first node respectively, and a second electrode of the ninth transistor is electrically connected to a fifth reference voltage terminal to receive the fifth reference voltage.

10. The shift register unit according to claim 5, characterized in that: The output voltage control circuit further includes a first capacitor electrically connected between the first electrode of the fifth transistor and the control terminal of the fifth transistor.

11. The shift register unit according to any one of claims 4, 8 or 9, characterized in that: The output circuit further includes a second capacitor electrically connected between the output terminal and the control terminal of the fourth transistor.

12. The shift register unit according to claim 5 or 10, characterized in that: The output voltage control circuit also includes a tenth transistor, a first electrode and a second electrode of the tenth transistor are respectively connected to the first node and the control end of the fifth transistor, and the control end of the tenth transistor is configured to receive a sixth reference voltage to put the tenth transistor in an on state. 13 . The shift register cell according to claim 8 , wherein a width-to-length ratio of a channel of the fourth transistor is greater than a width-to-length ratio of a channel of the eighth transistor.

14. A gate drive circuit, characterized in that: The gate driving circuit includes a plurality of cascaded shift register units according to any one of claims 1 to 13.

15. A display device comprising the gate driving circuit according to claim 14.

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