Two-D material gate-all-around complementary field effect transistor integration

Abstract

Disclosed is a complementary field effect transistor (CFET) formed from stacked two-dimensional (2D) material transistors. The 2D material transistor is formed from a transition metal dichalcogenide (TMD), which is an atomic scale thin semiconductor. The stacked TMD transistors allow for enhanced drive current and lower switched capacitance, both of which are desirable.

Description

Technical Field

[0001] The present disclosure relates generally to high performance devices, and more particularly, but not exclusively, to devices having 2D material gate-all-around (GAA) complementary field effect transistor (CFET) integration. Background Art

[0002] Integrated circuit technology has made great progress in advancing computing power through miniaturized components such as semiconductor transistors. The development of semiconductors has progressed from bulk substrate and planar CMOS, FinFET, nanowire or nanoribbon, FinFET 3D stacking to nanowire or nanoribbon 3D stacking. Semiconductor technology is mainly based on silicon. However, the fabrication of silicon-based transistors may be problematic when scaling down further (e.g., to a few nanometers).

[0003] Therefore, there is a need for systems, apparatuses, and methods that overcome the deficiencies of conventional devices, including the methods, systems, and apparatuses provided herein. Summary of the invention

[0004] A simplified overview of one or more aspects and / or examples associated with the apparatus and methods disclosed herein is presented below. Therefore, the following summary of the invention should not be considered as a broad overview involving all expected aspects and / or examples, nor should the following summary of the invention be considered as identifying key or important elements involving all expected aspects and / or examples or delineating the scope associated with any particular aspect and / or example. Therefore, the sole purpose of the following summary of the invention is to present certain concepts involving one or more aspects and / or examples related to the apparatus and methods disclosed herein in a simplified form before the detailed description presented below.

[0005] An exemplary complementary field effect transistor (CFET) structure is disclosed. The CFET structure may include a lower source contact and a lower drain contact in an intermetallic dielectric (IMD) layer. The CFET structure may also include a lower all-around gate (GAA) gate region, the lower GAA gate region being in the IMD layer between the lower source contact and the lower drain contact. The lower GAA gate region may be of a first conductivity type and may include one or more lower channel structures. Each lower channel structure may include a lower transition metal dichalcogenide (TMD) channel, the TMD channel being electrically coupled to the lower source contact and the lower drain contact. Each lower channel structure may also include a first lower gate oxide layer and a second lower gate oxide layer, the first lower gate oxide layer and the second lower gate oxide layer being on the lower surface and the upper surface of the lower TMD channel, respectively. The CFET structure may also include an upper source contact and an upper drain contact in the IMD layer, above the lower source contact and the lower drain contact. The CFET structure may further include an upper GAA gate region in the IMD layer, above the lower GAA gate region and between the upper source contact and the upper drain contact. The upper GAA gate region may be a second conductivity type opposite to the first conductivity type, and may include one or more upper channel structures. Each upper channel structure may include an upper TMD channel, which is electrically coupled to the upper source contact and the upper drain contact. Each upper channel structure may also include a first upper gate oxide layer and a second upper gate oxide layer, the first upper gate oxide layer and the second upper gate oxide layer being respectively on the lower surface and the upper surface of the upper TMD channel. The CFET structure may further include a common gate in the IMD layer, the common gate being located between the lower source contact and the lower drain contact, and between the upper source contact and the upper drain contact. The common gate may be configured to apply a common voltage to the lower channel structure and the upper channel structure.

[0006] A method for manufacturing a complementary field effect transistor (CFET) structure is disclosed. The method may include forming a lower source contact and a lower drain contact in an intermetallic dielectric (IMD) layer. The method may also include forming a lower all-around gate (GAA) gate region in the IMD layer, the lower GAA gate region being between the lower source contact and the lower drain contact. The lower GAA gate region may be of a first conductivity type and may include one or more lower channel structures. Each lower channel structure may include a lower transition metal dichalcogenide (TMD) channel, the TMD channel being electrically coupled to the lower source contact and the lower drain contact. Each lower channel structure may also include a first lower gate oxide layer and a second lower gate oxide layer, the first lower gate oxide layer and the second lower gate oxide layer being respectively on the lower surface and the upper surface of the lower TMD channel. The method also includes forming an upper source contact and an upper drain contact in the IMD layer, the upper source contact and the upper drain contact being above the lower source contact and the lower drain contact. The method further includes forming an upper GAA gate region in the IMD layer, the upper GAA gate region is above the lower GAA gate region and between the upper source contact and the upper drain contact. The upper GAA gate region can be a second conductivity type opposite to the first conductivity type, and can include one or more upper channel structures. Each upper channel structure can include an upper TMD channel, and the upper TMD channel is electrically coupled to the upper source contact and the upper drain contact. Each upper channel structure can also include a first upper gate oxide layer and a second upper gate oxide layer, and the first upper gate oxide layer and the second upper gate oxide layer are respectively on the upper surface and the lower surface of the upper TMD channel. The method also includes forming a common gate in the IMD layer between the lower source contact and the lower drain contact and between the upper source contact and the upper drain contact. The common gate can be configured to apply a common voltage to the lower channel structure and the upper channel structure.

[0007] Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more complete understanding of the various aspects of the present disclosure and many of its attendant advantages will be readily obtained by referring to the following detailed description when considered in conjunction with the accompanying drawings, which are intended to illustrate only and not to limit the present disclosure.

[0009] Figure 1 An example of a CFET structure according to one or more aspects of the present disclosure is illustrated.

[0010] Figure 2A Picture shows Figure 1 Detailed view of the lower GAA gate region of an example CFET structure.

[0011] Figure 2B Picture shows Figure 1 Detailed view of the upper GAA gate region of an example CFET structure.

[0012] Figure 3 An example of a CFET structure formed as NAND logic according to one or more aspects of the present disclosure is illustrated.

[0013] Figure 4 An example of a CFET structure formed into NOR logic according to one or more aspects of the present disclosure is illustrated.

[0014] Figure 5 Another example of a CFET structure according to one or more aspects of the present disclosure is illustrated.

[0015] Fig. 6A Picture shows Figure 5 Detailed view of the lower GAA gate region of an example CFET structure.

[0016] Figure 6B Picture shows Figure 5 Detailed view of the upper GAA gate region of an example CFET structure.

[0017] Figure 7 An example of a CFET structure formed as NAND logic according to one or more aspects of the present disclosure is illustrated.

[0018] Figure 8 An example of a CFET structure formed into NOR logic according to one or more aspects of the present disclosure is illustrated.

[0019] FIG. 9A to FIG. 9J An example of stages in fabricating a CFET according to one or more aspects of the present disclosure is illustrated.

[0020] FIG. 10A to FIG. 10J Other examples of stages in fabricating a CFET according to one or more aspects of the present disclosure are illustrated.

[0021] Figures 11 to 15 A flow chart of an example method of fabricating a CFET according to one or more aspects of the present disclosure is illustrated.

[0022] Fig.16 Various electronic devices are illustrated that may utilize one or more aspects of the present disclosure.

[0023] Based on the drawings and detailed description, other purposes and advantages associated with the various aspects disclosed herein will be apparent to those skilled in the art. According to convention, the features depicted by the drawings may not be drawn to scale. Therefore, for the sake of clarity, the size of the depicted features may be arbitrarily enlarged or reduced. According to convention, some drawings are simplified for the sake of clarity. Therefore, the drawings may not depict all components of a particular device or method. In addition, throughout the entire specification and drawings, the same reference numerals represent the same features. DETAILED DESCRIPTION

[0024] Various aspects of the present disclosure are illustrated in the following description and related drawings for specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of the teachings herein. Additionally, known elements of the illustrative embodiments herein may not be described in detail or may be omitted to avoid obscuring the relevant details of the teachings in the present disclosure.

[0025] In some of the described example implementations, instances are identified in which portions of various component structures and operations can be obtained from known conventional techniques and then arranged according to one or more exemplary embodiments. In such instances, internal details of portions of known conventional component structures and / or operations may be omitted to help avoid potentially obscuring the concepts illustrated in the illustrative embodiments disclosed herein.

[0026] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises", "comprising", "includes", and / or "including" when used herein specify the presence of the features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] As indicated above, transistor scaling beyond FinFETs and nanowires (e.g., down to single-digit nanometers) is challenging. In this regard, it is proposed to use two-dimensional (2D) materials for transistor fabrication to fabricate transistors. 2D materials may also be referred to as transition metal dichalcogenides (TMDs) having MX2 as a general molecular formula. Here, 'M' represents a transition metal (e.g., titanium (Ti), molybdenum (Mo), tungsten (W), etc.), and 'X' represents an oxychalcogenide (e.g., sulfur (S), selenium (Se), tellurium (Te), etc.). Thus, examples of TMDs include molybdenum disulfide (MoS2), tungsten disulfide (WS2), and tungsten diselenide (WSe2). Note that there may be more than 1500 different MX2 TMD combinations.

[0028] In one or more aspects, it is proposed to stack 2D TMDs to obtain a 3D transistor configuration. The technical advantages of 2D stacked TMDs as transistors include better drive current and lower switching capacitance relative to transistors with silicon (Si)-based channels between source and drain. In short, 2D enables scaling leading to better performance and lower energy.

[0029] Figure 1 An example of a complementary field effect transistor (CFET) structure 100 using a gate-all-around (GAA) TMD channel is illustrated. In this example, the CFET structure 100 is configured as an inverter (NOT logic). However, as will be seen further below, the CFET structure can be configured for other purposes. It is foreseeable that the proposed 3D GAA TMD channel CFET integration can be a roadmap for future technologies that shrink to below 1nm.

[0030] exist Figure 1 In the present invention, the proposed CFET structure 100 can be formed in multiple intermetal dielectric (IMD) layers. Here, 130 represents the main IMD layer - layer (x), 110 represents IMD (x-1), and 150 represents IMD layer (x+1). For ease of description, the main IMD layer 130 may be simply referred to as the "IMD layer". As shown, the IMD layers 110 and 150 may be below and above the IMD layer 130, respectively. Therefore, also for ease of description, layer 110 may be referred to as the "lower IMD layer" and layer 150 may be referred to as the "upper IMD layer". It should be noted that other IMD layers may exist below the lower IMD layer 110 and / or above the upper IMD layer 150.

[0031] Before proceeding further, the following should be recognized. Terms such as "above", "below", "left", "right", etc. are terms used for convenience of description. Therefore, unless otherwise expressly indicated, such terms are not meant to limit the aspects to a particular direction or orientation.

[0032] Within the IMD layer 130, a lower transistor and an upper transistor may be formed. The lower transistor may include a lower source contact 132, a lower drain contact 134, and a lower GAA gate region 135, and the upper transistor may include an upper source contact 142, an upper drain contact 144, and an upper GAA gate region 145. In one aspect, the lower GAA gate region 135 may be a first conductivity type (e.g., P-type), and the upper GAA gate region 145 may be a second conductivity type (e.g., N-type) opposite to the first conductivity type. Thus, the lower transistor and the upper transistor may form a complementary transistor. Details of the lower and upper GAA gate regions 135, 145 will be further described below.

[0033] The lower source contact and the lower drain contact and the upper source contact and the upper drain contact 132, 134, 142, 144 can be conductive. In one aspect, these contacts 132, 134, 142, 144 can be formed of materials including palladium (Pd), nickel (Ni), gold (Au), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TaN), bismuth (Bi), antimony (Sb), molybdenum (Mo), ruthenium (Ru), etc. Each contact 132, 134, 142, 144 can be formed of any combination of such materials. In addition, it is not required that all contacts 132, 134, 142, 144 are made of the same material. That is, each of the contacts 132, 134, 142, 144 can be formed of a material independent of the other contacts 132, 134, 142, 144.

[0034] A common gate 139 and a spacer 137 may be formed in the IMD layer 130. The common gate 139 may be between the lower source and drain contacts 132, 134 and between the upper source and drain contacts 142, 144. The common gate 139 may be conductive. For example, the common gate 139 may be formed of a metal such as tungsten (W), titanium nitride (TiN), etc. On the other hand, the spacer 137 may be electrically insulating, for example, may be formed of oxide, silicon nitride, aluminum oxide, etc.

[0035] For ease of reference, the spacer 137 to the left of the common gate 139 (between the upper source contact 142 and the common gate 139 and also between the lower source contact 132 and the common gate 139) may be referred to as a source spacer. Conversely, the spacer 137 to the right of the common gate 139 (between the upper drain contact 144 and the common gate 139 and also between the lower drain contact 134 and the common gate 139) may be referred to as a drain spacer. In one aspect, the source spacer may contact any one of the common gate 139, the lower source contact 132, and / or the upper source contact 142. Similarly, the drain spacer may contact any one of the common gate 139, the lower drain contact 134, and / or the upper drain contact 144. In another aspect, the common gate 139 and / or the spacer 137 may vertically span the entire height of the IMD layer 130, i.e., from the upper surface to the lower surface of the IMD layer 130.

[0036] Figure 2A An example embodiment of a lower GAA gate region 135 is illustrated. As shown, the lower GAA gate region 135 may include one or more lower channel structures 210 spaced apart from each other. Each lower channel structure 210 may include a lower TMD channel 212. In one aspect, the lower TMD channel 212 may be the 2D material described above. For example, the lower TMD channel 212 may be formed of tungsten diselenide (WSe2). The lower TMD channel 212 may be very thin. As an example, the lower TMD channel 212 may be formed of one or two layers of 2D material (e.g., one or two layers of WSe2). The thickness of the lower TMD channel 212 may be in a range between 1nm and 2nm. In addition, adjacent lower TMD channels 212 may be spaced apart from each other by approximately 10nm to 20nm.

[0037] The gate oxide layer 214 may be formed on both the lower surface and the upper surface of the lower TMD channel 212. In one aspect, the gate oxide layer 214 may physically contact the lower surface and / or the upper surface of the lower TMD channel 212. For ease of reference, the gate oxide layers 214 on the lower surface and the upper surface of the lower TMD channel 212 may be referred to as "first lower gate oxide layer" and "second lower gate oxide layer", respectively. The first lower gate oxide layer and / or the second lower gate oxide layer 214 may be a high-k dielectric layer. Each gate oxide layer 214 may be a combination of hafnium oxide (HfO2) and aluminum oxide (Al2O3) or a combination of hafnium (Hf), HfO2 and Al2O3. The thickness of each gate oxide layer 214 may be in the range between 2nm and 5nm.

[0038] The work function layer 216 may also be formed below and above the lower TMD channel 212, for example, below the first lower gate oxide layer and above the second lower gate oxide layer. In one aspect, the work function layer 216 may physically contact the lower surface of the first lower gate oxide layer and / or the upper surface of the second lower gate oxide layer. For ease of reference, the work function layer 216 on the lower surface of the first lower gate oxide layer may be referred to as the "first lower work function layer", and the work function layer 216 on the upper surface of the second lower gate oxide layer may be referred to as the "second lower work function layer". The work function layer 216 may be formed of a metal such as TiN, titanium aluminide (TiAl), or both TiN and TiAl. The thickness of each work function layer 216 may be in the range between 1 nm and 2 nm.

[0039] In one aspect, adjacent lower channel structures 210 may be spaced about 2 nm to 5 nm apart from each other. This means that the distance between adjacent lower channel structures 210 is about 2 nm to 5 nm. Figure 2A The thickness of the common gate 139 can be seen in FIG.

[0040] Figure 2B An example embodiment of an upper GAA gate region 145 is illustrated. As shown, the upper GAA gate region 145 may include one or more upper channel structures 250 spaced apart from each other. Each upper channel structure 250 may include an upper TMD channel 252. The upper TMD channel 252 may also be the 2D material described above. For example, the upper TMD channel 252 may be formed of molybdenum disulfide (MoS2). The upper TMD channel 252 may be very thin. As an example, the upper TMD channel 252 may be formed of one or two layers of 2D material (e.g., one or two layers of MoS2). The thickness of the upper TMD channel 252 may be in a range between 1nm and 2nm. In addition, adjacent upper TMD channels 212 may be spaced apart from each other by approximately 10nm to 20nm.

[0041] The gate oxide layer 254 may be formed on both the lower surface and the upper surface of the upper TMD channel 252. In one aspect, the gate oxide layer 254 may physically contact the lower surface and / or the upper surface of the upper TMD channel 252. For ease of reference, the gate oxide layer 254 on the lower surface and the upper surface of the upper TMD channel 252 may be referred to as a "first upper gate oxide layer" and a "second upper gate oxide layer", respectively. The first upper gate oxide layer and / or the second upper gate oxide layer 254 may be a high-k dielectric layer. Each gate oxide layer 254 may be a combination of hafnium oxide (HfO2) and aluminum oxide (Al2O3) or a combination of hafnium (Hf), HfO2, and Al2O3. The thickness of each gate oxide layer 254 may be in a range between 2nm and 5nm.

[0042] A work function layer 256 may also be formed below and above the upper TMD channel 252, for example, below the first upper gate oxide layer and above the second upper gate oxide layer. In one aspect, the work function layer 256 may physically contact the lower surface of the first upper gate oxide layer and / or the upper surface of the second upper gate oxide layer. For ease of reference, the work function layer 256 on the lower surface of the first upper gate oxide layer may be referred to as the "first upper work function layer", and the work function layer 256 on the upper surface of the second upper gate oxide layer may be referred to as the "second upper work function layer". The work function layer 256 may be formed of a metal such as TiN. The thickness of each work function layer 256 may be in the range between 1 nm and 2 nm.

[0043] In one aspect, adjacent upper channel structures 250 may be spaced about 2 nm to 5 nm apart from each other. This means that the distance between adjacent upper channel structures 250 is about 2 nm to 5 nm. Figure 2B The thickness of the common gate 139 can be seen in FIG.

[0044] Refer to Figure 1 , note that the TMD channel 212 (not in Figure 1 The lower TMD channel 212 may be electrically coupled to the lower source contact 132 and the lower drain contact 134. For example, the lower TMD channel 212 may be in physical contact with the lower source contact and the lower drain contact 132, 134. Similarly, the upper TMD channel 252 (not shown) may be electrically coupled to the lower source contact 132 and the lower drain contact 134. Figure 1 The upper TMD channel 252 may be electrically coupled to the upper source contact 142 and the upper drain contact 144. For example, the upper TMD channel 252 may be in physical contact with the upper source contact and the upper drain contact 142, 144.

[0045] The common gate 139 can be configured to apply a common voltage to the lower and upper channel structures 210, 250 to introduce a conductive path in the lower TMD channel 212 between the lower source and drain contacts 132, 134, and in the upper TMD channel 252 between the upper source and drain contacts 142, 144. In one aspect, the upper surfaces of the upper source contact 142, the spacer 137, the common gate 139, and the upper drain contact 144 can be flush with the upper surface of the IMD layer 130.

[0046] The CFET structure 100 may include a lower source terminal 112 and a lower drain terminal 114 in the lower IMD layer 110. The lower source terminal 112 and / or the lower drain terminal 114 may be formed of a conductive material, such as highly doped silicon and a metal (e.g., copper (Cu)). The lower source terminal 112 and / or the lower drain terminal 114 may be exposed at the upper surface of the lower IMD layer 110. For example, the terminals 112, 114 and the upper surface of the lower IMD layer 110 may be flush. The lower source terminal 112 may be electrically coupled to the lower source contact 132, and the lower drain terminal 114 may be electrically coupled to the lower drain contact 134. For example, the lower source terminal 112 may physically contact the lower source contact 132 and / or the lower drain terminal 114 may physically contact the lower drain contact 134.

[0047] The CFET structure 100 may include an upper source terminal 152, an upper drain terminal 154, and an upper gate terminal 156 in an upper IMD layer 150. The upper source terminal 152, the upper drain terminal 154, and / or the upper gate terminal 156 may be formed of a conductive material, such as highly doped silicon and a metal (e.g., copper (Cu)). The upper source terminal 152, the upper drain terminal 154, and / or the upper gate terminal 156 may be exposed at an upper surface of the upper IMD layer 150. For example, the terminals 152, 154, 156 and the upper surface of the upper IMD layer 150 may be flush.

[0048] The upper source terminal 152, the upper drain terminal 154, and the upper gate terminal 156 can be electrically coupled with the upper source contact 142, the upper drain contact 144, and the common gate 139. In one aspect, a source via 153 can be formed in the upper IMD layer 150 to electrically couple the upper source terminal 152 with the upper source contact 142. Alternatively or additionally, a drain via 155 can be formed in the upper IMD layer 150 to electrically couple the upper drain terminal 154 with the upper drain contact 144. Also alternatively or additionally thereto, a drain via 155 can be formed in the upper IMD layer 150 to electrically couple the upper drain terminal 154 with the upper drain contact 144. When present, the lower surfaces of the source via, the drain via, and the gate vias 153, 155, 157 can be flush with the lower surface of the upper IMD layer 150.

[0049] In one aspect, the CFET structure 100 may include a lower protective layer 120 and an upper protective layer 160. The lower protective layer 120 may be between the lower IMD layer 110 and the IMD layer 130, and the upper protective layer 160 may be on a top surface of the upper IMD layer 150. One or both of the lower and upper protective layers 120, 160 may be formed of silicon carbon nitride (SiCN).

[0050] Notice, Figure 1The CFET structure 100 includes a tail via 147 in the lower IMD layer 110 and in the IMD layer 130. In particular, the tail via 147 electrically couples the lower drain terminal 114 with the upper drain terminal 154 (e.g., can be in physical contact with the lower drain terminal 114 and / or with the upper drain terminal 154). In this configuration, the CFET structure can be used as an inverter, that is, as a NOT logic. That is, the Vout voltage (at the drain terminals 114, 154) can be logically opposite to the voltage applied at the gate 156.

[0051] However, the GAA TMD may be configured in other CFET structures to perform other functions. Figure 3 An example C112FET structure 300 configured to perform two-input NAND logic is illustrated. As shown, the CFET structure 300 is shown to include Figure 1 The components of the structure in the lower IMD layer 110 are lower source and drain terminals 112, 114; upper source, drain and gate terminals 152, 154, 156 and source, drain and gate vias 153, 155, 157 in the upper IMD layer 150; and lower source and drain contacts 132, 134, upper source and drain contacts 142, 144, lower gate and upper GAA gate regions 135, 145, spacers 137 and common gate 139. It can be assumed that about Figure 1 The descriptions provided for these components may also apply to Figure 3 .

[0052] As shown, the CFET structure 300 may also include a second spacer 337, a second common gate 339, a second lower source contact 332, a second lower drain contact 334, a second lower GAA gate region 335, a second upper source contact 342, a second upper drain contact 344, and a second upper GAA gate region 345. The second contacts 332, 334, 342, 344 may be formed similarly to the contacts 132, 134, 142, 144 (e.g., formed of any one or more of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.).

[0053] The second lower GAA gate region and the second upper GAA gate region 335, 345 may also be similar to the lower GAA gate region and the upper GAA gate region 135, 145. That is, the second lower GAA gate region 335 may be of the first conductivity type, and the second upper GAA gate region 335 may be of the second conductivity type (e.g., see Figure 2B ). The second lower GAA gate region 335 may include one or more lower channel structures 210 (see Figure 2A), and the second upper GAA gate region 345 may include one or more upper channel structures 250 (see Figure 2B ). For the purpose of distinction, the components associated with the second lower GAA gate region 335 and the second upper GAA gate region 345 will be prefixed with "second". Therefore, each second lower channel structure 210 of the second lower GAA gate region 335 may include a second lower TMD channel 212, a second-first lower gate oxide layer and a second-second lower gate oxide layer 214, and a second-first work function layer and a second-second work function layer 216. Similarly, each second upper channel structure 250 of the second upper GAA gate region 345 may include a second upper TMD channel 252, a second-first upper gate oxide layer and a second-second upper gate oxide layer 254, and a second-first work function layer and a second-second work function layer 256.

[0054] A second lower source terminal 312 and a second lower drain terminal 314 may be formed in the lower IMD layer 110 . The second lower source terminal 312 may be electrically coupled with the second lower source contact 332 , and the second lower drain terminal 314 may be electrically coupled with the second lower drain contact 334 .

[0055] A second upper drain terminal 354 and a second upper gate terminal 356 may be formed in the upper IMD layer 150. The second upper drain terminal 354 may be electrically coupled to the second upper drain contact 344 (e.g., through a second drain via 355). The second upper gate terminal 356 may be electrically coupled to the second common gate 339 (e.g., through a second gate via 357). A second upper source terminal 352 may also be formed that is electrically coupled (e.g., through a second source via 353). However, in one aspect, the second source terminal 352 and the drain terminal 154 may be common, i.e., the same.

[0056] Note that the tail via 347 electrically couples the second lower drain terminal 314 with the second upper drain terminal 354. In this configuration, the CFET structure 300 can perform NAND logic with inputs provided to the upper gate terminal 156 and the second upper gate terminal 356.

[0057] Figure 4 An example CFET structure 400 configured to perform two-input NOR logic is illustrated. As shown, the CFET structure 400 is shown to include Figure 1The components of the structure in the lower IMD layer 110 are lower source and drain terminals 112, 114; upper source, drain and gate terminals 152, 154, 156 and source, drain and gate vias 153, 155, 157 in the upper IMD layer 150; and lower source and drain contacts 132, 134, upper source and drain contacts 142, 144, lower gate and upper GAA gate regions 135, 145, spacers 137 and common gate 139. It can be assumed that about Figure 1 The descriptions provided for these components may also apply to Figure 4 .

[0058] As shown, the CFET structure 400 may also include a third spacer 437, a third common gate 439, a third lower source contact 432, a third lower drain contact 434, a third lower GAA gate region 435, a third upper source contact 442, a third upper drain contact 444, and a third upper GAA gate region 445. The third contacts 432, 434, 442, 444 may be formed similarly to the contacts 132, 134, 142, 144 (e.g., formed of any one or more of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.).

[0059] The third lower GAA gate region and the third upper GAA gate region 435, 445 may also be similar to the lower GAA gate region and the upper GAA gate region 135, 145. That is, the third lower GAA gate region 435 may be of the first conductivity type, and the third upper GAA gate region 445 may be of the second conductivity type (e.g., see Figure 2B ). The third lower GAA gate region 435 may include one or more lower channel structures 210 (see Figure 2A ), and the third upper GAA gate region 445 may include one or more upper channel structures 250 (see Figure 2B ). For the purpose of distinction, the components associated with the third lower GAA gate region 435 and the third upper GAA gate region 445 will be prefixed with "third". Therefore, each third lower channel structure 210 of the third lower GAA gate region 435 may include a third lower TMD channel 212, a third-first gate oxide layer and a third-second gate oxide layer 214, and a third-first work function layer and a third-second work function layer 216. Similarly, each third upper channel structure 250 of the third upper GAA gate region 445 may include a third upper TMD channel 252, a third-first gate oxide layer and a third-second gate oxide layer 254, and a third-first work function layer and a third-first work function layer 256.

[0060] A third lower drain terminal 414 electrically coupled to the third lower drain contact 434 may be formed in the lower IMD layer 110. A third lower source terminal 412 may also be formed. However, in one aspect, the lower drain terminal and the third lower source terminal 412 may be common.

[0061] A third upper source terminal 452, a third upper drain terminal 454, and a third upper gate terminal 456 may be formed in the upper IMD layer 150. The third upper source terminal 452 may be electrically coupled to the third upper source contact 442 (e.g., through a third source via 453). The third upper drain terminal 454 may be electrically coupled to the third upper drain contact 444 (e.g., through a third drain via 455). The third upper gate terminal 456 may be electrically coupled to the third common gate 439 (e.g., through a third gate via 457).

[0062] Note that the tail via 447 electrically couples the third lower drain terminal 414 with the third upper drain terminal 454. In this configuration, the CFET structure 400 can perform NOR logic of the inputs provided to the upper gate terminal 156 and the third upper gate terminal 456.

[0063] Figure 5 Another example of a CFET structure 500 according to one or more aspects of the present disclosure is shown. Figure 1 The CFET structure 100 is very similar in that both include many of the same elements. It can be assumed that elements with the same number behave the same in both structures. Therefore, the description will be Figure 1 and Figure 5 The difference between.

[0064] One difference is that the illustrated CFET structure 500 may include a lower GAA gate region 535 and an upper GAA gate region 545 (instead of lower and upper GAA gate regions 135, 145). Lower GAA gate region 535 may be of a first conductivity type and upper GAA gate region 545 may be of a second conductivity type opposite the first conductivity type.

[0065] like Fig. 6A As shown in , the lower GAA gate region 535 may include one or more lower channel structures 610. Each lower channel structure 610 may include a lower TMD channel 612. The lower TMD channel 612 may be formed of a 2D material. In one aspect, the lower TMD channel 612 may be formed of one of WSe2 and MoS2. The lower TMD channel 612 may be very thin. As an example, the lower TMD channel 612 may be formed of one or two layers of 2D material. The thickness of the lower TMD channel 612 may be in the range between 1nm and 2nm. In addition, adjacent lower TMD channels 612 may be spaced about 10nm to 20nm from each other.

[0066] Each lower channel structure 610 may further include a first lower gate oxide layer and a second lower gate oxide layer 614 (eg, below and above the lower TMD channel 612). The first lower gate oxide layer and the second lower gate oxide layer 614 may be similar to Figure 2A The first lower gate oxide layer and the second lower gate oxide layer 214. Each lower channel structure 610 may also include a first lower work function layer and a second lower work function layer 616. The first lower work function layer and the second lower work function layer 616 may be similar to Figure 2A The first lower work function layer and the second lower work function layer 216 are formed.

[0067] like Figure 6B As shown in , the upper GAA gate region 545 may include one or more upper channel structures 650. Each upper channel structure 650 may include an upper TMD channel 652. The upper TMD channel 652 may be formed of a 2D material. In one aspect, the upper TMD channel 652 may be formed of one of WSe2 and MoS2. The upper TMD channel 652 may be very thin. As an example, the upper TMD channel 652 may be formed of one or two layers of 2D material. The thickness of the upper TMD channel 652 may be in a range between 1nm and 2nm. In addition, adjacent upper TMD channels 652 may be spaced about 10nm to 20nm from each other.

[0068] Each upper channel structure 650 may also include a first upper gate oxide layer and a second upper gate oxide layer 654 (eg, below and above the upper TMD channel 652). The first upper gate oxide layer and the second upper gate oxide layer 654 may be similar to Figure 2A The first upper gate oxide layer and the second upper gate oxide layer 214. Each upper channel structure 650 may also include a first upper work function layer and a second upper work function layer 656. The first upper work function layer and the second upper work function layer 656 may be similar to Figure 2B The first upper work function layer and the second upper work function layer 216 are formed.

[0069] Return to reference Figure 5, another difference is that the CFET structure 500 can also include a lower internal source contact 531 and a lower external drain contact 533. The lower internal source contact 531 can be between the lower source contact 132 and the lower GAA gate region 535, and the lower internal drain contact 533 can be between the lower GAA gate region 535 and the lower drain contact 134. The lower internal source contact and the lower internal drain contacts 531, 533 can be conductive. In one aspect, the contacts 531, 533 can be formed of a material similar to the contacts 132, 134. The lower source contact 132 can be shifted to the left so as to be laterally outside the upper source contact 142. Alternatively or additionally, the lower drain contact 134 can be shifted to the right so as to be laterally outside the upper drain contact 144.

[0070] Note that the lower source contact 132 may be connected to the lower TMD channel 612 (not shown) via the lower inner source contact 531, for example. Figure 5 In one aspect, the lower inner source contact 531 may physically contact the lower source contact 132 and the lower TMD channel 612. Alternatively or additionally, the lower inner drain contact 533 may physically contact the lower drain contact 134 and the lower TMD channel 612.

[0071] As shown, the lower TMD channel 612 can extend into the lower inner source contact 531 and / or the lower inner drain contact 533. Alternatively or additionally thereto, the lower TMD channel 612 can also extend into the lower source contact 132 and / or the lower drain contact 134. Furthermore, alternatively or additionally, the upper TMD channel 652 (not shown in FIG. Figure 5 The lower TMD channel and / or the upper TMD channel 612, 652 may extend into the upper source contact and / or the upper drain contact 142, 144. When the lower TMD channel and / or the upper TMD channel 612, 652 extend into the contacts 132, 531, 134, 532, 432, 434, the contact area increases. This may reduce the contact resistance, which is beneficial.

[0072] The CFET structure 500 includes a tail via 147 in the lower IMD layer 110 and in the IMD layer 130. Thus, as ( Figure 1 ) CFET structure 100, CFET structure 500 is also configured to perform NOT logic.

[0073] Figure 7 The diagram shows a system configured to perform such as ( Figure 3 The following is a CFET structure 700 of a NAND logic of the CFET structure 300. Figure 3 and Figure 7First, the CFET structure 700 may include a lower inner source contact 531, a lower inner drain contact 533, a second lower inner source contact 731, and a second lower inner drain contact 733. In addition, the second lower TMD channel 612 (not in Figure 7 The second upper TMD channel 616 (not shown) may extend into the second lower inner source contact 731 and / or the second lower inner drain contact 733, respectively. Figure 7 The second upper source contact 342 and / or the second upper drain contact 344 may extend into the second upper source contact 342 and / or the second upper drain contact 344, respectively. Note that the CFET structure 700 may include a second lower GAA gate region 735 and a second upper GAA gate region 745.

[0074] Figure 8 The diagram shows a system configured to perform such as ( Figure 4 The following is a CFET structure 800 of the NOR logic of the CFET structure 400. Figure 4 and Figure 8 First, the CFET structure 800 may include a lower inner source contact 531, a lower inner drain contact 533, a third lower inner source contact 831, and a third lower inner drain contact 833. In addition, the third lower TMD channel 612 (not shown in FIG. Figure 8 The third upper TMD channel 616 (not shown) may extend into the third lower inner source contact 831 and / or the third lower inner drain contact 833, respectively. Figure 8 The third upper source contact 442 and / or the third upper drain contact 444 may extend into the third upper source contact 442 and / or the third upper drain contact 444, respectively. Note that the CFET structure 800 may include a third lower GAA gate region 835 and a third upper GAA gate region 845.

[0075] FIG. 9A to FIG. 9J Illustrated are examples of stages in fabricating a CFET structure (eg, CFET structures 100 , 300 , 400 ) according to one or more aspects of the present disclosure.

[0076] Fig. 9A The diagram illustrates a stage where fabrication begins with a back-end-of-line (BEOL) IMD layer (x-1), i.e., a lower IMD layer 110. Here, the metal layer x-1 may be deposited and patterned to form a lower source terminal 112 and a lower drain terminal 114. A lower protective layer 120 may be formed on the lower IMD layer 110 by depositing and patterning (e.g., polishing) a protective material (e.g., SiCn).

[0077] Fig. 9BThe stage in which multiple oxide / HfO2 / 2D film (e.g., WSe2) layers are deposited for a first conductivity type transistor (e.g., P-type) is illustrated. While maintaining the 2D film material, the active film and the oxide film can be patterned in the gate region. The spacer material (e.g., SiN) can be deposited and etched to form the spacer 137. In short, the lower TMD channel 212 and the HfO2 layer 920 (which is temporary) can be formed. Note that the spacer 137 is partial at this stage.

[0078] Fig. 9C Illustrated is a stage where an IMD oxide material may be deposited and planarized (eg, by chemical mechanical polishing (CMP)) to form the IMD layer 130. The gate region may be opened and the oxide in the gate region may be removed. The IMD layer 130 is partial at this stage.

[0079] Fig.9D A stage is illustrated in which the previous HfO2 layer 920 is removed. HfO2 / Al2O3 or Hf / HfO2 / Al2O3 can then be deposited (e.g., by atomic layer deposition (ALD)) to form a lower gate oxide layer 214. A lower work function layer 216 can be formed (e.g., by ALD deposition of TiN). In addition, a common gate 139 can be formed (e.g., by depositing W and polishing). Note that the common gate 139 is partial at this stage.

[0080] Fig.9E The stage in which the lower GAA gate region 135 is formed is illustrated. Here, the lower source and drain contacts 132, 134 may be formed by patterning the IMD layer 130 and the lower protective layer 120 and depositing a conductive material (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) in the patterned region. The deposited material may then be polished (e.g., CMP).

[0081] Fig.9F The stage in which multiple oxide / HfO2 / 2D film (e.g., MoS2) layers are deposited for a second conductivity type transistor (e.g., N-type) is illustrated. While maintaining the 2D film material, the active film and the oxide film can be patterned in the gate region. Spacer material (e.g., SiN) can be deposited and etched to further form a spacer 137. In short, an upper TMD channel 252 and a HfO2 layer 925 (which is temporary) can be formed. Note that the spacer 137 can be at full height at this stage.

[0082] Figure 9GIllustrated is a stage where more IMD oxide may be deposited and planarized (eg, by CMP) to further form the IMD layer 130. The gate region may be opened and the oxide in the gate region may be removed. The IMD layer 130 may be at full height at this stage.

[0083] Figure 9H The stage in which the previous HfO2 layer 925 is removed is illustrated. HfO2 / Al2O3 or Hf / HfO2 / Al2O3 may then be deposited (e.g., by ALD) to form an upper gate oxide layer 254. An upper work function layer 256 may be formed (e.g., by ALD deposition of TiN). In addition, a common gate 139 may be further formed (e.g., by depositing W and polishing). Note that the common gate 139 may be at full height at this stage.

[0084] Fig.9I The stage is illustrated in which the upper GAA gate region 145 is formed. Here, the regions of the upper source and drain contacts 142, 144 may be patterned in the IMD layer 130. The patterned regions may be deposited with a conductive material (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) and polished (e.g., CMP).

[0085] Figure 9J The stage in which more IMD oxide layers may be deposited and patterned to form an upper IMD layer 150 is illustrated. Here, a metal layer x+1 may be deposited and patterned to form an upper source terminal 152, an upper drain terminal 154, and an upper gate terminal 156. Source vias, drain vias, and gate vias 153, 155, 157 may also be formed. In addition, the lower protective layer 120, the IMD layer 130, and the upper IMD layer 150 may be patterned, and a conductive material may be deposited in the patterned area to form a tail via 147. An upper protective layer 160 may be formed on the upper IMD layer 150 by depositing and patterning (e.g., polishing) a protective material (e.g., SiCN).

[0086] FIG. 10A to FIG. 10J Illustrated are examples of stages in fabricating a CFET structure, such as CFET structures 500 , 700 , 800 , according to one or more aspects of the present disclosure.

[0087] Fig. 10AThe diagram illustrates a stage where fabrication begins with a back-end-of-line (BEOL) IMD layer (x-1), i.e., a lower IMD layer 110. Here, the metal layer x-1 may be deposited and patterned to form a lower source terminal 112 and a lower drain terminal 114. A lower protective layer 120 may be formed on the lower IMD layer 110 by depositing and patterning (e.g., polishing) a protective material (e.g., SiCN).

[0088] Fig. 10B The diagram shows a stage in which multiple oxide / HfO2 / 2D film (e.g., one of MoS2 and WSe2) layers are deposited for a first conductivity type transistor (e.g., P-type). While maintaining the 2D film material, the active film and the oxide film can be patterned in the gate area. The spacer material (e.g., SiN) can be deposited and etched to form the spacer 137. In short, the lower TMD channel 612 and the HfO2 layer 1020 (which is temporary) can be formed. Note that the lower TMD channel 612 is smaller than ( Fig. 9B For example, the lower TMD channel 612 may extend beyond the spacer 137. Note also that the spacer 137 is partial at this stage.

[0089] Fig. 10C Illustrated is a stage where an IMD oxide material may be deposited and planarized (eg, by CMP) to form the IMD layer 130. The gate region may be opened and the oxide in the gate region may be removed. The IMD layer 130 is partial at this stage.

[0090] Fig. 10D A stage is illustrated in which the previous HfO2 layer 1020 is removed. HfO2 / Al2O3 or Hf / HfO2 / Al2O3 may then be deposited (e.g., by ALD) to form a lower gate oxide layer 614. A lower work function layer 616 may be formed (e.g., by ALD deposition of TiN). In addition, a common gate 139 may be formed (e.g., by depositing W and polishing). Note that the common gate 139 is partial at this stage.

[0091] Fig. 10EThe stage in which the lower GAA gate region 535 is formed is illustrated. Here, the lower inner source and drain contacts 531, 533 may be formed by patterning the IMD layer 130 and depositing a conductive material (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) in the patterned region. In addition, the lower source and drain contacts 132, 134 may be formed by patterning the IMD layer 130 and the lower protective layer 120 and depositing a conductive material (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) in the patterned region. The deposited materials for the inner source and drain contacts 531, 533 and for the lower source and drain contacts 132, 134 may be polished (e.g., CMP).

[0092] Fig.10F The diagram shows a stage where multiple oxide / HfO2 / 2D film (e.g., MoS2) layers are deposited for a second conductivity type transistor (e.g., N-type). While maintaining the 2D film material, the active film and oxide film can be patterned in the gate region. Spacer material (e.g., SiN) can be deposited and etched to form spacer 137. In short, the upper TMD channel 652 and HfO2 layer 1025 (which is temporary) can be formed. Note that the spacer 137 can be at full height at this stage.

[0093] Figure 10G Illustrated is a stage where more IMD oxide may be deposited and planarized (eg, by CMP) to further form the IMD layer 130. The gate region may be opened and the oxide in the gate region may be removed. The IMD layer 130 may be at full height at this stage.

[0094] Fig. 10H The stage in which the previous HfO2 layer 1025 is removed is illustrated. HfO2 / Al2O3 or Hf / HfO2 / Al2O3 may then be deposited (e.g., by ALD) to form an upper gate oxide layer 654. An upper work function layer 656 may be formed (e.g., by ALD deposition of TiN). In addition, a common gate 139 may be further formed (e.g., by depositing W and polishing). Note that the upper TMD channel 656 is larger than ( Figure 9H For example, the upper TMD channel 656 may extend beyond the spacer 137. Also note that the common gate 139 may be full height at this stage.

[0095] Fig.10IThe stage is illustrated in which the upper GAA gate region 545 is formed. At this point, the regions of the upper source and drain contacts 142, 144 may be patterned in the IMD layer 130. The patterned regions may be deposited with a conductive material (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) and polished (e.g., CMP).

[0096] Fig.10J The stage in which more IMD oxide layers may be deposited and patterned to form an upper IMD layer 150 is illustrated. Here, a metal layer x+1 may be deposited and patterned to form an upper source terminal 152, an upper drain terminal 154, and an upper gate terminal 156. Source vias, drain vias, and gate vias 153, 155, 157 may also be formed. In addition, the lower protective layer 120, the IMD layer 130, and the upper IMD layer 150 may be patterned, and a conductive material may be deposited in the patterned area to form a tail via 147. An upper protective layer 160 may be formed on the upper IMD layer 150 by depositing and patterning (e.g., polishing) a protective material (e.g., SiCN).

[0097] Fig.11 A flow chart of an example method 1100 of manufacturing a CFET structure (such as CFET structures 100, 300, 400, 500, 700, 800) according to one or more aspects of the present disclosure is illustrated. In block 1110, a lower source contact (e.g., lower source contact 132) and a lower drain contact (e.g., lower drain contact 134) may be formed in an intermetal dielectric (IMD) layer (e.g., IMD layer 130). Block 1110 may correspond to Fig.9E and Fig. 10E The stages shown in the figure.

[0098] In block 1120, a lower all-around gate (GAA) gate region (e.g., lower GAA gate region 135) may be formed in the IMD layer between the lower source contact and the lower drain contact (e.g., lower source contact and lower drain contact 132, 134). The lower GAA gate region may be of a first conductivity type (e.g., P-type) and may include one or more lower channel structures (e.g., lower channel structures 210, 610). Each lower channel structure may include a lower transition metal dichalcogenide (TMD) channel (e.g., lower TMD channel 212, 612). The lower TMD channel may be electrically coupled to the lower source contact and the lower drain contact. The lower TMD channel may also include a first lower gate oxide layer and a second lower gate oxide layer (e.g., lower gate oxide layer 214, 614) on the lower surface and upper surface of the lower TMD channel, respectively. The lower channel structure may also include a first lower work function layer and a second lower work function layer (eg, lower work function layers 216, 616) on a lower surface of the first lower gate oxide layer and an upper surface of the second lower gate oxide layer, respectively. Block 1120 may correspond to FIG. 9B to FIG. 9E and FIG. 10B to FIG. 10E The stages shown in the figure.

[0099] At block 1130, an upper source contact (eg, upper source contact 142) and an upper drain contact (eg, upper drain contact 144) may be formed in the IMD layer over the lower source contact and the lower drain contact. Block 1130 may correspond to Fig.9I and Fig.10I The stages shown in the figure.

[0100] In block 1140, an upper all-around gate (GAA) gate region (e.g., upper GAA gate region 145) may be formed in the IMD layer, the upper GAA gate region being between the upper source contact and the upper drain contact. The upper GAA gate region may be of a second conductivity type (e.g., N-type) opposite to the first conductivity type, and may include one or more upper channel structures (e.g., upper channel structures 250, 650). Each upper channel structure may include an upper transition metal dichalcogenide (TMD) channel (e.g., upper TMD channel 252, 652). The upper TMD channel may be electrically coupled to the upper source contact and the upper drain contact. The upper TMD channel may also include a first upper gate oxide layer and a second upper gate oxide layer (e.g., upper gate oxide layer 254, 654) on the lower surface and the upper surface of the upper TMD channel, respectively. The upper channel structure may also include a first upper work function layer and a second upper work function layer (eg, upper work function layers 256, 656) on an upper surface of the first upper gate oxide layer and an upper surface of the second upper gate oxide layer, respectively. Block 1140 may correspond to FIG. 9F to FIG. 9I and FIG. 10F to FIG. 10IThe stages shown in the figure.

[0101] In block 1150, a common gate (e.g., common gate 139) may be formed in the IMD layer between the lower source contact and the lower drain contact and between the upper source contact and the upper drain contact. The common gate may be configured to apply a common voltage to the lower channel structure and the upper channel structure to introduce a conductive path in the lower TMD channel between the lower source contact and the lower drain contact and to introduce a conductive path in the upper TMD channel between the upper source contact and the upper drain contact. Block 1150 may correspond to Fig.9D , Figure 9H , Fig. 10D ,as well as Fig. 10H Diagram of the stages.

[0102] Fig.12 A flow chart of an example method 1200 of fabricating a CFET structure (eg, CFET structures 100 , 300 , 400 , 500 , 700 , 800 ) according to one or more aspects of the present disclosure is illustrated. Fig.12 Can be Fig.11 A more comprehensive view.

[0103] Therefore, blocks 1210 to 1250 may be similar to blocks 1110 to 1150. Therefore, for the sake of brevity, a detailed description of blocks 1210 to 1250 will be omitted.

[0104] In block 1255 , a lower inner contact may be formed in the IMD layer. Fig.13 A flow chart of an example process for implementing block 1255 is illustrated. In block 1310, a lower intrinsic source contact (eg, lower intrinsic source 531) may be formed between the lower extrinsic source contact and the lower GAA gate region. Block 1310 may correspond to Fig. 10H Diagram of the stages.

[0105] In block 1320, a lower inner drain contact (eg, lower inner contact 533) may be formed between the lower GAA gate region and the lower outer drain contact. Block 1310 may also correspond to Fig. 10H Diagram of the stages.

[0106] Refer to Fig.12 , in block 1260 , spacers may be formed in the IMD layer. Fig.14 A flow chart of an example process for implementing block 1260 is illustrated. In block 1410, source spacers (e.g., left spacers 137, 537) may be formed between the lower source contact and the common gate and between the upper source contact and the common gate. The source spacers may span from the upper surface of the IMD layer to the lower surface of the IMD layer. Block 1410 may correspond to Fig. 9C , Fig.9F , Fig. 10C ,as well as Fig.10F Diagram of the stages.

[0107] In block 1420, drain spacers (e.g., right spacers 137, 537) may be formed between the lower drain contact and the common gate and between the upper drain contact and the common gate 139. The drain spacers may span from the upper surface of the IMD layer to the lower surface of the IMD layer. Block 1420 may also correspond to Fig. 9C , Fig.9F , Fig. 10C ,as well as Fig.10F Diagram of the stages.

[0108] Return to reference Fig.12 In block 1270 , terminals may be formed in the upper IMD layer and the lower IMD layer (eg, the upper IMD layer 150 , the lower IMD layer 110 ). Fig.15 A flow chart of an example process for implementing block 1270 is illustrated. In block 1510, a lower source terminal (e.g., lower source terminal 112) may be formed in the lower IMD layer. The lower source terminal may be electrically coupled to a lower source contact. The lower IMD layer may be on a lower surface of the IMD layer. Block 1510 may correspond to Fig. 9A and Fig. 10A Diagram of the stages.

[0109] In block 1520, a lower drain terminal (eg, lower drain terminal 114) may be formed in the lower IMD layer. The lower drain terminal may be electrically coupled to the lower source contact. Block 1520 may correspond to Fig. 9A and Fig. 10A Diagram of the stages.

[0110] In block 1530, an upper source terminal (eg, upper source terminal 152) may be formed in the upper IMD layer. The upper source terminal may be electrically coupled to an upper source contact. The upper IMD layer may be on an upper surface of the IMD layer. Block 1530 may correspond to Figure 9J and Fig.10J Diagram of the stages.

[0111] In block 1535, a source via (eg, source via 153) may be formed in the upper IMD layer. The source via may electrically couple the upper source terminal with the upper source contact. Block 1535 may correspond to Figure 9J and Fig.10J Diagram of the stages.

[0112] In block 1540, an upper drain terminal (eg, upper drain terminal 154) may be formed in the upper IMD layer. The upper drain terminal may be electrically coupled to an upper drain contact. Block 1540 may correspond to Figure 9J and Fig.10JDiagram of the stages.

[0113] In block 1545, a drain via (eg, drain via 155) may be formed in the upper IMD layer. The drain via may electrically couple the upper drain terminal with the upper drain contact. Block 1545 may correspond to Figure 9J and Fig.10J The stages shown in the figure.

[0114] In block 1550, an upper gate terminal (eg, upper gate terminal 156) may be formed in the upper IMD layer. The upper gate terminal may be electrically coupled to the common gate. Block 1550 may correspond to Figure 9J and Fig.10J Diagram of the stages.

[0115] In block 1555, a gate via (eg, gate via 157) may be formed in the upper IMD layer. The gate via may electrically couple the upper gate terminal to the common gate. Block 1555 may correspond to Figure 9J and Fig.10J The stages shown in the figure.

[0116] It will be understood that the foregoing manufacturing processes and related discussions are provided only as a general description of some aspects of the present disclosure and are not intended to limit the present disclosure or the appended claims. In addition, many details of the manufacturing processes known to those skilled in the art may have been omitted or combined in the overview process section to facilitate understanding of the various aspects disclosed without reproducing each detail and / or all possible process variations in detail. In addition, it will be understood that the provided diagrammatic configurations and descriptions are only used to help illustrate the various aspects disclosed herein. For example, the number and position of inductors, the metallization structure may have more or fewer conductive layers and insulating layers, cavity orientation, size, whether it is formed by multiple cavities, closed or open, and other aspects may have variations driven by specific application design features, such as the number of antennas, antenna type, frequency range, power, etc. Therefore, the foregoing illustrative examples and associated drawings should not be interpreted as limiting the various aspects disclosed and claimed herein.

[0117] Fig.16 Various electronic devices 1600 are illustrated that may be integrated with any of the aforementioned devices according to various aspects of the present disclosure. For example, a mobile phone device 1602, a laptop device 1604, and a fixed location terminal device 1606 may each generally be considered a user equipment (UE) and may include one or more CFET structures (e.g., 100, 300, 400, 500, 700, 800) as described herein. Fig.16The devices 1602, 1604, 1606 shown are exemplary only. Other electronic devices may also include RF filters, including but not limited to a group of devices (e.g., electronic devices) including the following devices: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smart phones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things devices, or any other device that stores or retrieves data or computer instructions or any combination thereof.

[0118] The aforementioned disclosed devices and functions may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer readable medium. Some or all of such files may be provided to a manufacturing processor that manufactures devices based on such files. The resulting product may include a semiconductor wafer that is then cut into semiconductor dies and packaged into an antenna on glass device. The antenna on glass device may then be used in the devices described herein.

[0119] Implementation examples are described in the following numbered clauses:

[0120] Item 1: A complementary field effect transistor (CFET) structure comprising: a lower source contact and a lower drain contact in an intermetal dielectric (IMD) layer; a lower gate all around (GAA) gate region in the IMD layer between the lower source contact and the lower drain contact, the lower GAA gate region being of a first conductivity type and comprising one or more lower channel structures, each lower channel structure comprising: a lower transition metal dichalcogenide (TMD) channel electrically coupled to the lower source contact and the lower drain contact; and a first lower gate oxide layer and a second lower gate oxide layer, respectively, on a lower surface and an upper surface of the lower TMD channel; an upper source contact and an upper drain contact in the IMD layer, between the lower source contact and the lower drain contact; contact; an upper GAA gate region in the IMD layer, above the lower GAA gate region and between the upper source contact and the upper drain contact, the upper GAA gate region being a second conductivity type opposite to the first conductivity type and comprising one or more upper channel structures, each upper channel structure comprising: an upper TMD channel electrically coupled to the upper source contact and the upper drain contact; and a first upper gate oxide layer and a second upper gate oxide layer, respectively on the lower surface and the upper surface of the upper TMD channel; and a common gate in the IMD layer, between the lower source contact and the lower drain contact and between the upper source contact and the upper drain contact, the common gate being configured to apply a common voltage to the lower channel structure and the upper channel structure.

[0121] Item 2: A CFET structure according to Item 1, wherein each lower channel structure further includes: a first lower work function layer on the lower surface of the first lower gate oxide layer; and a second lower work function layer on the upper surface of the second lower gate oxide layer, and wherein each upper channel structure further includes: a first upper work function layer on the lower surface of the first upper gate oxide layer; and a second upper work function layer on the upper surface of the second upper gate oxide layer.

[0122] Item 3: A CFET structure according to Item 2, wherein the first lower work function layer or the second lower work function layer or both the first lower work function layer and the second lower work function layer are formed of one or both of titanium nitride (TiN) or titanium aluminide (TiAl), or wherein the first upper work function layer or the second upper work function layer or both the first lower work function layer and the second lower work function layer are formed of one or both of TiN or TiAl, or both of the above.

[0123] Clause 4: A CFET structure according to any one of clauses 1 to 3, wherein the lower TMD channel is formed of tungsten diselenide (WSe2) and the upper TMD channel is formed of molybdenum disulfide (MoS2).

[0124] Item 5: A CFET structure according to Item 4, wherein the lower TMD channel is formed of one or two layers of WSe2, and wherein the upper TMD channel is formed of one or two layers of MoS2.

[0125] Clause 6: A CFET structure according to any one of clauses 1 to 5, wherein the common gate spans from an upper surface of the IMD layer to a lower surface of the IMD layer.

[0126] Item 7: A CFET structure according to any one of items 1 to 6, wherein the common gate is formed of tungsten W, titanium nitride TiN, or both tungsten (W) and titanium nitride (TiN).

[0127] Item 8: A CFET structure according to any one of Items 1 to Item 7, further comprising: a source spacer between the lower source contact and the common gate and between the upper source contact and the common gate, the source spacer spanning from the upper surface of the IMD layer to the lower surface of the IMD layer; and a drain spacer between the lower drain contact and the common gate and between the upper drain contact and the common gate, the drain spacer spanning from the upper surface of the IMD layer to the lower surface of the IMD layer.

[0128] Item 9: A CFET structure according to any one of Items 1 to 8, wherein the first lower gate oxide layer or the second lower gate oxide layer or both the first lower gate oxide layer and the second lower gate oxide layer are high-k dielectric layers, or wherein the first upper gate oxide layer or the second upper gate oxide layer or both the first lower gate oxide layer and the second lower gate oxide layer are high-k dielectric layers, or both.

[0129] Item 10: A CFET structure according to Item 9, wherein the first lower gate oxide layer or the second lower gate oxide layer or both the first lower gate oxide layer and the second lower gate oxide layer are formed of a combination of hafnium oxide (HfO2) and aluminum oxide (Al2O3) or a combination of Hf, HfO2, and Al2O3, or wherein the first upper gate oxide layer or the second upper gate oxide layer or both the first upper gate oxide layer and the second upper gate oxide layer are formed of a combination of HfO2 and Al2O3 or a combination of Hf, HfO2, and Al2O3, or both of the above.

[0130] Item 11: A CFET structure according to any one of Items 1 to Item 10, further comprising: a lower inner source contact between the lower source contact and the lower GAA gate region; and a lower inner drain contact between the lower GAA gate region and the lower drain contact.

[0131] Item 12: A CFET structure according to Item 11, wherein the lower TMD channel extends into the lower inner source contact and / or into the lower inner drain contact, or wherein the upper TMD channel extends into the upper source contact and / or into the upper drain contact, or both.

[0132] Item 13: A CFET structure according to any one of Items 11 to Item 12, wherein the lower TMD channel is formed of one of tungsten diselenide (WSe2) and molybdenum disulfide (MoS2), and wherein the upper TMD channel is formed of the other of WSe2 and MoS2.

[0133] Item 14: A CFET structure according to any one of Items 1 to Item 13, further comprising: a lower source terminal in the lower IMD layer and electrically coupled to a lower source contact, the lower IMD layer being on a lower surface of the IMD layer; a lower drain terminal in the lower IMD layer and electrically coupled to a lower drain contact; an upper source terminal in the upper IMD layer and electrically coupled to an upper source contact, the upper IMD layer being on an upper surface of the IMD layer; an upper drain terminal in the upper IMD layer and electrically coupled to an upper drain contact; and an upper gate terminal in the upper IMD layer and electrically coupled to a common gate.

[0134] Item 15: The CFET structure according to Item 14 further includes: a source via in the upper IMD layer, the source via being between the upper source terminal and the upper source contact, and electrically coupling the upper source terminal with the upper source contact; a drain via in the upper IMD layer, the drain via being between the upper drain terminal and the upper drain contact, and electrically coupling the upper drain terminal with the upper drain contact; and a gate via in the upper IMD layer between the upper gate terminal and the common gate, and electrically coupling the upper gate terminal with the common gate.

[0135] Clause 16: The CFET structure of any one of clauses 14 to 15, further comprising: a tail via, in the IMD layer and the upper IMD layer, the tail via electrically connecting the lower drain terminal with the upper drain terminal, wherein the CFET structure is configured to function as an inverter.

[0136] Item 17: A CFET structure according to any one of Items 14 to Item 15, further comprising: a second lower source contact and a second lower drain contact in the IMD layer; a second lower GAA gate region in the IMD layer, located between the second lower source contact and the second lower drain contact, the second lower GAA gate region being of the first conductivity type and comprising one or more second lower channel structures, each second lower channel structure comprising: a second lower TMD channel, electrically coupled to the second lower source contact and the second lower drain contact; and a second-first lower gate oxide layer and a second-second lower gate oxide layer, respectively on the lower surface and the upper surface of the second lower TMD channel; a second upper source contact and a second upper drain contact in the IMD layer, above the second lower source contact and the second lower drain contact; a second upper GAA gate region in the IMD layer, above the second lower GAA gate region and between the second upper source contact and the second upper drain contact, the second upper GAA gate region being of the second conductivity type, and The invention comprises one or more second upper channel structures, each of which comprises: a second upper TMD channel electrically coupled to a second upper source contact and a second upper drain contact; and a second-first upper gate oxide layer and a second-second upper gate oxide layer, respectively on the upper surface and the lower surface of the second upper TMD channel; a second common gate in the IMD layer, between the second lower source contact and the second lower drain contact and between the second upper source contact and the second upper drain contact, the second common gate being configured to apply a second common voltage to the second lower channel structure and the second upper channel structure; a second lower drain terminal, in the lower IMD layer and electrically coupled to the second lower drain contact; a second upper drain terminal, in the upper IMD layer and electrically coupled to the second upper drain contact; and a tail via, in the IMD layer and the upper IMD layer, the tail via electrically coupling the second lower drain terminal to the second upper drain terminal, wherein the upper drain terminal is also electrically coupled to the second upper source contact, and wherein the CFET structure is configured to be used as NAND logic.

[0137] Item 18: A CFET structure according to any one of Items 14 to Item 15, further comprising: a third lower source contact and a third lower drain contact in the IMD layer; a third lower GAA gate region in the IMD layer, between the third lower source contact and the third lower drain contact, the third lower GAA gate region being of the first conductivity type and comprising one or more third lower channel structures, each third lower channel structure comprising: a third lower TMD channel, electrically coupled to the third lower source contact and the third lower drain contact; and a third-first lower gate oxide layer and a third-second lower gate oxide layer, respectively on the lower surface and the upper surface of the third lower TMD channel; a third upper source contact and a third upper drain contact in the IMD layer, above the third lower source contact and the third lower drain contact; a third upper GAA gate region in the IMD layer, located above the third lower GAA gate region and between the third upper source contact and the third upper drain contact, the third upper GAA gate region being of the second conductivity type and comprising One or more third upper channel structures, each of the third upper channel structures comprising: a third upper TMD channel electrically coupled to a third upper source contact and a third upper drain contact; and a third-first upper gate oxide layer and a third-second upper gate oxide layer, respectively on the upper surface and the lower surface of the third upper TMD channel; a third common gate in the IMD layer, located between the third lower source contact and the third lower drain contact and between the third upper source contact and the third upper drain contact, the third common gate being configured for applying a third common voltage to the third lower channel structure and the third upper channel structure; a third lower drain terminal, in the lower IMD layer, and electrically coupled to the third lower drain contact; a third upper drain terminal, in the upper IMD layer, and electrically coupled to the third upper drain contact; and a tail via, in the IMD layer and the upper IMD layer, the tail via electrically coupling the third lower drain terminal with the third upper drain terminal, wherein the lower drain terminal is also electrically coupled to the third lower source contact, and wherein the CFET structure is configured to function as NOR logic.

[0138] Clause 19: The CFET structure of any one of clauses 14 to 18, further comprising: a lower protection layer between the lower IMD layer and the IMD layer; and an upper protection layer on the upper IMD layer.

[0139] Item 20: A CFET structure according to any one of items 1 to 19, wherein the lower source contact is formed of palladium (Pd), nickel (Ni), gold (Au), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), ruthenium (Ru), or any combination thereof, and / or wherein the lower drain contact is formed of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof, and / or wherein the upper source contact is formed of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof, and / or the upper drain contact is formed of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof.

[0140] Clause 21: A CFET structure according to any of clauses 1 to 20, wherein the CFET structure is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

[0141] Item 22: A method of manufacturing a complementary field effect transistor (CFET) structure, the method comprising: forming a lower source contact and a lower drain contact in an intermetal dielectric (IMD) layer; forming a lower all-around gate GAA gate region in the IMD layer, the lower GAA gate region being between the lower source contact and the lower drain contact, the lower GAA gate region being of a first conductivity type and comprising one or more lower channel structures, each lower channel structure comprising: a lower transition metal dichalcogenide (TMD) channel electrically coupled to the lower source contact and the lower drain contact; and a first lower gate oxide layer and a second lower gate oxide layer, respectively on the lower surface and the upper surface of the lower TMD channel; forming an upper source contact and an upper drain contact in the IMD layer, the upper source contact and the upper drain contact above the lower source contact and the lower drain contact; forming an upper GAA gate region in the IMD layer, the upper GAA gate region being above the lower GAA gate region and between the upper source contact and the upper drain contact, the upper GAA gate region being of a second conductivity type opposite to the first conductivity type and comprising one or more upper channel structures, each upper channel structure comprising: an upper TMD channel electrically coupled to the upper source contact and the upper drain contact; and a first upper gate oxide layer and a second upper gate oxide layer, respectively on the upper surface and the lower surface of the upper TMD channel; and forming a common gate in the IMD layer, between the lower source contact and the lower drain contact and between the upper source contact and the upper drain contact, the common gate being configured to apply a common voltage to the lower channel structure and the upper channel structure.

[0142] Item 23: A method according to Item 22, wherein each lower channel structure further includes: a first lower work function layer on a lower surface of the first lower gate oxide layer; and a second lower work function layer on an upper surface of the second lower gate oxide layer, and wherein each upper channel structure further includes: a first upper work function layer on a lower surface of the first upper gate oxide layer; and a second upper work function layer on an upper surface of the second upper gate oxide layer.

[0143] Clause 24: The method of any one of clauses 22 to 23, wherein the lower TMD channel is formed of tungsten diselenide (WSe2) and the upper TMD channel is formed of molybdenum disulfide (MoS2).

[0144] Clause 25: The method of any one of clauses 22 to 24, wherein the common gate is formed of tungsten W, titanium nitride TiN, or both tungsten (W) and titanium nitride (TiN).

[0145] Item 26: The method according to any one of Items 22 to Item 25, further comprising: forming a spacer in the IMD layer, including: forming a source spacer between the lower source contact and the common gate and between the upper source contact and the common gate, the source spacer spanning from the upper surface of the IMD layer to the lower surface of the IMD layer; forming a drain spacer between the lower drain contact and the common gate and between the upper drain contact and the common gate, the drain spacer spanning from the upper surface of the IMD layer to the lower surface of the IMD layer.

[0146] Clause 27: The method of any one of clauses 22 to 26, further comprising: forming a lower inner contact in the IMD layer, including: forming a lower inner source contact between the lower source contact and the lower GAA gate region; and forming a lower inner drain contact between the lower GAA gate region and the lower drain contact.

[0147] Item 28: The method of Item 27, wherein the lower TMD channel extends into the lower inner source contact and / or into the lower inner drain contact, or wherein the upper TMD channel extends into the upper source contact and / or into the upper drain contact, or both.

[0148] Item 29: The method according to any one of Items 22 to Item 28, further comprising: forming terminals in an upper IMD layer and a lower IMD layer, including: forming a lower source terminal in the lower IMD layer and electrically coupled to a lower source contact, the lower IMD layer being on a lower surface of the IMD layer; forming a lower drain terminal in the lower IMD layer and electrically coupled to a lower drain contact; forming an upper source terminal in the upper IMD layer and electrically coupled to an upper source contact, the upper IMD layer being on an upper surface of the IMD layer; forming an upper drain terminal in the upper IMD layer and electrically coupled to an upper drain contact; and forming an upper gate terminal in the upper IMD layer and electrically coupled to a common gate.

[0149] Item 30: A method according to Item 29, wherein forming a terminal further comprises: forming a source via in an upper IMD layer, the source via being between an upper source terminal and an upper source contact and electrically coupling the upper source terminal with the upper source contact; forming a drain via in an upper IMD layer, the drain via being between an upper drain terminal and an upper drain contact and electrically coupling the upper drain terminal with the upper drain contact; and forming a gate via in an upper IMD layer, the gate via being between an upper gate terminal and a common gate and electrically coupling the upper gate terminal with the common gate.

[0150] As used herein, the terms "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal" and variations thereof refer interchangeably to any suitable mobile or fixed device that can receive wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smart phones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in motor vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with another device that can receive wireless communication and / or navigation signals, such as through short-range wireless, infrared, wired connections, or other connections, regardless of whether satellite signal reception, assistance data reception, and / or location-related processing occurs at the device or other device. In addition, these terms are intended to include all devices that can communicate with the core network via a radio access network (RAN), including wireless communication devices and wired communication devices, and the UE can be connected to external networks such as the Internet and other UEs through the core network. Of course, other mechanisms for connecting to the core network and / or the Internet are also possible for the UE, such as through a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11, etc.). The UE can be implemented by any of a variety of types of devices, including but not limited to: a printed circuit (PC) card, a compact flash device, an external modem or an internal modem, a wireless phone or a wired phone, a smart phone, a tablet computer, a tracking device, an asset tag, etc. The communication link through which the UE can send a signal to the RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). The communication link through which the RAN can send a signal to the UE is called a downlink or forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). The term traffic channel (TCH) used herein may refer to one of an uplink / reverse or downlink / forward traffic channel.

[0151] Wireless communication between electronic devices can be based on different technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiplexing (OFDM), global system for mobile communications (GSM), 3GPP long term evolution (LTE), 5G new radio, Bluetooth (BT), Bluetooth low energy (BLE), IEEE 802.11 (WiFi), and IEEE802.15.4 (Zigbee / Thread) or other protocols that can be used in wireless communication networks or data communication networks. Bluetooth low energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network technology designed and sold by the Bluetooth Special Interest Group, aiming to provide significantly reduced power consumption and cost while maintaining a similar communication range. With the adoption of Bluetooth Core Specification Version 4.0, BLE was incorporated into the main Bluetooth standard in 2010 and updated in Bluetooth 5.

[0152] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as preferred over other examples. Likewise, the term "example" does not mean that all examples include the discussed features, advantages, or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Furthermore, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0153] It should be noted that the terms “connected”, “coupled” or any variations thereof mean any connection or coupling, direct or indirect, between elements, and may encompass the presence of intermediate elements between two elements that are “connected” or “coupled” together via intermediate elements, unless the connection is explicitly disclosed as a direct connection.

[0154] Any reference to an element using designations such as "first," "second," etc. herein does not limit the quantity and / or order of these elements. Instead, these designations are used as a convenient method of distinguishing two or more elements and / or element instances. In addition, unless otherwise stated, a collection of elements may include one or more elements.

[0155] Those skilled in the art will appreciate that any of a variety of different techniques and methods may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0156] Nothing described, illustrated, or claimed in this application is intended to dedicate any component, act, feature, benefit, advantage, or equivalent to the public regardless of whether the component, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0157] It can be seen in the above detailed description that different features are combined together in the examples. This disclosure should not be understood as the following intention: the examples claimed have more features than those explicitly mentioned in the corresponding claims. On the contrary, the present disclosure may include less than all the features of the disclosed single examples. Therefore, the following claims should be further deemed to be incorporated into the specification, where each claim itself can be a separate example. Although each claim itself can be a separate example, it should be noted that although a dependent claim can refer to a specific combination with one or more claims in a claim, other examples can also cover or include a combination of the dependent claim with the subject matter of any other dependent claim or any feature with other dependent and independent claims. Such a combination is proposed herein unless it is explicitly stated that it is not intended to be a specific combination. In addition, the following situation is also intended: the features of a claim can also be included in any other independent claim, even if the claim is not directly subordinate to the independent claim.

[0158] It should also be noted that the methods, systems, and apparatuses disclosed in the specification or claims may be implemented by a device including means for performing the corresponding actions and / or functions of the disclosed methods.

[0159] In addition, in some examples, a single action can be subdivided into one or more sub-actions or include one or more sub-actions. Such sub-actions can be included in the disclosure of a single action and are part of the disclosure of a single action.

[0160] Although the foregoing disclosure shows illustrative examples of the present disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and / or actions of the method claims according to the examples of the present disclosure described herein do not need to be performed in any particular order. Additionally, well-known elements will not be described in detail or may be omitted to avoid confusion regarding the relevant details of the various aspects and examples disclosed herein. In addition, although the elements of the present disclosure may be described or claimed in the singular, the plural form is encompassed unless expressly stated to be limited to the singular form.

Claims

1. A complementary field effect transistor (CFET) structure, comprising: a lower source contact and a lower drain contact in an intermetal dielectric (IMD) layer; a lower all-around gate (GAA) gate region, in the IMD layer, between the lower source contact and the lower drain contact, the lower GAA gate region being of a first conductivity type and comprising one or more lower channel structures, each lower channel structure comprising: a lower transition metal dichalcogenide (TMD) channel electrically coupled to the lower source contact and the lower drain contact; and a first lower gate oxide layer and a second lower gate oxide layer, respectively on a lower surface and an upper surface of the lower TMD channel; an upper source contact and an upper drain contact in the IMD layer, above the lower source contact and the lower drain contact; an upper GAA gate region in the IMD layer, above the lower GAA gate region and between the upper source contact and the upper drain contact, the upper GAA gate region being of a second conductivity type opposite to the first conductivity type and comprising one or more upper channel structures, each upper channel structure comprising: an upper TMD channel electrically coupled to the upper source contact and the upper drain contact; and a first upper gate oxide layer and a second upper gate oxide layer, respectively on a lower surface and an upper surface of the upper TMD channel; and The common gate in the IMD layer is located between the lower source contact and the lower drain contact and between the upper source contact and the upper drain contact, and is configured to apply a common voltage to the lower channel structure and the upper channel structure.

2. The CFET structure according to claim 1, Each lower channel structure further comprises: a first lower work function layer on a lower surface of the first lower gate oxide layer; as well as a second lower work function layer on an upper surface of the second lower gate oxide layer, and Each upper channel structure further comprises: a first upper work function layer on a lower surface of the first upper gate oxide layer; as well as A second upper work function layer is on an upper surface of the second upper gate oxide layer.

3. The CFET structure according to claim 2, wherein the first lower work function layer or the second lower work function layer or both the first lower work function layer and the second lower work function layer are formed of one or both of titanium nitride (TiN) or titanium aluminide (TiAl), or wherein the first upper work function layer or the second upper work function layer or both the first lower work function layer and the second lower work function layer are formed of one or both of TiN and TiAl, or Both of the above.

4. The CFET structure of claim 1, wherein the lower TMD channel is formed of tungsten diselenide (WSe2) and the upper TMD channel is formed of molybdenum disulfide (MoS2).

5. The CFET structure according to claim 4, wherein the lower TMD channel is formed by one or two layers of WSe2, and The upper TMD channel is formed by one or two layers of MoS2. The CFET structure of claim 1 , wherein the common gate spans from an upper surface of the IMD layer to a lower surface of the IMD layer. 7 . The CFET structure of claim 1 , wherein the common gate is formed of tungsten (W), titanium nitride (TiN), or both tungsten (W) and titanium nitride (TiN).

8. The CFET structure of claim 1, further comprising: a source spacer between the lower source contact and the common gate and between the upper source contact and the common gate, the source spacer spanning from the upper surface of the IMD layer to the lower surface of the IMD layer; as well as A drain spacer is between the lower drain contact and the common gate and between the upper drain contact and the common gate, the drain spacer spanning from the upper surface of the IMD layer to the lower surface of the IMD layer.

9. The CFET structure according to claim 1, wherein the first lower gate oxide layer or the second lower gate oxide layer or both the first lower gate oxide layer and the second lower gate oxide layer are high-k dielectric layers, or wherein the first upper gate oxide layer or the second upper gate oxide layer or both the first lower gate oxide layer and the second lower gate oxide layer are high-k dielectric layers, or Both of the above.

10. The CFET structure according to claim 9, wherein the first lower gate oxide layer or the second lower gate oxide layer or both are formed of a combination of hafnium oxide (HfO2) and aluminum oxide (Al2O3) or a combination of Hf, HfO2 and Al2O3, or wherein the first upper gate oxide layer or the second upper gate oxide layer or both the first upper gate oxide layer and the second upper gate oxide layer are formed of a combination of HfO2 and Al2O3 or a combination of Hf, HfO2 and Al2O3, or Both of the above.

11. The CFET structure of claim 1 , further comprising: a lower inner source contact between the lower source contact and the lower GAA gate region; as well as A lower inner drain contact is between the lower GAA gate region and the lower drain contact.

12. The CFET structure according to claim 11, wherein the lower TMD channel extends into the lower inner source contact and / or into the lower inner drain contact, or wherein the upper TMD channel extends into the upper source contact and / or into the upper drain contact, or Both of the above.

13. The CFET structure according to claim 11, wherein the lower TMD channel is formed of one of tungsten diselenide (WSe2) and molybdenum disulfide (MoS2), and The upper TMD channel is formed by the other of WSe2 and MoS2.

14. The CFET structure of claim 1 , further comprising: a lower source terminal in a lower IMD layer and electrically coupled to the lower source contact, the lower IMD layer being on a lower surface of the IMD layer; a lower drain terminal in the lower IMD layer and electrically coupled to the lower drain contact; an upper source terminal in an upper IMD layer and electrically coupled to the upper source contact, the upper IMD layer being on an upper surface of the IMD layer; an upper drain terminal in the upper IMD layer and electrically coupled to the upper drain contact; as well as An upper gate terminal is in the upper IMD layer and electrically coupled to the common gate.

15. The CFET structure of claim 14, further comprising: a source via in the upper IMD layer, the source via being located between and electrically coupling the upper source terminal and the upper source contact; a drain via in the upper IMD layer, the drain via being between and electrically coupling the upper drain terminal and the upper drain contact; as well as A gate via is provided in the upper IMD layer, the gate via being located between the upper gate terminal and the common gate and electrically coupling the upper gate terminal with the common gate.

16. The CFET structure of claim 14, further comprising: a tail via hole, in the IMD layer and the upper IMD layer, the tail via hole electrically connecting the lower drain terminal with the upper drain terminal, Wherein the CFET structure is configured to function as an inverter.

17. The CFET structure of claim 14, further comprising: a second lower source contact and a second lower drain contact in the IMD layer; A second lower GAA gate region in the IMD layer is located between the second lower source contact and the second lower drain contact, the second lower GAA gate region is of the first conductivity type and includes one or more second lower channel structures, each of the second lower channel structures includes: a second lower TMD channel electrically coupled to the second lower source contact and the second lower drain contact; and a second-first lower gate oxide layer and a second-second lower gate oxide layer, respectively on a lower surface and an upper surface of the second lower TMD channel; a second upper source contact and a second upper drain contact in the IMD layer, above the second lower source contact and the second lower drain contact; A second upper GAA gate region in the IMD layer, above the second lower GAA gate region and between the second upper source contact and the second upper drain contact, the second upper GAA gate region being of the second conductivity type and comprising one or more second upper channel structures, each second upper channel structure comprising: a second upper TMD channel electrically coupled to the second upper source contact and the second upper drain contact; and a second-first upper gate oxide layer and a second-second upper gate oxide layer, respectively on an upper surface and a lower surface of the second upper TMD channel; a second common gate in the IMD layer, located between the second lower source contact and the second lower drain contact and between the second upper source contact and the second upper drain contact, the second common gate being configured to apply a second common voltage to the second lower channel structure and the second upper channel structure; a second lower drain terminal in the lower IMD layer and electrically coupled to the second lower drain contact; a second upper drain terminal in the upper IMD layer and electrically coupled to the second upper drain contact; and a tail via, in the IMD layer and the upper IMD layer, the tail via electrically coupling the second lower drain terminal with the second upper drain terminal, wherein the upper drain terminal is also electrically coupled to the second upper source contact, and The CFET structure is configured to function as NAND logic.

18. The CFET structure of claim 14, further comprising: a third lower source contact and a third lower drain contact in the IMD layer; The third lower GAA gate region in the IMD layer is located between the third lower source contact and the third lower drain contact, the third lower GAA gate region is of the first conductivity type and includes one or more third lower channel structures, each of the third lower channel structures includes: a third lower TMD channel electrically coupled to the third lower source contact and the third lower drain contact; and a third-first lower gate oxide layer and a third-second lower gate oxide layer, respectively on the lower surface and the upper surface of the third lower TMD channel; a third upper source contact and a third upper drain contact in the IMD layer, above the third lower source contact and the third lower drain contact; The third upper GAA gate region in the IMD layer is located above the third lower GAA gate region and between the third upper source contact and the third upper drain contact, the third upper GAA gate region is of the second conductivity type and includes one or more third upper channel structures, each of the third upper channel structures includes: a third upper TMD channel electrically coupled to the third upper source contact and the third upper drain contact; and a third-first upper gate oxide layer and a third-second upper gate oxide layer, respectively on the upper surface and the lower surface of the third upper TMD channel; a third common gate in the IMD layer, located between the third lower source contact and the third lower drain contact and between the third upper source contact and the third upper drain contact, the third common gate being configured to apply a third common voltage to the third lower channel structure and the third upper channel structure; a third lower drain terminal in the lower IMD layer and electrically coupled to the third lower drain contact; a third upper drain terminal in the upper IMD layer and electrically coupled to the third upper drain contact; and a tail via hole, in the IMD layer and the upper IMD layer, the tail via hole electrically coupling the third lower drain terminal with the third upper drain terminal, wherein the lower drain terminal is also electrically coupled to the third lower source contact, and The CFET structure is configured to function as NOR logic.

19. The CFET structure of claim 14, further comprising: a lower protection layer, between the lower IMD layer and the IMD layer; as well as An upper protection layer is on the upper IMD layer.

20. The CFET structure according to claim 1, wherein the lower source contact is formed of palladium (Pd), nickel (Ni), gold (Au), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), ruthenium (Ru), or any combination thereof, and / or wherein the lower drain contact is formed of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof, and / or wherein the upper source contact is formed of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof, and / or The upper drain contact is formed of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof.

21. A CFET structure according to claim 1, wherein the CFET structure is incorporated into a device, and the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

22. A method of manufacturing a complementary field effect transistor (CFET) structure, the method comprising: forming a lower source contact and a lower drain contact in an intermetal dielectric (IMD) layer; A lower all-around gate (GAA) gate region is formed in the IMD layer, the lower GAA gate region is between the lower source contact and the lower drain contact, the lower GAA gate region is of a first conductivity type and includes one or more lower channel structures, each lower channel structure includes: a lower transition metal dichalcogenide (TMD) channel electrically coupled to the lower source contact and the lower drain contact; and a first lower gate oxide layer and a second lower gate oxide layer, respectively on a lower surface and an upper surface of the lower TMD channel; forming an upper source contact and an upper drain contact in the IMD layer, the upper source contact and the upper drain contact being above the lower source contact and the lower drain contact; forming an upper GAA gate region in the IMD layer, the upper GAA gate region being above the lower GAA gate region and between the upper source contact and the upper drain contact, the upper GAA gate region being of a second conductivity type opposite to the first conductivity type and comprising one or more upper channel structures, each upper channel structure comprising: an upper TMD channel electrically coupled to the upper source contact and the upper drain contact; and a first upper gate oxide layer and a second upper gate oxide layer, respectively on an upper surface and a lower surface of the upper TMD channel; and A common gate is formed in the IMD layer between the lower source contact and the lower drain contact and between the upper source contact and the upper drain contact, the common gate being configured to apply a common voltage to the lower channel structure and the upper channel structure.

23. The method according to claim 22, Each lower channel structure further comprises: a first lower work function layer on a lower surface of the first lower gate oxide layer; as well as a second lower work function layer on an upper surface of the second lower gate oxide layer, and Each upper channel structure further comprises: a first upper work function layer on a lower surface of the first upper gate oxide layer; as well as A second upper work function layer is on an upper surface of the second upper gate oxide layer.

24. The method of claim 22, wherein the lower TMD channel is formed of tungsten diselenide (WSe2) and the upper TMD channel is formed of molybdenum disulfide (MoS2).

25. The method of claim 22, wherein the common gate is formed of tungsten (W), titanium nitride (TiN), or both tungsten (W) and titanium nitride (TiN).

26. The method of claim 22, further comprising: forming a spacer in the IMD layer, comprising: forming a source spacer between the lower source contact and the common gate and between the upper source contact and the common gate, the source spacer spanning from an upper surface of the IMD layer to a lower surface of the IMD layer; and Drain spacers are formed between the lower drain contact and the common gate and between the upper drain contact and the common gate, the drain spacers spanning from the upper surface of the IMD layer to the lower surface of the IMD layer.

27. The method of claim 22, further comprising: forming a lower inner contact in the IMD layer, comprising: forming a lower inner source contact between the lower source contact and the lower GAA gate region; and A lower inner drain contact is formed between the lower GAA gate region and the lower drain contact.

28. The method according to claim 27, wherein the lower TMD channel extends into the lower inner source contact and / or into the lower inner drain contact, or wherein the upper TMD channel extends into the upper source contact and / or into the upper drain contact, or Both of the above.

29. The method of claim 22, further comprising: Terminals are formed in the upper IMD layer and the lower IMD layer, including: forming a lower source terminal in the lower IMD layer and electrically coupled to the lower source contact, the lower IMD layer being on a lower surface of the IMD layer; forming a lower drain terminal in the lower IMD layer and electrically coupled to the lower drain contact; forming an upper source terminal in the upper IMD layer and electrically coupled to the upper source contact, the upper IMD layer being on an upper surface of the IMD layer; forming an upper drain terminal in the upper IMD layer and electrically coupled to the upper drain contact; and An upper gate terminal is formed in the upper IMD layer and electrically coupled to the common gate.

30. The method of claim 29, wherein forming the terminal further comprises: forming a source via in the upper IMD layer, the source via being between the upper source terminal and the upper source contact and electrically coupling the upper source terminal with the upper source contact; forming a drain via in the upper IMD layer, the drain via being between the upper drain terminal and the upper drain contact and electrically coupling the upper drain terminal with the upper drain contact; as well as A gate via is formed in the upper IMD layer, the gate via being between the upper gate terminal and the common gate and electrically coupling the upper gate terminal with the common gate.

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