Display substrate and display device

Abstract

A display substrate and a display device. The pixel driving circuit includes a first storage capacitor, a second storage capacitor, at least one shielding electrode and at least one double-gate transistor. The first storage capacitor includes at least a first plate (71) and a third plate (73), and the first plate (71) and the third plate (73) at least partially overlap on the substrate. The second storage capacitor includes at least a second plate (72) and a fourth plate (74), and the second plate (72) and the fourth plate (74) at least partially overlap on the substrate. The second plate (72) is connected to the third plate (73), and the fourth plate (74) is connected to a first power supply line (51). The shielding electrode at least partially overlaps with a node between two gate electrodes of the double-gate transistor on the substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, and low cost. With the continuous development of display technology, flexible display devices with OLED or QLED as light emitting devices and signal control by thin film transistors (TFT) have become the mainstream products in the current display field. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0004] In one aspect, the present disclosure provides a display substrate, comprising a driving circuit layer disposed on a substrate, the driving circuit layer comprising at least a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising a first storage capacitor, a second storage capacitor, at least one shielding electrode, and at least one transistor with a double-gate structure, the first storage capacitor comprising at least a first plate and a third plate, a projection of the first plate on the substrate at least partially overlapping a projection of the third plate on the substrate; the second storage capacitor comprising at least a second plate and a fourth plate, a projection of the second plate on the substrate at least partially overlapping a projection of the fourth plate on the substrate; the second plate being connected to the third plate, and the fourth plate being connected to a first power supply line; a projection of the shielding electrode on the substrate at least partially overlapping a node between two gate electrodes of the transistor with the double-gate structure on the substrate.

[0005] In an exemplary embodiment, the at least one transistor with the double-gate structure comprises an initialization transistor, a first pole of the initialization transistor being connected to a first initialization signal line, and a second pole of the initialization transistor being connected to the first plate of the first storage capacitor; the at least one shielding electrode comprises a first shielding electrode, the first shielding electrode being connected to the fourth plate, and a projection of the first shielding electrode on the substrate at least partially overlapping the node between the two gate electrodes of the initialization transistor on the substrate.

[0006] In an exemplary embodiment, the fourth plate and the first shield electrode are in one piece.

[0007] In an exemplary embodiment, the first shield electrode comprises a first extension and a first shield segment, the first extension is in a shape of a strip extending along a second direction, a first end of the first extension is connected to the fourth plate, a second end of the first extension is connected to a first end of the first shield segment; the first shield segment is in a shape of a strip extending along a first direction, a first end of the first shield segment is connected to the second end of the first extension, a second end of the first shield segment extends along the first direction, a projection of the first shield segment on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the first initialization transistor on the substrate, the first direction intersects the second direction.

[0008] In an exemplary embodiment, the at least one circuit unit further comprises at least one first power supply connection line extending along the first direction, the first power supply line is in a shape of a line extending along a second direction, the first direction intersects the second direction; the first power supply line is connected to the first power supply connection line, forming a mesh structure for transmitting a first power supply signal.

[0009] In an exemplary embodiment, the at least one transistor of the double-gate structure comprises an initialization transistor, a first pole of the initialization transistor is connected to a first initialization signal line, a second pole of the initialization transistor is connected to a first plate of the first storage capacitor; the at least one shield electrode comprises a first shield electrode, the first shield electrode is connected to the first power supply connection line, a projection of the first shield electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the initialization transistor on the substrate.

[0010] In an exemplary embodiment, the first power supply connection line and the first shield electrode are in one piece.

[0011] In an exemplary embodiment, the at least one circuit unit further comprises a shield connection line, the shield connection line is connected to the first power supply connection line; the at least one transistor of the double-gate structure comprises an initialization transistor, a first pole of the initialization transistor is connected to a first initialization signal line, a second pole of the initialization transistor is connected to a first plate of the first storage capacitor; the at least one shield electrode comprises a first shield electrode, the first shield electrode is connected to the shield connection line, a projection of the first shield electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the initialization transistor on the substrate.

[0012] In an example embodiment, the at least one double-gate structure transistor comprises a compensation transistor, a first electrode of the compensation transistor is connected with a first electrode plate of the first storage capacitor; the at least one shielding electrode comprises a second shielding electrode, the second shielding electrode is connected with the fourth electrode plate, a projection of the second shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the compensation transistor on the substrate.

[0013] In an example embodiment, the fourth electrode plate and the second shielding electrode are an integral structure.

[0014] In an example embodiment, the second shielding electrode comprises a second extension segment and a second shielding segment, the second extension segment is in a strip shape extending along a second direction, a first end of the second extension segment is connected with the fourth electrode plate, a second end of the second extension segment is connected with a first end of the second shielding segment; the second shielding segment is in a strip shape extending along a first direction, a first end of the second shielding segment is connected with the second end of the second extension segment, a second end of the second shielding segment extends along an opposite direction of the first direction, a projection of the second shielding segment on the substrate at least partially overlaps with a projection of the node between the two gate electrodes of the compensation transistor on the substrate, the first direction intersects with the second direction.

[0015] In an example embodiment, the at least one double-gate structure transistor comprises a compensation transistor, a first electrode of the compensation transistor is connected with a first electrode plate of the first storage capacitor; the at least one shielding electrode comprises a second shielding electrode, the second shielding electrode is connected with the first power connection line, a projection of the second shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the compensation transistor on the substrate.

[0016] In an example embodiment, the first power connection line and the second shielding electrode are an integral structure.

[0017] In an example embodiment, the at least one circuit unit further comprises a shielding connection line, the shielding connection line is connected with the first power connection line; the at least one double-gate structure transistor comprises a compensation transistor, a first electrode of the compensation transistor is connected with a first electrode plate of the first storage capacitor; the at least one shielding electrode comprises a second shielding electrode, the second shielding electrode is connected with the shielding connection line, a projection of the second shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the compensation transistor on the substrate.

[0018] In an exemplary embodiment, the transistor of the at least one double-gate structure comprises a data write transistor, a first electrode of the data write transistor is connected with a data signal line, and a second electrode of the data write transistor is connected with a second electrode plate of a second storage capacitor; the at least one shielding electrode comprises a third shielding electrode, the third shielding electrode is connected with the fourth electrode plate, and a projection of the third shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the data write transistor on the substrate.

[0019] In an exemplary embodiment, the fourth electrode plate and the third shielding electrode are an integral structure.

[0020] In an exemplary embodiment, the transistor of the at least one double-gate structure comprises a reference transistor, a first electrode of the reference transistor is connected with a second reference signal line, and a second electrode of the reference transistor is connected with a second electrode plate of a second storage capacitor; the at least one shielding electrode comprises a fourth shielding electrode, the fourth shielding electrode is connected with the fourth electrode plate, and a projection of the fourth shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the reference transistor on the substrate.

[0021] In an exemplary embodiment, the fourth electrode plate and the fourth shielding electrode are an integral structure.

[0022] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0023] In another aspect, the present disclosure also provides a display substrate, comprising a driving circuit layer disposed on a base, the driving circuit layer comprising at least a plurality of circuit units, at least one of the circuit units comprising a pixel driving circuit, the pixel driving circuit comprising a first storage capacitor, a second storage capacitor, at least one shielding electrode, and at least one double-gate transistor, the first storage capacitor comprising at least a first plate and a third plate, the second storage capacitor comprising at least a second plate and a fourth plate, a normal projection of the shielding electrode on the base at least partially overlapping a node between two gate electrodes of the double-gate transistor on the base; the at least one double-gate transistor comprising a first transistor to a ninth transistor, the pixel driving circuit further comprising a first node, a second node, a third node, a fourth node, and a fifth node, the first node being connected to a second electrode of the first transistor, a first electrode of the second transistor, a gate electrode of the third transistor, and the first plate of the first storage capacitor respectively, the second node being connected to a first electrode of the third transistor, a second electrode of the eighth transistor, and a second electrode of the fifth transistor respectively, the third node being connected to a second electrode of the second transistor, a second electrode of the third transistor, and a first electrode of the sixth transistor respectively, the fourth node being connected to a second electrode of the sixth transistor and a second electrode of the seventh transistor respectively, the fifth node being connected to a second electrode of the fourth transistor, a second electrode of the ninth transistor, a third plate of the first storage capacitor, and a second plate of the second storage capacitor respectively; and the fourth plate of the second storage capacitor being connected to a first power supply line.

[0024] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0025] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and serve to explain the principles of the present disclosure, and should not be considered limiting of the present disclosure's scope.

[0027] Figure 1 FIG. 1 is a structural schematic diagram of a display device;

[0028] Figure 2 FIG. 2 is a plan structural schematic diagram of a display substrate;

[0029] Figure 3 FIG. 3 is a cross-sectional structural schematic diagram of a display substrate;

[0030] Figure 4 FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0031] Figure 5This is a schematic diagram of a planar structure of a display substrate, which is an exemplary embodiment of the present disclosure.

[0032] Figure 6 for Figure 5 Enlarged view of the first and second storage capacitor regions in the middle;

[0033] Figure 7 This is a schematic diagram of a display substrate after a semiconductor layer pattern has been formed.

[0034] Figure 8A and Figure 8B This is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0035] Figure 9A and Figure 9B This is a schematic diagram of a display substrate after the formation of a second conductive layer pattern according to the present disclosure;

[0036] Figure 10 This is a schematic diagram of a display substrate after the formation of a fourth insulating layer pattern according to the present disclosure;

[0037] Figure 11A and Figure 11B This is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0038] Figure 12 This is a schematic diagram of a display substrate after the formation of a fifth insulating layer pattern according to the present disclosure;

[0039] Figure 13A and 13B This is a schematic diagram of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure;

[0040] Figure 14 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0041] Figure 15a for Figure 14 A schematic diagram of the second conductive layer in the middle;

[0042] Figure 15b for Figure 14 A schematic diagram of the third conductive layer in the middle;

[0043] Figure 16 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0044] Figure 17 for Figure 16 A schematic diagram of the third conductive layer in the middle;

[0045] Figure 18 This is an enlarged view of the regions of the first and second storage capacitors in a display substrate according to an exemplary embodiment of the present disclosure;

[0046] Figure 19 FIG. 6 is a schematic view of a third conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0047] Figure 20 FIG. 6 is a schematic view of a third conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0048] Figure 21 FIG. 6 is a schematic view of a third conductive layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0049] BRIEF DESCRIPTION OF THE DRAWINGS

[0050] 11 - first active layer; 12 - second active layer; 13 - third active layer;

[0051] 14 - fourth active layer; 15 - fifth active layer; 16 - sixth active layer;

[0052] 17 - seventh active layer; 18 - eighth active layer; 19 - ninth active layer;

[0053] 21 - first gate electrode; 22 - second gate electrode; 24 - fourth gate electrode;

[0054] 25 - fifth gate electrode; 26 - sixth gate electrode; 29 - ninth gate electrode;

[0055] 31 - first light emitting signal line; 32 - second light emitting signal line; 33 - repair line;

[0056] 36 - first shielding electrode; 37 - second shielding electrode; 38 - third shielding electrode;

[0057] 39 - fourth shielding electrode; 41 - first connection electrode; 42 - second connection electrode;

[0058] 43 - third connection electrode; 44 - fourth connection electrode; 45 - fifth connection electrode;

[0059] 46 - sixth connection electrode; 47 - seventh connection electrode; 48 - eighth connection electrode;

[0060] 49 - ninth connection electrode; 51 - first power supply line; 53 - data signal line;

[0061] 54 - reference signal connection line; 55 - anode connection electrode; 61 - first scan signal line;

[0062] 62 - second scan signal line; 63 - third scan signal line; 64 - fourth scan signal line;

[0063] 65 - fifth scan signal line; 68 - first power supply connection line; 69 - shield connection line;

[0064] 71 - first plate; 72 - second plate; 73 - third plate;

[0065] 74 - fourth plate; 81 - first initial signal line; 82 - second initial signal line;

[0066] 91 - first reference signal line; 92 - second reference signal line;

[0067] 101 - substrate; 102 - driving circuit layer; 103 - light emitting structure layer;

[0068] 104 - encapsulation structure layer; 10 - first active connection line; 20 - second active connection line. DETAILED DESCRIPTION

[0069] For the purpose of making the object, technical scheme and advantages of the present disclosure more clear, the following will describe the embodiments of the present disclosure in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. It can be easily understood by those skilled in the art that the means and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0070] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0071] The ordinal numbers "first", "second", "third" and the like in the present specification are set in order to avoid confusion of the constituent elements, and are not intended to be limited in terms of quantity.

[0072] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or directional relationship of components are used to describe the positional relationship of components with reference to the drawings for the convenience of explanation and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting on the present disclosure. The positional relationship of components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0073] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0074] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0075] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit during operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other, and "source terminal" and "drain terminal" can be exchanged with each other.

[0076] In this specification, "electrically connected" includes the case where components are connected together through an element having some electrical effect. The element having some electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected components. Examples of the element having some electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0077] In this specification, "parallel" means a state where an angle formed by two straight lines is -10° or more and 10° or less, and thus, an angle of -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is 80° or more and 100° or less, and thus, an angle of 85° or more and 95° or less is also included.

[0078] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be sometimes interchanged with "a conductive film". Similarly, "an insulating film" can be sometimes interchanged with "an insulating layer".

[0079] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily strict, and can be an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or the like.

[0080] In this specification, "about" means not strict limitation of a boundary and allows a value within a range of a process and measurement error.

[0081] Figure 1 A structure diagram of a display device. As Figure 1As shown, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller connected to the data driver, the scan driver, and the light emitting driver, respectively, the data driver connected to a plurality of data signal lines (D1 to Dn), respectively, the scan driver connected to a plurality of scan signal lines (S1 to Sm), respectively, and the light emitting driver connected to a plurality of light emitting signal lines (E1 to Eo), respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit connected to the scan signal line, the light emitting signal line, and the data signal line, respectively, and the light emitting unit can include a light emitting device, the light emitting device connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver can sample the gray scale value using the clock signal, and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signals having on-pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signals in a manner that sequentially transfers the scan start signal provided in the form of an on-pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signals having off-pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signals in a manner that sequentially transfers the emission stop signal provided in the form of an off-pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0082] Figure 2This is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a border area surrounding the display area. Figure 2 As shown, the display area of ​​the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0083] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0084] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0085] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels within the substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0086] In an example embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 can include a plurality of circuit units, which can at least include a pixel driving circuit, and the pixel driving circuit can include a plurality of transistors and a storage capacitor. The light emitting structure layer 103 can include a plurality of light emitting units, which can at least include a light emitting device, and the light emitting device can include an anode, an organic light emitting layer and a cathode, the anode is connected with the pixel driving circuit, the organic light emitting layer is connected with the anode, and the cathode is connected with the organic light emitting layer, and the organic light emitting layer emits light of a corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external water vapor from entering the light emitting structure layer 103.

[0087] In an example embodiment, the organic light emitting layer can include a light emitting layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL).

[0088] An example embodiment of the present disclosure provides a display substrate, which includes a driving circuit layer arranged on a substrate, the driving circuit layer including a plurality of circuit units, at least one of which includes a pixel driving circuit, the pixel driving circuit including a first storage capacitor, a second storage capacitor, at least one shielding electrode and at least one transistor with a double-gate structure, the first storage capacitor including at least a first electrode plate and a third electrode plate, a projection of the first electrode plate on the substrate at least partially overlapping a projection of the third electrode plate on the substrate; the second storage capacitor including at least a second electrode plate and a fourth electrode plate, a projection of the second electrode plate on the substrate at least partially overlapping a projection of the fourth electrode plate on the substrate; the second electrode plate is connected with the third electrode plate, and the fourth electrode plate is connected with a first power supply line; a projection of the shielding electrode on the substrate at least partially overlaps a node between two gate electrodes of the transistor with the double-gate structure on the substrate.

[0089] In an exemplary embodiment, the at least one double-gate structure transistor comprises an initialization transistor, a first electrode of the initialization transistor is connected with a first initialization signal line, a second electrode of the initialization transistor is connected with a first electrode plate of the first storage capacitor; the at least one shielding electrode comprises a first shielding electrode, the first shielding electrode is connected with the fourth electrode plate, a projection of the first shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the initialization transistor on the substrate.

[0090] In an exemplary embodiment, the at least one double-gate structure transistor comprises an initialization transistor, a first electrode of the initialization transistor is connected with a first initialization signal line, a second electrode of the initialization transistor is connected with a first electrode plate of the first storage capacitor; the at least one shielding electrode comprises a first shielding electrode, the first shielding electrode is connected with the fourth electrode plate, a projection of the first shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the initialization transistor on the substrate.

[0091] In an exemplary embodiment, the at least one double-gate structure transistor comprises an initialization transistor, a first electrode of the initialization transistor is connected with a first initialization signal line, a second electrode of the initialization transistor is connected with a first electrode plate of the first storage capacitor; the at least one shielding electrode comprises a first shielding electrode, the first shielding electrode is connected with the fourth electrode plate, a projection of the first shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the initialization transistor on the substrate.

[0092] In an exemplary embodiment, the at least one double-gate structure transistor comprises an initialization transistor, a first electrode of the initialization transistor is connected with a first initialization signal line, a second electrode of the initialization transistor is connected with a first electrode plate of the first storage capacitor; the at least one shielding electrode comprises a first shielding electrode, the first shielding electrode is connected with the fourth electrode plate, a projection of the first shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the initialization transistor on the substrate.

[0093] In an example embodiment, the second shielding electrode comprises a second extension section and a second shielding section, the second extension section is in a shape of a strip extending along a second direction, a first end of the second extension section is connected with the fourth plate, and a second end of the second extension section is connected with a first end of the second shielding section; the second shielding section is in a shape of a strip extending along a first direction, a first end of the second shielding section is connected with the second end of the second extension section, and a second end of the second shielding section extends along a reverse direction of the first direction, and a projection of the second shielding section on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the compensation transistor on the substrate.

[0094] In an example embodiment, the at least one double-gate structure transistor comprises a compensation transistor, a first electrode of the compensation transistor is connected with a first plate of the first storage capacitor; and the at least one shielding electrode comprises a second shielding electrode, the second shielding electrode is connected with the first power connection line, and a projection of the second shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the compensation transistor on the substrate.

[0095] In an example embodiment, the at least one circuit unit further comprises a shielding connection line, the shielding connection line is connected with the first power connection line; the at least one double-gate structure transistor comprises a compensation transistor, a first electrode of the compensation transistor is connected with a first plate of the first storage capacitor; and the at least one shielding electrode comprises a second shielding electrode, the second shielding electrode is connected with the shielding connection line, and a projection of the second shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the compensation transistor on the substrate.

[0096] In an example embodiment, the at least one double-gate structure transistor comprises a data write transistor, a first electrode of the data write transistor is connected with a data signal line, and a second electrode of the data write transistor is connected with a second plate of a second storage capacitor; and the at least one shielding electrode comprises a third shielding electrode, the third shielding electrode is connected with the fourth plate, and a projection of the third shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the data write transistor on the substrate.

[0097] In an example embodiment, the transistor of the at least one double-gate structure comprises a reference transistor, a first pole of the reference transistor is connected with a second reference signal line, a second pole of the reference transistor is connected with a second pole plate of a second storage capacitor; the at least one shielding electrode comprises a fourth shielding electrode, the fourth shielding electrode is connected with the fourth pole plate, a normal projection of the fourth shielding electrode on the substrate at least partially overlaps a normal projection of a node between two gate electrodes of the reference transistor on the substrate.

[0098] The substrate of the present disclosure is exemplified by some example embodiments below.

[0099] Figure 4 An equivalent circuit diagram of a pixel driving circuit for example embodiments of the present disclosure is shown. In an example embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C or 9T2C structure. As shown, the pixel driving circuit of example embodiments of the present disclosure can be a 9T2C structure, which can include 9 transistors (first transistor T1 to ninth transistor T9) and 2 storage capacitors (first storage capacitor C1 and second storage capacitor C2), and the pixel driving circuit is connected with 12 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first emission signal line EM1, second emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, first reference signal line REF1, second reference signal line REF2, data signal line DATA and first power supply line VDD). Figure 4

[0100] In an example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, a fourth node N4 and a fifth node N5. Wherein the first node N1 is connected with a second pole of the first transistor, a first pole of the second transistor T2, a gate electrode of the third transistor T3 and a first end of the first storage capacitor C1 respectively, the second node N2 is connected with a first pole of the third transistor T3, a second pole of the eighth transistor T8 and a second pole of the fifth transistor T5 respectively, the third node N3 is connected with a second pole of the second transistor T2, a second pole of the third transistor T3 and a first pole of the sixth transistor T6 respectively, the fourth node N4 is connected with a second pole of the sixth transistor T6 and a second pole of the seventh transistor T7 respectively, and the fifth node N5 is connected with a second pole of the fourth transistor T4, a second pole of the ninth transistor T9, a second end of the first storage capacitor C1 and a second end of the second storage capacitor C2 respectively.

[0101] ​In an exemplary embodiment, a first end (lower plate) of the first storage capacitor C1 is connected to the first node N1, a second end (upper plate) of the first storage capacitor C1 is connected to the fifth node N5, a first end (upper plate) of the second storage capacitor C2 is connected to the first power supply line VDD, and a second end (lower plate) of the second storage capacitor C2 is connected to the fifth node N5.

[0102] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the fourth scan signal line S4, and when an ON signal is applied to the fourth scan signal line S4, the first transistor T1 transmits the first initial voltage to the gate electrode of the third transistor T3 and the first end of the first storage capacitor C1, releases the accumulated charge in the first storage capacitor C1, and realizes initialization. The first transistor T1 can be referred to as a first initialization transistor.

[0103] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3. When an ON signal is applied to the second scan signal line S2, the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode. The second transistor T2 can be referred to as a compensation transistor.

[0104] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1, i.e., the gate electrode of the third transistor T3 is connected to the first end of the first storage capacitor C1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0105] The third transistor T3 determines the size of the driving current according to the potential difference between the gate electrode and the first electrode thereof.

[0106] The third transistor T3 can be referred to as a driving transistor.

[0107] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the fifth node N5. When an ON signal is applied to the third scan signal line S3, the fourth transistor T4 inputs the data voltage of the data signal line DATA to the second end of the first storage capacitor C1 and the second end of the second storage capacitor C2. The fourth transistor T4 can be referred to as a data write transistor.

[0108] In an example embodiment, a gate electrode of the fifth transistor T5 is connected to the first emission signal line EM1, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. A gate electrode of the sixth transistor T6 is connected to the second emission signal line EM2, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. When an ON signal is applied to the first emission signal line EM1 and the second emission signal line EM2, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power supply line VDD and the second power supply line VSS to cause the light emitting device EL to emit light. The fifth transistor T5 can be referred to as a first emission write transistor. The sixth transistor T6 can be referred to as a second emission write transistor.

[0109] In an example embodiment, a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. When an ON signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initial voltage to the first electrode of the light emitting device EL to cause the charge accumulated in the first electrode of the light emitting device EL to be released, thereby achieving initialization. The seventh transistor T7 can be referred to as a second initialization transistor.

[0110] In an example embodiment, a gate electrode of the eighth transistor T8 is connected to the first scan signal line S1, a first electrode of the eighth transistor T8 is connected to the second reference signal line REF2, and a second electrode of the eighth transistor T8 is connected to the second node N2. When an ON signal is applied to the first scan signal line S1, the eighth transistor T8 transmits the second reference signal to the second node N2. The eighth transistor T8 can be referred to as a second reference transistor.

[0111] In an example embodiment, a gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, a first electrode of the ninth transistor T9 is connected to the first reference signal line REF1, and a second electrode of the ninth transistor T9 is connected to the fifth node N5. When an ON signal is applied to the second scan signal line S2, the ninth transistor T9 transmits the first reference signal to the fifth node N5. The ninth transistor T9 can be referred to as a first reference transistor.

[0112] In an example embodiment, the light emitting device EL can be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked. The first electrode of the light emitting device EL is connected to the fourth node N4, and the second electrode of the light emitting device EL is connected to the second power supply line VSS, and the signal of the second power supply line VSS is a low level signal continuously provided, and the signal of the first power supply line VDD is a high level signal continuously provided.

[0113] In an example embodiment, the first transistor T1 to the ninth transistor T9 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the ninth transistor T9 can include P-type transistors and N-type transistors.

[0114] In an example embodiment, the first transistor T1 to the ninth transistor T9 can be low temperature poly-silicon thin film transistors, or can be oxide thin film transistors, or can be low temperature poly-silicon thin film transistors and oxide thin film transistors. The active layer of the low temperature poly-silicon thin film transistor uses low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor uses oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate, i.e., an LTPO display substrate, can take advantage of both, can achieve low frequency driving, can reduce power consumption, and can improve display quality.

[0115] In an example embodiment, Figure 4 The working process of the pixel driving circuit shown can include a first stage to a fifth stage.

[0116] The first stage can include a plurality of sub-stages repeatedly executed, and each sub-stage can include a first sub-stage and a second sub-stage executed in sequence.

[0117] In the first sub-stage, the signals of the fourth scan signal line S4 and the first emission signal line EM1 are conductive signals, and the signals of the other signal lines are disconnected signals. The signal of the fourth scan signal line S4 being a conductive signal can make the first transistor T1 conductive, and the first initial signal of the first initial signal line INIT1 can be provided to the first node N1 to initialize the first node N1. When the third transistor T3 is a P-type transistor, the third transistor T3 is conductive. The conductive signal of the first emission signal line EM1 can make the fifth transistor T5 conductive, and the first power supply signal of the first power supply line VDD can be provided to the second node N2.

[0118] In the second sub-stage, the signals of the second scan signal line S2 and the first emission signal line EM1 are conductive signals, and the signals of the other signal lines are disconnected signals. The signal of the second scan signal line S2 being a conductive signal can make the second transistor T2 conductive, connecting the first node N1 and the third node N3, and writing the threshold voltage of the third transistor T3 to the first node N1. The signal of the second scan signal line S2 being a conductive signal can make the ninth transistor T9 conductive, and the first reference signal of the first reference signal line REF1 is provided to the fifth node N5 to initialize the fifth node N5. The conductive signal of the first emission signal line EM1 can make the fifth transistor T5 conductive, and the first power supply signal of the first power supply line VDD can be provided to the second node N2.

[0119] The second stage. The signal of the third scan signal line S3 is a conductive signal, and the signals of the other signal lines are disconnected signals. The signal of the third scan signal line S3 being a conductive signal can make the fourth transistor T4 conductive, and the data voltage provided by the data signal line DATA is written to the fifth node N5.

[0120] The third stage. The signal of the first scan signal line S1 is a conductive signal, and the signals of the other signal lines are disconnected signals. The signal of the first scan signal line S1 being a conductive signal makes the seventh transistor T7 conductive, and the second initial signal of the second initial signal line INIT2 can be written to the fourth node N4 to initialize the fourth node N4 and avoid the influence of the residual signal of the last frame on the display of the current frame. The signal of the first scan signal line S1 being a conductive signal makes the eighth transistor T8 conductive, and the second reference signal of the second reference signal line REF2 can be written to the second node N2.

[0121] The fourth stage. The signal of the second emission signal line EM2 is a conductive signal, and the signals of the other signal lines are disconnected signals. The signal of the second emission signal line EM2 being a conductive signal makes the sixth transistor T6 conductive, connecting the third node N3 and the fourth node N4 so that the potentials of the third node N3 and the fourth node N4 are the same.

[0122] In the fifth stage, the signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are conductive signals, and the signals of the other signal lines are off signals. The signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are conductive signals, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the first power supply signal of the first power supply line VDD can be provided to the light emitting device EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, to drive the light emitting device EL to emit light.

[0123] In the exemplary embodiments, since the driving transistor (i.e., the third transistor T3) is in a state for a long time, electrons can be trapped in traps, causing hysteresis. Therefore, in the first stage, by performing the initialization and threshold voltage writing processes on the first node N1 multiple times (e.g., three times), not only can the hysteresis of the driving transistor be reduced, but also the potential stability of the first node N1 can be ensured. In the third stage, the second reference signal is written to the second node N2, and by changing the potential of the second node N2, the hysteresis of the driving transistor can be reduced. In the fourth stage, by connecting the third node N3 and the fourth node N4, the potential of the fourth node N4 can be increased, which is beneficial to reducing the time required to reach the turn-on voltage of the light emitting device subsequently.

[0124] The pixel driving circuit provided by the present disclosure can effectively improve the hysteresis of the driving transistor, and is beneficial to improving the display effect.

[0125] Figure 5 A display substrate plane structure schematic diagram of an exemplary embodiment of the present disclosure illustrates the structure of the pixel driving circuit in one circuit unit in the display substrate. In the exemplary embodiments, the display substrate can include a driving circuit layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer can include at least a plurality of circuit units, the light emitting structure layer can include at least a plurality of light emitting units, at least one circuit unit includes a pixel driving circuit, and at least one light emitting unit includes a light emitting device, the light emitting device can include at least an anode, an organic light emitting layer and a cathode, and the anode in the light emitting unit is connected to the pixel driving circuit in the corresponding circuit unit. In the exemplary embodiments, the circuit unit referred to in the present disclosure refers to a region divided according to the pixel driving circuit, and the light emitting unit referred to in the present disclosure refers to a region divided according to the light emitting device. In the exemplary embodiments, the position of the light emitting unit orthogonally projected on the substrate can correspond to the position of the circuit unit orthogonally projected on the substrate, or the position of the light emitting unit orthogonally projected on the substrate can not correspond to the position of the circuit unit orthogonally projected on the substrate.

[0126] In an exemplary embodiment, a plurality of circuit units arranged sequentially along a first direction X can be referred to as a unit row, and a plurality of circuit units arranged sequentially along a second direction Y can be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array. The first direction X intersects the second direction Y. For example, the first direction X is perpendicular to the second direction Y.

[0127] like Figure 5 As shown, in an exemplary embodiment, the driving circuit layer may further include at least one first power line 51 extending along the second direction Y and at least one first power connection line 68 extending along the first direction X. In an exemplary embodiment, the first power line 51 is connected to the pixel driving circuit in a plurality of circuit units, and the first power line 51 is configured to continuously provide a high-level signal to the pixel driving circuit. In an exemplary embodiment, the first power line 51 extending along the second direction Y and the first power connection line 68 extending along the first direction X are interconnected to form a mesh structure for transmitting power signals.

[0128] In this disclosure, A extending along the direction of B means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip shape. The main part extends along the direction of B, and the length of the main part extending along the direction of B is greater than the length of the secondary part extending in other directions.

[0129] In an exemplary embodiment, the driving circuit layer may further include a reference signal connection line 54 and a first reference signal line 91. The first reference signal line 91 may be a line extending along a first direction X, and the reference signal connection line 54 may be a line extending along a second direction Y. The reference signal connection line 54 and the first reference signal line 91 are interconnected to form a mesh structure for transmitting the first reference signal.

[0130] In an exemplary embodiment, on a plane perpendicular to the display substrate, the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. The first power line 51 and the first power connection line 68 may be disposed in different conductive layers, and the first power line 51 and the first power connection line 68 may be connected through vias.

[0131] In an exemplary embodiment, the first power connection line 68 may be disposed in the third conductive layer, and the first power line 51 may be disposed in the fourth conductive layer.

[0132] In an exemplary embodiment, the reference signal connection line 54 and the first reference signal line 91 can be disposed in different conductive layers, and the reference signal connection line 54 and the first reference signal line 91 can be connected by vias.

[0133] In an exemplary embodiment, the first reference signal line 91 can be provided in the third conductive layer, and the reference signal connection line 54 can be provided in the fourth conductive layer.

[0134] In an exemplary embodiment, the at least one pixel driving circuit can include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emitting transistor, a sixth transistor T6 as a second light emitting transistor, a seventh transistor T7 as a second initialization transistor, an eighth transistor T8 as a second reference transistor, a ninth transistor T9 as a first reference transistor, a first storage capacitor, and a second storage capacitor.

[0135] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the fourth scan signal line 64, a first electrode of the first transistor T1 is connected to the first initial signal line 81, and a second electrode of the first transistor T1 is connected to a first electrode of the second transistor T2 and a first plate 71 of the first storage capacitor, respectively. A gate electrode of the second transistor T2 is connected to the fifth scan signal line 65, and a second electrode of the second transistor T2 is connected to a second electrode of the third transistor T3 and a first electrode of the sixth transistor T6, respectively. A gate electrode of the third transistor T3 is the first plate 71 of the first storage capacitor, a first electrode of the third transistor T3 is connected to a second electrode of the fifth transistor T5 and a second electrode of the eighth transistor T8, respectively. A gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, a first electrode of the fourth transistor T4 is connected to the data signal line 53, and a second electrode of the fourth transistor T4 is connected to a second electrode of the ninth transistor T9, a third plate 73 of the first storage capacitor, and a second plate 72 of the second storage capacitor, respectively. A gate electrode of the fifth transistor T5 is connected to the first light emitting signal line 31, and a first electrode of the fifth transistor T5 is connected to the first power line 51. A gate electrode of the sixth transistor T6 is connected to the second light emitting signal line 32, and a second electrode of the sixth transistor T6 is connected to a second electrode of the seventh transistor T7. A gate electrode of the seventh transistor T7 is connected to the first scan signal line 61, and a first electrode of the seventh transistor T7 is connected to the second initial signal line 82. A gate electrode of the eighth transistor T8 is connected to the first scan signal line 61, and a first electrode of the eighth transistor T8 is connected to the second reference signal line 92. A gate electrode of the ninth transistor T9 is connected to the second scan signal line 62, and a first electrode of the ninth transistor T9 is connected to the first reference signal line 91.

[0136] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 transmit the same scan signal.

[0137] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first light emission signal line 31, the second light emission signal line 32, the first initial signal line 81, the second initial signal line 82, the first reference signal line 91, and the second reference signal line 92 can be line shapes extending along the first direction X of the main body, and the shapes of the first power line 51 and the data signal line 53 can be line shapes extending along the second direction Y of the main body.

[0138] In an exemplary embodiment, at least one circuit unit may further include an anode connection electrode 55, which is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 respectively, and is also connected to the anode of the light-emitting unit.

[0139] In an exemplary embodiment, the driving circuit layer may further include a repair line 33. The repair line 33 may be a line shape in which the main body extends along the first direction X. The orthographic projection of the repair line 33 on the substrate at least partially overlaps with the orthographic projection of the anode connection electrode 55 on the substrate. The repair line 33 is configured to input a signal to the anode of the sub-pixel with the bright spot defect when a bright spot defect occurs on the display substrate, thereby repairing it into a dark spot.

[0140] Figure 6 for Figure 5 An enlarged view of the first and second storage capacitor regions. (See image below.) Figure 5 and Figure 6 As shown, in an exemplary embodiment, the first storage capacitor may include at least a first electrode 71 and a third electrode 73, wherein the orthographic projection of the third electrode 73 onto the substrate at least partially overlaps with the orthographic projection of the first electrode 71 onto the substrate. The second storage capacitor may include at least a second electrode 72 and a fourth electrode 74, wherein the orthographic projection of the fourth electrode 74 onto the substrate at least partially overlaps with the orthographic projection of the second electrode 72 onto the substrate.

[0141] In an exemplary embodiment, the first electrode 71 and the second electrode 72 can be disposed in the first conductive layer, the third electrode 73 and the fourth electrode 74 can be disposed in the second conductive layer, the first electrode 71 can serve as the gate electrode of the third transistor T3, the second electrode 72 is connected to the third electrode 73, and the fourth electrode 74 is connected to the first power line 51.

[0142] like Figure 5 and Figure 6As shown, in the exemplary embodiment, the at least one circuit unit can further include a first connection electrode 41 connected with the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the first electrode plate 71 of the first storage capacitor respectively, and the first connection electrode 41 can serve as the first node N1 of the pixel driving circuit.

[0143] In the exemplary embodiment, the at least one circuit unit can further include a second connection electrode 42 connected with the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor and the second electrode plate 72 of the second storage capacitor respectively, and the second connection electrode 42 can serve as the fifth node N5 in the pixel driving circuit.

[0144] In the exemplary embodiment, the first power supply line 51 has an orthographic projection on the substrate at least partially overlapping with an orthographic projection of the second connection electrode 42 on the substrate, so as to shield the fifth node from other signals in the pixel driving circuit.

[0145] In the exemplary embodiment, the at least one circuit unit can further include a first shielding electrode 36 connected with the fourth electrode plate 74, and the first shielding electrode 36 has an orthographic projection on the substrate at least partially overlapping with an orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 on the substrate. In the exemplary embodiment, the first shielding electrode 36 is configured to shield the first transistor T1 from the data voltage jump, so as to avoid the data voltage jump affecting the normal operation of the pixel driving circuit and improving the display effect.

[0146] In the exemplary embodiment, the at least one circuit unit can further include a second shielding electrode 37 connected with the fourth electrode plate 74, and the second shielding electrode 37 has an orthographic projection on the substrate at least partially overlapping with an orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 on the substrate. In the exemplary embodiment, the second shielding electrode 37 is configured to shield the second transistor T2 from the data voltage jump, so as to avoid the data voltage jump affecting the normal operation of the pixel driving circuit and improving the display effect.

[0147] In the exemplary embodiment, the fourth electrode plate 74, the first shielding electrode 36 and the second shielding electrode 37 can be an integrated structure connected with each other.

[0148] In the example embodiment, the at least one circuit unit can further include a third shielding electrode 38 connected with the fourth plate 74, and a projection of the third shielding electrode 38 on the substrate at least partially overlaps a projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 on the substrate. In the example embodiment, the third shielding electrode 38 is configured to shield the fourth transistor T4 from the data voltage jump, so as to avoid the data voltage jump affecting the normal operation of the pixel driving circuit and improving the display effect.

[0149] In the example embodiment, the at least one circuit unit can further include a fourth shielding electrode 39 connected with the fourth plate 74, and a projection of the fourth shielding electrode 39 on the substrate at least partially overlaps a projection of the semiconductor layer between the two gate electrodes of the ninth transistor T9 on the substrate. In the example embodiment, the fourth shielding electrode 39 is configured to shield the ninth transistor T9 from the data voltage jump, so as to avoid the data voltage jump affecting the normal operation of the pixel driving circuit and improving the display effect.

[0150] The preparation process of the display substrate is exemplarily described below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development and the like for organic materials. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the example embodiment of the present disclosure, "the projection of B is located within the projection of A" or "the projection of A contains the projection of B" means that the boundary of the projection of B falls within the boundary of the projection of A, or the boundary of the projection of A overlaps the boundary of the projection of B.

[0151] In the example embodiment, taking one circuit unit in the nth unit row as an example, the preparation process of the display substrate can include the following operations.

[0152] (11) forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern can include sequentially depositing a first insulating thin film and a semiconductor thin film on a substrate, patterning the semiconductor thin film by a patterning process, forming a first insulating layer covering the substrate and a semiconductor layer disposed on the first insulating layer, as shown in Figure 7

[0153] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display substrate can include at least a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, a seventh active layer 17 of a seventh transistor T7, an eighth active layer 18 of an eighth transistor T8, and a ninth active layer 19 of a ninth transistor T9, and the first active layer 11 to the third active layer 13 and the fifth active layer 15 to the eighth active layer 18 can be an integral structure connected to each other, and the fourth active layer 14 and the ninth active layer 19 can be an integral structure connected to each other.

[0154] In an exemplary embodiment, the fourth active layer 14 and the ninth active layer 19 of the nth unit row can be located on a side of the third active layer 13 close to the (n-1)th unit row, i.e., the fourth active layer 14 and the ninth active layer 19 can be located on a side opposite to the second direction Y of the third active layer 13 of the present circuit unit. The first active layer 11, the second active layer 12, the fifth active layer 15 to the eighth active layer 18 of the nth unit row can be located on a side of the third active layer 13 close to the (n+1)th unit row, i.e., the first active layer 11, the second active layer 12, the fifth active layer 15 to the eighth active layer 18 can be located on a side of the third active layer 13 of the present circuit unit in the second direction Y.

[0155] In an exemplary embodiment, the first active layer 11 can be located on a side of the third active layer 13 of the present circuit unit in the second direction Y, the fifth active layer 15 can be located on a side of the first active layer 11 of the present circuit unit in the second direction Y, and the eighth active layer 18 can be located on a side of the fifth active layer 15 of the present circuit unit in the second direction Y. The second active layer 12 can be located on a side of the third active layer 13 of the present circuit unit in the second direction Y, the sixth active layer 16 can be located on a side of the second active layer 12 of the present circuit unit in the second direction Y, and the seventh active layer 17 can be located on a side of the sixth active layer 16 of the present circuit unit in the second direction Y.

[0156] ​In the exemplary embodiment, the first active layer 11, the fourth active layer 14, the fifth active layer 15, and the eighth active layer 18 can be located on one side (e.g., the opposite side of the first direction X) of the first direction X of the present circuit unit, and the second active layer 12, the sixth active layer 16, the seventh active layer 17, and the ninth active layer 19 can be located on the other side (e.g., the side of the first direction X) of the first direction X of the present circuit unit.

[0157] In the exemplary embodiment, the first active layer 11, the second active layer 12, the fourth active layer 14, and the ninth active layer 19 can have an "L" shape, the third active layer 13 can have a "C" shape, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 can have an "I" shape.

[0158] In the exemplary embodiment, the fourth active layer 14 and the ninth active layer 19 can have an "L" shape, so that the node between the two gate electrodes of the fourth transistor T4 and the ninth transistor T9 is closer to the VDD signal.

[0159] In the example embodiment, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region. In the example embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer can be connected to each other, and the second region 11-2 of the first active layer can serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 15-2 of the fifth active layer, and the second region 18-2 of the eighth active layer can be connected to each other, and the first region 13-1 of the third active layer can serve as both the second region 15-2 of the fifth active layer and the second region 18-2 of the eighth active layer, constituting a second node N2 of the pixel driving circuit. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer can be connected to each other, and the second region 13-2 of the third active layer can serve as both the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer, constituting a third node N3 of the pixel driving circuit. The second region 14-2 of the fourth active layer and the second region 19-2 of the ninth active layer can be connected to each other, and the second region 14-2 of the fourth active layer can serve as the second region 19-2 of the ninth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer, constituting a fourth node N4 of the pixel driving circuit. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the first region 19-1 of the ninth active layer can be separately provided, and the first region 14-1 of the fourth active layer can be located on a side of the channel region of the fourth active layer close to the third active layer 13, and the first region 19-1 of the ninth active layer can be located on a side of the channel region of the ninth active layer away from the third active layer 13.

[0160] In the example embodiment, the display substrate can further include a first active connection line 10 and a second active connection line 20. The first active connection line 10 can be located on a side of the ninth active layer 19 in the second direction Y and connected to the first region 19-1 of the ninth active layer of each circuit unit. The second active connection line 20 can be located on a side of the seventh active layer 17 in the second direction Y and connected to the first region 17-1 of the seventh active layer of each circuit unit.

[0161] In the example embodiment, the first active connection line 10 can be in a shape of a fold line with a main body extending along the first direction X, and the first active connection line 10 and the ninth active layer of the plurality of circuit units can be in an integrated structure connected with each other. Since the first region of the ninth active layer is connected with the first reference signal line formed subsequently, the first active connection line 10 can be reused as the first reference signal line extending along the first direction X, which not only ensures that the first regions of the plurality of ninth active layers in a unit row have the same potential, but also reduces the voltage drop of the first reference signal, which is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0162] In the example embodiment, the second active connection line 20 can be in a shape of a straight line with a main body extending along the first direction X, and the second active connection line 20 and the seventh active layer of the plurality of circuit units can be in an integrated structure connected with each other. Since the first region of the seventh active layer is connected with the second initial signal line formed subsequently, the second active connection line 20 can be reused as the second initial signal line extending along the first direction X, which not only ensures that the first regions of the plurality of seventh active layers in a unit row have the same potential, but also reduces the voltage drop of the second initial signal, which is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0163] (12) Forming a first conductive layer pattern. In the example embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a second insulating layer covering the semiconductor layer pattern, and forming the first conductive layer pattern on the second insulating layer, as shown in Figure 8A and Figure 8B Figure 8B Figure 8A which is a schematic diagram of the first conductive layer in the example embodiment. In the example embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0164] In the example embodiment, the first conductive layer pattern of each circuit unit in the display substrate at least includes: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a ninth gate electrode 29, a first scan signal line 61, a first plate 71 of a first storage capacitor, and a second plate 72 of a second storage capacitor.

[0165] In the example embodiment, the first gate electrode 21 can be in a shape of an "L" character, and can be located on one side of the first plate 71 in the second direction Y. The area where the first gate electrode 21 overlaps with the first active layer can be used as a gate electrode of a first transistor T1 of a double-gate structure. ​​

[0166] In an example embodiment, the second gate electrode 22 can have a "T" shape, can be located on one side of the second direction Y of the first plate 71, and an area where the second gate electrode 22 overlaps the second active layer can serve as a gate electrode of the second transistor T2 of the dual gate structure.

[0167] In an example embodiment, the fourth gate electrode 24 can have an "L" shape, can be located on the opposite side of the second direction Y of the second plate 72, and an area where the fourth gate electrode 24 overlaps the fourth active layer can serve as a gate electrode of the fourth transistor T4 of the dual gate structure.

[0168] In an example embodiment, the fifth gate electrode 25 can have a bar shape extending along the second direction Y, can be located on one side of the second direction Y of the first gate electrode 21, and an area where the fifth gate electrode 25 overlaps the fifth active layer can serve as a gate electrode of the fifth transistor T5.

[0169] In an example embodiment, the sixth gate electrode 26 can have a bar shape extending along the first direction X, can be located on one side of the second direction Y of the second gate electrode 22, and an area where the sixth gate electrode 26 overlaps the sixth active layer can serve as a gate electrode of the sixth transistor T6.

[0170] In an example embodiment, the ninth gate electrode 29 can have a "T" shape, can be located on the opposite side of the second direction Y of the second plate 72, and an area where the ninth gate electrode 29 overlaps the ninth active layer can serve as a gate electrode of the ninth transistor T9 of the dual gate structure.

[0171] In an example embodiment, the first scan signal line 61 can have a line shape in which a main body portion extends along the first direction X, can be located on one side of the second direction Y of the fifth gate electrode 25 and the sixth gate electrode 26, an area where the first scan signal line 61 overlaps the seventh active layer can serve as a gate electrode of the seventh transistor T7, and an area where the first scan signal line 61 overlaps the eighth active layer can serve as a gate electrode of the eighth transistor T8.

[0172] In an example embodiment, the first plate 71 of the first storage capacitor can have a rectangular shape, a normal projection of the first plate 71 on a substrate at least partially overlaps a normal projection of the third active layer of the third transistor T3 on the substrate, and the first plate 71 can simultaneously serve as a lower plate of the first storage capacitor and a gate electrode of the third transistor T3.

[0173] In the example embodiment, the main body shape of the second plate 72 of the second storage capacitor can be rectangular, can be located on the side of the second direction Y opposite to the first plate 71, and on the side of the fourth gate electrode 24 and the ninth gate electrode 29 in the second direction Y, that is, in the second direction Y, the second plate 72 is located between the first plate 71 and the fourth gate electrode 24 (the ninth gate electrode 29), and the orthographic projection of the second plate 72 on the substrate does not overlap with the orthographic projection of the semiconductor layer on the substrate. In the example embodiment, the second plate 72 can serve as the lower plate of the second storage capacitor.

[0174] In the example embodiment, the area where the first active connection line 10 is connected to the first region of the ninth active layer is bent towards the ninth active layer, so that a recess is formed on the side of the ninth active layer away from the first active connection line 10. The second plate 72 is provided with a protruding portion 72-1 on the side close to the first active connection line 10, the shape of the protruding portion 72-1 can be rectangular, the first end of the protruding portion 72-1 is connected to the second plate 72, and the second end of the protruding portion 72-1 extends into the recess of the first active connection line 10.

[0175] In the example embodiment, the second plate 72 and the protruding portion 72-1 can be an integrated structure connected to each other. By providing the recess of the first active connection line 10 and the protruding portion 72-1 of the second plate 72, the present disclosure can effectively increase the area of the second plate 72 and effectively increase the capacitance of the second storage capacitor.

[0176] In the example embodiment, after forming the first conductive layer pattern, the semiconductor layer can be subjected to a conductorization process using the first conductive layer as a shield. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the ninth active layer are conductorized.

[0177] (13) Forming a second conductive layer pattern. In the example embodiment, forming the second conductive layer pattern can include: sequentially depositing a third insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second conductive thin film by a patterning process, forming a third insulating layer covering the first conductive layer, and forming a second conductive layer pattern on the third insulating layer, as shown in Figure 9A and Figure 9B , Figure 9B , Figure 9A , which is a schematic view of the second conductive layer in the example embodiment. In the example embodiment, the second conductive layer can be referred to as the second gate metal (GATE2) layer.

[0178] In the exemplary embodiments, the second conductive layer pattern of each circuit unit in the display substrate at least includes: a first light emitting signal line 31, a second light emitting signal line 32, a repair line 33, a third plate 73 of a first storage capacitor, a fourth plate 74 of a second storage capacitor, a first initial signal line 81, and a second reference signal line 92.

[0179] In the exemplary embodiments, the first light emitting signal line 31, the second light emitting signal line 32, the repair line 33, the first initial signal line 81, and the second reference signal line 92 can have a linear shape with a main body extending along the first direction X, the first light emitting signal line 31, the second light emitting signal line 32, the repair line 33, and the first initial signal line 81 can be located between the first gate electrode 21 and the first scan signal line 61, and the second reference signal line 92 can be located on the side opposite to the second direction Y of the fourth gate electrode 24.

[0180] In the exemplary embodiments, the first light emitting signal line 31 can be located on the side of the second direction Y of the first gate electrode 21 of the present circuit unit, the first initial signal line 81 can be located on the side of the second direction Y of the first light emitting signal line 31 of the present circuit unit, the second light emitting signal line 32 can be located on the side of the second direction Y of the first initial signal line 81 of the present circuit unit, and the repair line 33 can be located on the side of the second direction Y of the second light emitting signal line 32 of the present circuit unit, i.e., the second light emitting signal line 32 and the first initial signal line 81 can be located between the first light emitting signal line 31 and the repair line 33.

[0181] In the exemplary embodiments, the first light emitting signal line 31 is provided with a first light emitting connecting block 31-1 on the side close to the first initial signal line 81, the first light emitting connecting block 31-1 can be provided in each circuit unit, a first end of the first light emitting connecting block 31-1 is connected with the first light emitting signal line 31, a second end of the first light emitting connecting block 31-1 extends towards the direction of the first initial signal line 81, and the first light emitting connecting block 31-1 is configured to be connected with the fifth gate electrode 25 through a seventh connecting electrode formed subsequently. In the exemplary embodiments, the first light emitting signal line 31 and the plurality of first light emitting connecting blocks 31-1 can be an integrated structure connected with each other.

[0182] In the example embodiment, the first initial signal line 81 is provided with a first initial connecting block 81-1 on the side close to the first light-emitting signal line 31, the first initial connecting block 81-1 can be provided in each circuit unit, a first end of the first initial connecting block 81-1 is connected with the first initial signal line 81, a second end of the first initial connecting block 81-1 extends towards the direction of the first light-emitting signal line 31, and the first initial connecting block 81-1 is configured to be connected with the first area of the first active layer through the ninth connecting electrode formed subsequently. In the example embodiment, the first initial signal line 81 and the plurality of first initial connecting blocks 81-1 can be an integral structure connected with each other.

[0183] In the example embodiment, the second light-emitting signal line 32 is provided with a second light-emitting connecting block 32-1 on the side close to the first initial signal line 81, the second light-emitting connecting block 32-1 can be provided in each circuit unit, a first end of the second light-emitting connecting block 32-1 is connected with the second light-emitting signal line 32, a second end of the second light-emitting connecting block 32-1 extends towards the direction of the first initial signal line 81, and the second light-emitting connecting block 32-1 is configured to be connected with the sixth gate electrode 26 through the eighth connecting electrode formed subsequently. In the example embodiment, the second light-emitting signal line 32 and the plurality of second light-emitting connecting blocks 32-1 can be an integral structure connected with each other.

[0184] In the example embodiment, the second reference signal line 92 does not overlap with the orthographic projection of the fourth active layer of the fourth transistor T4 on the substrate, and the second reference signal line 92 does not overlap with the orthographic projection of the ninth active layer of the ninth transistor T9 on the substrate, which greatly reduces the capacitance between the scanning signal and the second reference signal line 92, and improves the driving load of the gate driving circuit.

[0185] In the example embodiment, the second reference signal line 92 of the nth unit row is provided with a second reference connecting block 92-1 on the side away from the second plate 72 of the nth unit row, the second reference connecting block 92-1 can be provided in each circuit unit, a first end of the second reference connecting block 92-1 is connected with the second reference signal line 92, and a second end of the second reference connecting block 92-1 extends towards the direction away from the second plate 72, i.e. towards the direction of the (n-1)th unit row. In the example embodiment, the second reference connecting block 92-1 of the second reference signal line 92 in the nth unit row is configured to be connected with the first area of the eighth active layer in the (n-1)th unit row through the sixth connecting electrode formed subsequently, and to provide the second reference signal to the first electrode of the eighth transistor T8 in the (n-1)th unit row. In the example embodiment, the second reference signal line 92 and the plurality of second reference connecting blocks 92-1 can be an integral structure connected with each other.

[0186] In the example embodiment, the third plate 73 of the first storage capacitor can have a rectangular shape, and the corners of the rectangular shape can be chamfered. The third plate 73 can be located between the first light-emitting signal line 31 and the second reference signal line 92 of the circuit unit, and the orthographic projection of the third plate 73 on the substrate at least partially overlaps the orthographic projection of the first plate 71 on the substrate. The third plate 73 can serve as the upper plate of the first storage capacitor, and the first plate 71 and the third plate 73 constitute the first storage capacitor of the pixel driving circuit.

[0187] In the example embodiment, the fourth plate 74 of the second storage capacitor can have a shape similar to the second plate 72, and the fourth plate 74 can be located between the second reference signal line 92 and the third plate 73 of the circuit unit. The orthographic projection of the fourth plate 74 on the substrate at least partially overlaps the orthographic projection of the second plate 72 on the substrate. The fourth plate 74 can serve as the upper plate of the second storage capacitor, and the second plate 72 and the fourth plate 74 constitute the second storage capacitor C2 of the pixel driving circuit.

[0188] In the example embodiment, the fourth plate 74 can be provided with a first shielding electrode 36 on the side close to the first light-emitting signal line 31. The first shielding electrode 36 is located on the side of the fourth plate 74 in the second direction Y. The first shielding electrode 36 can have an "L" shape, and the first shielding electrode 36 can be provided in each circuit unit. The first shielding electrode 36 can include a first extension section 36-1 and a first shielding section 36-2. The first extension section 36-1 can have a strip shape extending in the second direction Y. The first end of the first extension section 36-1 is connected to the fourth plate 74, and the second end of the first extension section 36-1 is connected to the first end of the first shielding section 36-2 after extending toward the first light-emitting signal line 31. The first shielding section 36-2 can have a strip shape extending in the first direction X. The first end of the first shielding section 36-2 is connected to the second end of the first extension section 36-1, and the second end of the first shielding section 36-2 extends in the first direction X. The orthographic projection of the first shielding section 36-2 on the substrate at least partially overlaps the orthographic projection of the first active layer between the two gate electrodes of the first transistor T1 on the substrate. In the example embodiment, the first shielding electrode 36 is configured to shield the influence of the data voltage jump on the first transistor T1, to avoid the influence of the data voltage jump on the normal operation of the pixel driving circuit, and to improve the display effect.

[0189] In the example embodiment, the fourth plate 74 and the first shielding electrode 36 can be an integrated structure connected to each other.

[0190] In the example embodiment, the fourth plate 74 is provided with a second shielding electrode 37 on the side close to the first light-emitting signal line 31, and the second shielding electrode 37 is located on the side of the fourth plate 74 in the second direction Y. The second shielding electrode 37 can have an "L" shape, and the second shielding electrode 37 can be provided in each circuit unit. The second shielding electrode 37 having the "L" shape can include a second extension section 37-1 and a second shielding section 37-2. The second extension section 37-1 can have a strip shape extending in the second direction Y, a first end of the second extension section 37-1 is connected to the fourth plate 74, and a second end of the second extension section 37-1 is connected to the second shielding section 37-2 after extending toward the first light-emitting signal line 31. The second shielding section 37-2 can have a strip shape extending in the opposite direction of the first direction X, a first end of the second shielding section 37-2 is connected to the second end of the second extension section 37-1, and a second end of the second shielding section 37-2 extends in the opposite direction of the first direction X. The second shielding section 37-2 is at least partially overlapped with the second active layer between the two gate electrodes of the second transistor T2 in the orthographic projection of the second shielding section 37-2 on the substrate. In the example embodiment, the second shielding electrode 37 is configured to shield the influence of the data voltage jump on the second transistor T2, avoid the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0191] In the example embodiment, the fourth plate 74 and the second shielding electrode 37 can be an integrated structure connected to each other.

[0192] In the example embodiment, the fourth plate 74 is provided with a third shielding electrode 38 on the side away from the first light-emitting signal line 31, and the third shielding electrode 38 is located on the side of the fourth plate 74 in the opposite direction of the second direction Y. The third shielding electrode 38 can have a strip shape extending in the second direction Y, a first end of the third shielding electrode 38 is connected to the fourth plate 74, and a second end of the third shielding electrode 38 extends in the direction of the second reference signal line 92. The third shielding electrode 38 can be provided in each circuit unit. The third shielding electrode 38 is at least partially overlapped with the fourth active layer between the two gate electrodes of the fourth transistor T4 in the orthographic projection of the third shielding electrode 38 on the substrate. In the example embodiment, the third shielding electrode 38 is configured to shield the influence of the data voltage jump on the fourth transistor T4, avoid the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0193] In the example embodiment, the fourth plate 74 and the third shielding electrode 38 can be an integrated structure connected to each other.

[0194] In the example embodiment, the fourth shielding electrode 39 is arranged on the side of the fourth plate 74 away from the first light-emitting signal line 31, and is arranged on one side of the fourth plate 74 in the second direction Y. The fourth shielding electrode 39 can have a strip shape extending along the second direction Y, and a first end of the fourth shielding electrode 39 is connected to the fourth plate 74, and a second end of the fourth shielding electrode 39 extends in the direction of the second reference signal line 92. The fourth shielding electrode 39 can be arranged in each circuit unit. A projection of the fourth shielding electrode 39 on the substrate at least partially overlaps a projection of the ninth active layer between the two gate electrodes of the ninth transistor T9 on the substrate. In the example embodiment, the fourth shielding electrode 39 is configured to shield the influence of the data voltage jump on the ninth transistor T9, so as to avoid the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0195] In the example embodiment, the fourth plate 74 and the fourth shielding electrode 39 can be an integrated structure connected to each other.

[0196] In the example embodiment, the third plate 73 of each circuit unit is provided with a first opening 75, which can be arranged in the middle of the third plate 73. The first opening 75 can have a rectangular shape, so that the third plate 73 forms a ring-shaped structure. The first opening 75 exposes the third insulating layer covering the first plate 71, and a projection of the first plate 71 on the substrate contains a projection of the first opening 75 on the substrate. In the example embodiment, the first opening 75 is configured to accommodate a tenth via to be formed later, and the tenth via is arranged in the first opening 75 and exposes the first plate 71, so that a first connecting electrode to be formed later is connected to the first plate 71.

[0197] In the example embodiment, the fourth plate 74 of each circuit unit is provided with a second opening 76, which can be arranged in the middle of the fourth plate 74. The second opening 76 can have a rectangular shape, so that the fourth plate 74 forms a ring-shaped structure. The second opening 76 exposes the third insulating layer covering the second plate 72, and a projection of the second plate 72 on the substrate contains a projection of the second opening 76 on the substrate. In the example embodiment, the second opening 76 is configured to accommodate an eleventh via to be formed later, and the eleventh via is arranged in the second opening 76 and exposes the second plate 72, so that a second connecting electrode to be formed later is connected to the second plate 72.

[0198] In the example embodiment, the repair line 33 is configured as a pre-provided repair signal line, and is configured to input a signal to the anode of a sub-pixel with a bright spot defect through the repair line 33 when the display substrate has a bright spot defect, so as to repair the sub-pixel with a bright spot defect into a dark spot.

[0199] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth insulating thin film, patterning the fourth insulating thin film using a patterning process, forming the fourth insulating layer covering the second conductive layer, and in each circuit unit, a plurality of vias are provided, as shown in Figure 10

[0200] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0201] In an exemplary embodiment, the first via V1 has a normal projection on the substrate within the normal projection range of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the first via V1 are etched away, exposing the surface of the first region of the first active layer, and the first via V1 is configured to allow the ninth connection electrode formed subsequently to connect with the first region of the first active layer through the via.

[0202] In an exemplary embodiment, the second via V2 has a normal projection on the substrate within the normal projection range of the second region of the first active layer (also the first region of the second active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the second via V2 are etched away, exposing the surface of the second region of the first active layer (also the first region of the second active layer), and the second via V2 is configured to allow the first connection electrode formed subsequently to connect with the second region of the first active layer (also the first region of the second active layer) through the via.

[0203] In an exemplary embodiment, the third via V3 has a normal projection on the substrate within the normal projection range of the first region of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the third via V3 are etched away, exposing the surface of the first region of the fourth active layer, and the third via V3 is configured to allow the third connection electrode formed subsequently to connect with the first region of the fourth active layer through the via.

[0204] ​In an example embodiment, the fourth via V4 is configured such that the second connection electrode formed subsequently is connected to the second region of the fourth active layer (also the second region of the ninth active layer) through the via.

[0205] In an example embodiment, the fifth via V5 is configured such that the fourth connection electrode formed subsequently is connected to the first region of the fifth active layer through the via.

[0206] In an example embodiment, the sixth via V6 is configured such that the fifth connection electrode formed subsequently is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0207] In an example embodiment, the seventh via V7 is configured such that the second initial signal line formed subsequently is connected to the first region of the seventh active layer through the via.

[0208] In an example embodiment, the eighth via V8 is configured such that the sixth connection electrode formed subsequently is connected to the first region of the eighth active layer through the via.

[0209] In the example embodiment, the normal projection of the ninth via V9 on the substrate is located within the range of the normal projection of the first region of the ninth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the ninth via V9 are etched away to expose the surface of the first region of the ninth active layer, and the ninth via V9 is configured to enable the first reference signal line formed subsequently to be connected to the first region of the ninth active layer through the via.

[0210] In the example embodiment, the normal projection of the tenth via V10 on the substrate is located within the range of the normal projection of the first opening 75 of the third plate 73 on the substrate, the fourth insulating layer and the third insulating layer within the tenth via V10 are etched away to expose the surface of the first plate 71, and the tenth via V10 is configured to enable the first connecting electrode formed subsequently to be connected to the first plate 71 through the via.

[0211] In the example embodiment, the normal projection of the eleventh via V11 on the substrate is located within the range of the normal projection of the second opening 76 of the fourth plate 74 on the substrate, the fourth insulating layer and the third insulating layer within the eleventh via V11 are etched away to expose the surface of the second plate 72, and the eleventh via V11 is configured to enable the second connecting electrode formed subsequently to be connected to the second plate 72 through the via.

[0212] In the example embodiment, the normal projection of the twelfth via V12 on the substrate is located within the range of the normal projection of the third plate 73 on the substrate, the fourth insulating layer within the twelfth via V12 is etched away to expose the surface of the third plate 73, and the twelfth via V12 is configured to enable the second connecting electrode formed subsequently to be connected to the third plate 73 through the via.

[0213] In the example embodiment, the normal projection of the thirteenth via V13 on the substrate is located within the range of the normal projection of the fourth plate 74 on the substrate, the fourth insulating layer within the thirteenth via V13 is etched away to expose the surface of the fourth plate 74, and the thirteenth via V13 is configured to enable the first power supply connecting line formed subsequently to be connected to the fourth plate 74 through the via.

[0214] In the example embodiment, the normal projection of the fourteenth via V14 on the substrate is located within the range of the normal projection of the first gate electrode 21 on the substrate, the fourth insulating layer and the third insulating layer within the fourteenth via V14 are etched away to expose the surface of the first gate electrode 21, and the fourteenth via V14 is configured to enable the fourth scanning signal line formed subsequently to be connected to the first gate electrode 21 through the via.

[0215] In the example embodiment, the fifteenth via V15 is located within the range of the orthogonal projection of the second gate electrode 22 on the substrate, the fourth insulating layer and the third insulating layer within the fifteenth via V15 are etched away to expose the surface of the second gate electrode 22, and the fifteenth via V15 is configured to connect the fifth scan signal line formed subsequently therewith the second gate electrode 22.

[0216] In the example embodiment, the sixteenth via V16 is located within the range of the orthogonal projection of the fourth gate electrode 24 on the substrate, the fourth insulating layer and the third insulating layer within the sixteenth via V16 are etched away to expose the surface of the fourth gate electrode 24, and the sixteenth via V16 is configured to connect the third scan signal line formed subsequently therewith the fourth gate electrode 24.

[0217] In the example embodiment, the seventeenth via V17 is located within the range of the orthogonal projection of the fifth gate electrode 25 on the substrate, the fourth insulating layer and the third insulating layer within the seventeenth via V17 are etched away to expose the surface of the fifth gate electrode 25, and the seventeenth via V17 is configured to connect the seventh connection electrode formed subsequently therewith the fifth gate electrode 25.

[0218] In the example embodiment, the eighteenth via V18 is located within the range of the orthogonal projection of the sixth gate electrode 26 on the substrate, the fourth insulating layer and the third insulating layer within the eighteenth via V18 are etched away to expose the surface of the sixth gate electrode 26, and the eighteenth via V18 is configured to connect the eighth connection electrode formed subsequently therewith the sixth gate electrode 26.

[0219] In the example embodiment, the nineteenth via V19 is located within the range of the orthogonal projection of the ninth gate electrode 29 on the substrate, the fourth insulating layer and the third insulating layer within the nineteenth via V19 are etched away to expose the surface of the ninth gate electrode 29, and the nineteenth via V19 is configured to connect the second scan signal line formed subsequently therewith the ninth gate electrode 29.

[0220] In the example embodiment, the twentieth via V20 is located within the range of the orthogonal projection of the first light emitting connection block 31-1 of the first light emitting signal line 31 on the substrate, the fourth insulating layer within the twentieth via V20 is etched away to expose the surface of the first light emitting connection block 31-1, and the twentieth via V20 is configured to connect the seventh connection electrode formed subsequently therewith the first light emitting connection block 31-1.

[0221] In an example embodiment, a normal projection of the twenty-first via V21 on the substrate is located within a range of a normal projection of the second light emitting connecting block 32-1 of the second light emitting signal line 32 on the substrate, the fourth insulating layer in the twenty-first via V21 is etched away to expose a surface of the second light emitting connecting block 32-1, and the twenty-first via V21 is configured to enable the eighth connecting electrode formed subsequently to connect with the second light emitting connecting block 32-1 through the via.

[0222] In an example embodiment, a normal projection of the twenty-second via V22 on the substrate is located within a range of a normal projection of the second reference connecting block 92-1 of the second reference signal line 92 on the substrate, the fourth insulating layer in the twenty-second via V22 is etched away to expose a surface of the second reference connecting block 92-1, and the twenty-second via V22 is configured to enable the sixth connecting electrode formed subsequently to connect with the second reference connecting block 92-1 through the via.

[0223] In an example embodiment, a normal projection of the twenty-third via V23 on the substrate is located within a range of a normal projection of the first initial connecting block 81-1 of the first initial signal line 81 on the substrate, the fourth insulating layer in the twenty-third via V23 is etched away to expose a surface of the first initial connecting block 81-1, and the twenty-third via V23 is configured to enable the ninth connecting electrode formed subsequently to connect with the first initial connecting block 81-1 through the via.

[0224] (15) Forming a third conductive layer pattern. In an example embodiment, forming the third conductive layer can include: on the substrate on which the aforementioned patterns are formed, depositing a third conductive thin film, patterning the third conductive thin film by using a patterning process, and forming the third conductive layer disposed on the fourth insulating layer, as shown in Figure 11A and Figure 11B . Figure 11B is Figure 11A a schematic view of the third conductive layer in

[0225] In an example embodiment, the third conductive layer pattern of the plurality of circuit units in the display substrate can each include: the first connecting electrode 41, the second connecting electrode 42, the third connecting electrode 43, the fourth connecting electrode 44, the fifth connecting electrode 45, the sixth connecting electrode 46, the seventh connecting electrode 47, the eighth connecting electrode 48, the ninth connecting electrode 49, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second initial signal line 82, and the first reference signal line 91.

[0226] In the example embodiment, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second initial signal line 82, and the first reference signal line 91 can have a linear shape with a main body extending along the first direction X. The second scan signal line 62, the third scan signal line 63, and the first reference signal line 91 can be located on the side opposite to the second direction Y of the fourth plate 74, the fourth scan signal line 64, the fifth scan signal line 65, and the second initial signal line 82 can be located on the side of the second direction Y of the third plate 73, and the first power connection line 68 can be located on the side of the second direction Y of the fourth plate 74, and the orthographic projection of the first power connection line 68 on the substrate at least partially overlaps the orthographic projection of the third plate 73 on the substrate.

[0227] In the example embodiment, the third scan signal line 63 can be located on the side opposite to the second direction Y of the fourth plate 74, the second scan signal line 62 can be located on the side opposite to the second direction Y of the third scan signal line 63, and the first reference signal line 91 can be located on the side opposite to the second direction Y of the second scan signal line 62.

[0228] In the example embodiment, the fourth scan signal line 64 can be located on the side of the second direction Y of the third plate 73, the fifth scan signal line 65 can be located on the side of the second direction Y of the fourth scan signal line 64, and the second initial signal line 82 can be located on the side of the second direction Y of the fifth scan signal line 65.

[0229] In the example embodiment, the first power connection line 68 can have a broken line shape with a main body extending along the first direction X, the orthographic projection of the first power connection line 68 on the substrate does not overlap the orthographic projection of the fourth plate 74 on the substrate, and the first power connection line 68 is configured to be connected with a first power line formed later to form a high-voltage power grid structure with a mesh communication structure on the display substrate.

[0230] In the example embodiment, the second scan signal line 62 is connected with the ninth gate electrode 29 in each circuit unit through the nineteenth via V19, so that the second scan signal line 62 is connected with the ninth gate electrode 29 of the ninth transistor T9, and the second scan signal line 62 can control the on and off of the ninth transistor T9.

[0231] In the example embodiment, the fifth scan signal line 65 is connected with the second gate electrode 22 in each circuit unit through the fifteenth via V15, so that the fifth scan signal line 65 is connected with the second gate electrode 22 of the second transistor T2, and the fifth scan signal line 65 can control the on and off of the second transistor T2.

[0232] In the example embodiment, the second scan signal line 62 and the fifth scan signal line 65 can extend to the back of the frame area and be connected to the same gate drive circuit to realize the output of the same scan signal.

[0233] In the example embodiment, the third scan signal line 63 is connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via V16, so that the third scan signal line 63 is connected to the fourth gate electrode 24 of the fourth transistor T4, and the third scan signal line 63 can control the on and off of the fourth transistor T4.

[0234] In the example embodiment, the fourth scan signal line 64 is connected to the first gate electrode 21 in each circuit unit through the fourteenth via V14, so that the fourth scan signal line 64 is connected to the first gate electrode 21 of the first transistor T1, and the fourth scan signal line 64 can control the on and off of the first transistor T1.

[0235] In the example embodiment, the second initial signal line 82 is connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, so that the second initial signal line 82 is connected to the first electrode of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal to the first electrode of the seventh transistor T7.

[0236] In the example embodiment, the second active connection line 20 of the semiconductor layer is directly connected to the first region of the seventh active layer of the plurality of circuit units in one unit row, and the second initial signal line 82 of the third conductive layer is connected to the first region of the seventh active layer in the plurality of circuit units in one unit row through the via, so that the second active connection line 20 and the second initial signal line 82 form a double-layer structure signal line, which not only ensures that the plurality of first regions of the seventh active layer in one unit row have the same potential, but also reduces the resistance of the signal line, reduces the voltage drop of the second initial signal, and is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0237] In the example embodiment, the second initial signal line 82 is provided with a second initial connection block 82-1 on one side close to the fifth scan signal line 65, the first end of the second initial connection block 82-1 is connected to the second initial signal line 82, and the second end of the second initial connection block 82-1 extends towards the direction of the fifth scan signal line 65 and is connected to the first region of the seventh active layer through the seventh via V7.

[0238] In the example embodiment, the first reference signal line 91 is connected with the first area of the ninth active layer in each circuit unit through the ninth via hole V9, so that the first reference signal line 91 is connected with the first electrode of the ninth transistor T9, and the first reference signal line 91 can write the first reference signal to the first electrode of the ninth transistor T9.

[0239] In the example embodiment, since the first active connection line 10 of the semiconductor layer is directly connected with the first area of the ninth active layer of the plurality of circuit units in one unit row, and the first reference signal line 91 of the third conductive layer is connected with the first area of the ninth active layer of the plurality of circuit units in one unit row through the via hole, the first active connection line 10 and the first reference signal line 91 form a double-layer signal line, which not only ensures that the plurality of first areas of the ninth active layer in one unit row have the same potential, but also reduces the resistance of the signal line, reduces the voltage drop of the first reference signal, and is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0240] In the example embodiment, the first reference signal line 91 is provided with a first reference connection block 91-1 away from the side of the second scan signal line 62, the first end of the first reference connection block 91-1 is connected with the first reference signal line 91, and the second end of the first reference connection block 91-1 extends away from the second scan signal line 62, respectively. The first reference connection block 91-1 is configured to be connected with the subsequently formed reference signal connection line.

[0241] In the example embodiment, the first power connection line 68 is connected with the fourth electrode plate 74 in each circuit unit through the thirteenth via hole V13, so that the first power connection line 68 is connected with the fourth electrode plate 74. Since the first power connection line 68 is connected with the subsequently formed first power line, the first power connection line 68 can write the first power signal to the upper electrode plate of the second storage capacitor.

[0242] In the example embodiment, the first power connection line 68 is provided with a first power connection block 68-1 on the side close to the fourth electrode plate 74, the first end of the first power connection block 68-1 is connected with the first power connection line 68, and the second end of the first power connection block 68-1 extends towards the fourth electrode plate 74. In the example embodiment, the first power connection block 68-1 is configured to be connected with the fourth electrode plate 74 through the thirteenth via hole V13, and is configured to be connected with the subsequently formed first power line.

[0243] In an example embodiment, the first connection electrode 41 can have a shape of a bar with a main body portion extending along the second direction Y, and can be disposed on a side of the first power supply connection line 68 close to the fourth scan signal line 64. A first end of the first connection electrode 41 is connected to a second region of the first active layer (also a first region of the second active layer) through a second via V2, and a second end of the first connection electrode 41 is connected to the first plate 71 through a tenth via V10.

[0244] In an example embodiment, the first connection electrode 41 can make the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first plate 71 of the first storage capacitor have the same potential, and the first connection electrode 41 can serve as a first node N1 in the pixel driving circuit.

[0245] In an example embodiment, the second connection electrode 42 can have a shape of a bar with a main body portion extending along the second direction Y, and can be disposed on a side of the first reference signal line 91 close to the first power supply connection line 68. A first end of the second connection electrode 42 is connected to the third plate 73 through a twelfth via V12, a second end of the second connection electrode 42 is connected to a second region of the fourth active layer (also a second region of the ninth active layer) through a fourth via V4, and a middle portion of the first end and the second end of the second connection electrode 42 is connected to the second plate 72 through an eleventh via V11.

[0246] In an example embodiment, the second connection electrode 42 can make the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third plate 73 of the first storage capacitor, and the second plate 72 of the second storage capacitor have the same potential, and the second connection electrode 42 can serve as a fifth node N5 in the pixel driving circuit.

[0247] In an example embodiment, the third connection electrode 43 can have a shape of a block, and can be located between the first reference signal line 91 and the first power supply connection line 68. The third connection electrode 43 can be connected to a first region of the fourth active layer through a third via V3. In an example embodiment, the third connection electrode 43 can serve as a first electrode of the fourth transistor T4, and can be configured to be connected to a data signal line formed later.

[0248] In an example embodiment, the fourth connection electrode 44 can have a shape of a block, and can be located between the fifth scan signal line 65 and the second initial signal line 82. The fourth connection electrode 44 can be connected to a first region of the fifth active layer through a fifth via V5. In an example embodiment, the fourth connection electrode 44 can serve as a first electrode of the fifth transistor T5, and can be configured to be connected to a first power supply line formed later.

[0249] In an exemplary embodiment, the fifth connection electrode 45 can have an "L" shape, can be located between the fifth scan signal line 65 and the second initial signal line 82, and the fifth connection electrode 45 can be connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the sixth via V6. In an exemplary embodiment, the fifth connection electrode 45 can be configured as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and can be connected to the anode connection electrode formed later.

[0250] In an exemplary embodiment, the sixth connection electrode 46 can have a bar shape in which a main body portion extends along the first direction X, can be located between the fifth scan signal line 65 and the second initial signal line 82, and a first end of the sixth connection electrode 46 can be connected to the first region of the eighth active layer through the eighth via V8, and a second end of the sixth connection electrode 46 can be connected to the second reference connection block 92-1 through the twenty-second via V22. In an exemplary embodiment, the sixth connection electrode 46 can be configured as the first electrode of the eighth transistor T8, and since the second reference connection block 92-1 is connected to the second reference signal line 92, the second reference signal line 92 is connected to the first electrode of the eighth transistor T8, and the second reference signal line 92 in the nth unit row can write the second reference signal to the first electrode of the eighth transistor T8 in the (n-1)th unit row.

[0251] In an exemplary embodiment, the seventh connection electrode 47 can have a bar shape in which a main body portion extends along the first direction X, can be located between the fifth scan signal line 65 and the second initial signal line 82, a first end of the seventh connection electrode 47 can be connected to the fifth gate electrode 25 through the seventeenth via V17, and a second end of the seventh connection electrode 47 can be connected to the first light emitting connection block 31-1 through the twentieth via V20. Since the first light emitting connection block 31-1 is connected to the first light emitting signal line 31, the first light emitting signal line 31 is connected to the fifth gate electrode 25 of the fifth transistor T5, and the first light emitting signal line 31 can control the turn-on and turn-off of the fifth transistor T5.

[0252] In an exemplary embodiment, the eighth connection electrode 48 can have a bar shape in which a main body portion extends along the first direction X, can be located between the fifth scan signal line 65 and the second initial signal line 82, a first end of the eighth connection electrode 48 can be connected to the sixth gate electrode 26 through the eighteenth via V18, and a second end of the eighth connection electrode 48 can be connected to the second light emitting connection block 32-1 through the twenty-first via V21. Since the second light emitting connection block 32-1 is connected to the second light emitting signal line 32, the second light emitting signal line 32 is connected to the sixth gate electrode 26 of the sixth transistor T6, and the second light emitting signal line 32 can control the turn-on and turn-off of the sixth transistor T6.

[0253] In the example embodiment, the ninth connection electrode 49 can have a strip shape with a main body extending along the first direction X, can be located between the fifth scan signal line 65 and the second initial signal line 82, a first end of the ninth connection electrode 49 is connected to the first region of the first active layer through the first via V1, and a second end of the ninth connection electrode 49 is connected to the first initial connection block 81-1 through the twenty-third via V23. Since the first initial connection block 81-1 is connected to the first initial signal line 81, the first initial signal line 81 is connected to the first electrode of the first transistor T1, and the first initial signal line 81 can write the first initial signal to the first electrode of the first transistor T1.

[0254] In the example embodiment, since the first plate 71 is connected to the second region of the first active layer (also the first region of the second active layer) through the first connection electrode 41, the first plate 71 has the potential of the first node N1. Since the third plate 73 is connected to the second region of the fourth active layer (also the second region of the ninth active layer) through the second connection electrode 42, the third plate 73 has the potential of the fifth node N5. In this way, the first plate 71 having the potential of the first node N1 and the third plate 73 having the potential of the fifth node N5 constitute the first storage capacitor of the pixel driving circuit.

[0255] In the example embodiment, since the second plate 72 is connected to the second region of the fourth active layer (also the second region of the ninth active layer) through the second connection electrode 42, the second plate 72 has the potential of the fifth node N5. Since the fourth plate 74 is connected to the first power connection line 68, and the first power connection line 68 is connected to the first power line formed subsequently, the fourth plate 74 has the potential of the first power line. In this way, the second plate 72 having the potential of the fifth node N5 and the fourth plate 74 having the potential of the first power line constitute the second storage capacitor of the pixel driving circuit.

[0256] (16) Forming a fifth insulating layer pattern. In the example embodiment, forming the fifth insulating layer pattern can include: depositing a fifth insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the fifth insulating thin film by using a patterning process to form a fifth insulating layer covering the third conductive layer, and a plurality of vias are arranged in each circuit unit, as shown in Figure 12

[0257] In the example embodiment, the plurality of vias in each circuit unit of the display substrate at least includes: a thirty-first via V31, a thirty-second via V32, a thirty-third via V33, a thirty-fourth via V34, and a thirty-fifth via V35.

[0258] ​In an example embodiment, the third thirty-one via V31 has a projection on the substrate within a projection of the third connection electrode 43 on the substrate, the fifth insulating layer within the third thirty-one via V31 is removed to expose a surface of the third connection electrode 43, and the third thirty-one via V31 is configured to connect a data signal line formed subsequently therethrough to the third connection electrode 43.

[0259] In an example embodiment, the third thirty-two via V32 has a projection on the substrate within a projection of the fourth connection electrode 44 on the substrate, the fifth insulating layer within the third thirty-two via V32 is removed to expose a surface of the fourth connection electrode 44, and the third thirty-two via V32 is configured to connect a first power supply line formed subsequently therethrough to the fourth connection electrode 44.

[0260] In an example embodiment, the third thirty-three via V33 has a projection on the substrate within a projection of the fifth connection electrode 45 on the substrate, the fifth insulating layer within the third thirty-three via V33 is removed to expose a surface of the fifth connection electrode 45, and the third thirty-three via V33 is configured to connect an anode connection electrode formed subsequently therethrough to the fifth connection electrode 45.

[0261] In an example embodiment, the third thirty-four via V34 has a projection on the substrate within a projection of the first reference connection block 91-1 of the first reference signal line 91 on the substrate, the fifth insulating layer within the third thirty-four via V34 is removed to expose a surface of the first reference connection block 91-1, and the third thirty-four via V34 is configured to connect a reference signal connection line formed subsequently therethrough to the first reference connection block 91-1.

[0262] In an example embodiment, the third thirty-five via V35 has a projection on the substrate within a projection of the first power supply connection block 68-1 of the first power supply connection line 68 on the substrate, the fifth insulating layer within the third thirty-five via V35 is removed to expose a surface of the first power supply connection block 68-1, and the third thirty-five via V35 is configured to connect a first power supply line formed subsequently therethrough to the first power supply connection block 68-1.

[0263] (17) Forming a fourth conductive layer pattern. In an example embodiment, forming a fourth conductive layer pattern can include: on a substrate on which the aforementioned pattern is formed, depositing a fourth conductive thin film, patterning the fourth conductive thin film using a patterning process, forming a fourth conductive layer disposed on the fifth insulating layer, as shown in Figure 13A and 13B Figure 13B Figure 13A ​​A schematic view of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0264] In an exemplary embodiment, the fourth conductive layer pattern of each of the plurality of circuit units in the display substrate can include a first power supply line 51, a data signal line 53, a reference signal connection line 54, and an anode connection electrode 55.

[0265] In an exemplary embodiment, the first power supply line 51, the data signal line 53, and the reference signal connection line 54 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, the first power supply line 51 can be located on one side of the data signal line 53 in the first direction X, and the reference signal connection line 54 can be located on one side of the first power supply line 51 in the first direction X, i.e., the first power supply line 51 can be located between the data signal line 53 and the reference signal connection line 54.

[0266] In an exemplary embodiment, the first power supply line 51 can have a shape of a broken line with a main body portion extending along the second direction Y, and a power supply shielding electrode 51-1 can be disposed on one side of the first power supply line 51 close to the reference signal connection line 54, a first end of the power supply shielding electrode 51-1 can be connected to the first power supply line 51, and a second end of the power supply shielding electrode 51-1 can extend toward the reference signal connection line 54. The power supply shielding electrode 51-1 can have a shape of a rectangle, and an orthographic projection of the power supply shielding electrode 51-1 on the base can at least partially overlap an orthographic projection of the first connection electrode 41 on the base. Since the first connection electrode 41 serves as the first node N1 in the pixel driving circuit, the power supply shielding electrode 51-1 with a constant voltage can effectively shield the first node N1 in the pixel driving circuit from other signals, thereby avoiding the influence of other signals (such as data voltage jump) on the potential of the first node N1 in the pixel driving circuit, and improving the display effect.

[0267] In an exemplary embodiment, the first power supply line 51 and the power supply shielding electrode 51-1 can be an integrated structure connected to each other.

[0268] In an exemplary embodiment, the orthographic projection of the power supply shielding electrode 51-1 on the base can contain the orthographic projection of the first connection electrode 41 on the base.

[0269] In the example embodiment, the first power line 51 is provided with a first connecting electrode block 51-2 on the side close to the data signal line 53, the first end of the first connecting electrode block 51-2 is connected with the first power line 51, and the second end of the first connecting electrode block 51-2 extends towards the data signal line 53. The first connecting electrode block 51-2 can be connected with the fourth connecting electrode 44 through the thirty-second via V32. Since the fourth connecting electrode 44 is connected with the first area of the fifth active layer through the via, the first power line 51 writes the first power signal to the first electrode of the fifth transistor T5.

[0270] In the example embodiment, the first power line 51 is provided with a second connecting electrode block 51-3 on the side close to the reference signal connecting line 54, the first end of the second connecting electrode block 51-3 is connected with the first power line 51, and the second end of the second connecting electrode block 51-3 extends towards the reference signal connecting line 54. The second connecting electrode block 51-3 can be connected with the first power connecting block 68-1 through the thirty-fifth via V35. Since the first power connecting block 68-1 is connected with the first power connecting line 68, the first power connecting line 68 extending along the first direction X is connected with the first power line 51 extending along the second direction Y, so that the first power line 51 and the first power connecting line 68 form a mesh structure for transmitting power signals on the display substrate, which not only can effectively reduce the resistance of the first power line 51 and the voltage drop of the first power signal, but also can effectively improve the uniformity of the first power signal in the display substrate and the display uniformity, thereby improving the display quality and display performance.

[0271] In the example embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode 42 on the substrate. Since the second connecting electrode 42 is the fifth node N5 in the pixel driving circuit, the first power line 51 with constant voltage can effectively shield the influence of other signals in the pixel driving circuit on the fifth node N5, thereby avoiding the influence of other signals on the potential of the fifth node N5 in the pixel driving circuit and improving the display effect.

[0272] In the example embodiment, the first power line 51 can be designed with non-equal width, which not only can facilitate the layout of the pixel structure, but also can reduce the parasitic capacitance between the first power line and the data signal line.

[0273] In an exemplary embodiment, the data signal line 53 can be in a shape of a straight line with a main body extending along the second direction Y, and a data signal connecting block 53-1 is disposed on the data signal line 53, a first end of the data signal connecting block 53-1 is connected with the data signal line 53, and a second end of the data signal connecting block 53-1 extends towards the first end along the first direction X and the opposite direction of the first direction X. The data signal connecting block 53-1 is connected with the third connection electrode 43 through the thirty-first via V31. Since the third connection electrode 43 is connected with the first area of the fourth active layer through the via, the data signal line 53 writes the data signal to the first electrode of the fourth transistor T4.

[0274] In an exemplary embodiment, the reference signal connecting line 54 can be in a shape of a straight line with a main body extending along the second direction Y, and a reference signal connecting block 54-1 is disposed on the reference signal connecting line 54, a first end of the reference signal connecting block 54-1 is connected with the reference signal connecting line 54, and a second end of the reference signal connecting block 54-1 extends towards the direction of the first power supply line 51. The reference signal connecting block 54-1 can be connected with the first reference connecting block 91-1 through the thirty-fourth via V34. Since the first reference connecting block 91-1 is connected with the first reference signal line 91, the first reference signal line 91 extending along the first direction X and the reference signal connecting line 54 extending along the second direction Y are connected with each other, so that the first reference signal line 91 and the reference signal connecting line 54 form a mesh structure for transmitting the first reference signal on the display substrate, which not only effectively reduces the resistance of the first reference signal line and the voltage drop of the first reference signal, but also effectively improves the uniformity of the first reference signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display performance.

[0275] In an exemplary embodiment, the anode connecting electrode 55 can be in a shape of a rectangle, and the anode connecting electrode 55 is connected with the fifth connection electrode 45 through the thirty-third via V33. Since the fifth connection electrode 45 is connected with the second area of the sixth active layer (also the second area of the seventh active layer) through the via, the anode connecting electrode 55 is connected with the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the anode connecting electrode 55 is configured to be connected with the anode to be formed subsequently, so that the pixel driving circuit can drive the light emitting device.

[0276] In an exemplary embodiment, the anode connecting electrode 55 has an orthographic projection on the substrate that at least partially overlaps with an orthographic projection of the anode repair line 33 on the substrate.

[0277] In the example embodiment, the first power supply connection lines 68 of the third conductive layer can be arranged in each unit row, the first power supply lines 51 of the fourth conductive layer can be arranged in each unit column, and the plurality of first power supply lines 51 are connected to the plurality of first power supply connection lines 68 respectively, forming a mesh structure for transmitting power supply signals.

[0278] In the example embodiment, the first reference signal lines 91 of the third conductive layer can be arranged in each unit row, the reference signal connection lines 54 of the fourth conductive layer can be arranged in each unit column, and the plurality of first reference signal lines 91 are connected to the plurality of reference signal connection lines 54 respectively, forming a mesh structure for transmitting first reference signals.

[0279] The subsequent preparation process can include forming a first flat layer pattern, the first flat layer being provided with a plurality of anode vias, the orthographic projection of the anode via on the substrate being within the range of the orthographic projection of the anode connection electrode on the substrate, the first flat layer in the anode via being removed to expose the surface of the anode connection electrode, and the anode via being configured to enable the subsequently formed anode to be connected to the anode connection electrode through the via.

[0280] At this point, the drive circuit layer of the embodiment is prepared on the substrate. In the example embodiment, after the drive circuit layer is prepared, the light emitting structure layer and the packaging structure layer can be prepared in sequence on the drive circuit layer, which will not be described here.

[0281] The first shielding electrode, the second shielding electrode, the third shielding electrode, and the fourth shielding electrode are provided in the embodiment of the present disclosure, which can shield the influence of data voltage jump on the first transistor T1, the second transistor T2, the fourth transistor T4, the ninth transistor T9, and the fifth node N5, avoid the influence of data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0282] The power supply shielding electrode is provided in the embodiment of the present disclosure, which can effectively shield the influence of other signals in the pixel driving circuit on the first node N1, avoid the influence of other signals on the potential of the first node N1 of the pixel driving circuit, and improve the display effect.

[0283] The first power supply connection lines 68 extending along the first direction X of the main body part are connected to the first power supply lines 51 extending along the second direction Y of the main body part, and a high-voltage power supply grid structure forming a mesh communication structure on the display substrate is formed.

[0284] The preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.

[0285] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device with pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), etc., which are not limited herein.

[0286] Figure 14 Another schematic diagram of the planar structure of the display substrate of the exemplary embodiment of the present disclosure is shown, which illustrates the structure of the pixel driving circuit in one circuit unit of the display substrate. As shown in the figure, the structure of the pixel driving circuit of the present exemplary embodiment is basically the same as that of the foregoing embodiments, except that the first shielding electrode 36 and the second shielding electrode 37 are arranged in the third conductive layer, and the first shielding electrode 36 and the second shielding electrode 37 are both connected with the first power supply connection line 68, the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 on the substrate; the orthographic projection of the second shielding electrode 37 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 on the substrate. Figure 14

[0287] Figure 15a Figure 14 A schematic diagram of the second conductive layer in the present exemplary embodiment is shown, Figure 15b Figure 14 A schematic diagram of the third conductive layer in the present exemplary embodiment is shown. As shown in the figure, Figure 14 Figure 15a As shown in the figures, the fourth plate 74 is not provided with the first shielding electrode 36 and the second shielding electrode 37 on the side close to the first light-emitting signal line 31, and the edge of the fourth plate 74 on the side close to the first light-emitting signal line 31 is in a straight line shape, which is located on the side away from the first light-emitting signal line 31 of the third plate 73.

[0288] As shown in the figures, Figure 14 Figure 15b ​​​​​As shown, the first power supply connection line 68 can have a shape of a broken line with a main body extending along the first direction X. The first power supply connection line 68 can be located on one side of the fourth polar plate 74 in the second direction Y, and a projection of the first power supply connection line 68 on the substrate at least partially overlaps a projection of the third polar plate 73 on the substrate. The first power supply connection line 68 is provided with a first shielding electrode 36 on a side close to the fourth scan signal line 64. The first shielding electrode 36 can have a shape of a line with a main body extending along the second direction Y. A first end of the first shielding electrode 36 is connected to the first power supply connection line 68, and a second end of the first shielding electrode 36 extends toward the fourth scan signal line 64. A projection of the first shielding electrode 36 on the substrate at least partially overlaps a projection of the first active layer between the two gate electrodes of the first transistor T1 on the substrate. In an example embodiment, the first shielding electrode 36 is configured to shield the influence of data voltage jump on the first transistor T1, avoid the influence of data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0289] In an example embodiment, the first power supply connection line 68 and the first shielding electrode 36 can be an integrated structure connected to each other.

[0290] In an example embodiment, as shown in Figure 14 and Figure 15b the first power supply connection line 68 is provided with a second shielding electrode 37 on a side close to the fourth scan signal line 64. The second shielding electrode 37 can have a shape of a line with a main body extending along the second direction Y. A first end of the second shielding electrode 37 is connected to the first power supply connection line 68, and a second end of the second shielding electrode 37 extends toward the fourth scan signal line 64. A projection of the second shielding electrode 37 on the substrate at least partially overlaps a projection of the first active layer between the two gate electrodes of the second transistor T2 on the substrate. In an example embodiment, the second shielding electrode 37 is configured to shield the influence of data voltage jump on the second transistor T2, avoid the influence of data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0291] In an example embodiment, the first power supply connection line 68 and the second shielding electrode 37 can be an integrated structure connected to each other.

[0292] In an example embodiment, the at least one circuit unit of the example embodiment further includes a shielding connection line 69, which can be located in the third conductive layer. The shielding connection line 69 can have a shape of a line with a main body extending along the first direction X. The shielding connection line 69 can be located between the first power supply connection line 68 and the fourth scan signal line 64. The shielding connection line 69 is connected to the second end of the first shielding electrode 36, and the shielding connection line 69 is connected to the first power supply connection line 68 through the first shielding electrode 36.

[0293] In the example embodiment, the shielding connection line 69 and the first shielding electrode 36 can be an integrated structure connected to each other.

[0294] In the example embodiment, the shielding connection line 69 of the example embodiment can be connected with the second end of the second shielding electrode 37, and the shielding connection line 69 is connected with the first power supply connection line 68 through the second shielding electrode 37.

[0295] In the example embodiment, the shielding connection line 69 and the second shielding electrode 37 can be an integrated structure connected to each other.

[0296] The example embodiment of the present disclosure connects the shielding connection line with the first power supply connection line, and the first power supply connection line is connected with the first power supply line, so that the first power supply line forms a mesh structure for transmitting power supply signals on the display substrate with the first power supply connection line and the shielding connection line. This not only can effectively reduce the resistance of the first power supply line and reduce the voltage drop of the first power supply signal, but also can effectively improve the uniformity of the first power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0297] Figure 16 Another schematic diagram of a planar structure of a display substrate of the example embodiment of the present disclosure is shown, which shows the structure of a pixel driving circuit in one circuit unit in the display substrate. As shown in Figure 16 , the structure of the pixel driving circuit of the example embodiment is basically the same as that of the Figure 14 , the difference is that the first power supply connection line 68 of the example embodiment is arranged on one side of the second direction Y of the first connection electrode 41, and the at least one circuit unit further comprises a second power supply connection block 68-2.

[0298] Figure 17 A schematic diagram of the third conductive layer in the Figure 16 . In the example embodiment, as shown in Figure 16 and Figure 17 , the at least one circuit unit further comprises a second power supply connection block 68-2, and the shape of the second power supply connection block 68-2 can be block-shaped. The second power supply connection block 68-2 is located on one side of the third scan signal line 63 in the second direction Y, on the side opposite to the first connection electrode 41 in the second direction Y, and on one side of the second connection electrode 42 in the first direction X. The second power supply connection block 68-2 is configured to be connected with the fourth plate 74 through the thirteenth via V13, and is configured to be connected with the first power supply line through the thirty-fifth via V35.

[0299] In an exemplary embodiment, the shape of the first power connection line 68 in this exemplary embodiment can be a line shape extending along the first direction X of the main body portion. The first power connection line 68 can be located on the side of the fourth scan signal line 64 opposite to the second direction Y, and on the side of the first connection electrode 41 in the second direction Y, that is, the first power connection line 68 can be located between the fourth scan signal line 64 and the first connection electrode 41. The first power connection line 68 can be connected to the first power line 51 through the thirty-sixth via V36, thus realizing the interconnection between the first power connection line 68 extending along the first direction X of the main body portion and the first power line 51 extending along the second direction Y of the main body portion.

[0300] In an exemplary embodiment, the first shielding electrode 36 may have a block-like shape in its main body. The first shielding electrode 36 is connected to the first power connection line 68, and the orthographic projection of the first shielding electrode 36 onto the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor T1 onto the substrate. In this exemplary embodiment, the first shielding electrode 36 is configured to shield the first transistor T1 from the influence of data voltage transitions, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0301] In an exemplary embodiment, the first power connection line 68 and the first shielding electrode 36 can be an integral structure that is interconnected.

[0302] In an exemplary embodiment, the second shielding electrode 37 can be block-shaped with its main body. The second shielding electrode 37 is connected to the first power connection line 68, and the orthographic projection of the second shielding electrode 37 onto the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the second transistor T2 onto the substrate. In this exemplary embodiment, the second shielding electrode 37 is configured to shield the second transistor T2 from the influence of data voltage transitions, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0303] In an exemplary embodiment, the first power connection line 68 and the second shielding electrode 37 can be an integral structure that is interconnected.

[0304] like Figure 16 and Figure 17 As shown, the orthographic projection of the thirty-fifth via V35, one of the multiple vias of the circuit unit in the display substrate, is located within the range of the orthographic projection of the second power connection block 68-2 on the substrate. The fifth insulating layer inside the thirty-fifth via V35 is removed, exposing the surface of the second power connection block 68-2. The thirty-fifth via V35 is configured to allow the first power line 51 to be connected to the second power connection block 68-2 through the via.

[0305] In the example embodiment, the plurality of via holes of the circuit unit in the display substrate further include a thirty-sixth via hole V36, a projection of the thirty-sixth via hole V36 on the base is located within a projection of the first power connection line 68 on the base, a fifth insulating layer in the thirty-sixth via hole V36 is removed to expose a surface of the first power connection line 68, and the thirty-sixth via hole V36 is configured to connect the first power line 51 to the first power connection line 68 through the via hole.

[0306] In the example embodiment, the first power line 51 of the circuit unit in the display substrate can have a shape of a polyline with a main body extending along the second direction Y, a third connection electrode block 51-4 is arranged on a side of the first power line 51 close to the data signal line 53, a first end of the third connection electrode block 51-4 is connected to the first power line 51, and a second end of the third connection electrode block 51-4 extends toward the data signal line 53. The third connection electrode block 51-4 can be connected to the first power connection line 68 through the thirty-sixth via hole V36. Since the third connection electrode block 51-4 is connected to the first power connection line 68, the first power connection line 68 with the main body extending along the first direction X and the first power line 51 with the main body extending along the second direction Y are connected to each other, so that the first power line 51 and the first power connection line 68 form a mesh structure for transmitting a power signal on the display substrate. This not only effectively reduces the resistance of the first power line 51 and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display performance.

[0307] In some embodiments, the first power connection line of the example embodiment can also be connected to other constant-voltage lines other than the first power line through a via hole, such as a second power line (VSS), a reference signal connection line, or an initial signal line.

[0308] Figure 18 FIG. 8 is a schematic view of another example embodiment of a display substrate according to the present disclosure. Figure 18 FIG. 9 is a schematic view of another example embodiment of a display substrate according to the present disclosure. Figure 5 FIG. 10 is a schematic view of another example embodiment of a display substrate according to the present disclosure. Figure 5 FIG. 11 is a schematic view of another example embodiment of a display substrate according to the present disclosure. Figure 5 FIG. 12 is a schematic view of another example embodiment of a display substrate according to the present disclosure.

[0309] In an example embodiment, the area of the orthogonal projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 onto the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the area of the orthogonal projection of the fourth active layer of the fourth transistor T4 onto the substrate.

[0310] In an example embodiment, the area of the orthogonal projection of the semiconductor layer between the two gate electrodes of the ninth transistor T9 onto the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the area of the orthogonal projection of the ninth active layer of the ninth transistor T9 onto the substrate.

[0311] In an example embodiment, the length of the semiconductor layer between the two gate electrodes of the fourth transistor T4 in the first direction X of the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the length of the fourth active layer of the fourth transistor T4 in the first direction X of the substrate. Figure 5 In an example embodiment, the length of the semiconductor layer between the two gate electrodes of the fourth transistor T4 in the first direction X of the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the length of the fourth active layer of the fourth transistor T4 in the first direction X of the substrate; and the length of the semiconductor layer between the two gate electrodes of the fourth transistor T4 in the second direction Y of the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the length of the fourth active layer of the fourth transistor T4 in the second direction Y of the substrate. Figure 5 In an example embodiment, the length of the semiconductor layer between the two gate electrodes of the fourth transistor T4 in the second direction Y of the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the length of the fourth active layer of the fourth transistor T4 in the second direction Y of the substrate.

[0312] In an example embodiment, the length of the semiconductor layer between the two gate electrodes of the ninth transistor T9 in the first direction X of the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the length of the ninth active layer of the ninth transistor T9 in the first direction X of the substrate. Figure 5 In an example embodiment, the length of the semiconductor layer between the two gate electrodes of the ninth transistor T9 in the first direction X of the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the length of the ninth active layer of the ninth transistor T9 in the first direction X of the substrate; and the length of the semiconductor layer between the two gate electrodes of the ninth transistor T9 in the second direction Y of the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the length of the ninth active layer of the ninth transistor T9 in the second direction Y of the substrate. Figure 5 In an example embodiment, the length of the semiconductor layer between the two gate electrodes of the ninth transistor T9 in the second direction Y of the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the length of the ninth active layer of the ninth transistor T9 in the second direction Y of the substrate.

[0313] In an example embodiment, the fourth transistor T4 and the ninth transistor T9 are configured to reduce the leakage current by increasing the area of the orthogonal projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 and the ninth transistor T9 onto the substrate.

[0314] Figure 19 In another example embodiment of the present disclosure, a magnified view of the first storage capacitor region and the second storage capacitor region in the display substrate is shown. As shown in FIG. 6, the structure of the pixel driving circuit of the present example embodiment is substantially the same as that of the example embodiment shown in FIG. 5, except that the present example embodiment shows that the semiconductor layer in the display substrate is not provided with the first active connection line, and the area of the orthogonal projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 onto the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the area of the orthogonal projection of the fourth active layer of the fourth transistor T4 onto the substrate. Figure 19 As shown in FIG. 6, the structure of the pixel driving circuit of the present example embodiment is substantially the same as that of the example embodiment shown in FIG. 5, except that the present example embodiment shows that the semiconductor layer in the display substrate is not provided with the first active connection line, and the area of the orthogonal projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 onto the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the area of the orthogonal projection of the fourth active layer of the fourth transistor T4 onto the substrate. Figure 18 As shown in FIG. 6, the structure of the pixel driving circuit of the present example embodiment is substantially the same as that of the example embodiment shown in FIG. 5, except that the present example embodiment shows that the semiconductor layer in the display substrate is not provided with the first active connection line, and the area of the orthogonal projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 onto the substrate is greater than or equal to 3 times, for example, 5 times, 7 times, 10 times, 15 times, 20 times, etc., the area of the orthogonal projection of the fourth active layer of the fourth transistor T4 onto the substrate.Figure 18 The illustrated embodiment shows the area of the semiconductor layer between the two gate electrodes of the fourth transistor T4 in the substrate. The illustrated embodiment shows the area of the semiconductor layer between the two gate electrodes of the ninth transistor T9 in the substrate. Figure 18 The illustrated embodiment shows the area of the semiconductor layer between the two gate electrodes of the ninth transistor T9 in the substrate.

[0315] In the exemplary implementation, since the first active connection line is not provided, the illustrated embodiment shows that the semiconductor layer between the two gate electrodes of the fourth transistor T4 and the semiconductor layer between the two gate electrodes of the ninth transistor T9 in the substrate can extend along the second direction Y, thereby increasing the area of the semiconductor layer in the substrate. The illustrated embodiment shows the length of the semiconductor layer between the two gate electrodes of the fourth transistor T4 in the second direction Y, which is greater than Figure 18 The illustrated embodiment shows the length of the semiconductor layer between the two gate electrodes of the fourth transistor T4 in the second direction Y. The illustrated embodiment shows the length of the semiconductor layer between the two gate electrodes of the ninth transistor T9 in the second direction Y, which is greater than Figure 18 The illustrated embodiment shows the length of the semiconductor layer between the two gate electrodes of the ninth transistor T9 in the second direction Y.

[0316] The illustrated embodiment shows that the substrate reduces the leakage current of the fourth transistor T4 and the ninth transistor T9 by increasing the area of the semiconductor layer between the two gate electrodes of the fourth transistor T4 and the ninth transistor T9 in the substrate.

[0317] Figure 20 Another enlarged view of the first storage capacitor and the second storage capacitor region in the substrate is shown in the exemplary embodiment of the present disclosure. As shown in Figure 20 The structure of the pixel driving circuit in the illustrated embodiment is substantially the same as that shown in Figure 14 The illustrated embodiment shows that the pattern of the second conductive layer in the substrate further includes a fifth shielding electrode 74-1, the fifth shielding electrode 74-1 is connected with the fourth plate 74, and the projection of the fifth shielding electrode 74-1 on the substrate at least partially overlaps with the projection of the data signal line 53 on the substrate. The fifth shielding electrode 74-1 is configured to shield the signal of the data signal line 53 and ensure the uniform load of the data signal line 53.

[0318] In an exemplary embodiment, the first shielding electrode 36 and the second shielding electrode 37 are disposed in the third conductive layer, and both the first shielding electrode 36 and the second shielding electrode 37 are connected to the first power connection line 68. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 on the substrate; the orthographic projection of the second shielding electrode 37 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 on the substrate.

[0319] In an exemplary embodiment, the fifth shielding electrode 74-1 is located on one side of the fourth electrode plate 74 in the second direction Y. The fifth shielding electrode 74-1 can be a strip shape extending along the second direction Y. The first end of the fifth shielding electrode 74-1 is connected to the fourth electrode plate 74, and the second end of the fifth shielding electrode 74-1 extends along the second direction Y.

[0320] In an exemplary embodiment, the fourth electrode 74 and the fifth shielding electrode 74-1 can be an integral structure that is interconnected.

[0321] In some embodiments, the orthographic projection of the fifth shielding electrode on the substrate may not overlap with the orthographic projection of the data signal line on the substrate.

[0322] Figure 21 This is a schematic diagram of a third conductive layer in a display substrate, which is an exemplary embodiment of this disclosure. Figure 21 As shown, the structure of the pixel driving circuit in this exemplary embodiment is similar to... Figure 16 The illustrated embodiments are essentially the same, except that the third conductive layer in the display substrate of this exemplary embodiment further includes a sixth shielding electrode 68-3. The sixth shielding electrode 68-3 is connected to the first power connection line 68, and the orthographic projection of the sixth shielding electrode 68-3 on the substrate at least partially overlaps with the orthographic projection of the data signal line 53 on the substrate. The sixth shielding electrode 68-3 is configured to shield the signal of the data signal line 53 and ensure uniform load on the data signal line 53.

[0323] In an exemplary embodiment, the sixth shielding electrode 68-3 is located on the side of the first power connection line 68 opposite to the second direction Y. The sixth shielding electrode 68-3 can be a strip shape extending along the second direction Y. The first end of the sixth shielding electrode 68-3 is connected to the first power connection line 68, and the second end of the fifth shielding electrode 74-1 extends along the second direction Y.

[0324] In an exemplary embodiment, the first power connection line 68 and the sixth shielding electrode 68-3 can be an integral structure that is interconnected.

[0325] In the exemplary embodiments, the orthogonal projection of the sixth shielding electrode on the substrate is located in the orthogonal projection of the data signal line on the substrate, so as to avoid the sixth shielding electrode from affecting the light transmittance of the display substrate.

[0326] In the exemplary embodiments, the length of the sixth shielding electrode in the first direction X is greater than the length of the data signal line 53 in the first direction X, so as to ensure the flatness of the subsequently formed data signal line 53.

[0327] The present disclosure also provides a preparation method of a display substrate, for preparing the display substrate provided in the above embodiments.

[0328] In the exemplary embodiments, the preparation method of the display substrate can include:

[0329] forming a driving circuit layer on the substrate, the driving circuit layer including at least a plurality of circuit units, at least one circuit unit including a pixel driving circuit, the pixel driving circuit including a first storage capacitor, a second storage capacitor, at least one shielding electrode, and at least one transistor with a double-gate structure, the first storage capacitor including at least a first plate and a third plate, the orthogonal projection of the first plate on the substrate at least partially overlapping the orthogonal projection of the third plate on the substrate; the second storage capacitor including at least a second plate and a fourth plate, the orthogonal projection of the second plate on the substrate at least partially overlapping the orthogonal projection of the fourth plate on the substrate; the second plate being connected to the third plate, and the fourth plate being connected to a first power supply line; the orthogonal projection of the shielding electrode on the substrate at least partially overlapping the orthogonal projection of a node between two gate electrodes of the transistor with the double-gate structure on the substrate.

[0330] The present disclosure also provides a display device including the display substrate described above. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., and the embodiments of the present disclosure are not limited thereto.

[0331] Although the embodiments of the present disclosure are described above, the above description is only used to facilitate the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art can make any modifications and changes in the implementation form and details without departing from the spirit and scope of the present disclosure. The patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, The device includes a driving circuit layer disposed on a substrate. The driving circuit layer includes at least a plurality of circuit units. At least one circuit unit includes a pixel driving circuit. The pixel driving circuit includes a first storage capacitor, a second storage capacitor, at least one shielding electrode, and at least one transistor with a dual-gate structure. The first storage capacitor includes at least a first electrode plate and a third electrode plate. The orthographic projection of the first electrode plate on the substrate and the orthographic projection of the third electrode plate on the substrate at least partially overlap. The second storage capacitor includes at least a second plate and a fourth plate, wherein the orthographic projection of the second plate onto the substrate and the orthographic projection of the fourth plate onto the substrate at least partially overlap; The second electrode plate is connected to the third electrode plate, and the fourth electrode plate is connected to the first power line; The orthogonal projection of the shielding electrode on the substrate at least partially overlaps with the orthogonal projection of the node between the two gate electrodes of the dual-gate transistor on the substrate; The at least one dual-gate transistor includes a first initialization transistor, the first terminal of which is connected to a first initial signal line, and the second terminal of which is connected to the first plate of the first storage capacitor; the at least one shielding electrode includes a first shielding electrode, which is connected to the fourth plate, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate. The first shielding electrode includes a first extension segment and a first shielding segment. The first extension segment is a strip shape extending along a second direction. The first end of the first extension segment is connected to the fourth electrode plate, and the second end of the first extension segment is connected to the first end of the first shielding segment. The first shielding segment is a strip shape extending along a first direction. The first end of the first shielding segment is connected to the second end of the first extension segment, and the second end of the first shielding segment extends along the first direction. The orthographic projection of the first shielding segment on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate. The first direction intersects the second direction.

2. The display substrate as described in claim 1, characterized in that, The fourth electrode plate and the first shielding electrode are an integral structure.

3. The display substrate as described in claim 1, characterized in that, At least one circuit unit further includes at least one first power connection line extending along a first direction, the first power line having a shape that extends along a second direction, the first direction intersecting the second direction; the first power line is connected to the first power connection line to form a mesh structure for transmitting a first power signal.

4. The display substrate as described in claim 3, characterized in that, The at least one dual-gate transistor includes a first initialization transistor, the first electrode of which is connected to a first initial signal line, and the second electrode of which is connected to a first plate of the first storage capacitor; the at least one shielding electrode includes a first shielding electrode, which is connected to the first power supply connection line, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate.

5. The display substrate as described in claim 4, characterized in that, The first power connection line and the first shielding electrode are integrated into one structure.

6. The display substrate as described in claim 3, characterized in that, At least one circuit unit further includes a shielded connection line connected to the first power connection line; the at least one dual-gate transistor includes a first initialization transistor, the first electrode of the first initialization transistor is connected to a first initial signal line, and the second electrode of the first initialization transistor is connected to a first plate of the first storage capacitor; the at least one shielding electrode includes a first shielding electrode connected to the shielded connection line, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate.

7. The display substrate as described in claim 1, characterized in that, The at least one dual-gate transistor includes a compensation transistor, the first electrode of which is connected to the first plate of the first storage capacitor; the at least one shielding electrode includes a second shielding electrode, which is connected to the fourth plate, and the orthographic projection of the second shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate.

8. The display substrate as described in claim 7, characterized in that, The fourth electrode plate and the second shielding electrode are an integral structure.

9. The display substrate as described in claim 7, characterized in that, The second shielding electrode includes a second extension segment and a second shielding segment. The second extension segment is a strip shape extending along a second direction. The first end of the second extension segment is connected to the fourth electrode plate, and the second end of the second extension segment is connected to the first end of the second shielding segment. The second shielding segment is a strip shape extending along a first direction. The first end of the second shielding segment is connected to the second end of the second extension segment, and the second end of the second shielding segment extends in the opposite direction to the first direction. The orthographic projection of the second shielding segment on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate. The first direction intersects the second direction.

10. The display substrate as described in claim 3, characterized in that, The at least one dual-gate transistor includes a compensation transistor, the first electrode of which is connected to the first plate of the first storage capacitor; the at least one shielding electrode includes a second shielding electrode, which is connected to the first power supply connection line, and the orthographic projection of the second shielding electrode on the substrate at least partially overlaps the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate.

11. The display substrate as claimed in claim 10, characterized in that, The first power connection line and the second shielding electrode are integrated into one structure.

12. The display substrate as claimed in claim 3, characterized in that, At least one circuit unit further includes a shielded connection line connected to the first power connection line; the at least one dual-gate transistor includes a compensation transistor, the first electrode of the compensation transistor being connected to the first plate of the first storage capacitor; the at least one shielding electrode includes a second shielding electrode connected to the shielded connection line, and the orthographic projection of the second shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate.

13. The display substrate as described in any one of claims 1 to 12, characterized in that, The at least one dual-gate transistor includes a data writing transistor, the first terminal of which is connected to a data signal line, and the second terminal of which is connected to the second plate of a second storage capacitor. The at least one shielding electrode includes a third shielding electrode connected to the fourth electrode plate, wherein the orthographic projection of the third shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the data writing transistor on the substrate.

14. The display substrate as claimed in claim 13, characterized in that, The fourth electrode plate and the third shielding electrode are an integral structure.

15. The display substrate as described in any one of claims 1 to 12, characterized in that, The at least one dual-gate transistor includes a reference transistor, the first terminal of which is connected to a second reference signal line, and the second terminal of which is connected to a second plate of a second storage capacitor. The at least one shielding electrode includes a fourth shielding electrode connected to the fourth electrode plate, and the orthographic projection of the fourth shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the reference transistor on the substrate.

16. The display substrate as claimed in claim 15, characterized in that, The fourth electrode plate and the fourth shielding electrode are an integral structure.

17. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 16.

18. A display substrate, characterized in that, The device includes a driving circuit layer disposed on a substrate. The driving circuit layer includes at least a plurality of circuit units. At least one circuit unit includes a pixel driving circuit. The pixel driving circuit includes a first storage capacitor, a second storage capacitor, at least one shielding electrode, and at least one dual-gate transistor. The first storage capacitor includes at least a first electrode plate and a third electrode plate. The second storage capacitor includes at least a second electrode plate and a fourth electrode plate. The orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the dual-gate transistor on the substrate. The at least one dual-gate transistor includes a first transistor to a ninth transistor. The pixel driving circuit further includes a first node, a second node, a third node, a fourth node, and a fifth node. The first node is connected to the second electrode of the first transistor, the first electrode of the second transistor, the gate electrode of the third transistor, and the first plate of the first storage capacitor, respectively. The second node is connected to the first electrode of the third transistor, the second electrode of the eighth transistor, and the second electrode of the fifth transistor, respectively. The third node is connected to the second electrode of the second transistor, the second electrode of the third transistor, and the first electrode of the sixth transistor, respectively. The fourth node is connected to the second electrode of the sixth transistor and the second electrode of the seventh transistor, respectively. The fifth node is connected to the second electrode of the fourth transistor, the second electrode of the ninth transistor, the third plate of the first storage capacitor, and the second plate of the second storage capacitor, respectively. The fourth plate of the second storage capacitor is connected to the first power supply line; The first transistor serves as a first initialization transistor, with its first terminal connected to a first initial signal line and its second terminal connected to a first plate of the first storage capacitor; the at least one shielding electrode includes a first shielding electrode, which is connected to the fourth plate, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate. The first shielding electrode includes a first extension segment and a first shielding segment. The first extension segment is strip-shaped extending along a second direction. The first end of the first extension segment is connected to the fourth electrode plate, and the second end of the first extension segment is connected to the first end of the first shielding segment. The first shielding segment is strip-shaped extending along a first direction. The first end of the first shielding segment is connected to the second end of the first extension segment, and the second end of the first shielding segment extends along the first direction. The orthographic projection of the first shielding segment on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate. The first direction intersects the second direction.

19. A display device, characterized in that, Includes the display substrate as described in claim 18.

Images