Field programmable gate array (FPGA)-based gear motor reduction ratio parameter testing device and method

Abstract

The invention belongs to the technical field of gear motor parameter testing, and particularly relates to an FPGA-based gear motor reduction ratio parameter testing device and method, and the device comprises a gear motor, a photoelectric limit switch module, and an FPGA module. The speed reduction ratio parameter is ingeniously converted into the rotation period ratio of the driven wheel and the driving wheel of the speed reduction motor from the rotation speed ratio of the driving wheel and the driven wheel of the speed reduction motor. On the basis of a photoelectric encoder and a precise timing technology, the FPGA-based multi-path sub-timer and a timing optimization algorithm are designed, and the FPGA-based multi-path sub-timer has the advantages of simple and easy test method, high test speed, high test precision, low cost, good repeatability, high reliability, good portability, good integration and the like.

Description

Technical Field

[0001] The present application belongs to the technical field of reduction motor testing, and specifically relates to a reduction motor reduction ratio parameter testing device and method based on FPGA. Background Art

[0002] A reduction DC motor (hereinafter referred to as a reduction motor or motor) is a device that converts a high-speed, low-torque motor into a low-speed, high-torque motor. It is widely used in precision testing instruments and industrial automation equipment. The reduction motor reduces the speed through internal gears or belts and other transmission mechanisms. For example, for a reduction motor with a reduction ratio of 30:1, when its driving wheel (or input shaft) rotates 30 times, its driven wheel (or output shaft) only rotates 1 time.

[0003] The nominal reduction ratio parameters of the reduction motor are usually expressed as integers, such as 1:5, 1:30 or 1:76. Different reduction ratios are suitable for different application scenarios. Due to the design, processing and assembly of the reduction gear, the actual reduction ratio of the reduction motor is difficult to achieve an ideal integer ratio, and generally has multiple decimal places, such as 1:5.01, 1:30.005, or 1:76.0109, etc., and due to processing accuracy or assembly errors, even for motors of the same specifications, the actual reduction ratio parameters of each motor are difficult to be completely consistent. In the field of precision measuring instruments or industrial automation based on reduction motors, accurate reduction ratio parameters are required to obtain higher displacement or angle measurement and control accuracy.

[0004] Traditional method 1 is the calculation method for gear train. It is calculated by the tooth ratio of each gear in the gear train, dividing the number of teeth on the driven wheel by the number of teeth on the driving wheel. For multi-stage gear reduction, it is necessary to divide the number of teeth on the driven wheel of all meshing pairs of gear sets by the number of teeth on the driving wheel, and multiply the results. Traditional method 2 is for reduction motors using belts, chains and friction wheels, dividing the diameter of the driven wheel by the diameter of the driving wheel. Among the above test methods, traditional method 1 can only obtain an integer ratio of the reduction ratio, and the accuracy is low. Traditional method 2 is an indirect test method, and there are many uncertain factors in the test results, and the test accuracy is difficult to guarantee. Summary of the invention

[0005] In view of the problems existing in the traditional reduction ratio parameter testing method of the reduction motor, the present invention proposes a reduction ratio parameter testing device and method of the reduction motor based on FPGA according to the physical definition of the reduction ratio parameter of the reduction motor, which cleverly converts the reduction ratio parameter from the speed ratio of the driving wheel and the driven wheel of the reduction motor to the rotation period ratio of the driving wheel and the driven wheel of the reduction motor. Based on the photoelectric encoder and precision timing technology, a multi-channel timer and timing optimization algorithm based on FPGA are designed, which has the advantages of simple and easy testing method, fast testing speed, high testing accuracy, low cost, good repeatability, high reliability, good portability and integration. The technical solution is as follows:

[0006] A reduction ratio parameter testing device for a reduction motor based on FPGA, comprising a reduction motor, a photoelectric limit switch module, and an FPGA module; wherein:

[0007] The reduction motor has a built-in photoelectric encoder to detect the rotation angle of the reduction motor driving wheel. Its output signals ChA, ChB and Index are channel A, channel B and index pulse signals respectively. The phase relationship between the rising edges of the signals ChA and ChB reflects the rotation direction of the motor.

[0008] A transmission rod is installed on the driven wheel shaft of the reduction motor. When the transmission rod rotates synchronously with the driven wheel, one end of the transmission rod can pass through the groove of the photoelectric limit switch module without obstacles. The output signal level of the photoelectric limit switch module will jump and be output to the FPGA for subsequent processing after passing through the shaping circuit. This is used as the absolute reference point when the driven wheel of the reduction motor rotates to a certain angle, or as a mark of one rotation of the driven wheel of the reduction motor.

[0009] The FPGA module is used to control the motor drive module, receive and post-process the output signals of the photoelectric limit switch module and the motor encoder, communicate with the host computer system, and execute the instructions of the host computer system.

[0010] Preferably, the photoelectric limit switch module includes a photoelectric limit switch and a signal shaping circuit. The photoelectric limit switch is a device with a U-shaped structure. The shaping circuit is used to shape the signal output by the photoelectric limit switch so that the signal level meets the TTL level requirements and the signal level jump edge is very steep; a transmission rod is installed on the driven wheel shaft of the reduction motor, and when the driven wheel rotates, the transmission rod is driven to rotate synchronously; the installation height and angle of the photoelectric limit switch module are appropriately adjusted so that one end of the transmission rod can pass through the U-shaped groove of the photoelectric limit switch in parallel without obstacles, and the bottom end of the transmission rod is about 0.5mm to 1mm away from the bottom of the U-shaped groove of the photoelectric limit switch.

[0011] Preferably, the FPGA module includes a digital phase-locked loop PLL and a clock management module, a motor rotation direction determination module and a motor drive control module;

[0012] The digital phase-locked loop PLL and clock management module generate four internal clock signals clk0, clk90, clk180 and clk270 with phases shifted by 90° in sequence, which are used as timing clocks for the four internal sub-timers Ta, Tb, Tc and Td of the timer respectively;

[0013] The motor rotation direction judgment module detects the ChA and ChB signals output from the reduction motor encoder and judges the actual rotation direction of the motor according to the phase relationship between ChA and ChB. When the judged direction is inconsistent with the direction set by the host computer, the LED indicator control module will light up the red indicator LED1;

[0014] The motor drive module can control the speed of the deceleration DC motor through the duty cycle of the PWM (pulse width modulation) signal, and control the rotation direction of the deceleration motor through the level of the Dir signal;

[0015] Preferably, the FPGA module also includes a timing enable module, a counter H1, a timer T1, a counter H2, a timer T2, a motor start / stop and direction control module, a PWM signal generation module, a host computer communication interface module and an LED indicator light control module;

[0016] The timing enable module provides a timing enable signal for each timer. When the reduction motor starts to rotate, it is not at a uniform speed. Only when the reduction motor is rotating at a uniform speed, the timing enable module generates a timing enable signal t_enable, and uses it as the timing enable signal of timer T1 and timer T2.

[0017] Counter H1 is used to count the number of rotations of the driven wheel of the motor detected; when the t_enable signal is valid, it counts each time the rising edge of the Sensor signal is detected; when the count value reaches the set number of rotations, counter H1 stops counting and generates a Ct_end signal to indicate that the counting of counter H1 has ended and stop the timing of timer H1, and also prepares for the counter H2 and timer T2 to stop working;

[0018] Timer T1 is used to measure the time it takes for the detected motor driven wheel to rotate a certain number of times; it starts measuring when the t_enable signal is valid and the rising edge of the Sensor signal is detected for the first time; when the Ct_end signal is valid, timer T1 stops measuring;

[0019] Counter H2 is used to count the number of index pulses detected by the encoder output; when the t_enable signal is valid and the rising edge of the Sensor signal is detected for the first time, the index pulse signal Index is detected, and the rising edge of the Index signal detected each time is counted; when the Ct_end signal is valid and the rising edge of Index is detected again, the counter H2 stops counting;

[0020] Timer T2 is used to count the time it takes to detect a certain number of index pulses. When the t_enable signal is valid and after the first rising edge of the Sensor signal is detected, the timer starts counting when the first rising edge of the Index signal is detected. When the Ct_end signal is valid and the rising edge of the Index is detected again, timer T2 stops counting.

[0021] The host computer interface module is used to implement the interface protocol for communicating with the host computer, receive and execute commands from the host computer; the host computer system can issue a start test command or read relevant test data in the FPGA through this interface.

[0022] Preferably, the LED indicator light control module includes LED1 and LED2; if the LED1 driving signal becomes a low level, the LED1 light emitting diode flashes red, indicating that the wiring sequence may be wrong; when the timer T2 stops timing, the LED indicator light control module will be used to make the LED2 driving signal become a low level, so that the LED2 light emitting diode flashes green, indicating that the test process is over.

[0023] A reduction ratio parameter testing method for a reduction motor based on FPGA, and a reduction ratio parameter testing working process of a reduction motor:

[0024] Step 101: Set the working parameters, the FPGA module outputs a PWM signal, and starts the motor to rotate counterclockwise at a constant speed;

[0025] Step 102: When the driving motor rotates at a constant speed, the FPGA module receives the ChA and ChB signals in real time, and determines in real time whether the motor rotation direction is consistent with the set direction according to the phase relationship between the rising edges of the ChA and ChB signals. If they are inconsistent, it means that the ChA and ChB lead wires or the Motor1 and Motor2 lead wires may be misaligned. The FPGA module will output an error indication signal through the LED indicator control module, and the driving indicator LED1 will flash red.

[0026] Step 103: When the motor rotates at a constant speed, the timing enable module generates a timing enable signal t_enable, and the FPGA module starts to detect the sensor signal output by the photoelectric limit switch module in real time. Once the sensor signal level is detected to jump from high to low for the first time, relevant counting and timing preparations are made;

[0027] Step 104: When the Sensor signal level is detected to change from low to high for the first time, the timer T1 is immediately started to time the Sensor signal, and the timer T1 is digitally labeled as Flag-1 through the timing management and timing sequence determination module; at the same time, the counter H1 is synchronously started to count the number of times the Sensor signal level changes from low to high, which is recorded as Ct_Sensor;

[0028] Step 105: While the timer T1 is timing, the index pulse signal Index output by the encoder is detected in real time. When the rising edge of the index pulse signal Index is detected for the first time, the timer T2 is immediately started to time the Index signal, and the timer T2 is digitally labeled by the timing management and timing sequence determination module, recorded as Flag-2; at the same time, the counter H2 is synchronously started to count the number of detected rising edges of the Index pulse, recorded as Ct_Index;

[0029] Step 106: Continue to rotate the motor at a constant speed until the Sensor signal level is detected again to change from high to low and from low to high, indicating that the driven wheel of the reduction motor has completed one circle of rotation and started the next circle of rotation;

[0030] Step 107: Continue to rotate the motor at a constant speed, and the timer and counter continue to work. Once the FPGA module detects that the count value Ct_Sensor of the counter H1 is equal to the set threshold Motor_cycles (i.e., the number of motor rotations), the counting of the counter H1 and the timing of the timer T1 are immediately stopped; at the same time, when the rising edge of the Index signal is subsequently detected, the counting of the counter H2 and the timing of the timer T2 are immediately stopped;

[0031] Step 108: The FPGA module controls the motor to stop rotating. At the same time, the LED indicator light control module controls the working status indicator light LED2 to flash green to indicate that the current test phase is over.

[0032] Step 109: The FPGA module starts the timing optimization algorithm, and optimizes the timing data of T1 and T2 respectively according to the timing data and digital label information of each of the four sub-timers in timer T1 and T2, and finally assigns the optimization results to t Sensor and t Index, and saved in the relevant registers in the FPGA;

[0033] Step 110: The host computer system reads and saves the count value Ct_Sensor of the counter H1, the count value Ct_Index of the counter H2, and the optimized timing values ​​t of the timers T1 and T2 in the FPGA module. Sensor and t Index According to the reduction motor parameter ratio calculation method, the reduction ratio parameter of the reduction motor in the current rotation direction is obtained, which is recorded as DR CW At this time, the host computer system can also read the original count values ​​of the four timers in the timers T1 and T2 in the FPGA and the digital label information Flag-1 and Flag-2 of T1 and T2 as needed, and execute the timing optimization algorithm to compare with the timing optimization algorithm in the FPGA to verify the consistency of the optimization results;

[0034] Step 111: The host computer system sets the motor rotation direction to clockwise through the FPGA module, keeps other working parameters of the motor unchanged, and then restarts the motor to rotate at a constant speed;

[0035] Step 112: Repeat steps 103 to 109 to obtain the reduction ratio parameter of the reduction motor after changing the rotation direction, recorded as DR CCW ;

[0036] Step 113: The upper computer system calculates an average value according to the reduction ratio parameters of the reduction motor in different rotation directions as the final reduction ratio parameter of the reduction motor.

[0037] Preferably, the timing order of each of the four sub-timers in the timers T1 and T2 depends on the rising edge of the timing clock after the timer is enabled, and the sub-timer where the timing clock with the first rising edge is located is timed first, and the FPGA module marks the timer with a digital label according to the sub-timer that is timed first;

[0038] The digital label is represented by 4-bit binary. If sub-timer Ta counts first, the digital label of the timer is assigned a value of "1000"; if sub-timer Tb counts first, the digital label of the timer is assigned a value of "1001"; if sub-timer Tc counts first, the digital label of the timer is assigned a value of "1010"; if sub-timer Td counts first, the digital label of the timer is assigned a value of "1011"; the host computer or FPGA module can determine the first sub-timer in the timer by reading the digital label of the timer, and use this as the basis for the timing optimization algorithm.

[0039] Preferably, timer T1 and timer T2 are represented by timer Ti, four sub-timers in timers T1 and T2 are represented by Tai, Tbi, Tci and Tdi respectively, digital labels Flag-1 and Flag-2 are represented by Flag-i, and the optimization steps are as follows:

[0040] Step 201: read the digital tag information Flag-i in the timer Ti and the timing values ​​Tai, Tbi, Tci and Tdi of the four-way timers, and assign them to Ta, Tb, Tc and Td respectively, and go to step 202;

[0041] Step 202: Determine whether Flag is equal to the binary number 1000, if yes, go to step 203, otherwise go to step 204;

[0042] Step 203: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timers to the replacement variables Tta, Ttb, Ttc and Ttd respectively, and go to step 211;

[0043] Step 204: Determine whether Flag is equal to the binary number 1001, if yes, go to step 205, otherwise go to step 206;

[0044] Step 205: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timers to the replacement variables Ttd, Tta, Ttb and Ttc respectively, and go to step 211;

[0045] Step 206: Determine whether Flag is equal to the binary number 1010, if yes, go to step 207, otherwise go to step 208;

[0046] Step 207: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timer to the replacement variables Ttc, Ttd, Tta and Ttb respectively, and go to step 211;

[0047] Step 208: Determine whether Flag is equal to the binary number 1011, if yes, go to step 209, otherwise go to step 210;

[0048] Step 209: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timer to the replacement variables Ttb, Ttc, Ttd and Tta respectively, and go to step 211;

[0049] Step 210: Assign TT to 0, and end;

[0050] Step 211: Determine whether Tta is greater than Ttb, if yes, go to step 212, otherwise go to step 213;

[0051] Step 212: Calculate 4×Tta-3, and assign the corrected calculation result to TT, and the optimization calculation ends;

[0052] Step 213: Determine whether Ttb is greater than Ttc, if yes, go to step 214, otherwise go to step 215;

[0053] Step 214: Calculate 4×Tta-2, and assign the corrected calculation result to TT, and the optimization calculation ends;

[0054] Step 215: Determine whether Ttc is greater than Ttd, if yes, go to step 216, otherwise go to step 217;

[0055] Step 216: Calculate 4×Tta-1, and assign the corrected calculation result to TT, and the optimization calculation ends;

[0056] Step 217: Assign the value of Tta to TT, and the optimization calculation is completed.

[0057] In the present invention, a timing optimization algorithm based on FPGA is designed. When the counter and timer finish working, the timing data in timers T1 and T2 are optimized and calculated simultaneously. After the optimization is completed, the optimization result of T1 timer is assigned to t Sensor , assign the optimization result of T2 timer to t Index .

[0058] Preferably, the reduction ratio of the reduction motor is equivalent to the average rotation period ratio of the driven wheel and the driving wheel of the reduction motor, and the calculation method is:

[0059] Assume that the clock period of the timer is T clk According to the count values ​​of counters H1 and H2 and the optimized timing value t of timer T1 during the counterclockwise rotation of the motor, Sensor And the optimized timing value t of timer T2 Index , through formula 1 to formula 4, the reduction ratio parameters of the reduction motor when rotating counterclockwise can be obtained;

[0060] Calculate the average rotation period of the driven wheel of the reduction motor Marked as formula 1:

[0061]

[0062] Where, t Sensor is the final timing data of timer T1 after optimization, and Ct_Sensor is the count value of counter H1;

[0063] Calculate the average index pulse period output by the gear motor encoder Marked as formula 2:

[0064]

[0065] Where, t Index is the final timing data of timer T2 after optimization, and Ct_Index is the count value of counter H2;

[0066] Calculate the average rotation period of the driving wheel of the reduction motor Marked as formula three:

[0067]

[0068] Where N is the resolution of the gear motor encoder, is the average index pulse period of the gear motor encoder calculated by formula 2;

[0069] Calculate the reduction ratio parameter DR of the reduction motor, marked as formula 4:

[0070]

[0071] Using formula 1 to formula 4, the reduction ratio parameter DR of the reduction motor when rotating clockwise is obtained. cw ;

[0072] Similarly, the reduction ratio parameter DR of the reduction motor when it rotates counterclockwise is obtained ccw ;

[0073] The final reduction ratio parameter of the reduction motor can be represented by the average value of the reduction ratio parameter of the reduction motor when it rotates counterclockwise and clockwise, that is:

[0074] DR=(DR cw +DR ccw ) / 2.

[0075] Compared with the prior art, the present invention has the following beneficial effects:

[0076] 1) FPGA-based reduction motor reduction ratio parameter test device

[0077] The device includes a reduction DC motor and cable accessories, a transmission rod and transmission rod fasteners, a motor support bracket, a test bench, a photoelectric limit switch module and cables, an FPGA module and other main related modules. The reduction motor is installed on the test bench through the motor support bracket, the transmission rod is fixed on the shaft of the driven wheel of the reduction motor through fasteners, and the photoelectric limit switch module is installed on the test bench. By adjusting the horizontal position of the photoelectric limit switch module, the U-shaped groove of the photoelectric limit switch is directly below the shaft of the driven wheel of the reduction motor. The switch transmission rod rotates in the vertical direction. By adjusting the installation height and horizontal angle of the photoelectric limit switch module, the transmission rod can smoothly pass through the U-shaped groove of the photoelectric limit switch when it rotates to the vertical position, and the bottom end of the transmission rod is about 0.5mm to 1mm away from the bottom of the U-shaped groove of the photoelectric limit switch.

[0078] By using large-scale programmable FPGA devices, we can realize the detection of the output signal of the reduction motor encoder and the photoelectric limit switch signal, the precise timing and dynamic timing management based on the four-way timer, the generation of motor drive signals (such as PWM signals) and motor drive control (such as motor start and stop control or rotation direction control, etc.) and the host computer communication interface (such as RS232C, etc.) and other functional modules.

[0079] The device and method have good versatility, practicality and ease of use.

[0080] 2) Gear motor reduction ratio parameter test working process

[0081] Under the control of the host computer, the large-scale programmable device FPGA generates the drive and control signals of the reduction motor, starts the motor to rotate, and synchronously detects the relevant signals output by the encoder and the photoelectric limit switch in the motor. The average rotation period of the reduction motor driving wheel is measured by technical and precise timing of the encoder index pulse that can reflect the rotation period of the reduction motor driving wheel. The average rotation period of the reduction motor driven wheel is measured by technical and precise timing of the number of jump edges of the photoelectric limit switch signal that can reflect the rotation period of the reduction motor driven wheel. The timing data can achieve very high accuracy through the optimization algorithm and correction of the timer timing data. Finally, the actual reduction ratio parameters of the reduction motor are obtained through the host computer software.

[0082] 3) Multi-channel timer timing method to improve timer timing accuracy

[0083] As an example, the present invention lists a method of using the clock management resources and phase-locked loop (PLL) in the FPGA to generate four clock signals with phases offset by 90° in sequence as the timing clock of the four-way sub-timer (actually, it is a four-way sub-counter for the timing clock cycle, and the count value multiplied by a single clock cycle is the timing time). The technical protection points of the present invention include but are not limited to this. By using the clock managers (DCMs or CMTs) and phase-locked loops (PLLs) in large-scale programmable FPGA devices of different models or specifications, more multi-channel clock signals with smaller phase offsets (such as offsets of 45° or less) can be generated, thereby achieving higher timing accuracy. All methods that use multiple clocks with fixed phase offsets in sequence for timing and counting and for motor reduction ratio parameter testing belong to the protection scope of the present invention. In fact, although increasing the input clock frequency of the FPGA can also improve the timing accuracy, to achieve the same timing accuracy, the input clock frequency of the FPGA needs to be increased by four times, so the performance requirements for the FPGA will be greatly increased, thereby increasing the selection cost of the FPGA.

[0084] 4) Timing optimization algorithm flow for improving timing accuracy

[0085] As an example, the present invention lists a timing optimization algorithm for four-way sub-timers. The technical protection points of the present invention include but are not limited to this. When more sub-timers are designed, the design idea of ​​the timing optimization algorithm process is the same. It only needs to expand the digital label value judgment interval, increase the corresponding number of intermediate substitution variables, expand the substitution variable judgment range, and make corresponding corrections to the real-time data according to the number of sub-timers. It should be noted that the timing optimization algorithm can be implemented in the host computer or in the FPGA. No matter which implementation method is used, it belongs to the protection scope of the present invention.

[0086] 5) Calculation method of reduction motor reduction ratio parameters

[0087] In the timing optimization algorithm, a division operation is required. In the present invention, as an example, a timing circuit design and a timing optimization algorithm of a four-way timer are listed, and Tta-1 / 4, Ttb-2 / 4, and Ttc-3 / 4 division operations are required (equivalent to Figure 6If an eight-way timer is designed, the number of substitution variables needs to be expanded, that is, Tta, Ttb, Ttc, Ttd of the four-way timer is expanded to Tta, Ttb, ..., Ttg, Tth, then in the timing optimization algorithm, Tta-1 / 8, Ttb-2 / 8, ..., Ttf-6 / 8, Ttg-7 / 8 division operations need to be performed. Although some FPGA chips support division operations (such as IP cores that support division operations or built-in DSPs), most of them are large-scale and high-priced high-performance FPGA chips, and the cost is high. Of course, you can also design a division operation circuit by yourself, but for FPGA circuits, you can only get the integer and modulus of the division operation result, and you cannot get the decimal part.

[0088] In the present invention, the test method of the reduction ratio parameter is converted from the speed ratio of the driving wheel and the driven wheel of the reduction motor to the rotation period ratio of the driven wheel and the driving wheel of the reduction motor. According to the above formulas (I), (II) and (IV), when the host computer performs division calculation, the clock cycle and the denominator in the above division formula (i.e., "4" when there are four sub-timers) will be offset in the division operation. Therefore, the above formula is simply converted. Taking the "Ttc-3 / 4" operation as an example, it is only necessary to convert the formula into the form of (4*Ttc-3) / 4. In the FPGA circuit design, it is only necessary to design the "4*Ttc-3" circuit, and the operation of dividing by 4 can be performed by the host computer or implemented by the shift operation in the FPGA circuit. The calculation accuracy of the final result of the two is different. The former has high accuracy and the latter has relatively low accuracy, which can be selected according to design needs. For sub-timers with more channels, the processing method is the same. Through the above simple conversion, the design difficulty of the FPGA circuit is simplified, and the selection requirements for the FPGA chip are also reduced, thereby reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] Figure 1 It is a schematic diagram of the encoding disk in the encoder;

[0090] Figure 2 This is a block diagram of the working principle of the device of the present invention;

[0091] Figure 3 This is a schematic diagram of the installation of the reduction motor, transmission rod and other structures of the device;

[0092] Figure 4 This is the functional block diagram of the FPGA circuit in this device;

[0093] Figure 5 This is the functional block diagram of the timer module circuit in the FPGA.

[0094] Figure 6 Flowchart of the algorithm for optimizing timer timing.

[0095] Figure 3 Among them, 1-reduction DC motor, 2-motor support frame, 3-transmission rod fastener, 4-driven wheel shaft, 5-transmission rod, 6-photoelectric limit switch module, 7-photoelectric limit switch, 8-test bench, 9-reduction motor electrical connection cable. DETAILED DESCRIPTION

[0096] The technical solution of the present application is described in detail below through specific embodiments and drawings. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application, and the specific technical features may be combined with each other.

[0097] like Figure 2 As shown, a principle block diagram of a reduction motor reduction ratio parameter testing device based on FPGA is composed of a reduction motor (a reduction DC motor is used in the embodiment) and auxiliary components (such as a transmission rod and electrical connection cables, etc.), a photoelectric limit switch module, an FPGA module, a host computer system, a motor drive module, a 100MHz high-stability crystal oscillator and an LED indicator light, etc.

[0098] Figure 1 As shown, the deceleration DC motor has a built-in photoelectric encoder to detect the rotation angle of the driving wheel of the deceleration DC motor. Assuming that the resolution of the encoder is N, its output signals ChA, ChB and Index are channel A, channel B and index pulse signals respectively. The phase relationship between the rising edges of ChA and ChB can reflect the rotation direction of the motor. When the motor rotates clockwise, ChA leads ChB by 90°. Conversely, when the motor rotates counterclockwise, ChA lags ChB by 90°. The index pulse signal Index is used to indicate the start or end of one rotation of the motor. A long strip transmission rod is installed on the driven wheel shaft of the deceleration motor. When the driven wheel rotates, it will drive the transmission rod to rotate synchronously.

[0099] The photoelectric limit switch module consists of a photoelectric limit switch and a signal shaping circuit, which is used to sense the absolute reference point when the driven wheel of the motor rotates to a certain angle. The photoelectric limit switch is a U-shaped structure, and the function of the shaping circuit is to make the transition edge of the signal level as steep as possible while meeting the TTL level requirements. Figure 3 As shown in the figure, the installation height, horizontal position and horizontal angle of the photoelectric limit switch module are properly adjusted so that when the transmission rod rotates to the vertical direction with the motor, the bottom end of the transmission rod can just pass through the U-shaped groove of the photoelectric limit switch smoothly, and the bottom end of the transmission rod is about 0.5mm to 1mm away from the bottom of the U-shaped groove of the photoelectric limit switch. When the transmission rod rotates into or out of the U-shaped groove of the photoelectric limit switch, the signal level output by the photoelectric limit switch will jump, and after the shaping circuit, a sensor signal that meets the TTL level will be formed and output to the FPGA for subsequent processing.

[0100] The motor drive module is composed of a drive chip that matches the reduction DC motor. It has four working modes: counterclockwise, clockwise, braking and stopping. The speed of the reduction motor can be controlled by adjusting the duty cycle of the PWM (pulse modulation) signal, and the rotation direction of the reduction motor can be controlled by the level of the Dir signal.

[0101] The 100MHz high-stability crystal oscillator is mainly used to provide a 100MHz high-stability working clock for the FPGA.

[0102] The LED status indicator module contains two light-emitting diode indicators, which are mainly used to dynamically indicate the working process of the device. During normal operation, the two indicators are not illuminated. When there is a connection error between Motor1 and Motor2 or ChA and ChB, the LED1 indicator will flash red. When the test is completed, the LED2 indicator will light green.

[0103] The FPGA module is mainly used to generate motor drive and control signals, receive and post-process the output signals of the photoelectric limit switch module and the motor encoder, communicate with the host computer system, and execute the instructions of the host computer system.

[0104] like Figure 4 The figure shows the functional block diagram of the reduction ratio parameter test based on the large-scale programmable device FPGA circuit in this device. It is mainly composed of a digital phase-locked loop PLL clock management module, a timing enable module, a counter H1, a timer T1, a counter H2, a timer T2, a motor drive and control module, a host computer communication interface module and an LED indicator light control module. Among them:

[0105] The digital phase-locked loop (PLL) clock management module mainly uses the resources inside the FPGA to generate four internal clock signals clk0, clk90, clk180 and clk270 with phases offset by 90° respectively, which are used as the timing clocks of the four sub-timers inside the timer.

[0106] The timing enable module mainly provides timing enable signals for each timer. When the reduction motor starts to rotate, it is not at a uniform speed. Only when the reduction motor is rotating at a uniform speed, the timing enable module generates a timing enable signal t_enable, which is used as the timing enable signal for timer T1 and timer T2. Only when the t_enable signal is valid, the timer and counter can start working;

[0107] Counter H1 is used to count the number of rotations of the detected motor driven wheel. When the t_enable signal is valid, it counts each time the rising edge of the Sensor signal is detected. When the count value reaches the set number of revolutions, counter H1 stops counting and generates a Ct_end signal to indicate that counter H1 has finished counting and timer T1 stops timing, and also prepares for counter H2 and timer T2 to stop working.

[0108] Timer T1 is used to measure the time it takes for the driven wheel of the motor to rotate a certain number of times. When the t_enable signal is valid and the rising edge of the Sensor signal is detected for the first time, the timer T1 stops measuring.

[0109] Counter H2 is used to count the detected index pulses. When the t_enable signal is valid and the rising edge of the Sensor signal is detected for the first time, the pulse index signal Index is detected, and the rising edge of the Index signal detected each time is counted. When the Ct_end signal is valid and the rising edge of Index is detected again, counter H2 stops counting.

[0110] Timer T2 is used to count the time it takes to detect a certain number of index pulses. When the t_enable signal is valid and after the first rising edge of the Sensor signal is detected, the timer starts counting when the first rising edge of the Index signal is detected. When the Ct_end signal is valid and the rising edge of Index is detected again, timer T2 stops counting.

[0111] The host computer interface module is mainly used to implement the interface protocol for communication with the host computer, and receive and execute the commands of the host computer. The host computer system can issue a start test command or read relevant test data in the FPGA through this interface, such as the data in the timer and counter.

[0112] The motor rotation direction judgment module mainly detects the ChA and ChB signals output from the reduction motor encoder, and judges the actual rotation direction of the motor according to the phase relationship between ChA and ChB. When the judged direction is inconsistent with the direction set by the host computer, the LED indicator control module will be used to make the LED1 drive signal become low level, so that the LED1 light-emitting diode will flash red, indicating that the wiring sequence may be wrong. When the timer T2 stops timing, the LED2 drive signal will be changed to a low level through the LED indicator control module, so that the LED2 light-emitting diode will flash green, indicating that the test process is over.

[0113] The motor drive and control module is mainly used to generate and output PWM (pulse modulation) signals. By adjusting its duty cycle, the rotation speed of the reduction motor can be adjusted. When the host computer system obtains the generator working parameters (PWM frequency, duty cycle and rotation direction, etc.) through the host computer interface module in the FPGA and issues a start test command, the motor drive and control module will generate and output the corresponding PWM signal according to the set working parameter requirements. When timer T2 stops timing, the output of the PWM signal will stop immediately.

[0114] Methods to improve the timing accuracy of the timer:

[0115] In order to improve the timing accuracy of the timer, four sub-timers are designed for the timer T1 and timer T2 inside the FPGA (actually counting the number of cycles of the timing clock). The timing values ​​of the four sub-timers of timer T1 are Ta1, Tb1, Tc1 and Td1 respectively. The timing values ​​of the four sub-timers of timer T2 are Ta2, Tb2, Tc2 and Td2 respectively. Its timing clock is provided by four clock signals with phases shifted by 90° in sequence, which are specifically generated by the digital phase-locked loop PLL clock management module inside the FPGA module, such as clk0, clk90, clk180 and clk270 in the figure below. Its frequency is the same as the frequency of the external input clock of the FPGA module. In this device, the external input clock frequency of the FPGA module is 100MHz (cycle is 10ns), the register bit number of each sub-timer inside the timer is 32bit, and the maximum timing time exceeds 42s (if the register bit number exceeds 32bit, a longer timing time can be achieved). By designing a timing optimization algorithm, the timing accuracy of the timer is better than 2.5ns.

[0116] Gear motor reduction ratio parameter test working process:

[0117] Step 101: Under the control of the host computer system, the FPGA module starts the relevant preparations of the motor drive module: according to the parameters provided by the motor manufacturer, set the frequency, duty cycle and rotation direction of the motor's PWM drive signal so that the motor can rotate at a uniform speed. As an example, assume that the operating frequency of the PWM drive signal is 100kHz, the duty cycle is 50%, and the rotation direction is counterclockwise. Set the number of revolutions of the sampled motor driven wheel (Note: the larger the number of revolutions, the higher the accuracy of the test reduction ratio parameters, but the longer the test time. When the number of revolutions reaches a certain level, the improvement in test accuracy will no longer be obvious. In actual testing, it can be flexibly set according to the nominal reduction ratio parameters of the reduction motor, which should generally not be less than 1.5 to 2 times the nominal reduction ratio parameters), recorded as Motor_cycles. After the working parameters are set, the FPGA module outputs a PWM signal to start the motor to rotate counterclockwise at a uniform speed;

[0118] Step 102: When the drive motor rotates at a constant speed, the FPGA module receives the ChA and ChB signals in real time, and synchronously determines whether the motor rotation direction is consistent with the set direction based on the phase relationship between the ChA and ChB signals. If they are inconsistent, it means that the pin sequence of ChA and ChB connected to the FPGA is opposite, and the FPGA module outputs an error indication signal, and the driving indicator LED1 flashes red. At this time, the power supply of the device should be turned off, and the above test steps should be repeated after checking and confirming the correct wiring sequence. The FPGA will only turn off the LED1 indicator and start the subsequent test process when it detects that the actual rotation direction of the motor is consistent with the set direction;

[0119] Step 103: When the motor rotates at a constant speed, the timing enable module generates a timing enable signal t_enable, and the FPGA module starts to detect the Sensor signal output by the photoelectric limit switch module in real time. Once the Sensor signal level is detected to jump from high to low for the first time, relevant counting and timing preparations are made (mainly to clear the various counters and timers used later in the FPGA).

[0120] Step 104: When the Sensor signal level is detected to change from low to high for the first time (indicating that the transmission rod installed on the driven wheel shaft has been rotated out of the groove of the photoelectric limit switch), the timer T1 is immediately started to time the Sensor signal, and the timer T1 is digitally labeled as Flag-1 through the timing management and timing sequence determination module. At the same time, the counter H1 is synchronously started to count the number of times the Sensor signal level changes from low to high, which is recorded as Ct_Sensor;

[0121] Step 105: When timer T1 starts timing, the index pulse signal Index output by the encoder is detected in real time. When the rising edge of the index pulse signal Index is detected for the first time, timer T2 is immediately started for timing, and the timer T2 is digitally labeled as Flag-2 through the timing management and timing sequence determination module. At the same time, the counter H2 is synchronously started to count the number of detected rising edges of the Index pulse, which is recorded as Ct_Index;

[0122] Step 106: Continue to rotate the motor at a constant speed until the Sensor signal level is detected to change from high to low and from low to high again, indicating that the driven wheel of the reduction motor has completed one circle of rotation and started the next circle of rotation. During the rotation of the motor, the number of times the Sensor signal level changes from low to high and the number of all Index signal pulses should be accumulated and counted, and at the same time, timer T1 and timer T2 continue to count;

[0123] Step 107: Continue to rotate the motor at a constant speed, and the timer and counter continue to work. Once the FPGA module detects that the count value Ct_Sensor of the counter H1 is equal to the set threshold Motor_cycles, the counting of the counter H1 and the timing of the timer T1 are immediately stopped. At the same time, when the rising edge of the Index signal is subsequently detected, the counting of the counter H2 and the timing of the timer T2 are immediately stopped.

[0124] Step 108: The FPGA module stops the PWM signal output through the motor drive control module, thereby controlling the motor to stop rotating. At the same time, the working status indicator LED2 is controlled to flash green to indicate that the current test phase is over;

[0125] Step 109: FPGA automatically starts the timing optimization algorithm, and optimizes the timing data of T1 and T2 respectively according to the timing data and digital label information of each of the four sub-timers in timer T1 and T2, and finally assigns the optimization results to t Sensor and t Index , and saved in the relevant registers in the FPGA;

[0126] Step 110: The host computer system reads and saves the count value Ct_Sensor of the counter H1, the count value Ct_Index of the counter H2, and the optimized timing values ​​t of the timers T1 and T2 in the FPGA module. Sensor and t Index According to the reduction motor parameter ratio calculation method, the reduction ratio parameter of the reduction motor in the current rotation direction is obtained, which is recorded as DR CW At this time, the host computer system can also read the original count values ​​of each of the four timers in the timers T1 and T2 in the FPGA and the digital label information Flag-1 and Flag-2 of T1 and T2 as needed, and execute the timing optimization algorithm to compare with the results of the timing optimization algorithm in the FPGA to verify consistency.

[0127] Step 111: The host computer system sets the motor rotation direction to clockwise through the FPGA module, keeps other working parameters of the motor unchanged, and then restarts the motor to rotate at a constant speed;

[0128] Step 112: Repeat steps 103 to 109. Get the reduction ratio parameter of the reduction motor after changing the rotation direction, recorded as DR CCW ;

[0129] Step 113: Calculate the average value of the reduction ratio parameters of the reduction motor in different rotation directions calculated according to the above steps as the final reduction ratio parameter of the reduction motor.

[0130] Timer timing optimization algorithm:

[0131] like Figure 5 As shown, according to the phase relationship between the timing clocks used by the four sub-timers in the timer, the timing order of the four sub-timers depends on the rising edge of the timing clock after the timer is enabled, and the sub-timer where the timing clock with the first rising edge arrives is the first to time. In order to facilitate the distinction, it is necessary to design a digital label for the sub-timer that starts timing first in the four-way timer and save it in the corresponding register so that the host computer can read it as the basis for the subsequent timing optimization algorithm to improve the timing accuracy. Among them, the digital label in timer T1 is Flag-1, and the digital label in timer T2 is Flag-2.

[0132] The digital label is represented by 4-bit binary. If the sub-timer Ta counts first, the digital label is assigned a value of "1000". If the sub-timer Tb counts first, the digital label is assigned a value of "1001". If the sub-timer Tc counts first, the digital label is assigned a value of "1010". If the sub-timer Td counts first, the digital label is assigned a value of "1011". The digital label is designed as a 4-bit binary number mainly to improve anti-interference and provide reserved bits for the future expansion of the digital label assignment range.

[0133] When the timer ends, according to the digital label in the timer and the size of the timing data of the four-way timer, Figure 6 The timing optimization algorithm flow shown can determine the final accurate timing data of the T1 and T2 timers.

[0134] In the present invention, as an example, the timing optimization steps are introduced below by taking timer T1 as an example:

[0135] Step 201: read the digital tag information Flag-1 in the timer T1 and the timing values ​​Ta1, Tb1, Tc1 and Td1 of the four-way timer, and assign them to Flag, Ta, Tb, Tc and Td respectively, and go to step 202;

[0136] Step 202: Determine whether Flag is equal to the binary number 1000, if yes, go to step 203, otherwise go to step 204;

[0137] Step 203: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timers to the replacement variables Tta, Ttb, Ttc and Ttd respectively, and go to step 211;

[0138] Step 204: Determine whether Flag is equal to the binary number 1001, if yes, go to step 205, otherwise go to step 206;

[0139] Step 205: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timers to the replacement variables Ttd, Tta, Ttb and Ttc respectively, and go to step 211;

[0140] Step 206: Determine whether Flag is equal to the binary number 1010, if yes, go to step 207, otherwise go to step 208;

[0141] Step 207: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timer to the replacement variables Ttc, Ttd, Tta and Ttb respectively, and go to step 211;

[0142] Step 208: Determine whether Flag is equal to the binary number 1011, if yes, go to step 209, otherwise go to step 210;

[0143] Step 209: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timer to the replacement variables Ttb, Ttc, Ttd and Tta respectively, and go to step 211;

[0144] Step 210: Assign TT to 0, and end;

[0145] Step 211: Determine whether Tta is greater than Ttb, if yes, go to step 212, otherwise go to step 213;

[0146] Step 212: Calculate 4×Tta-3, and assign the corrected calculation result to TT, and the optimization calculation ends;

[0147] Step 213: Determine whether Ttb is greater than Ttc, if yes, go to step 214, otherwise go to step 215;

[0148] Step 214: Calculate 4×Tta-2, and assign the corrected calculation result to TT, and the optimization calculation ends;

[0149] Step 215: Determine whether Ttc is greater than Ttd, if yes, go to step 216, otherwise go to step 217;

[0150] Step 216: Calculate 4×Tta-1, and assign the corrected calculation result to TT, and the optimization calculation ends;

[0151] Step 217: Assign the value of Tta to TT, and the optimization calculation is completed.

[0152] Through the above process, the optimized timing result TT of timer T1 is obtained, and TT is assigned to t Sensor .

[0153] Similarly, by reading the corresponding data of timer T2, according to the above process, the optimized timing result TT of timer T2 is obtained, and TT is assigned to t Index .

[0154] Calculation method of reduction ratio parameters of reduction motor:

[0155] 1) Assume that the clock period of the timer is T clk According to the count values ​​of counters H1 and H2 detected during the counterclockwise rotation of the motor and the optimized timing value t of timer T1, Sensor And the optimized timing value t of timer T2 Index , through the following calculation steps, the reduction ratio parameters of the reduction motor when it rotates counterclockwise can be obtained.

[0156] Step 301: Calculate the average rotation period of the driven wheel of the reduction motor

[0157]

[0158] Step 302: Calculate the average index pulse period output by the reduction motor encoder

[0159]

[0160] Step 303: Calculate the average rotation period of the driving wheel of the reduction motor

[0161]

[0162] Where N is the resolution of the reduction motor encoder.

[0163] Step 304: Calculate the reduction ratio parameter DR of the reduction motor:

[0164]

[0165] 2) Similarly, according to the count values ​​of counters H1 and H2 detected during the clockwise rotation of the reduction motor and the optimized timing value t of timer T1, Sensor And the optimized timing value t of timer T2 Index ,according to Figure 6 The flow chart shown and the above formulas (1) to (4) can be used to obtain the reduction ratio parameter DR of the reduction motor when it rotates clockwise. ccw .

[0166] 3) The final reduction ratio parameter of the reduction motor can be represented by the average value of the reduction ratio parameter of the reduction motor when it rotates counterclockwise and clockwise, that is:

[0167] DR=(DR cw +DR ccw ) / 2 (5)

[0168] According to the physical definition of the reduction ratio parameters of the reduction motor, the present invention proposes a reduction parameter testing device and method for the reduction motor based on FPGA, which cleverly converts the reduction ratio parameters from the speed ratio of the driving wheel and the driven wheel of the reduction motor into the rotation period ratio of the driving wheel and the driven wheel of the reduction motor, and designs a four-way timer timing method and a timing optimization algorithm, which greatly improves the timing accuracy. When the input clock frequency of the FPGA is 100MHz, the timing accuracy of the timer is as high as 2.5ns.

[0169] The expression of the speed of the driving wheel of the reduction motor is:

[0170]

[0171] In the formula, RPM is the number of revolutions per minute of the motor driving wheel (i.e., speed), is the rotation period of the driving wheel of the reduction motor. Assuming the speed of the driving wheel of the reduction motor is 5000 rpm, according to formula (6), the rotation period of the driving wheel of the reduction motor is for:

[0172]

[0173] Assuming that the input clock frequency of the FPGA is 100 MHz, the accuracy of the average rotation period of the driving wheel of the reduction motor tested by the device of the present invention reaches 2.5 ns, and the relative accuracy reaches 0.21 ppm. If converted into angle, the relative accuracy of the test result is equivalent to 0.27″ (arc seconds). Therefore, the reduction ratio parameters of the reduction motor tested by the method of the present invention have very high test accuracy.

[0174] The overall idea is to convert the traditional speed ratio test method into a cycle ratio, that is, to divide the rotation period of the driven wheel of the reduction motor by the rotation period of the driving wheel, so as to obtain the reduction ratio parameters of the reduction motor. A multi-channel timer and timing optimization algorithm based on FPGA is proposed. Based on this algorithm, the average rotation period of the driving wheel and the driven wheel when the reduction motor rotates clockwise and counterclockwise is detected and obtained respectively, and then the average reduction ratio parameters of the reduction motor are calculated.

[0175] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A reduction ratio parameter testing device for a reduction motor based on FPGA, characterized in that: It includes a reduction motor, a photoelectric limit switch module, and an FPGA module; among which: The reduction motor has a built-in photoelectric encoder to detect the rotation angle of the reduction motor driving wheel. Its output signals ChA, ChB and Index are channel A, channel B and index pulse signals respectively. The phase relationship between the rising edges of the signals ChA and ChB reflects the rotation direction of the motor. A transmission rod is installed on the driven wheel shaft of the reduction motor. When the transmission rod rotates synchronously with the driven wheel, one end of the transmission rod passes through the groove of the photoelectric limit switch module. The output signal level of the photoelectric limit switch module will jump. After being processed by the FPGA module, it will serve as the absolute reference point when the driven wheel of the reduction motor rotates to a certain angle, or as a mark of one rotation of the driven wheel of the reduction motor. The FPGA module is used to control the motor drive module, receive and post-process the output signals of the photoelectric limit switch module and the motor encoder, communicate with the host computer system, and execute the instructions of the host computer system.

2. The FPGA-based reduction motor reduction ratio parameter testing device according to claim 1 is characterized in that: The photoelectric limit switch module includes a photoelectric limit switch and a signal shaping circuit. The photoelectric limit switch is a device with a U-shaped structure. The shaping circuit is used to shape the signal output by the photoelectric limit switch so that the signal level meets the TTL level requirements and the signal level jump edge is very steep; a transmission rod is installed on the driven wheel shaft of the reduction motor, and when the driven wheel rotates, the transmission rod is driven to rotate synchronously; the installation height and angle of the photoelectric limit switch module are properly adjusted so that one end of the transmission rod can pass through the U-shaped groove of the photoelectric limit switch in parallel without obstacles, and the bottom end of the transmission rod is about 0.5mm to 1mm away from the bottom of the U-shaped groove of the photoelectric limit switch.

3. The FPGA-based reduction motor reduction ratio parameter testing device according to claim 1 is characterized in that: The FPGA module includes a digital phase-locked loop (PLL) and a clock management module, a motor rotation direction determination module, and a motor drive control module; The digital phase-locked loop PLL and clock management module generate four internal clock signals clk0, clk90, clk180 and clk270 with phases shifted by 90° in sequence, which are used as timing clocks for the four internal sub-timers Ta, Tb, Tc and Td of the timer respectively; The motor rotation direction judgment module detects the ChA and ChB signals output from the reduction motor encoder and judges the actual rotation direction of the motor according to the phase relationship between ChA and ChB. When the judged direction is inconsistent with the direction set by the host computer, the LED indicator control module will light up the red indicator LED1; The motor drive module can control the speed of the deceleration DC motor through the duty cycle of the PWM signal, and control the rotation direction of the deceleration motor through the level of the Dir signal.

4. The FPGA-based reduction motor reduction ratio parameter testing device according to claim 3 is characterized in that: The FPGA module also includes a timing enable module, a counter H1, a timer T1, a counter H2, a timer T2, a motor start / stop and direction control module, a PWM signal generation module, a host computer communication interface module and an LED indicator light control module; The timing enable module provides a timing enable signal for each timer; when the reduction motor starts to rotate, it is not at a uniform speed. Only when the reduction motor is rotating at a uniform speed, the timing enable module generates a timing enable signal t_enable, and uses it as the timing enable signal of timer T1 and timer T2; Counter H1 is used to count the number of rotations of the driven wheel of the motor detected; when the t_enable signal is valid, it counts each time the rising edge of the Sensor signal is detected; when the count value reaches the set number of rotations, counter H1 stops counting and generates a Ct_end signal to indicate that the counting of counter H1 has ended and stop the timing of timer H1, and also prepares for the counter H2 and timer T2 to stop working; Timer T1 is used to measure the time it takes for the detected motor driven wheel to rotate a certain number of times; it starts measuring when the t_enable signal is valid and the rising edge of the Sensor signal is detected for the first time; when the Ct_end signal is valid, timer T1 stops measuring; Counter H2 is used to count the number of index pulses detected by the encoder output; when the t_enable signal is valid and the rising edge of the Sensor signal is detected for the first time, the index pulse signal Index is detected, and the rising edge of the Index signal detected each time is counted; when the Ct_end signal is valid and the rising edge of Index is detected again, the counter H2 stops counting; Timer T2 is used to count the time it takes to detect a certain number of index pulses. When the t_enable signal is valid and after the first rising edge of the Sensor signal is detected, the timer starts counting when the first rising edge of the Index signal is detected. When the Ct_end signal is valid and the rising edge of the Index is detected again, timer T2 stops counting. The host computer interface module is used to implement the interface protocol for communicating with the host computer, receive and execute commands from the host computer; the host computer system can issue a start test command or read relevant test data in the FPGA through this interface.

5. The FPGA-based reduction motor reduction ratio parameter testing device according to claim 3 is characterized in that: The LED indicator control module includes LED1 and LED2; if the LED1 driving signal becomes a low level, the LED1 light emitting diode will flash red, indicating that the wiring sequence may be wrong; when the timer T2 stops timing, the LED indicator control module will be used to make the LED2 driving signal become a low level, so that the LED2 light emitting diode will flash green, indicating that the test process is over.

6. A method for testing the reduction ratio parameters of a reduction motor based on FPGA, configured in the testing device according to any one of claims 1 to 5, characterized in that: Gear motor reduction ratio parameter test working process: Step 101: Set the working parameters, the FPGA module outputs a PWM signal, and starts the motor to rotate counterclockwise at a constant speed; Step 102: When the driving motor rotates at a constant speed, the FPGA module receives the ChA and ChB signals in real time, and determines in real time whether the motor rotation direction is consistent with the set direction according to the phase relationship between the rising edges of the ChA and ChB signals. If they are inconsistent, it means that the ChA and ChB lead wires or the Motor1 and Motor2 lead wires may be misaligned. The FPGA module will output an error indication signal through the LED indicator control module, and the driving indicator LED1 will flash red. Step 103: When the motor rotates at a constant speed, the timing enable module generates a timing enable signal t_enable, and the FPGA module starts to detect the sensor signal output by the photoelectric limit switch module in real time. Once the sensor signal level is detected to jump from high to low for the first time, relevant counting and timing preparations are made; Step 104: When the Sensor signal level is detected to change from low to high for the first time, the timer T1 is immediately started to time the Sensor signal, and the timer T1 is digitally labeled as Flag-1 through the timing management and timing sequence determination module; at the same time, the counter H1 is synchronously started to count the number of times the Sensor signal level changes from low to high, which is recorded as Ct_Sensor; Step 105: While the timer T1 is timing, the index pulse signal Index output by the encoder is detected in real time. When the rising edge of the index pulse signal Index is detected for the first time, the timer T2 is immediately started to time the Index signal, and the timer T2 is digitally labeled by the timing management and timing sequence determination module, recorded as Flag-2; at the same time, the counter H2 is synchronously started to count the number of detected rising edges of the Index pulse, recorded as Ct_Index; Step 106: Continue to rotate the motor at a constant speed until the Sensor signal level is detected again to change from high to low and from low to high, indicating that the driven wheel of the reduction motor has completed one circle of rotation and started the next circle of rotation; Step 107: Continue to rotate the motor at a constant speed, and the timer and counter continue to work; once the FPGA module detects that the count value Ct_Sensor of the counter H1 is equal to the set threshold Motor_cycles, the counting of the counter H1 and the timing of the timer T1 are immediately stopped; at the same time, when the rising edge of the Index signal is subsequently detected, the counting of the counter H2 and the timing of the timer T2 are immediately stopped; Step 108: The FPGA module controls the motor to stop rotating. At the same time, the LED indicator light control module controls the working status indicator light LED2 to flash green to indicate that the current test phase is over. Step 109: The FPGA module starts the timing optimization algorithm, and optimizes the timing data of T1 and T2 respectively according to the timing data and digital label information of each of the four sub-timers in timer T1 and T2, and finally assigns the optimization results to t Sensor and t Index , and saved in the relevant registers in the FPGA; Step 110: The host computer system reads and saves the count value Ct_Sensor of the counter H1, the count value Ct_Index of the counter H2, and the optimized timing values ​​t of the timers T1 and T2 in the FPGA module. Sensor and t Index According to the reduction ratio parameter calculation method of the reduction motor, the reduction ratio parameter of the reduction motor in the current rotation direction is obtained, which is recorded as DR CW At this time, the host computer system can also read the original count values ​​of the four timers in the timers T1 and T2 in the FPGA and the digital label information Flag-1 and Flag-2 of T1 and T2 as needed, and execute the timing optimization algorithm to compare with the timing optimization algorithm in the FPGA to verify the consistency of the optimization results; Step 111: The host computer system sets the motor rotation direction to clockwise through the FPGA module, keeps other working parameters of the motor unchanged, and then restarts the motor to rotate at a constant speed; Step 112: Repeat steps 103 to 109 to obtain the reduction ratio parameter of the reduction motor after changing the rotation direction, recorded as DR CCW ; Step 113: The upper computer system calculates an average value according to the reduction ratio parameters of the reduction motor in different rotation directions as the final reduction ratio parameter of the reduction motor.

7. The FPGA-based reduction motor reduction ratio parameter testing method according to claim 6 is characterized in that: The timing order of each of the four sub-timers in timer T1 and T2 depends on the rising edge of the timing clock after the timer is enabled. The sub-timer where the timing clock with the first rising edge is located is the first to time. The FPGA module marks the timer with a digital label according to the sub-timer that is timed first. The digital label is represented by 4-bit binary. If sub-timer Ta counts first, the digital label of the timer is assigned a value of "1000"; if sub-timer Tb counts first, the digital label of the timer is assigned a value of "1001"; if sub-timer Tc counts first, the digital label of the timer is assigned a value of "1010"; if sub-timer Td counts first, the digital label of the timer is assigned a value of "1011"; the host computer or FPGA module can determine the sub-timer that counts first in the timer by reading the digital label of the timer, and use this as the basis for the timing optimization algorithm.

8. The FPGA-based reduction motor reduction ratio parameter testing method according to claim 6 is characterized in that: Timer T1 and timer T2 are represented by timer Ti, the four sub-timers in T1 and T2 are represented by Tai, Tbi, Tci and Tdi respectively, and the digital labels Flag-1 and Flag-2 are represented by Flag-i. The optimization steps are as follows: Step 201: read the digital tag information Flag-i in the timer Ti and the timing values ​​Tai, Tbi, Tci and Tdi of the four-way timers, and assign them to Ta, Tb, Tc and Td respectively, and go to step 202; Step 202: Determine whether Flag is equal to the binary number 1000, if yes, go to step 203, otherwise go to step 204; Step 203: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timers to the replacement variables Tta, Ttb, Ttc and Ttd respectively, and go to step 211; Step 204: Determine whether Flag is equal to the binary number 1001, if yes, go to step 205, otherwise go to step 206; Step 205: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timer to the replacement variables Ttd, Tta, Ttb and Ttc respectively, and go to step 211; Step 206: Determine whether Flag is equal to the binary number 1010, if yes, go to step 207, otherwise go to step 208; Step 207: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timer to the replacement variables Ttc, Ttd, Tta and Ttb respectively, and go to step 211; Step 208: Determine whether Flag is equal to the binary number 1011, if yes, go to step 209, otherwise go to step 210; Step 209: assign the timing values ​​Ta, Tb, Tc and Td of the four-way timer to the replacement variables Ttb, Ttc, Ttd and Tta respectively, and go to step 211; Step 210: Assign TT to 0, and end; Step 211: Determine whether Tta is greater than Ttb, if yes, go to step 212, otherwise go to step 213; Step 212: Calculate 4×Tta-3, and assign the corrected calculation result to TT, and the optimization calculation ends; Step 213: Determine whether Ttb is greater than Ttc, if yes, go to step 214, otherwise go to step 215; Step 214: Calculate 4×Tta-2, and assign the corrected calculation result to TT, and the optimization calculation ends; Step 215: Determine whether Ttc is greater than Ttd, if yes, go to step 216, otherwise go to step 217; Step 216: Calculate 4×Tta-1, and assign the corrected calculation result to TT, and the optimization calculation ends; Step 217: Assign the value of Tta to TT, and the optimization calculation is completed.

9. The FPGA-based reduction motor reduction ratio parameter testing method according to claim 5 is characterized in that: The reduction ratio of the reduction motor is equivalent to the average rotation period ratio of the driven wheel and the driving wheel of the reduction motor, and the calculation method is: Assume that the clock period of the timer is T clk According to the count values ​​of counters H1 and H2 and the optimized timing value t of timer T1 during the counterclockwise rotation of the motor, Sensor And the optimized timing value t of timer T2 Index , through formula 1 to formula 4, the reduction ratio parameters of the reduction motor when rotating counterclockwise can be obtained; Calculate the average rotation period of the driven wheel of the reduction motor Marked as formula 1: In the formula, t Sensor is the final timing data of timer T1 after optimization, and Ct_Sensor is the count value of counter H1; Calculate the average index pulse period output by the gear motor encoder Marked as formula 2: Where, t Index is the final timing data of timer T2 after optimization, and Ct_Index is the count value of counter H2; Calculate the average rotation period of the driving wheel of the reduction motor Marked as formula three: Where N is the resolution of the gear motor encoder, is the average index pulse period of the gear motor encoder calculated by formula 2; Calculate the reduction ratio parameter DR of the reduction motor, marked as formula 4: Using formula 1 to formula 4, the reduction ratio parameter DR of the reduction motor when rotating clockwise is obtained. cw ; Similarly, the reduction ratio parameter DR of the reduction motor when it rotates counterclockwise is obtained ccw ; The final reduction ratio parameter of the reduction motor can be represented by the average value of the reduction ratio parameter of the reduction motor when it rotates counterclockwise and clockwise, that is: DR=(DR cw +DR ccw ) / 2.

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