Overlay mark placement method

Abstract

The application discloses a kind of overlay mark placement methods, comprising: step one, determine the distribution structure of grain in exposure area.Step two, each grain is divided into lattice point region according to the distribution structure of grain to each grain.Step three, according to process layer, the mask is grouped.Step four, in the lattice point region of multiple selected in the grain of mask corresponding to each group process layer as mark placement area and in mark placement area, device area inside overlay mark is placed, the arrangement and quantity of device area inside overlay mark corresponding to grain meet the high-order compensation requirement of overlay error.The application can accurately simulate the compensation value of high-order correction overlay error of device area, so as to prevent the high-order compensation parameter of internal overlay error of exposure area from being compensated, improve the yield of product, especially large-size wafer product.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit manufacturing method, in particular to a method for placing overlay (OVL) marks. BACKGROUND

[0002] The existing photolithography relies on scribe line overlay (OVL) marks for measuring the overlay accuracy between chip layers. With the continuous progress of technology and the continuous reduction of device critical dimensions, the overlay accuracy between layers is increasingly important to the overall wafer yield. In particular, for large-size chips, due to the large device area and the small number of scribe lines, the scribe line OVL marks can only be placed in the scribe lines, so the number and distribution of the scribe line OVL marks are limited by the scribe lines. When the area of the scribe lines decreases, no matter how the scribe line OVL marks are laid out, it is impossible to accurately simulate and calculate the high-order correction OVL compensation in the device area, resulting in abnormal OVL high-order feedback.

[0003] For inline large-size die products, since the size of the exposure area (shot) is determined by the photolithography machine and is usually fixed, when the size of the die increases, the area of the scribe lines on the periphery of the die will decrease, which will reduce the number of scribe line OVL marks placed on the scribe lines and affect their distribution. In some products, the insufficient number of OVL marks will cause the K12, K13 and K14 corresponding high-order compensation of OVL to continuously rise; K12, K13 and K14 are the fitting parameters of high-order in the light field level model such as the intra-field high-order process correction (iHOPC) model.

[0004] After analysis, it is found that the insufficient number of OVL marks and the existing OVL mark placement layout cause the K12 / 13 / 14 high-order OVL compensation item to be miscompensated, which causes the system to alarm. The miscompensation causes the actual OVL impact to be about 3.5 nm.

[0005] For example, Figure 1The image shows the noise amplification factor (nMU) data measured using diffraction-based overlay (DBO) technology for overlay marks placed using existing overlay mark placement methods. It can be seen that six grains 102 are disposed on the exposure area 101, and each grain 102 has a cleavage path 103 on its periphery. Multiple overlay marks 104 are disposed on the cleavage path 103. Figure 1 The image shows a total of 13 overprinted marks.

[0006] The nMU data is two-dimensional, with nMU(x, y) representing the nMU values ​​for each coordinate. A smaller nMU value indicates less noise and more accurate measurement results for the corresponding overlay marks. Typically, the corresponding specification range (spec) is less than 1. It can be seen that the maximum nMU value in the x-direction, nMU max(x), is 2.177, and the maximum nMU value in the y-direction, nMU max(y), is 0.984. Therefore, nMU max(x) is greater than 1, which does not meet the specification requirements.

[0007] like Figure 2 The figure shows a vector distribution diagram of the overlay deviation after overlay compensation for overlay marks placed by the existing overlay mark placement method. In the exposure area 101, the corresponding overlay deviation is represented by arrow line 105. In the X direction, 99.7% of the overlay deviations reach 3.47nm. Therefore, the actual OVL effect caused by miscompensation is about 3.5nm. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a method for placing overlay marks that can accurately simulate and calculate the compensation value of higher-order correction overlay error in the device region, thereby preventing erroneous compensation of higher-order compensation parameters for overlay error inside the exposure area and improving the yield of products, especially large-size die products.

[0009] To solve the above-mentioned technical problems, the overlay mark placement method provided by the present invention includes the following steps:

[0010] Step 1: Determine the distribution structure of the grains in the exposed area.

[0011] Step 2: Divide each grain into grid regions based on the distribution structure of the grains.

[0012] Step 3: Group the photomasks according to the process layer.

[0013] Step four, selecting a plurality of lattice point regions as mark placement regions in the crystal grains of the mask corresponding to each group of process layers and placing in-cell overlay marks in the mark placement regions, the arrangement and number of the in-cell overlay marks in the device region corresponding to the crystal grains satisfying the high-order compensation requirement of overlay error.

[0014] Further improvement is that in step one, the distribution structure of the crystal grains includes X direction distribution and Y direction distribution.

[0015] The X direction distribution is obtained from the X direction size of the exposure area, the X direction size of the crystal grains and the X direction size of the cutting path.

[0016] The Y direction distribution is obtained from the Y direction size of the exposure area, the Y direction size of the crystal grains and the Y direction size of the cutting path.

[0017] Further improvement is that the number of columns of the X direction distribution of the distribution structure of the crystal grains is calculated by the formula:

[0018] m = integer [(Rx-Sx) / (Cx+Sx)].

[0019] m represents the number of columns of the X direction distribution of the distribution structure of the crystal grains, integer() represents rounding down, Rx represents the X direction size of the exposure area, Sx represents the X direction size of the cutting path, and Cx represents the X direction size of the crystal grains.

[0020] The number of rows of the Y direction distribution of the distribution structure of the crystal grains is calculated by the formula:

[0021] n = integer [(Ry-Sy) / (Cy+Sy)].

[0022] n represents the number of rows of the Y direction distribution of the distribution structure of the crystal grains, Ry represents the Y direction size of the exposure area, Sy represents the Y direction size of the cutting path, and Cy represents the Y direction size of the crystal grains. Further improvement is that the X direction size of the crystal grains is the sum of the X direction size of the prime chip and the X direction size of the seal ring around the prime chip.

[0023] The Y direction size of the crystal grains is the sum of the Y direction size of the prime chip and the Y direction size of the seal ring around the prime chip.

[0024] Further improvement is that when the seal ring is added at the factory end:

[0025] The calculation formula of the X direction size of the crystal grains is:

[0026] Cx = (C0x * 0.9 + 2 * 22.2) pm;

[0027] The calculation formula of the Y direction size of the die is:

[0028] Cy = (C0y * 0.9 + 2 * 22.2) pm;

[0029] Cox represents the X direction size of the main chip;

[0030] Coy represents the Y direction size of the main chip.

[0031] Alternatively, when the sealing ring is added at the client end:

[0032] The calculation formula of the X direction size of the die is:

[0033] Cx = (C0x + 2 * 24) * 0.9 pm;

[0034] The calculation formula of the Y direction size of the die is:

[0035] Cy = (C0y + 2 * 24) * 0.9 pm.

[0036] Further improvement is that the maximum size of the exposure area in the X direction is 26 mm; the maximum size of the exposure area in the Y direction is 33 mm.

[0037] Further improvement is that the grid point division in step two includes: dividing each die in the X direction by a first value and dividing each die in the Y direction by a second value.

[0038] In the exposure area, the X direction size of each grid point area is equal, the Y direction size of each grid point area is equal, and the values of the first value and the second value ensure that the difference between the X direction size and the Y direction size of each grid point area is minimized.

[0039] Further improvement is that m takes one of 1, 2 and 3, and n takes one of 1, 2 and 3; and the combination of m x n includes: 1 x 1, 1 x 2, 2 x 1, 2 x 2, 1 x 3, 3 x 1.

[0040] Further improvement is that in step three, the process layer includes a FEOL layer and a BEOL layer.

[0041] Further improvement is that before step four, it further includes obtaining a plurality of legends in advance, each of the legends is a corresponding mark placement area distribution map.

[0042] The combination of each group of the process layer and each group of the distribution structure corresponding to the crystal grain has a legend, and the mark placement area distribution in the legend ensures that the high-order compensation of overlay error of the crystal grain corresponding to the legend meets the requirement.

[0043] In step four, the legend corresponding to the process layer and the distribution structure of the crystal grain is selected to obtain the distribution of the mark placement area corresponding to the crystal grain.

[0044] Further improvement is that in step four, the distance between the edge of the overlay mark in the device area and the edge of the corresponding mark placement area is greater than or equal to 2380 μm.

[0045] Further improvement is that in step four, the high-order compensation parameter of the overlay error is a fitting parameter of a product term of a quadratic term or more of X coordinate or a quadratic term or more of Y coordinate in a fitting formula of the overlay error at the corresponding coordinate.

[0046] Further improvement is that in step four, the arrangement and number of the overlay marks in the device area corresponding to the crystal grain meet the high-order compensation requirement of the overlay error, which means that after the overlay marks in the device area are set, the normalized model uncertainty (nMU) of the overlay error obtained by measuring the overlay marks in the device area is less than 1.

[0047] The present application sets the overlay mark in the device area, that is, the overlay mark in the device area, and performs grid division on the distribution structure of the crystal grain in the exposure area to obtain the grid area of the crystal grain, groups the process layer according to the process layer, and finally sets the distribution of the mark placement area according to the distribution structure of the crystal grain and the grouping of the corresponding process layer, and sets the overlay mark in the device area in the selected mark placement area. By combining the overlay mark in the device area set according to the distribution structure of the crystal grain and the grouping of the process layer, the high-order correction overlay error of the device area can be accurately simulated and calculated, so as to prevent the high-order compensation parameter of the overlay error in the exposure area from being compensated, and improve the yield of the product, especially the large-size crystal grain product.

[0048] The present application can form a legend of the mark placement area corresponding to the crystal grain with each distribution structure and process layer according to various distribution structures of the crystal grain and various groupings of the corresponding process layer. After the legend is formed, the subsequent crystal grain directly applies the distribution of the mark placement area in the legend to realize the setting of the overlay mark in the device area, which can simplify the process of setting the overlay mark in the device area. BRIEF DESCRIPTION OF DRAWINGS

[0049] The application will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0050] Figure 1 is an nMU data graph for DBO measurement of overlay marks placed by the overlay mark placement method of the prior art;

[0051] Figure 2 is a vector distribution graph of overlay mark placement error after overlay compensation of overlay marks placed by the overlay mark placement method of the prior art;

[0052] Figure 3 is a flow chart of the overlay mark placement method of the embodiment of the application;

[0053] Figure 4 is a schematic diagram of the distribution structure of the crystal grains in the exposure area of the overlay mark placement method of the embodiment of the application;

[0054] Figure 5A is a legend of the mark placement area distribution graph of the crystal grains of various distribution structures corresponding to the FEOL layer in the overlay mark placement method of the embodiment of the application;

[0055] Figure 5B is a legend of the mark placement area distribution graph of the crystal grains of various distribution structures corresponding to the BEOL layer in the overlay mark placement method of the embodiment of the application;

[0056] Figure 6 is a schematic diagram of the placement of the overlay marks in the mark placement area in the device area in the overlay mark placement method of the embodiment of the application;

[0057] Figure 7 is an nMU data graph for DBO measurement of overlay marks placed by the overlay mark placement method of the embodiment of the application. DETAILED DESCRIPTION

[0058] As shown in Figure 3 , it is a flow chart of the overlay mark placement method of the embodiment of the application; as shown in Figure 4 , it is a schematic diagram of the distribution structure of the crystal grains in the exposure area of the overlay mark placement method of the embodiment of the application; as shown in Figure 5A , it is a legend of the mark placement area distribution graph of the crystal grains 202 of various distribution structures corresponding to the FEOL layer in the overlay mark placement method of the embodiment of the application; as shown in Figure 5B , it is a legend of the mark placement area distribution graph of the crystal grains 202 of various distribution structures corresponding to the BEOL layer in the overlay mark placement method of the embodiment of the application; the overlay mark placement method of the embodiment of the application comprises the following steps:

[0059] Step one, as shown in Figure 4The distribution structure of the die 202 in the exposure area 201 is determined.

[0060] In the embodiment of the present application, the distribution structure of the die 202 includes an X-direction distribution and a Y-direction distribution.

[0061] The X-direction distribution is obtained from an X-direction size of the exposure area 201, an X-direction size of the die 202 and an X-direction size of the cutting lane 203.

[0062] The Y-direction distribution is obtained from a Y-direction size of the exposure area 201, a Y-direction size of the die 202 and a Y-direction size of the cutting lane 203.

[0063] In the embodiment of the present application, the number of columns of the X-direction distribution of the distribution structure of the die 202 is calculated by the following formula:

[0064] m = integer [(Rx-Sx) / (Cx+Sx)].

[0065] m represents the number of columns of the X-direction distribution of the distribution structure of the die 202, integer() represents rounding down, Rx represents the X-direction size of the exposure area 201, Sx represents the X-direction size of the cutting lane 203, and Cx represents the X-direction size of the die 202. Rx, Sx and Cx are also marked in the figure. Figure 4

[0066] The number of rows of the Y-direction distribution of the distribution structure of the die 202 is calculated by the following formula:

[0067] n = integer [(Ry-Sy) / (Cy+Sy)].

[0068] n represents the number of rows of the Y-direction distribution of the distribution structure of the die 202, Ry represents the Y-direction size of the exposure area 201, Sy represents the Y-direction size of the cutting lane 203, and Cy represents the Y-direction size of the die 202. Ry, Sy and Cy are also marked in the figure. Figure 4

[0069] Further, the X-direction size of the die 202 is the sum of the X-direction sizes of the main chip and the sealing ring around the main chip.

[0070] The Y-direction size of the die 202 is the sum of the Y-direction sizes of the main chip and the sealing ring around the main chip.

[0071] In some embodiments, when the sealing ring is added at the factory end:

[0072] The calculation formula of the X-direction size of the die 202 is: ​​

[0073] Cx = (C0x * 0.9 + 2 * 22.2) μm;

[0074] The formula for calculating the Y-direction dimension of the grain 202 is as follows:

[0075] Cy = (C0y * 0.9 + 2 * 22.2) μm;

[0076] Cox represents the X-axis dimension of the main chip;

[0077] Coy represents the Y-axis dimension of the main chip.

[0078] In some embodiments, it can also be: when the sealing ring is added at the client:

[0079] The formula for calculating the X-direction dimension of the grain 202 is as follows:

[0080] Cx = (C0x + 2 * 24) * 0.9 μm;

[0081] The formula for calculating the Y-direction dimension of the grain 202 is as follows:

[0082] Cy = (C0y + 2 * 24) * 0.9 μm.

[0083] In some embodiments, the maximum dimension of the exposure area 201 in the X direction is 26 mm; the maximum dimension of the exposure area 201 in the Y direction is 33 mm.

[0084] In some embodiments, the following specific settings are included for Sx and Sy:

[0085] The width of a single scribe line is 66 μm; the width of other scribe lines is k*60 μm, where k = 2, 3, 4, 5, 6...

[0086] Depend on Figure 4 As shown, more than one die 202 can be placed within one exposure area 201. The main purpose of this invention is to solve the technical problems caused by large-sized dies 202. Specifically, the area of ​​the dicing channel 203 corresponding to a large-sized die 202 is smaller, and its distribution is not conducive to placing overlay marks within the dicing channel area. Consequently, the number of overlay marks within the dicing channel area is smaller, and their layout is poor, resulting in a situation where the actual overlay cannot be reflected, thus leading to the technical problem of this invention.

[0087] For the large size of the crystal grain 202, in some embodiments, m takes one of 1, 2 and 3, n takes one of 1, 2 and 3, and the combination of m x n includes: 1x1, 1x2, 2x1, 2x2, 1x3, 3x1.

[0088] Figure 5A And Figure 5B In the above, the distribution structure of the crystal grain 202 corresponding to various combinations of m x n is also respectively represented by 1x1 die, 2x1 die, 1x2 die, 2x2 die, 1x3 die, 3x1 die.

[0089] Figure 5A The size of various crystal grains 202 shown in the above is relatively large, and the existing method for placing overlay marks is prone to the technical problems pointed out by the present application. If the size of the crystal grain 202 is further reduced, the value of m or n will be further increased, the number of the crystal grains 202 in the same exposure area 201 will be increased, and the number of the cutting paths 203 will also be increased. If the number and distribution of the cutting paths 203 are sufficient to place overlay marks 301 that can meet the requirement of avoiding high-order overlay compensation, the device area overlay marks 301 can be placed by selecting or not selecting the method of the embodiment of the present application.

[0090] Step two, according to the distribution structure of the crystal grain 202, the lattice division of each crystal grain 202 is carried out to obtain the lattice area 204 of each crystal grain 202.

[0091] In the embodiment of the present application, the lattice division includes: dividing each crystal grain 202 by a first value in the X direction and dividing each crystal grain 202 by a second value in the Y direction.

[0092] In the exposure area 201, the X direction size of each lattice area 204 is equal, the Y direction size of each lattice area 204 is equal, and the values of the first value and the second value ensure that the difference between the X direction size and the Y direction size of each lattice area 204 is minimized.

[0093] Figure 5A And Figure 5B In the above, taking the maximum size of 26mm in the X direction of the exposure area 201 and the maximum size of 33mm in the Y direction of the exposure area 201 as an example, in the distribution structure of various crystal grains 202, the lattice division can be made as follows:

[0094] For 1x1 die, it is divided by 11 in the X direction and by 13 in the Y direction. Figure 5A In the above, the corresponding crystal grain is individually represented by a mark 202a.

[0095] For 2x1 die, it is 5-division in X direction and 13-division in Y direction; Figure 5A In the middle, the corresponding said grain is individually represented by a mark 202b, and the corresponding said cutting path is individually represented by a mark 203b.

[0096] For 1x2 die, it is 11-division in X direction and 5-division in Y direction;

[0097] For 2x2 die, it is 7-division in X direction and 9-division in Y direction;

[0098] For 1x3 die, it is 11-division in X direction and 5-division in Y direction;

[0099] For 3x1 die, it is 5-division in X direction and 13-division in Y direction.

[0100] In other embodiments, when the size of the exposure area 201 is not 26mm x 33mm, the grid division can be performed as needed, and is not necessarily limited to the above division results.

[0101] Step three, grouping the masks according to the process layers.

[0102] In wafer manufacturing, the said grains 202 need to go through multiple processes, and in some process steps, masks need to be used for definition. Therefore, the said grains 202 need to use multiple masks in actual processes. Usually, one layer corresponds to one mask, and multiple process layers can share the same mask.

[0103] The process of the said grains 203 is usually divided into front-end-of-line (FEOL), middle-of-line (MOL) and back-end-of-line (BEOL). FEOL process is mainly used to form semiconductor device structures on wafers, i.e. to complete the manufacturing of gate structures, source regions and drain regions of semiconductor devices such as MOSFETs. MOL is mainly used to form contact holes to realize the connection of gate structures, source regions and drain regions of semiconductor devices. BEOL is used to form metal interconnection layers.

[0104] FEOL process includes multiple process layers, and BEOL process also includes multiple process layers. In this application, each process layer in FEOL is collectively referred to as FEOL layer, and each process layer in BEOL is collectively referred to as BEOL layer. In the embodiments of the present application, the process layers related to the masks used in the manufacturing process of the said grains 202 are grouped according to the said FEOL layers and the said BEOL layers, i.e. the said process layers include FEOL layers and BEOL layers.

[0105] In this way, Figure 5Athe distribution structure of the dies 202 corresponding to each process layer in the FEOL layer requiring the use of a mask and the corresponding lattice division; Figure 5B the distribution structure of the dies 202 corresponding to each process layer in the FEOL layer requiring the use of a mask and the corresponding lattice division.

[0106] Step four, select a plurality of lattice regions 204 as mark placement regions 204a in the dies 202 corresponding to each group of process layers of the mask and place device area inner overlay marks 301 in the mark placement regions 204a, the arrangement and number of the device area inner overlay marks 301 corresponding to the dies 202 meet the high-order compensation requirements of overlay error.

[0107] In the embodiments of the present application, step four further includes obtaining a plurality of legends in advance, each of the legends being a distribution map of the mark placement regions 204a corresponding to the legend.

[0108] Each group of the process layers and each of the distribution structures corresponding to the dies 202 has a legend, and the distribution map of the mark placement regions 204a in the legend ensures that the high-order compensation of the overlay error of the dies 202 corresponding to the legend meets the requirements.

[0109] In step four, the distribution map of the mark placement regions 204a corresponding to the dies 202 is obtained according to the corresponding process layers and the distribution structure of the dies 202.

[0110] In some embodiments, the distribution structure of the dies 202 with large size includes 1x1 die, 2x1 die, 1x2 die, 2x2 die, 1x3 die, and 3x1 die.

[0111] For the FEOL layer, six legends shown in FIG. 1 can be set. Figure 5A Figure 5A In FIG. 1, the mark placement regions are individually represented by marks 204a.

[0112] For the BEOL layer, six legends shown in FIG. 2 can be set. Figure 5B The specific distribution of the mark placement regions 204a in each of the legends can be referred to FIG. 3 and FIG. 4.

[0113] Figure 5A Here, the legends are not described one by one. Figure 5B Figure 5A Each of the legends of FIG. 1 and FIG. 2 is verified by experiment and meets the high-order compensation requirements of overlay error. In other embodiments, each of the legends shown in FIG. 1 and FIG. 2 can be changed as needed. Figure 5B Figure 5A Figure 5B The legends of FIG. 1 and FIG. 2 are verified by experiment and meet the high-order compensation requirements of overlay error. In other embodiments, each of the legends shown in FIG. 1 and FIG. 2 can be changed as needed.​​​​​

[0114] When the process layer and distribution structure corresponding to the die 202 are obtained, the corresponding legend can be selected, and then the mark placement area 204a is set according to the legend. For example, when the process layer of the die 202 is an FEO layer and the distribution structure is 1x3 die, the mark placement area 204a can be set according to the legend corresponding to 1x3 die. Figure 5A

[0115] As shown in FIG. 2, the edge of the mark placement area 204a is set to be greater than or equal to 2380 μm from the edge of the device area mark 301. Figure 6 As shown in FIG. 3, the edge of the mark placement area 204a is set to be greater than or equal to 2380 μm from the edge of the device area mark 301. Figure 6 As shown in FIG. 3, the edge of the mark placement area 204a is set to be greater than or equal to 2380 μm from the edge of the device area mark 301.

[0116] In the embodiment of the present application, the high-order compensation parameter of the overlay error is a fitting parameter of a product term of a square or higher power of X coordinate or a square or higher power of Y coordinate in a fitting formula of the overlay error at a corresponding coordinate. For example, in some fitting formulas of the overlay error, a light field level model is used, and the high-order compensation includes fitting parameters K12, K13 and K14 in the light field level model, wherein:

[0117] K12 is a fitting parameter of a product term of x direction overlay error, i.e., OVLx, and y direction overlay error, i.e., OVLy; 2 y 0

[0118] K13 is a fitting parameter of a product term of x direction overlay error, i.e., OVLx, and y direction overlay error, i.e., OVLy; 3 y 0

[0119] K14 is a fitting parameter of a product term of x direction overlay error, i.e., OVLx, and y direction overlay error, i.e., OVLy. 0 y 3

[0120] In the embodiment of the present application, the arrangement and number of the device area mark 301 corresponding to the die 202 meet the high-order compensation requirement of the overlay error, which means that the noise magnification factor nMU of the overlay error obtained by measuring the device area mark 301 is less than 1.

[0121] As shown in FIG. 2, the edge of the mark placement area 204a is set to be greater than or equal to 2380 μm from the edge of the device area mark 301. Figure 7 ​​​​The nMU data graph shown is the DBO measurement of the overlay marks placed by the overlay mark placement method of the embodiment of the application; Figure 7 The exposure area is marked by 201c, and the die is marked by 202c. Figure 5A The 1x3 die in the exposure area is marked by 201c, and the die is marked by 202c. Figure 7 The 1x3 die in the exposure area is marked by 201c, and the die is marked by 202c. The nMU data is two-dimensional data, and the nMU data of each coordinate is nMU(x, y). The smaller the nMU data is, the more accurate the measurement result of the overlay mark is. The maximum value of nMU in the x direction is nMU max(x), which is 0.692, and the maximum value of nMU in the y direction is nMU max(y), which is 0.967, both of which meet the requirement of being less than 1.

[0122] The embodiment of the application sets the overlay mark in the device area, i.e., the device area overlay mark, and performs grid point division according to the distribution structure of the die 202 in the exposure area 201 to obtain the grid point area 204 of the die 202. The mask is grouped according to the process layer, and finally the distribution of the mark placement area 204a is set according to the distribution structure of the die 202 and the grouping of the corresponding process layer, and the device area overlay mark 301 is set in the selected mark placement area 204a. The device area overlay mark 301 set by combining the distribution structure of the die 202 and the grouping of the process layer can accurately simulate and calculate the high-order correction overlay error compensation value of the device area, thereby preventing the high-order compensation parameter of the overlay error inside the exposure area 201 from being compensated, and improving the yield of the product, especially the large-size die 202 product.

[0123] The embodiment of the application can form the legend of the mark placement area 204a corresponding to the die 202 with various distribution structures and process layer combinations in advance. After the legend is formed, the subsequent die 202 can directly use the distribution of the mark placement area 204a in the legend to set the device area overlay mark 301 under the condition of obtaining the distribution structure and the grouping of the process layer. In this way, the process of setting the device area overlay mark 301 can be simplified.

[0124] The lack of OVL measurement marks or the insufficient arrangement and quantity of the marks in a large die product shot can cause the calculation of high-order OVL correction parameters to have a false compensation for the mark-free area, leading to a deviation of actual wafer layer-to-layer overlay in the mark-free area, and causing a large range of low good products. The arrangement rules of in-cell OVL marks balance the valuable in-cell space and the high-order calculation demand, so that both are considered during layout design, and the situation of low good products and layout area waste is avoided. Embodiments of the present application standardize the placement mode and quantity rules of in-cell OVL marks in the device area, so as to standardize the arrangement of in-cell OVL marks in a large Die product, and avoid the occurrence of the false high-order OVL compensation situation caused by mark arrangement.

[0125] The above has been described in detail through specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can also make many modifications and improvements without departing from the principles of the present application, and these should also be considered as the protection scope of the present application.

Claims

1. A mark placement method for overlay marking, characterized by, The method comprises the following steps: Step one, determining the distribution structure of the grains in the exposure area; Step two, performing lattice division on each grain according to the distribution structure of the grains to obtain lattice regions of each grain; Step three, grouping the photomasks according to the process layers; Step four, selecting a plurality of lattice regions as mark placement regions in the grains of the photomasks corresponding to each group of process layers and placing in-region overlay marks in the mark placement regions, the arrangement and number of the in-region overlay marks corresponding to the grains satisfying the high-order compensation requirement of overlay error; Before step four, a plurality of legends are obtained in advance, each legend being a distribution map of the corresponding mark placement region; The combination of each group of process layers and each distribution structure corresponding to the grains has a legend, and the distribution map of the mark placement region in the legend guarantees that the high-order compensation of the overlay error of the grains corresponding to the legend meets the requirement; In step four, the distribution map of the mark placement region corresponding to the grains is obtained by selecting the corresponding legend according to the corresponding process layers and the distribution structure of the grains.

2. The overlay mark placement method of claim 1, wherein: In step one, the distribution structure of the grains comprises X-direction distribution and Y-direction distribution; The X-direction distribution is obtained from the X-direction size of the exposure area, the X-direction size of the grains and the X-direction size of the scribe lane; The Y-direction distribution is obtained from the Y-direction size of the exposure area, the Y-direction size of the grains and the Y-direction size of the scribe lane.

3. The overlay mark placement method of claim 2, wherein: The column number of the X-direction distribution of the distribution structure of the grains is calculated by the following formula: m=integer[(Rx-Sx) / (Cx+Sx)]; m represents the column number of the X-direction distribution of the distribution structure of the grains, integer() represents rounding down, Rx represents the X-direction size of the exposure area, Sx represents the X-direction size of the scribe lane, and Cx represents the X-direction size of the grains; The row number of the Y-direction distribution of the distribution structure of the grains is calculated by the following formula: n=integer[(Ry-Sy) / (Cy+Sy)]; n represents the row number of the Y-direction distribution of the distribution structure of the grains, Ry represents the Y-direction size of the exposure area, Sy represents the Y-direction size of the scribe lane, and Cy represents the Y-direction size of the grains.

4. The in-region overlay mark placement method according to claim 3, wherein: the X-direction size of the grains is the sum of the X-direction sizes of the main chip and the sealing ring around the main chip; and the Y-direction size of the grains is the sum of the Y-direction sizes of the main chip and the sealing ring around the main chip.

5. The overlay mark placement method of claim 4, wherein: When the sealing ring is added at the factory end: the calculation formula of the X-direction size of the grains is: Cx=(C0x*0.9+2*22.2)μm; the calculation formula of the Y-direction size of the grains is: Cy=(C0y*0.9+2*22.2)μm; Cox represents the X-direction size of the main chip; Coy represents the Y-direction size of the main chip; or when the sealing ring is added at the customer end: The calculation formula of the X direction size of the crystal grain is: Cx= (C0x+2*24)*0.9 μm; The calculation formula of the Y direction size of the crystal grain is: Cy= (C0y+2*24)*0.9 μm.

6. The overlay mark placement method of claim 3, wherein: The maximum size of the exposure area in the X direction is 26 mm; the maximum size of the exposure area in the Y direction is 33 mm.

7. The overlay mark placement method of claim 3, wherein: The grid point division in step two includes: dividing each crystal grain by a first value in the X direction and dividing each crystal grain by a second value in the Y direction; In the exposure area, the X direction size of each grid point area is equal, the Y direction size of each grid point area is equal, and the values of the first value and the second value ensure that the difference between the X direction size and the Y direction size of each grid point area is minimum.

8. The overlay mark placement method of claim 6, wherein: m takes one of 1, 2 and 3, and n takes one of 1, 2 and 3; And, the combination of m*n includes: 1*1, 1*2, 2*1, 2*2, 1*3, 3*1.

9. The overlay mark placement method of claim 1, wherein: In step three, the process layer includes a FEOL layer and a BEOL layer.

10. The overlay mark placement method of claim 1, wherein: In step four, the distance between the edge of the device area inner overlay mark and the edge of the corresponding mark placement area is greater than or equal to 2380 μm.

11. The overlay mark placement method of claim 1, wherein: In step four, the high-order compensation parameter of the overlay error is a fitting parameter of a product term of the square of X coordinate or the square of Y coordinate in a fitting formula of the overlay error at the corresponding coordinate.

12. The overlay mark placement method of claim 11, wherein: In step four, the arrangement and number of the device area inner overlay marks corresponding to the crystal grain meet the high-order compensation requirement of the overlay error, which means that after setting the device area inner overlay mark, the noise amplification factor of the overlay error obtained by measuring the device area inner overlay mark is less than 1.

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