Time-to-digital converter and control method

Abstract

An embodiment of the present disclosure provides a time-to-digital converter and a control method. The time-to-digital converter includes: at least one time-to-digital conversion unit, the time-to-digital conversion unit including a delay locking module and a signal acquisition module, the delay locking module and the signal acquisition module including a common delay link, the time-to-digital converter having a delay locking mode and a time-to-digital conversion mode; in the delay locking mode, the delay locking module locks the basic delay time of the delay link; in the time-to-digital conversion mode, the signal acquisition module acquires the output signal of the delay link based on the basic delay time of the delay link to determine a signal time difference.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a time-to-digital converter and a control method thereof. Background Art

[0002] Time-to-digital converters (TDCs) are becoming increasingly important in time-of-flight (TOF) measurement and instrumentation. The TDC's measurement accuracy depends on the stability and accuracy of its core circuitry—the delay link. However, variations in process voltage and temperature (PVT) significantly impact the stability of the delay link.

[0003] Therefore, it is urgent to propose a time-to-digital converter with stability. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a time-to-digital converter and a control method thereof.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a time-to-digital converter, comprising at least one time-to-digital conversion unit, the time-to-digital conversion unit comprising a delay locking module and a signal acquisition module, the delay locking module and the signal acquisition module comprising a common delay link, the time-to-digital converter having a delay locking mode and a time-to-digital conversion mode; in the delay locking mode, the delay locking module locks the basic delay time of the delay link; in the time-to-digital conversion mode, the signal acquisition module acquires the output signal of the delay link based on the basic delay time of the delay link to determine the signal time difference.

[0007] In a second aspect, an embodiment of the present disclosure provides a control method for a time-to-digital converter, wherein the time-to-digital converter includes at least one time-to-digital conversion unit, the time-to-digital conversion unit includes a delay locking module and a signal acquisition module, the delay locking module and the signal acquisition module include a common delay link, and the time-to-digital converter has a delay locking mode and a time-to-digital conversion mode; the method includes: in the delay locking mode, locking the basic delay time of the delay link; in the time-to-digital conversion mode, acquiring the output signal of the delay link according to the basic delay time to determine the signal time difference.

[0008] The present disclosure provides a time-to-digital converter and control method. The time-to-digital converter includes at least one time-to-digital conversion unit, the time-to-digital conversion unit including a delay lock module and a signal acquisition module. The delay lock module and the signal acquisition module share a common delay link. The time-to-digital converter has a delay lock mode and a time-to-digital conversion mode. In the delay lock mode, the delay lock module locks the basic delay time of the delay link. In the time-to-digital conversion mode, the signal acquisition module acquires the output signal of the delay link based on the basic delay time of the delay link to determine the signal time difference. In the time-to-digital converter provided by the embodiments of the present disclosure, the delay locking module and the signal acquisition module include a shared delay link, which can effectively reduce manufacturing costs. It can also avoid the problem of inaccurate time quantization precision in the time-to-digital converter caused by the basic delay times of the two delay links being inconsistent due to process mismatch when the delay locking module and the signal acquisition module each include two different delay links. Therefore, by including a shared delay link in the delay locking module and the signal acquisition module, the problem of inaccurate quantization precision caused by the delay locking module and the signal acquisition module each using different delay links can be avoided, thereby improving the accuracy of measuring signal time differences. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic diagram of the structure of a time-to-digital conversion system in the related art;

[0010] Figure 2 A schematic diagram of the structure of the time-to-digital converter provided in the embodiment of the present disclosure Figure 1 ;

[0011] Figure 3 A schematic diagram of the structure of the time-to-digital converter provided in the embodiment of the present disclosure Figure 2 ;

[0012] Figure 4 A schematic diagram of the structure of a voltage modulation circuit provided in an embodiment of the present disclosure;

[0013] Figure 5 A schematic diagram of the structure of the time-to-digital converter provided in the embodiment of the present disclosure Figure 3 ;

[0014] Figure 6 A schematic diagram of the structure of the time-to-digital converter provided in the embodiment of the present disclosure Figure 4 ;

[0015] Figure 7 A schematic diagram of the structure of the time-to-digital converter provided in the embodiment of the present disclosure Figure 5 ;

[0016] Figure 8A schematic diagram of the steps of a control method for a time-to-digital converter provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0018] The purpose of the terms used in this disclosure is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0019] The main application areas of time-to-digital converters (TDCs) include 3D imaging, laser radar (LiDAR), and high-speed data sampling. In 3D imaging, TDCs are used in direct time-of-flight (TOF) 3D imaging technology. This technology calculates depth of field by measuring the time it takes for a light pulse to be emitted and returned, thereby generating a 3D image. This technology offers the advantages of high precision, high speed, compact system size, and high robustness. In LiDAR, TDCs are used to measure the flight time of laser pulses to determine the distance and speed of objects. This technology is widely used in fields such as autonomous driving, robotic navigation, and terrain mapping.

[0020] Figure 1 FIG. 1 is a structural diagram of a time-to-digital conversion system in the related art. Figure 1As shown in the related art, the reference voltage Vc for the multiple delay cells in Delay Chain 1, the core circuit of a TDC, is typically generated by a delay-locked loop (DLL) (or phase-locked loop (PLL)). Each delay cell in Delay Chain 2 of the DLL / PLL has a fixed, single control voltage and delay time. By replicating the control voltage of each delay cell in the DLL / PLL to each delay cell in Delay Chain 1 of the TDC, the delay time of each delay cell in Delay Chain 1 (i.e., the TDC's quantization accuracy) is referenced by the delay time of each delay cell in the DLL / PLL, achieving a fixed, single characteristic. This avoids the problem of inaccurate and unstable TDC quantization accuracy caused by the delay cells being affected by voltage V and temperature T.

[0021] However, in related technologies, the delay-locked loop (DLL) (or phase-locked loop (PLL)) and the time-delayed circuit (TDC) each use a set of delay cell arrays (i.e., delay chains). The delay cells in the two delay chains may have different manufacturing processes P. This can cause the delay times of the delay cells in the two delay chains to differ even at the same temperature T and control voltage V. This means that the two delay chains may have a process mismatch. This process mismatch can still lead to inaccurate and non-uniform quantization accuracy of the TDC.

[0022] To overcome the TDC quantization accuracy issues caused by factors such as temperature T, voltage V, and process P, this application provides the following solutions:

[0023] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0024] Figure 2 A schematic diagram of the structure of the time-to-digital converter provided in the embodiment of the present disclosure Figure 1 See also Figure 2 The time-to-digital converter includes at least one time-to-digital conversion unit, which includes a delay locking module and a signal acquisition module. The delay locking module and the signal acquisition module include a common delay link 10. The time-to-digital converter has a delay locking mode and a time-to-digital conversion mode. In the delay locking mode, the delay locking module locks the basic delay time of the delay link 10. In the time-to-digital conversion mode, the signal acquisition module collects the output signal of the delay link 10 according to the basic delay time of the delay link 10 to determine the signal time difference.

[0025] In the embodiments of the present disclosure, the delay lock module functions as a delay-locked loop (DLL) (or phase-locked loop (PLL)) in related art, and the signal acquisition module functions as a time-delayed circuit (TDC) in related art. For ease of description and understanding, the delay lock module is labeled "DLL / PLL" in the drawings of the present disclosure, and the signal acquisition module is labeled "TDC."

[0026] It should be noted that since the functions of the delay-locked loop (DLL) and the phase-locked loop (PLL) are similar—both can provide a stable and single control voltage—the present embodiment only illustrates the circuit structure of the delay-locked loop (DLL) used in the delay-locked loop module. The circuit structure of the delay-locked loop (PLL) used in the delay-locked loop module can be similarly deduced. It is only necessary to replace the entire DLL in the diagram with the structure of the PLL and maintain a shared delay link between the TDC and the PLL. Since the circuit structure of the PLL is a prior art, the present embodiment does not elaborate on it here.

[0027] In the embodiment of the present disclosure, in the delay locking mode, the delay locking module works. The delay locking module receives the reference signal Clk_ref, which is a clock signal with a period of T. The delay link 10 delays the reference signal Clk_ref. When the phase difference and frequency difference between the output signal of the delay link 10 (the delayed reference signal Clk_ref_delay) and the reference signal Clk_ref are zero, the delay locking module reaches a stable (locked) state. At this time, the delay time of the delay link 10 is exactly locked to a period T of the reference signal Clk_ref, and the highest time accuracy that can be quantified by the delay link 10 - the basic delay time t d .

[0028] In the time-to-digit conversion mode, the signal acquisition module works. The signal acquisition module receives the start signal Start, and the delay link 10 is based on the basic delay time t locked above. d The start signal Start is delayed step by step. At the same time, the signal acquisition module also delays the start signal Start in the delay link 10 step by step when it receives the stop signal Stop. d The number x of samples is collected to obtain the signal time difference Δt between the start signal Start and the stop signal Stop. It can be understood that Δt=x*t d .

[0029] In the time-to-digital converter provided by the embodiments of the present disclosure, the delay locking module and the signal acquisition module include a shared delay link, which can effectively reduce manufacturing costs. It can also avoid the problem of inaccurate time quantization precision in the time-to-digital converter caused by the basic delay times of the two delay links being inconsistent due to process mismatch when the delay locking module and the signal acquisition module each include two different delay links. Therefore, by including a shared delay link in the delay locking module and the signal acquisition module, the problem of inaccurate quantization precision caused by the delay locking module and the signal acquisition module each using different delay links can be avoided, thereby improving the accuracy of measuring signal time differences.

[0030] In some embodiments, the delay locking module may only lock the basic delay time of the delay link once. In the time-to-digital conversion mode, the signal acquisition module determines the signal time difference of different signals based on the same basic delay time. In other embodiments, before each measurement of the signal time difference by the signal acquisition module, the delay locking module may lock the basic delay time of the delay link based on different reference signals Clk_ref (with different periods T) to lock the basic delay time t of different time accuracies. d ,In this way, the signal acquisition module can have different quantization accuracy each time it measures the signal time difference.

[0031] Figure 3 A schematic diagram of the structure of the time-to-digital converter provided in the embodiment of the present disclosure Figure 2 See also Figure 3 In some embodiments, the delay locking module further includes a feedback link 20, wherein a first input terminal of the feedback link 20 and an input terminal of the delay link 10 are commonly coupled to the first signal input terminal, a second input terminal of the feedback link 20 is coupled to the output terminal of the delay link 10, and an output terminal of the feedback link 20 is coupled to the control terminal of the delay link 10; wherein the feedback link 20 is configured to: in the delay locking mode, generate a control signal Vctrl of the delay link 10 based on a reference signal at the first signal input terminal and an output signal at the output terminal of the delay link 10 to lock the basic delay time; and in the time-to-digital conversion mode, keep the control signal Vctrl at the control terminal of the delay link 10 unchanged.

[0032] See also Figure 3, in the delay locking mode, the delay locking module works. The delay link 10 receives the reference signal Clk_ref and delays it, and the output signal at the output end of the delay link 10 is the delayed reference signal Clk_ref_delay. The first input end of the feedback link 20 is used to receive the reference signal Clk_ref, and the second input end of the feedback link 20 can receive the output signal of the delay link 10 (the delayed reference signal Clk_ref_delay). The feedback link 20 can compare the phase difference and frequency difference between the reference signal Clk_ref and the output signal Clk_ref_delay of the delay link 10, and accordingly adjust the control signal of the control end of the delay link 10 to Vctrl, so that the phase difference and frequency difference between the reference signal Clk_ref and the output signal Clk_ref_delay of the delay link 10 are zero. At this time, the delay time of the delay link 10 is exactly one period T of the reference signal Clk_ref, thereby locking the basic delay time t of the delay link 10. d In the time-to-digit conversion mode, the feedback link 20 can keep the control signal of the control end of the delay link 10 unchanged at Vctrl, so that the basic delay time t of the delay link 10 is d Remain unchanged.

[0033] In some embodiments, the feedback link 20 includes a voltage modulation circuit 21, a first switching circuit 22 and a voltage holding circuit 23 connected in sequence, the first input terminal and the second input terminal of the voltage modulation circuit 21 are coupled to the first signal input terminal and the output terminal of the delay link 10 respectively, the first switching circuit 22 connects the output terminal of the voltage modulation circuit 21 and the input terminal of the voltage holding circuit 23, and the output terminal of the voltage holding circuit 23 is connected to the control terminal of the delay link 10; the first switching circuit 22 is configured to: in the delay lock mode, turn on the connection between the output terminal of the voltage modulation circuit 21 and the input terminal of the voltage holding circuit 23; in the time-to-digital conversion mode, disconnect the connection between the output terminal of the voltage modulation circuit 21 and the input terminal of the voltage holding circuit 23.

[0034] See also Figure 3 The first input end of the voltage modulation circuit 21 serves as the first input end of the feedback link 20 , the second input end of the voltage modulation circuit 21 serves as the second input end of the feedback link 20 , and the output end of the voltage holding circuit 23 serves as the output end of the feedback link 20 .

[0035] In delay lock mode, the first switch circuit 22 is closed, connecting the output of the voltage modulation circuit 21 to the input of the voltage holding circuit 23. The voltage modulation circuit 21 can output and adjust a control signal by comparing the phase and frequency differences between the reference signal Clk_ref and the output signal Clk_ref_delay of the delay link 10. The control signal is transmitted to the control terminal of the delay link 10 via the first switch circuit 22 and the voltage holding circuit 23. The delay link 10 is a voltage-controlled delay line (VCDL). The control terminal of the delay link 10 is controlled by a voltage signal. Therefore, the control signal is essentially a voltage signal. The voltage-controlled delay line can have different delay performance under the control of different voltage signals. Before the delay lock module reaches a stable (locked) state, the voltage modulation circuit 21 continuously adjusts the voltage of the output control signal by comparing the phase difference and frequency difference between the reference signal Clk_ref and the output signal Clk_ref_delay of the delay link 10, thereby adjusting the delay time of the delay link 10, and then adjusting the phase difference and frequency difference between the reference signal Clk_ref and the output signal Clk_ref_delay of the delay link 10 until the reference signal Clk_ref and the output signal Clk_ref_delay of the delay link 10 reach a stable (locked) state. The phase difference and frequency difference are zero. At this time, there is no phase difference and frequency difference between the signals at the two input ends of the voltage modulation circuit 21 (i.e., the reference signal Clk_ref and the output signal Clk_ref_delay of the delay link 10). Then the voltage modulation circuit 21 no longer adjusts the voltage of the control signal, that is, the delay locking module reaches a stable (locked) state. At this time, the control signal generated by the voltage modulation circuit 21 is Vctrl, and the delay time of the delay link 10 is exactly locked to one period T of the reference signal Clk_ref, thereby locking the basic delay time t of the delay link 10. d .

[0036] In the time-to-digital conversion mode, the first switch circuit 22 is in an off state to disconnect the output terminal of the voltage modulation circuit 21 from the input terminal of the voltage holding circuit 23. The voltage holding circuit 23 is configured to hold the control signal Vctrl and output it to the control terminal of the delay link 10, so that the basic delay time t d It should be noted that the output signal of the voltage holding circuit 23 changes with the input signal of the voltage holding circuit 23. When the input end of the voltage holding circuit 23 does not receive a signal, the output signal of the voltage holding circuit 23 will remain the previous input signal.

[0037] Figure 4 This is a schematic diagram of the structure of the voltage modulation circuit provided by the embodiment of the present disclosure. Figure 4 The voltage modulation circuit 21 may include an identification unit 211 and a filtering unit 212 connected in sequence. The first input terminal of the identification unit 211 serves as the first input terminal of the voltage modulation circuit 21, the second input terminal of the identification unit 211 serves as the second input terminal of the voltage modulation circuit 21, and the output terminal of the filtering unit 212 serves as the output terminal of the voltage modulation circuit 21.

[0038] In delay lock mode, identification unit 211 compares the phase and frequency differences between reference signal Clk_ref and the delay link's output signal Clk_ref_delay and generates an identification signal Vpd proportional to the phase or frequency difference. Filter unit 212 filters voltage signal Vpd to output a control signal. Filter unit 212 is specifically configured to remove high-frequency noise and spurious signals from identification signal Vpd. The control signal output by filter unit 212 is used to adjust the phase and frequency of the delay link 10's output signal until the phase and frequency differences between reference signal Clk_ref and delay link 10's output signal Clk_ref_delay are zero.

[0039] In some embodiments, the structure of the delay lock module is similar to that of a delay locked loop (DLL). In this case, the identification unit 211 may include a phase frequency detector (PFD) and a charge pump (CP) connected in series. In other embodiments, the structure of the delay lock module is similar to that of a phase locked loop (PLL). In this case, the identification unit 211 may include a phase detector (PD). It should be noted that the filtering unit in the embodiments of the present disclosure may be a low-pass filter or a loop filter.

[0040] In some embodiments, the delay link includes multiple cascaded delay units, and the signal acquisition module also includes multiple registers corresponding to the delay units; wherein the data input end of each register is connected to the output end of the corresponding delay unit, and the clock input end of each register is connected to the second signal input end.

[0041] In some embodiments, when the delay lock module reaches a stable state, the delay time of the delay link is exactly locked to one period T of the reference signal Clk_ref. At this time, the delay time of each delay unit is the same and the basic delay time is t d , where t d=T / N (N is the number of delay units in the delay link). It should be noted that the multiple delay units in the delay link are all voltage-controlled delay units. The voltage-controlled end of each delay unit is connected in parallel to form the control end of the delay link. The multiple delay units have the same delay performance under the control of the same voltage signal, and the same delay unit has different delay performance under the control of different voltage signals. The embodiments of this disclosure do not impose any restrictions on the number of delay units in the delay link.

[0042] Figure 3 Take the delay link including 5 cascaded delay units as an example for explanation, see Figure 3 The delay link includes delay unit 11, delay unit 12, delay unit 13, delay unit 14, and delay unit 15. The signal acquisition module also includes five registers (registers 31 to 35) corresponding to the delay units. The voltage control terminal of each delay unit is connected to the output terminal of the feedback link 20, the data input terminal D (Data) of each register is connected to the output terminal of the corresponding delay unit, and the clock input terminal C (Clk) of each register is synchronously connected to the second signal input terminal so that the stop signal Stop received by the second signal input terminal can be synchronously (simultaneously) transmitted to the clock input terminal C (Clk) of each register. It should be noted that registers 31 to 35 can constitute a register array 30.

[0043] See also Figure 3 In the delay lock mode, when the delay lock module reaches a stable state, the delay time of the delay link 10 is exactly one period T of the reference signal Clk_ref. At this time, the delay time of each delay unit is the same and is the basic delay time t d =T / 5.

[0044] In the time conversion mode, the delay unit 11 to the delay unit 15 sequentially delay the start signal Start, and the delay time (delay duration) of each delay unit is the basic delay time t d , and the output end of each delay unit outputs its delayed signal to the data input end D of the corresponding register, so that when the second signal input end receives the stop signal Stop, the register corresponding to the delay unit through which the start signal Start has passed can be flipped and output a valid signal, and then the basic delay time t of each delay unit can be calculated based on the number of registers that have been flipped (that is, the number of valid signals, the number of delay units that have delayed the start signal Start) and the basic delay time t of each delay unit. d To determine the signal time difference Δt=x*t between the start signal Start and the stop signal Stop d (x is the basic delay time t of the start signal Start being delayed step by step dThe number of registers that are flipped).

[0045] For example, when a stop signal Stop is input to the second signal input terminal, if the Q terminal of a certain register outputs a logic "1", it indicates that the start signal Start has passed through its corresponding delay unit. If the Q terminal of another register outputs a logic "0", it indicates that the start signal Start has not yet reached its corresponding delay unit. In this case, the aforementioned valid signal is a logic "1". In a specific example, registers 31 to 35 output 11100, indicating that the start signal Start has passed through the three delay levels of the three delay units (delay units 11 to 13) corresponding to registers 31, 32, and 33. At this time, the signal acquisition module can determine the signal time difference Δt = 3*t between the start signal Start and the stop signal Stop. d It should be noted that the valid signal can be a logic "1" or a logic "0", and the present disclosure does not impose any restrictions on this. In addition, in the embodiments of the present disclosure, the signal corresponding to the aforementioned valid signal is not an invalid signal. The different logical values ​​only indicate whether the start signal passes through the corresponding delay unit. The two are only different in meaning.

[0046] In some embodiments, the time-to-digital converter may further include a first selector 40, wherein the first input terminal and the second input terminal of the first selector 40 are respectively connected to the reference signal Clk_ref and the start signal Start, and the output terminal of the first selector 40 is the first signal input terminal; the first selector 40 is configured to: in the delay lock mode, output the reference signal Clk_ref to the delay lock module; in the time-to-digital conversion mode, output the start signal Start to the signal acquisition module.

[0047] In some embodiments, the first selector 40 may be a multi-way switch, which is a common circuit structure in the prior art. The present disclosure does not impose any restrictions on the specific circuit structure of the first selector. By providing the first selector 40, this embodiment enables the first signal input terminal to receive different signal inputs in different operating modes, thereby implementing delay lock and signal acquisition functions, simplifying circuit design, and improving integration.

[0048] By designing the time-to-digital converter unit as a structure in which the TDC and DLL / PLL share a delay link, the disclosed embodiments can avoid process mismatch issues caused by using two sets of delay links for the TDC and DLL / PLL. This overcomes the problem of inaccurate quantization accuracy of the time-to-digital converter caused by process mismatch in related technologies, ensuring that the quantization accuracy of the time-to-digital converter is unaffected by process P, voltage V, and temperature T (i.e., the time-to-digital converter has PVT stability). Furthermore, the shared delay link between the TDC and DLL / PLL can streamline circuit design, improve chip integration, and reduce manufacturing costs.

[0049] It should be understood that the above description focuses on the specific structure of a single time-to-digital conversion unit. In some multi-channel TDC application areas, such as laser ranging, medical imaging, automated semiconductor testing, high-energy physics experiments, mass spectrometry, quantum communication experiments, and automotive multi-line lidar, the time-to-digital converter in the disclosed embodiments may include multiple of these time-to-digital conversion units.

[0050] In some embodiments, the time-to-digital converter includes at least a first time-to-digital conversion unit and a second time-to-digital conversion unit, the first time-to-digital conversion unit and the second time-to-digital conversion unit include a common delay locking module, the first time-to-digital conversion unit includes a first signal acquisition module, and the second time-to-digital conversion unit includes a second signal acquisition module; the first signal acquisition module and the second signal acquisition module are configured to: in the time-to-digital conversion mode, collect signals in time-sharing manner.

[0051] It should be noted that when the time-to-digital converter includes multiple time-to-digital conversion units, each of these units has the same structure and operating principle as the unit in the aforementioned embodiment. The delay lock module and signal acquisition module contained in each unit also have the same structure and operating principle as those in the aforementioned embodiment. This embodiment differs from the aforementioned embodiment solely in the duplication or reuse of certain modules or electrical components. The following detailed description of the disclosed embodiment is provided with reference to the accompanying diagrams.

[0052] Figure 5 A schematic diagram of the structure of the time-to-digital converter provided in the embodiment of the present disclosure Figure 3 . Figure 5 Take the time-to-digital converter including two time-to-digital conversion units as an example for explanation, see Figure 5 In the delay locking mode, the shared delay locking module can only lock the basic delay time of the delay link once, and then in the time-to-digital conversion mode, the first signal acquisition module and the second signal acquisition module can respectively collect signals according to this basic delay time in different measurement time periods to determine the signal time difference.

[0053] In some embodiments, the first signal acquisition module and the second signal acquisition module may measure the signal time difference of signals in different areas within different measurement time periods.

[0054] Specifically, during a first measurement period in the hour-to-digital conversion mode, the first signal acquisition module can measure a signal time difference Δt1 between the first start signal Start and the first stop signal Stop1. During a second measurement period in the hour-to-digital conversion mode, the second signal acquisition module can measure a signal time difference Δt2 between the second start signal Start and the second stop signal Stop2.

[0055] In some embodiments, the first signal acquisition module and the second signal acquisition module include a common delay link 10, the first signal acquisition module also includes a first register array 30a, and the second signal acquisition module also includes a second register array 30b; the time-to-digital converter also includes a second switching circuit 50, the input end of the second switching circuit 50 is coupled to the delay link 10, and the first output end and the second output end of the second switching circuit 50 are respectively connected to the data input end of the first register array 30a and the data input end of the second register array 30b; the second switching circuit 50 is configured to: in the time-to-digital conversion mode, time-share the connection between the delay link 10 and the data input end of the first register array 30a and the connection between the delay link 10 and the data input end of the second register array 30b.

[0056] See also Figure 5 , the second signal input terminal may include a first sub-signal input terminal and a second sub-signal input terminal to transmit different stop signals to the clock input terminals of different register arrays. The first register array 30a and the delay link 10 may constitute a first signal acquisition module, and the second register array 30b and the delay link 10 may constitute a second signal acquisition module. Among them, the clock input terminal of the first register array 30a is connected to the first sub-signal input terminal to receive the first stop signal Stop1, and the clock input terminal of the second register array 30b is connected to the second sub-signal input terminal to receive the second stop signal Stop2. It should be noted that, Figure 5 The time-to-digital converter including two register arrays is merely an exemplary description, and the embodiment of the present disclosure does not impose any limitation on the number of register arrays.

[0057] During the first measurement period in the time-to-digital conversion mode, the second switch circuit 50 can conduct the connection between the delay link 10 and the data input terminal of the first register array 30a, and the delay link 10 can receive the first start signal Start. The delay link 10 delays the first start signal Start. When the first register array 30a receives the first stop signal Stop1, the first start signal Start in the delay link 10 is delayed step by step by a basic delay time td The number x of valid signals output by the register that generates the flip is collected to obtain the signal time difference Δt1 between the first start signal Start and the first stop signal Stop1.

[0058] During the second measurement period in the time-to-digital conversion mode, the second switch circuit 50 can conduct the connection between the delay link 10 and the data input terminal of the second register array 30b, and the delay link 10 can receive the second start signal Start. The delay link 10 delays the second start signal Start. When the second register array 30b receives the second stop signal Stop2, the basic delay time t of the second start signal Start in the delay link 10 is gradually delayed. d The number x of samples is collected to obtain the signal time difference Δt2 between the second start signal Start and the second stop signal Stop2.

[0059] In some embodiments, the delay link 10 may include delay units 11 to 15, the second switch circuit 50 includes five second switches (second switches 51 to 55) corresponding to the delay units, the first register array 30a includes first registers 31a to 35a, and the second register array 30b includes second registers 31b to 35b. The input ends of the second switches 51 to 55 are respectively connected to the output ends of the delay units 11 to 15, the first output ends of the second switches 51 to 55 are respectively connected to the data input ends of the first registers 31a to 35a, and the second output ends of the second switches 51 to 55 are respectively connected to the data input ends of the second registers 31b to 35b. The number of second switches is the same as the number of delay units, and the number of output ends of the second switches is the same as the number of register arrays.

[0060] In the delay lock mode, the delay lock module reaches a stable state. At this time, the delay time of the delay link 10 is exactly locked to one period T of the reference signal Clk_ref. At this time, the delay time of each delay unit is the same and is the basic delay time t d .

[0061] During the first measurement period in the time-to-digital conversion mode, the second switch circuit 50 can connect the delay link 10 to the data input terminal of the first register array 30a. Delay units 11 through 15 sequentially delay the first start signal Start. This ensures that when the first sub-signal input terminal receives the first stop signal Stop1, the first register corresponding to the delay unit through which the first start signal Start has passed can flip and output a valid signal, thereby determining the signal time difference Δt1 between the first start signal Start and the first stop signal Stop1.

[0062] During the second measurement period in the time-to-digital conversion mode, the second switch circuit 50 can connect the delay link 10 to the data input terminal of the second register array 30b. Delay units 11 through 15 sequentially delay the second start signal Start. This ensures that when the second sub-signal input terminal receives the second stop signal Stop2, the second register corresponding to the delay unit through which the second start signal Start has passed can flip and output a valid signal, thereby determining the signal time difference Δt2 between the second start signal Start and the second stop signal Stop2.

[0063] In some embodiments, the delay locking module may only lock the basic delay time of the delay link once, and multiple signal acquisition modules respectively acquire signals according to the basic delay time in different measurement time periods to determine the signal time difference.

[0064] In the time-to-digital converter provided by the embodiments of the present disclosure, multiple time-to-digital conversion units may include a shared delay lock module, which not only enables the time-to-digital converter to have PVT stability, but also makes the circuit design of the multi-channel TDC more streamlined, improves integration, and effectively reduces manufacturing costs.

[0065] Figure 6 A schematic diagram of the structure of the time-to-digital converter provided in the embodiment of the present disclosure Figure 4 See also Figure 6The time-to-digital converter includes at least a first time-to-digital conversion unit and a second time-to-digital conversion unit; the first time-to-digital conversion unit includes a first signal acquisition module, and the second time-to-digital conversion unit includes a second signal acquisition module; the first signal acquisition module includes a first delay link 10c, and the second signal acquisition module includes a second delay link 10d; the first time-to-digital conversion unit and the second time-to-digital conversion unit include a common voltage modulation circuit 21 and a third switch circuit 24, the input end of the third switch circuit 24 is connected to the output end of the voltage modulation circuit 21, and the first output end and the second output end of the third switch circuit 24 are respectively connected to the control end of the first delay link 10c and the control end of the second delay link 10d; the third switch circuit 24 is configured to: in the delay lock mode, time-share the connection between the output end of the voltage modulation circuit 21 and the control end of the first delay link 10c and the connection between the output end of the voltage modulation circuit 21 and the control end of the second delay link 10d.

[0066] The first time-to-digital conversion unit and the second time-to-digital conversion unit may include a shared feedback link 20'. The feedback link 20' may include a voltage modulation circuit 21, a third switching circuit 24, a first voltage holding circuit 23c, and a second voltage holding circuit 23d. The first voltage holding circuit 23c corresponds to the first time-to-digital conversion unit, and the second voltage holding circuit 23d corresponds to the second time-to-digital conversion unit. The feedback link 20' uses different voltage holding circuits when working in different time-to-digital conversion units. The first output end of the third switching circuit 24 is connected to the input end of the first voltage holding circuit 23c, and the output end of the first voltage holding circuit 23c is connected to the control end of the first delay link 10c; the second output end of the third switching circuit 24 is connected to the input end of the second voltage holding circuit 23d, and the output end of the second voltage holding circuit 23d is connected to the control end of the second delay link 10d. It should be noted that, Figure 6 The inclusion of two signal acquisition modules in the time-to-digital converter is merely an example. The presently disclosed embodiments do not impose any restrictions on the number of signal acquisition modules. The third switching circuit may be a multi-way switch, with the third switching circuit having the same number of output terminals, the same number of voltage holding circuits, and the same number of signal acquisition modules. The number of delay units in the multiple delay chains may be the same or different.

[0067] In the embodiment of the present disclosure, the first hour conversion unit and the second hour conversion unit can enter the delayed locking mode in different time periods (the delayed locking modes of the two different time periods can be respectively recorded as the first delayed locking mode and the second delayed locking mode), and can enter the hour conversion mode at the same time. Figure 6In the first delay lock mode, the third switch circuit 24 can connect the output end of the voltage modulation circuit 21 to the control end of the first delay chain 10c, so that the voltage modulation circuit 21 can compare the phase difference and frequency difference between the reference signal Clk_ref (with a period of T) and the output signal Clk_ref_delay of the first delay chain 10c, and accordingly adjust the control signal of the control end of the delay chain 10c to Vctrl, so that the phase difference and frequency difference between the reference signal Clk_ref and the output signal Clk_ref_delPay of the delay chain 10c are zero. At this time, the delay time of the first delay chain 10c is exactly one period T of the reference signal Clk_ref, thereby locking the first basic delay time t of the delay chain 10c. d1 .

[0068] In the second delay lock mode, the third switch circuit 24 can conduct the connection between the output end of the voltage modulation circuit 21 and the control end of the second delay chain 10d, so that the voltage modulation circuit 21 can compare the phase difference and frequency difference between the reference signal Clk_ref (with a period of T) and the output signal Clk_ref_delay of the second delay chain 10d, and accordingly adjust the control signal of the control end of the delay chain 10d to Vctrl, so that the phase difference and frequency difference between the reference signal Clk_ref and the output signal Clk_ref_delay of the delay chain 10d are zero. At this time, the delay time of the second delay chain 10d is exactly one period T of the reference signal Clk_ref, thereby locking the second basic delay time t of the delay chain 10d. d2 .

[0069] It should be noted that the reference signals in the first delay lock mode and the second delay lock mode can be the same or different, and can be set as needed. When the reference signals in the first delay lock mode and the second delay lock mode are different (the period T is different), the control voltage Vctrl of the delay link 10c and the delay link 10d may also be different, and the first basic delay time t d1 With the second basic delay time t d2 In addition, the number of delay units in the first delay link 10c and the number of delay units in the second delay link 10d may be the same or different, and the present disclosure does not impose any limitation on this.

[0070] In some embodiments, the time-to-digital converter further includes a second selector 60, wherein the first input terminal and the second input terminal of the second selector 60 are respectively connected to the output terminal of the first delay link 10c and the output terminal of the second delay link 10d, and the output terminal of the second selector 60 is connected to the input terminal of the voltage modulation circuit 21; the second selector 60 is configured to: in the delay lock mode, time-share the connection between the input terminal of the voltage modulation circuit 21 and the output terminal of the first delay link 10c and the connection between the input terminal of the voltage modulation circuit 21 and the output terminal of the second delay link 10d.

[0071] See also Figure 6 In the first delay lock mode, the second selector 60 can connect the input of the voltage modulation circuit 21 (specifically, the second input of the voltage modulation circuit) to the output of the first delay chain 10c. In the second delay lock mode, the second selector 60 can connect the input of the voltage modulation circuit 21 to the output of the second delay chain 10d. The second selector 60 can be a multi-way switch.

[0072] In the time-to-digit conversion mode, the third switch circuit 24 can disconnect the output of the voltage modulation circuit 21 from the control terminal of the first delay link 10c by disconnecting the output of the voltage modulation circuit 21 from the input of the first voltage holding circuit 23c, and disconnect the output of the voltage modulation circuit 21 from the control terminal of the second delay link 10d by disconnecting the output of the voltage modulation circuit 21 from the input of the second voltage holding circuit 23d. The first voltage holding circuit 23c can maintain the control signal Vctrl at the control terminal of the first delay link 10c unchanged, and the second voltage holding circuit 23d can maintain the control signal Vctrl at the control terminal of the second delay link 10d unchanged.

[0073] In the time conversion mode, the first selector 40 can output the start signal Start to the first signal acquisition module and the second signal acquisition module, and the first delay chain 10c and the second delay chain 10d respectively delay the start signal Start. When the first signal acquisition module receives the first stop signal Stop3, the first basic delay time t d1 The number x of samples is collected to obtain the signal time difference Δt1 between the start signal Start and the first stop signal Stop3; when the second signal acquisition module receives the second stop signal Stop4, the second basic delay time t of the start signal Start in the second delay link 10d is gradually delayed d2 The number x of samples is collected to obtain the signal time difference Δt2 between the start signal Start and the second stop signal Stop4.

[0074] See also Figure 6 The time-to-digital converter can further include a fourth switch circuit, comprising a fourth switch 71 and a fourth switch 72. The output of fourth switch 71 is connected to the input of first delay link 10c; the output of fourth switch 72 is connected to the input of second delay link 10d. In delay lock mode and time-to-digital conversion mode, fourth switches 71 and 72 can be turned on simultaneously or in a time-sharing manner, as needed.

[0075] Specifically, in the time-delay lock mode, the fourth switch 71 and the fourth switch 72 can be turned on in a time-sharing manner or simultaneously. In both cases, the third switch circuit 24 needs to turn on the connection between the voltage modulation circuit 21 and the first voltage holding circuit 23c and the second voltage holding circuit 23d in a time-sharing manner, so that the first time-to-digit conversion unit and the second time-to-digit conversion unit can enter the time-delay lock mode in a time-sharing manner. When the fourth switch 71 and the fourth switch 72 are turned on in a time-sharing manner, if the fourth switch 71 is turned on, the third switch circuit 24 turns on the connection between the voltage modulation circuit 21 and the first voltage holding circuit 23c; if the fourth switch 72 is turned on, the third switch circuit 24 turns on the connection between the voltage modulation circuit 21 and the second voltage holding circuit 23d.

[0076] In the time conversion mode, the fourth switch 71 and the fourth switch 72 can be turned on at the same time. When the fourth switch 71 and the fourth switch 72 are both turned on, the first selector 40 can simultaneously output the start signal Start to the first delay link 10c and the second delay link 10d. When the first signal acquisition module receives the first stop signal Stop3, the first basic delay time t d1 The number x of samples is collected to obtain the signal time difference Δt1 between the start signal Start and the first stop signal Stop3; when the second signal acquisition module receives the second stop signal Stop4, the second basic delay time t of the start signal Start in the second delay link 10d is gradually delayed d2 The number x of signals is collected to obtain the signal time difference Δt2 between the start signal Start and the second stop signal Stop4. It should be noted that the fourth switch 71 and the fourth switch 72 can also be turned on in time-sharing mode. At this time, the start signal transmitted to the first delay link 10c and the start signal transmitted to the second delay link 10d can be different signals. In the embodiment of the present disclosure, multiple time-to-digital conversion units include a shared voltage modulation circuit and a third switching circuit, which can not only lock the basic delay time of multiple delay links respectively in different time periods, but also simplify the circuit to reduce manufacturing costs. Multiple signal acquisition modules can also collect signals simultaneously to determine multiple signal time differences, which can reduce measurement time and improve measurement efficiency.

[0077] Figure 7 A schematic diagram of the structure of the time-to-digital converter provided in the embodiment of the present disclosure Figure 5 See also Figure 7 The time-to-digital converter includes at least a first time-to-digital conversion unit and a second time-to-digital conversion unit; the first time-to-digital conversion unit includes a first delay locking module and a first signal acquisition module, and the first delay locking module and the first signal acquisition module include a common first delay link 10e; the second time-to-digital conversion unit includes a second delay locking module and a second signal acquisition module, and the second delay locking module and the second signal acquisition module include a common second delay link 10f; the time-to-digital converter is configured as follows: in the delay locking mode, the first delay locking module and the second delay locking module respectively and simultaneously lock the first basic delay time of the first delay link 10e and the second basic delay time of the second delay link 10f; in the time-to-digital conversion mode, the first signal acquisition module and the second signal acquisition module respectively and simultaneously acquire the output signal of the first delay link 10e and the output signal of the second delay link 10f.

[0078] The first and second time-to-digital conversion units each have their own delay lock module and signal acquisition module. It is understood that since there is no module reuse between the first and second time-to-digital conversion units, they can operate independently, i.e., the first and second time-to-digital conversion units can enter the delay lock mode or the time-to-digital conversion mode simultaneously or at different times.

[0079] In the delay locking mode, the first selector 40 can output the reference signal Clk_ref to the first delay locking module and the second delay locking module, so that the first delay locking module and the second delay locking module can respectively and simultaneously lock the first basic delay time t of the first delay link 10e. d1 and the second basic delay time t of the second delay link 10f d2 In the time conversion mode, the first selector 40 can output the start signal Start to the first signal acquisition module and the second signal acquisition module, and the first delay link 10e and the second delay link 10f respectively delay the start signal Start. When the first signal acquisition module receives the first stop signal Stop5, the first basic delay time t of the start signal Start in the first delay link 10e is gradually delayed. d1 The number x of samples is collected to obtain the signal time difference Δt1 between the start signal Start and the first stop signal Stop5; when the second signal acquisition module receives the second stop signal Stop6, the second basic delay time t of the start signal Start in the second delay link 10f is gradually delayed d2The number x of samples is collected to obtain the signal time difference Δt2 between the start signal Start and the second stop signal Stop6.

[0080] See also Figure 7 The time-to-digital converter may further include a fourth switch circuit, comprising fourth switches 71 and 72. The output of fourth switch 71 is connected to the input of first delay link 10e; the output of fourth switch 72 is connected to the input of second delay link 10f. It should be noted that the fourth switch circuit may be a field-effect transistor, a photoelectric switch, or another type of switch, and this disclosure is not limited thereto. In delay lock mode and time-to-digital conversion mode, fourth switches 71 and 72 may be turned on simultaneously or in a time-sharing manner, as needed.

[0081] Specifically, in the time-delay lock mode, the fourth switch 71 and the fourth switch 72 can be turned on in time-sharing or simultaneously, so that the first hour conversion unit and the second hour conversion unit can enter the time-delay lock mode in time-sharing or simultaneously.

[0082] In the time conversion mode, the fourth switch 71 and the fourth switch 72 can be turned on at the same time. When the fourth switch 71 and the fourth switch 72 are both turned on, the first selector 40 can output the start signal Start to the first delay chain 10e and the second delay chain 10f. When the first signal acquisition module receives the first stop signal Stop5, the first basic delay time t d1 The number x of samples is collected to obtain the signal time difference Δt1 between the start signal Start and the first stop signal Stop5; when the second signal acquisition module receives the second stop signal Stop6, the second basic delay time t of the start signal Start in the second delay link 10f is gradually delayed d2 The number x of samples is collected to obtain the signal time difference Δt2 between the start signal Start and the second stop signal Stop6. It should be noted that the fourth switch 71 and the fourth switch 72 can also be turned on in a time-sharing manner. In this case, the start signal transmitted to the first delay link 10e and the start signal transmitted to the second delay link 10f can be different signals.

[0083] The time-to-digital converter provided by the disclosed embodiments can include multiple time-to-digital conversion units, which can simultaneously lock the basic delay time of different delay links and simultaneously measure signal time differences. This time-to-digital converter not only meets the needs of different scenarios but also saves a lot of time.

[0084] The disclosed embodiments also provide a method for controlling a time-to-digital converter. The time-to-digital converter includes at least one time-to-digital conversion unit, which includes a delay lock module and a signal acquisition module. The delay lock module and the signal acquisition module share a common delay link. The time-to-digital converter has a delay lock mode and a time-to-digital conversion mode. The method includes: in the delay lock mode, locking the basic delay time of the delay link; in the time-to-digital conversion mode, acquiring the output signal of the delay link based on the basic delay time to determine the signal time difference.

[0085] Figure 8 This is a schematic diagram of the steps of a control method for a time-to-digital converter provided in an embodiment of the present disclosure. The control method can be applied to the time-to-digital converter in any of the above embodiments. That is, the time-to-digital converter includes at least one time-to-digital conversion unit, which includes a delay lock module and a signal acquisition module. The delay lock module and the signal acquisition module include a shared delay link. The time-to-digital converter has a delay lock mode and a time-to-digital conversion mode.

[0086] See also Figure 8 , the control method of the time-to-digital converter comprises the following steps:

[0087] Step 810: In the delay lock mode, lock the basic delay time of the delay link.

[0088] Step 820: In the time-to-digital conversion mode, the output signal of the delay link is collected according to the basic delay time to determine the signal time difference.

[0089] The embodiments of the present disclosure can implement a control method for a time-to-digital converter with excellent quantization precision and measurement accuracy.

[0090] The control method also includes: in the delay locking mode, generating a control signal of the delay link based on the reference signal of the first signal input end and the output signal of the delay link output end to lock the basic delay time; in the time-to-digital conversion mode, keeping the control signal of the control end of the delay link unchanged.

[0091] The control method further includes: collecting signals in a time-sharing manner in a time-to-digital conversion mode.

[0092] It should be noted that the above description of the control method for a time-to-digital converter is similar to the description of the aforementioned embodiment of the time-to-digital converter, and has similar beneficial effects as the embodiment of the time-to-digital converter. For technical details not disclosed in the embodiment of the control method for a time-to-digital converter disclosed herein, please refer to the description of the embodiment of the time-to-digital converter disclosed herein.

[0093] The present disclosure provides a time-to-digital converter and control method. The time-to-digital converter includes at least one time-to-digital conversion unit, which includes a delay lock module and a signal acquisition module. The delay lock module and the signal acquisition module share a common delay link. The time-to-digital converter has a delay lock mode and a time-to-digital conversion mode. In the delay lock mode, the delay lock module locks the basic delay time of the delay link. In the time-to-digital conversion mode, the signal acquisition module acquires the output signal of the delay link based on the basic delay time of the delay link to determine the signal time difference. In the time-to-digital converter provided by the present disclosure, the delay lock module and the signal acquisition module share a common delay link, which can effectively reduce manufacturing costs. It can also avoid the problem of inaccurate time quantization accuracy in the time-to-digital converter caused by the inconsistent basic delay times of the two delay links due to process mismatch when the delay lock module and the signal acquisition module each include two different delay links. Therefore, by having the delay lock module and the signal acquisition module share a common delay link, the problem of inaccurate quantization accuracy caused by the delay lock module and the signal acquisition module each using different delay links can be avoided, thereby improving the accuracy of measuring signal time differences.

[0094] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0095] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A time-to-digital converter, comprising at least one time-to-digital conversion unit, the time-to-digital conversion unit comprising a delay lock module and a signal acquisition module, the delay lock module and the signal acquisition module comprising a shared delay link, the time-to-digital converter having a delay lock mode and a time-to-digital conversion mode; In the delay locking mode, the delay locking module locks the basic delay time of the delay link; In the time-to-digital conversion mode, the signal acquisition module acquires the output signal of the delay link according to the basic delay time of the delay link to determine the signal time difference.

2. The time-to-digital converter according to claim 1, wherein: The delay locking module further includes a feedback link, wherein a first input end of the feedback link and an input end of the delay link are commonly coupled to the first signal input end, a second input end of the feedback link is coupled to an output end of the delay link, and an output end of the feedback link is coupled to a control end of the delay link; In which, the feedback link is configured as follows: in the delay locking mode, based on the reference signal of the first signal input end and the output signal of the delay link output end, a control signal of the delay link is generated to lock the basic delay time; in the time-to-digital conversion mode, the control signal of the control end of the delay link is kept unchanged.

3. The time-to-digital converter according to claim 2, wherein: The feedback link includes a voltage modulation circuit, a first switch circuit, and a voltage holding circuit connected in sequence, wherein the first input terminal and the second input terminal of the voltage modulation circuit are coupled to the first signal input terminal and the output terminal of the delay link respectively, the first switch circuit is connected to the output terminal of the voltage modulation circuit and the input terminal of the voltage holding circuit, and the output terminal of the voltage holding circuit is connected to the control terminal of the delay link; The first switching circuit is configured to: in the delay locking mode, connect the connection between the output end of the voltage modulation circuit and the input end of the voltage holding circuit; in the hour conversion mode, disconnect the connection between the output end of the voltage modulation circuit and the input end of the voltage holding circuit.

4. The time-to-digital converter according to claim 1, wherein: The delay link includes a plurality of cascaded delay units, and the signal acquisition module further includes a plurality of registers corresponding to the delay units; The data input terminal of each register is connected to the output terminal of the corresponding delay unit, and the clock input terminal of each register is connected to the second signal input terminal.

5. The time-to-digital converter according to claim 2, wherein: The time-to-digital converter further comprises a first selector, wherein a first input terminal and a second input terminal of the first selector are respectively connected to a reference signal and a start signal, and an output terminal of the first selector is the first signal input terminal; The first selector is configured to: output the reference signal to the delay locking module in the delay locking mode; and output the start signal to the signal acquisition module in the time-to-digit conversion mode.

6. The time-to-digital converter according to claim 1, wherein: The time-to-digital converter comprises at least a first time-to-digital conversion unit and a second time-to-digital conversion unit, wherein the first time-to-digital conversion unit and the second time-to-digital conversion unit include a common delay locking module, the first time-to-digital conversion unit includes a first signal acquisition module, and the second time-to-digital conversion unit includes a second signal acquisition module; The first signal acquisition module and the second signal acquisition module are configured to: acquire signals in time-sharing mode in the time-to-digital conversion mode.

7. The time-to-digital converter according to claim 6, wherein: The first signal acquisition module and the second signal acquisition module include the common delay link, the first signal acquisition module further includes a first register array, and the second signal acquisition module further includes a second register array; The time-to-digital converter further includes a second switch circuit, wherein an input terminal of the second switch circuit is coupled to the delay link, and a first output terminal and a second output terminal of the second switch circuit are connected to a data input terminal of the first register array and a data input terminal of the second register array, respectively; The second switch circuit is configured to: in the time-to-digital conversion mode, time-share the connection between the delay link and the data input terminal of the first register array and the connection between the delay link and the data input terminal of the second register array.

8. The time-to-digital converter according to claim 1, wherein: The time-to-digital converter comprises at least a first time-to-digital conversion unit and a second time-to-digital conversion unit; the first time-to-digital conversion unit comprises a first signal acquisition module, and the second time-to-digital conversion unit comprises a second signal acquisition module; the first signal acquisition module comprises a first delay link, and the second signal acquisition module comprises a second delay link; The first time-to-digit conversion unit and the second time-to-digit conversion unit include a common voltage modulation circuit and a third switch circuit, the input end of the third switch circuit is connected to the output end of the voltage modulation circuit, and the first output end and the second output end of the third switch circuit are respectively connected to the control end of the first delay link and the control end of the second delay link; The third switch circuit is configured to: in the delay lock mode, time-sharingly conduct the connection between the output end of the voltage modulation circuit and the control end of the first delay link and the connection between the output end of the voltage modulation circuit and the control end of the second delay link.

9. The time-to-digital converter according to claim 8, wherein: The time-to-digital converter further includes a second selector, wherein a first input terminal and a second input terminal of the second selector are respectively connected to an output terminal of the first delay link and an output terminal of the second delay link, and an output terminal of the second selector is connected to an input terminal of the voltage modulation circuit; The second selector is configured to: in the delay lock mode, time-share the connection between the input end of the voltage modulation circuit and the output end of the first delay link and the connection between the input end of the voltage modulation circuit and the output end of the second delay link.

10. The time-to-digital converter according to claim 1, wherein: The time-to-digital converter comprises at least a first time-to-digital conversion unit and a second time-to-digital conversion unit; the first time-to-digital conversion unit comprises a first delay lock module and a first signal acquisition module, the first delay lock module and the first signal acquisition module comprising a common first delay link; the second time-to-digital conversion unit comprises a second delay lock module and a second signal acquisition module, the second delay lock module and the second signal acquisition module comprising a common second delay link; The time-to-digital converter is configured such that: in the delay locking mode, the first delay locking module and the second delay locking module simultaneously lock the first basic delay time of the first delay link and the second basic delay time of the second delay link respectively; In the time-to-digital conversion mode, the first signal acquisition module and the second signal acquisition module respectively and simultaneously acquire the output signal of the first delay link and the output signal of the second delay link.

11. A method for controlling a time-to-digital converter, characterized in that: The time-to-digital converter includes at least one time-to-digital conversion unit, the time-to-digital conversion unit includes a delay locking module and a signal acquisition module, the delay locking module and the signal acquisition module include a common delay link, and the time-to-digital converter has a delay locking mode and a time-to-digital conversion mode; the method includes: In the delay lock mode, the basic delay time of the delay link is locked; in the time-to-digital conversion mode, the output signal of the delay link is collected according to the basic delay time to determine the signal time difference.

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