Memory system, host, electronic device, method of operating electronic device,

Abstract

The embodiment of the invention provides a memory system, a host, electronic equipment, an operation method of the electronic equipment and a computer readable storage medium, and the memory system comprises a memory device; the multi-mode circuit has a data calculation processing capability and is configured to provide main function service in a busy state and provide additional function service in an idle state; the main function service comprises a normal access operation for realizing the data stored in the memory device, and the additional function service comprises a computing service except the normal access operation for realizing the data stored in the memory device; and a processor coupled with the memory device and the multi-mode circuit and configured to control the memory device and the multi-mode circuit.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a memory system, a host, an electronic device and an operating method thereof, and a computer-readable storage medium. Background Art

[0002] At present, memory devices are widely used in various fields, including embedded systems such as computers and network interconnection devices, as well as voice, image, and data storage products such as digital cameras and digital recorders. Memory devices require memory controllers to manage their functions, such as error correction code (ECC) checking, bad block management, address mapping, wear leveling, etc. As the requirements of these products for memory continue to increase, the burden on memory controllers is also increasing, affecting the performance and efficiency of memory systems. Summary of the invention

[0003] According to a first aspect of an embodiment of the present application, a memory system is provided, comprising: a memory device; a multi-mode circuit, having data computing and processing capabilities, and configured to: provide a main function service when in a busy state, and to provide an additional function service when in an idle state; the main function service includes implementing normal access operations to data stored in the memory device, and the additional function service includes implementing computing services other than normal access operations to data stored in the memory device; a processor, coupled to the memory device and the multi-mode circuit, and configured to: control the memory device and the multi-mode circuit.

[0004] In the above solution, the multi-mode circuit includes at least one of the following: an encryption circuit, a decryption circuit, an error correction encoding circuit, an error correction decoding circuit, a data randomization encoding circuit or a data randomization decoding circuit.

[0005] In the above scheme, the multi-mode circuit includes an encryption circuit; the main function service includes encrypting and encoding important data in the stored data to obtain verification data; the verification data is used to verify whether the important data has been tampered with; the additional function service includes providing a computing service of a secure hash algorithm for the data to be processed.

[0006] In the above scheme, the processor is configured to: receive a first command, the first command indicating a query for the state of the multi-mode circuit; in response to the first command, feedback the state of the multi-mode circuit; and in response to the multi-mode circuit being in an idle state, receive a second command, the second command at least including configuration parameters corresponding to the additional functional service; the multi-mode circuit is configured to: in response to the second command, perform calculation processing according to the requirements of the configuration parameters; the processor is also configured to: receive a third command, the third command indicating a query for the calculation result; and in response to the third command, feedback the calculation result.

[0007] In the above solution, the processor is configured such that: the first command and / or the second command is implemented through commands of a Small Computer System Interface (SCSI) bus.

[0008] In the above solution, the processor is configured to: receive the third command through a read interface with a priority higher than a preset value; and feed back the calculation result through a task (TASK).

[0009] In the above solution, the memory device includes a three-dimensional NAND memory.

[0010] According to a second aspect of an embodiment of the present application, a host is provided, comprising: a host memory and a control unit coupled to the host memory; the control unit is configured to: send a first command, the first command indicating a query for a state of a multi-mode circuit in a memory system; receive feedback on the state of the multi-mode circuit; in response to feedback that the multi-mode circuit in the memory system is in an idle state, send a second command, the second command including at least configuration parameters corresponding to an additional functional service provided by the multi-mode circuit when idle; send a third command, the third command indicating a query for a calculation result corresponding to the additional functional service; and receive feedback on the calculation result.

[0011] In the above solution, the control unit is further configured to: send data to be processed in response to feedback that the multi-mode circuit is in an idle state.

[0012] According to a third aspect of an embodiment of the present application, an electronic device is provided, comprising: a host and a memory system coupled to the host; wherein the host is configured to: send a first command, the first command indicating a query of a state of a multi-mode circuit in the memory system; the memory system is configured to: in response to the first command, feedback the state of the multi-mode circuit; the host is further configured to: in response to feedback that the multi-mode circuit is in an idle state, send a second command, the second command at least including configuration parameters corresponding to an additional functional service provided by the multi-mode circuit when idle; the multi-mode circuit is configured to: in response to the second command, perform calculation processing on data to be processed according to the requirements of the configuration parameters; the host is further configured to: send a third command, the third command indicating a query of a calculation result corresponding to the additional functional service; the memory system is further configured to: in response to the third command, feedback the calculation result.

[0013] In the above solution, the multi-mode circuit includes at least one of the following: an encryption circuit, a decryption circuit, an error correction encoding circuit, an error correction decoding circuit, a data randomization encoding circuit or a data randomization decoding circuit.

[0014] In the above solution, the host is further configured to: send the data to be processed in response to the feedback of the idle state.

[0015] According to a fourth aspect of an embodiment of the present application, a method for operating an electronic device is provided, comprising: a host in the electronic device sends a first command; a memory system in the electronic device responds to the first command and feeds back a state of a multi-mode circuit in the memory system; the first command indicates a query of a state of the multi-mode circuit; the host sends a second command in response to feedback that the multi-mode circuit in the memory system is in an idle state; the multi-mode circuit in the memory system responds to the second command and performs calculation processing on data to be processed according to requirements of configuration parameters; the second command includes at least the configuration parameters corresponding to the additional functional service provided by the multi-mode circuit when idle; the host sends a third command, the third command indicating a query of a calculation result corresponding to the additional functional service; the memory system responds to the third command and feeds back the calculation result.

[0016] In the above solution, the multi-mode circuit includes at least one of the following: an encryption circuit, a decryption circuit, an error correction encoding circuit, an error correction decoding circuit, a data randomization encoding circuit or a data randomization decoding circuit.

[0017] According to a fifth aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the operating method as described in any one of the fourth aspects is performed.

[0018] The embodiment of the present application provides a memory system, a host, an electronic device and an operation method thereof, and a computer-readable storage medium, wherein the memory system includes: a memory device; a multi-mode circuit, which has data computing and processing capabilities and is configured to: provide a main function service when in a busy state, and provide an additional function service when in an idle state; the main function service includes implementing a normal access operation of data stored in the memory device, and the additional function service includes implementing a computing service other than the normal access operation of data stored in the memory device; a processor, coupled with the memory device and the multi-mode circuit, and configured to: control the memory device and the multi-mode circuit. In this way, by utilizing the additional function service provided by the multi-mode circuit in the memory controller when it is in an idle state, the computing burden of the processor in the memory controller is reduced, while the provision of the main function service by the multi-mode circuit is not affected, thereby improving the utilization rate of the multi-mode circuit and the performance and efficiency of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A block diagram of an electronic device provided in one embodiment of the present application;

[0020] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0021] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0022] Figure 3a A schematic diagram of the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present application;

[0023] Figure 3b A schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present application;

[0024] Figure 4 A cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present application;

[0025] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present application;

[0026] Figure 6 A block diagram of an electronic device provided for another embodiment of the present application;

[0027] Figure 7 A schematic diagram of a command interaction situation in an electronic device provided in an embodiment of the present application;

[0028] Figure 8 A schematic diagram of an implementation flow of an operating method of an electronic device provided in an embodiment of the present application;

[0029] Fig. 9 A block diagram of a computer-readable storage medium provided for one embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the embodiments of the present application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present application. The described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. It is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0032] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0034] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0037] In the related art, the memory controller not only manages the functions of the memory, but also needs to perform calculations on a large amount of data, which further increases the burden on the memory controller and is not conducive to improving the performance and efficiency of the memory system.

[0038] In view of this, embodiments of the present application provide a memory system, a host, an electronic device and an operating method thereof, and a computer-readable storage medium.

[0039] Figure 1 A block diagram of an electronic device provided in one embodiment of the present application. Figure 1As shown, according to the first aspect of an embodiment of the present application, a memory system is provided, the memory system 102 including: a memory device 104; a multi-mode circuit 1062, having data computing and processing capabilities, configured to: provide main function services when in a busy state, and provide additional function services when in an idle state; the main function services include implementing normal access operations to data stored in the memory device 104, and the additional function services include implementing computing services other than normal access operations to data stored in the memory device 104; a processor 1061, coupled to the memory device 104 and the multi-mode circuit 1062, and configured to: control the memory device 104 and the multi-mode circuit 1062.

[0040] exist Figure 1 In the present invention, the electronic device 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein.

[0041] like Figure 1 As shown in , the electronic device 100 includes a host 108 and a memory system 102 , wherein the memory system 102 has one or more memory devices 104 and a memory controller 106 .

[0042] It should be noted that the processor 1061 and the multi-mode circuit 1062 both belong to the memory controller 106. The processor 1061 is usually relied on to implement the memory controller 106's computing function for a large amount of data. The embodiment of the present application reduces the computing burden of the processor 1061 in the memory controller 106 by utilizing the additional functional services provided by the multi-mode circuit 1062 in the memory controller 106 when it is in an idle state, while not affecting the multi-mode circuit 1062 providing the main functional services, thereby improving the utilization rate of the multi-mode circuit and the performance and efficiency of the memory system.

[0043] In some embodiments, the processor in the memory controller may be a microcontroller unit (MCU).

[0044] In some embodiments, the host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104. Alternatively, the host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0045] Specifically, the memory device 104 may be any memory device disclosed in the present application, such as a three-dimensional NAND type memory. According to some embodiments, the memory controller 106 is also coupled to the host 108. The memory controller 106 may manage data stored in the memory device 104 and communicate with the host 108.

[0046] In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices in low duty cycle environments such as personal computers, digital cameras, mobile phones, etc.

[0047] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a Solid State Driver (SSD) or an embedded Multi Media Card (eMMC), where the SSD or eMMC is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. in high duty cycle environments, as well as enterprise storage arrays.

[0048] The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes regarding data read from the memory device 104 or written to the memory device 104.

[0049] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0050] The memory controller 106 and one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an eMMC package). That is, the electronic device 100 may be implemented and packaged into different types of terminal electronic products.

[0051] In such Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0052] Figure 3a A schematic diagram of the structure of a storage cell array of a three-dimensional NAND memory is given as an example. Figure 3a As shown, the memory cell array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cell rows parallel to the gate isolation structure, every two rows of memory cell rows are separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory cell array into a plurality of memory blocks (Blocks), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (Fingers), and the upper selection gate isolation structure disposed in the middle of each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a A storage block shown in FIG. 1 includes 6 storage slices. In actual applications, the number of storage slices in a storage block is not limited thereto.

[0053] In some embodiments, each memory block may be coupled to a plurality of word lines, and a plurality of memory cells coupled to each individually controlled word line constitute a page. For example, Figure 3a All memory cells in each memory slice are coupled to form a page.

[0054] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the present application is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present application. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0055] Figure 3b 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present application. The memory device 300 may be Figure 1300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as an example of a three-dimensional NAND-type memory cell array, wherein the memory cell 306 is a NAND-type memory cell, and the memory cell 306 is provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0056] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" may correspond to a first voltage range, and the second storage state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-bit memory cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a two-bit memory cell, Double-Level Cell), three bits per cell (also referred to as a three-bit memory cell (TLC, Trinary-Level Cell)), four bits per cell (also referred to as a four-bit memory cell (QLC, Quad-Level Cell)), five bits per cell (also referred to as a five-bit memory cell (PLC, Penta-level cell)), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLCs can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0057] like Figure 3bAs shown in , each memory string 308 may include a lower selection transistor 310 (also known as a source selection transistor, which includes a source selection gate BSG) at its source terminal and an upper selection transistor 312 (also known as a drain side selection transistor, which includes a drain selection gate TSG) at its drain terminal. The source selection transistor and the drain selection transistor can be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each storage string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having a TSG) or a deselection voltage (e.g., 0 V) ​​to a corresponding TSG via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having a BSG) or a deselection voltage (e.g., 0 V) ​​to a corresponding BSG via one or more BSG lines 315.

[0058] like Figure 3b As shown in , the memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by the read and program operations. In some embodiments, in combination with the previous Figure 3a, multiple memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and multiple memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure. Among them, the memory cells in the memory slice sharing the same word line form a physical page 320, and each physical page 320 can be mapped to at least one logical page according to the storage mode of the corresponding memory cell 306 (for example, SLC or MLC as mentioned above), and the logical page can constitute the basic data unit of the programming operation and the reading operation.

[0059] refer to Figure 3a , Figure 3b Each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (eg, top selection transistor (TSG)).

[0060] Figure 4 FIG. 3 is a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 using NAND as an example according to some aspects of the present application. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412, wherein the channel structure is coupled with each gate layer to form a memory cell, and the channel structure is coupled with a plurality of gate layers in the stacked structure 410 to form a memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412.

[0061] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0062] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0063] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0064] Return to reference Figure 3b , the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface (Interface, I / F) 516 and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0065] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store the program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306, and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0066] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0067] The control logic 512 may be coupled to each of the other parts in the peripheral circuits described above, and is configured to control the operation of each of the other parts in the peripheral circuits. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0068] Next, the focus is on the multi-mode circuit 1062. The multi-mode circuit 1062 has two different working modes: one working mode is to provide main function services when in a busy state, and the main function services include implementing normal access operations for data stored in the memory device 104; the other working mode is to provide additional function services when in an idle state, and the additional function services include computing services other than the normal access operations for data stored in the memory device 104.

[0069] In some embodiments, the multi-mode circuit 1062 includes at least one of the following: an encryption circuit, a decryption circuit, an error correction encoding circuit, an error correction decoding circuit, a data randomization encoding circuit, or a data randomization decoding circuit.

[0070] A multi-mode circuit (such as an encryption circuit, a decryption circuit, an error correction coding circuit, an error correction decoding circuit, a data randomization coding circuit or a data randomization decoding circuit, etc.) is usually a specific functional circuit used to achieve specific data security, data integrity or data reliability requirements. Since not all usage scenarios require these requirements to be achieved, the multi-mode circuit will be in an idle state when there are no such requirements. It is understandable that the main function utilization of the multi-mode circuit is greatly reduced due to the limitation of specific requirements.

[0071] It is understandable that among the above-mentioned circuits, the encryption circuit used to encrypt important data in the stored data has the most special application scenario (only a small amount of the accessed data is important data, and the encryption circuit and decryption circuit are needed for the important data), so its main function utilization is the lowest. Based on this, if the additional functions of the circuit with the lowest main function utilization can be developed and used to the maximum extent, the effective utilization of the multi-mode circuit will be greatly improved.

[0072] In some embodiments, the multi-mode circuit 1062 includes an encryption circuit; the main function service includes encrypting and encoding important data in the stored data to obtain verification data; the verification data is used to verify whether the important data has been tampered with; the additional function service includes providing a computing service of a secure hash algorithm for the data to be processed.

[0073] In some specific embodiments, the storage area of ​​the three-dimensional NAND memory is divided into four categories, including a user data area (UDA), a replay protected memory block (RPMB), a boot area partition (Boot Area Partition) and a general purpose partition (GPP). Among them, the user data area is usually the largest partition in the eMMC and is the most important storage area in the actual product. The user data area mainly stores data generated during daily use by users, such as photos, recordings, logs, etc. The boot area partition is mainly used to store the boot program (Bootloader). Bootloader is a small program that runs before the operating system kernel runs. Through this small program, the hardware device can be initialized and a mapping of the memory space can be established, so as to bring the system's hardware and software environment to a suitable state, so as to prepare the correct environment for the final call to the operating system kernel. The general partition is mainly used to store system and application data.

[0074] The replay protection memory block partition is a partition with security features. When writing data to RPMB, the legitimacy of the data will be verified, and only the designated host can write. In practical applications, RPMB is usually used to store some important data that needs to be prevented from illegal tampering, such as public keys and serial numbers related to fingerprint payment.

[0075] Before storing these important data in RPMB, the encryption unit will first encrypt the important data in the data to be stored to obtain verification data. Exemplarily, the host and the three-dimensional NAND memory share a key, and before the host sends the important data in the data to be stored to the three-dimensional NAND memory, the key and the secure hash algorithm (Secure Hash Algorithm, SHA) will be used to generate a message authentication code (Message Authentication Code, MAC). The host sends the important data in the data to be stored together with the MAC to the three-dimensional NAND memory. The three-dimensional NAND memory recalculates the MAC for the important data in the data to be stored and the shared key, and then compares the calculated MAC with the received MAC. If they are consistent, the authentication is successful, and the important data in the data to be stored is written into RPMB, otherwise the writing of the data will be rejected.

[0076] Since the verification data is calculated based on the original data, once the data is tampered with, the verification data will also change accordingly, so that it is possible to verify whether the important data has been tampered with based on the verification data.

[0077] In some embodiments, the verification data is a message authentication code, which is used to verify the integrity of the data to determine whether the data has been tampered with during storage or transmission.

[0078] In some embodiments, the secure hash algorithm includes but is not limited to the SHA160 algorithm, the SHA256 algorithm, and the SHA512 algorithm.

[0079] In other embodiments, the additional functional service includes providing computing services including but not limited to symmetric algorithms (Symmetric Algorithm) and asymmetric algorithms (Asymmetric Algorithm) for the data to be processed.

[0080] Exemplarily, the multi-mode circuit 1062 may also include a decryption circuit; the main functional services include decrypting and decoding encrypted data and verifying whether the accessor has the right to access the encrypted data to ensure that authorized users or applications access and use the data when needed; additional functional services include providing computing services of a secure hash algorithm for the data to be processed.

[0081] It should be noted that the design and implementation of the decryption circuit needs to match the encryption algorithm used. Different applications and systems may use different encryption algorithms, so the specific implementation of the decryption circuit may be different.

[0082] In some embodiments, the additional functional services provided by the decryption circuit include providing calculation services including but not limited to SHA160 algorithm, SHA256 algorithm and SHA512 algorithm for the data to be processed.

[0083] In other embodiments, the additional functional services provided by the decryption circuit include providing computing services including but not limited to symmetric algorithms and asymmetric algorithms for the data to be processed.

[0084] Exemplarily, the multi-mode circuit 1062 may also include an error correction coding circuit; the main functional service includes encoding the data to be stored to obtain verification data; the verification data is used to detect and correct possible errors during data transmission; the additional functional service includes providing computing services for logical operations on the data to be processed, wherein the logical operations include but are not limited to: exclusive OR (XOR) operation, AND (AND) operation, OR (OR) operation, NOT (NOT) operation, and logical shift operation.

[0085] Exemplarily, the multi-mode circuit 1062 may also include an error correction decoding circuit; the main functional service includes decoding the received or read data, obtaining verification data corresponding to the verification data generated by the error correction coding circuit, so as to verify whether the received or read data is consistent with the data encoded when it was sent; the additional functional service includes providing computing services for providing logical operations for the data to be processed, wherein the logical operations include but are not limited to: exclusive OR (XOR) operation, AND (AND) operation, OR (OR) operation, NOT (NOT) operation, and logical shift operation.

[0086] Exemplarily, the multi-mode circuit 1062 may also include a data randomization encoding circuit; the main functional service includes randomizing the original data during data transmission or storage to enhance data security, reduce the risk of unauthorized access to data, and protect against malicious attacks and data leakage threats, that is, even if an attacker intercepts the encoded data in time, it is difficult to restore the original information; the additional functional service includes a computing service that provides logical operations on the data to be processed, where the logical operations include but are not limited to exclusive OR (XOR) operations.

[0087] Exemplarily, the multi-mode circuit 1062 may also include a data randomization decoding circuit; the main functional service includes decoding the data that has been data randomized and restoring it to the form of original data for subsequent processing and use; the additional functional service includes a computing service that provides logical operations for the data to be processed, wherein the logical operations include but are not limited to exclusive OR (XOR) operations.

[0088] It should be noted that the data randomization decoding circuit is usually used in conjunction with the data randomization encoding circuit to ensure that during the data transmission or storage process, the randomly encoded data can be correctly restored to the original data while maintaining the security and integrity of the data.

[0089] In some embodiments, the processor is configured to: receive a first command, the first command indicating a query for the state of the multi-mode circuit; in response to the first command, feedback the state of the multi-mode circuit; and in response to the multi-mode circuit being in an idle state, receive a second command, the second command including at least configuration parameters corresponding to the additional functional service; the multi-mode circuit is configured to: in response to the second command, perform calculation processing according to the requirements of the configuration parameters; the processor is also configured to: receive a third command, the third command indicating a query for the calculation result; and in response to the third command, feedback the calculation result.

[0090] In order not to affect the main function service of the multi-mode circuit, it is necessary to query the state of the multi-mode circuit and decide whether to use its additional function service according to the state of the multi-mode circuit. The processor is configured to query the state of the multi-mode circuit in response to the first command and feedback the state of the multi-mode circuit to an external device (such as a host).

[0091] When the multi-mode circuit is in an idle state, the multi-mode circuit is configured to respond to the second command and perform calculation processing according to the requirements of the configuration parameters.

[0092] The configuration parameters include but are not limited to the algorithm mode, the number of algorithm cycles, and initialization data.

[0093] In some embodiments, the algorithm mode in the configuration parameters is related to the type of the multi-mode circuit. For example, when the multi-mode circuit is an encryption circuit, the algorithm mode may be a secure hash algorithm. When the multi-mode circuit is an error correction coding circuit, the algorithm mode may be a logical shift algorithm.

[0094] Figure 6 This is a block diagram of an electronic device provided by another embodiment of the present application. Figure 6 As shown, the electronic device 100 includes a host 108 and a memory system 102, wherein the memory system 102 has one or more memory devices 104 and a memory controller 106. The memory controller 106 includes a processor 1061, a multi-mode circuit 1062, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, a front-end interface 1067, and a back-end interface 1068.

[0095] The front-end interface 1067 is a connection interface between the host 108 and the memory controller 106. The front-end interface 1067 allows the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The back-end interface 1068 is a connection interface between the memory controller 106 and the memory device 104. The back-end interface 1068 allows data to be transmitted between the memory controller 106 and the memory device 104.

[0096] ROM 1069 typically contains firmware or firmware program code for memory controller 106, which is used to initialize and operate various components of the memory controller, and RAM 1070 is typically used to cache data.

[0097] The multi-mode circuit 1062 includes an encryption circuit 1063, a decryption circuit 1064, an error correction coding circuit 1065, and an error correction decoding circuit 1066. The main functional service of the encryption circuit 1063 includes encrypting and encoding important data in the data to be stored to obtain verification data; the verification data is used to verify whether the important data has been tampered with; the main functional service of the decryption circuit 1064 includes decrypting and decoding the encrypted data, and verifying whether the visitor has the right to access the encrypted data to ensure that the authorized user or application program can access and use the data when needed; the additional functional services of the encryption circuit 1063 and the decryption circuit 1064 include providing a computing service of a secure hash algorithm for the data to be processed.

[0098] The main functional services of the error correction coding circuit 1065 include encoding the data to be stored and obtaining verification data; the verification data is used to detect and correct possible errors during data transmission; the main functional services of the error correction decoding circuit 1066 include decoding the received or read data and obtaining verification data corresponding to the verification data generated by the error correction coding circuit to verify whether the received or read data is consistent with the data encoded when it was sent; the additional functional services of the error correction coding circuit 1065 and the error correction decoding circuit 1066 include providing computing services for logical operations on the data to be processed, wherein the logical operations include but are not limited to: exclusive OR (XOR) operation, AND (AND) operation, OR (OR) operation, NOT (NOT) operation, and logical shift operation.

[0099] like Figure 6 As shown, the various components of the memory controller 106 may be connected to a bus 1071 .

[0100] It should be noted that when the multi-mode circuit includes multiple circuits such as an encryption circuit, a decryption circuit, an error correction coding circuit, and an error correction decoding circuit, the processor is configured to query the status of all circuits in the multi-mode circuit in response to the first command, and feed back the status of the above multiple circuits to an external device (such as the host 108). The algorithm mode in the configuration parameter may include an algorithm mode corresponding to one of the above multiple circuits in an idle state.

[0101] In some embodiments, the processor is further configured to feed back the calculation result obtained by the calculation service of the additional function of the multi-mode circuit to an external device (e.g., a host) in response to the third command. Specifically, the processor reads the calculation result in the multi-mode circuit and transmits it to the external device.

[0102] It should be noted that when the multi-mode circuit is providing additional functional services, if an external device sends a request instructing the multi-mode circuit to provide a main functional service, for example, the external device sends a request to write important data to the memory device, the multi-mode circuit will suspend the provision of additional functional services and give priority to providing the main functional service. During the provision of the main functional service, the additional functional service is in a waiting state or is completed by other parts (such as a processor). In this way, the embodiment of the present application reduces the computational burden of the processor in the memory controller by utilizing the additional functional services provided when the multi-mode circuit in the memory controller is in an idle state, while not affecting the provision of the main functional service by the multi-mode circuit, thereby improving the utilization rate of the multi-mode circuit and the performance and efficiency of the memory system.

[0103] In other embodiments, the multi-mode circuit and the processor can perform computing services simultaneously. It is understandable that in order to speed up the memory controller's calculation of a large amount of data, computing services for a portion of the data are provided by the processor, and computing services for another portion of the data are provided by the multi-mode circuit. In this way, the speed of computing services is greatly improved and the burden on the processor is reduced.

[0104] In some embodiments, the processor is configured such that: the first command and / or the second command is implemented via a command of a small computer system interface SCSI bus.

[0105] The SCSI interface is a computer peripheral device connection standard used to connect and manage external devices. On the one hand, the SCSI interface allows multiple devices to be connected to the same SCSI bus. Each device has a unique SCSI address, so the SCSI interface can connect multiple devices at the same time without the need for multiple independent interfaces. On the other hand, SCSI defines a set of standard command sets that allow the host to communicate with the connected devices by issuing commands and perform various operations (such as reading, writing, etc.).

[0106] By utilizing the SCSI interface of the memory system itself to realize the transmission of the first command and / or the second command, no additional interface and hardware settings are required, which helps to simplify the system architecture and reduce possible compatibility and integration problems. In addition, utilizing the existing SCSI interface can improve the efficiency and speed of data transmission. Furthermore, the cost of adding a new interface, including hardware design, production and maintenance costs, is avoided, thereby improving efficiency and reducing costs.

[0107] In some embodiments, the processor is configured to: receive the third command through a read interface with a priority higher than a preset value; and feed back the calculation result through a task TASK.

[0108] In some embodiments, the processor manages the execution order of different tasks or operations through priority control. Exemplarily, the processor is configured to have different priority levels, and the priority of the read operation of the query calculation result is set to be higher than the preset value. Therefore, the processor will receive the third command through the read interface with a priority higher than the preset value, and give priority to the read operation of the query calculation result.

[0109] The task TASK allows the processor to process other tasks in the background while executing a task, that is, the processor can process other tasks in the background while executing the task of querying the calculation result after receiving the third command, without having to wait for the calculation result to be queried before executing other tasks. In this way, the efficiency and responsiveness of the system can be improved.

[0110] like Figure 1 As shown, according to the second aspect of an embodiment of the present application, a host is provided, the host 108 comprising: a host memory 1082 and a control unit 1081 coupled to the host memory 1082; the control unit 1081 is configured to: send a first command, the first command indicating a query of a state of a multi-mode circuit in a memory system; receive feedback of the state of the multi-mode circuit; in response to feedback that the multi-mode circuit in the memory system is in an idle state, send a second command, the second command including at least configuration parameters corresponding to additional functional services provided by the multi-mode circuit when idle; send a third command, the third command indicating a query of a calculation result corresponding to the additional functional service; receive feedback of the calculation result.

[0111] Here, the structure of the host refers to the aforementioned Figure 1 , I will not go into details here.

[0112] In order not to affect the main function service of the multi-mode circuit, the control unit 1081 of the host 108 needs to query the state of the multi-mode circuit and decide whether to use its additional function service according to the received state of the multi-mode circuit. The control unit 1081 is configured to send a first command to query the state of the multi-mode circuit and receive feedback on the state of the multi-mode circuit.

[0113] In some embodiments, the control unit 1081 is configured to send a second command in response to feedback that the multi-mode circuit in the memory system is in an idle state, where the second command includes at least configuration parameters corresponding to the additional functional service provided by the multi-mode circuit when idle.

[0114] In some embodiments, the control unit 1081 is further configured to: send data to be processed in response to feedback that the multi-mode circuit is in an idle state.

[0115] Exemplarily, the control unit 1081 may send the data to be processed before, simultaneously with, or after sending the second command in response to feedback that the multi-mode circuit is in an idle state, that is, the timing of sending the data to be processed is not restricted and can be selected according to actual conditions.

[0116] In a specific implementation, the control unit 1081 sends the data to be processed while sending the second command. In other words, the second command may include the data to be processed.

[0117] It should be noted that the data to be processed can be understood as the data to be calculated.

[0118] In some embodiments, the configuration parameters include, but are not limited to, the algorithm mode, the number of algorithm loops, and initialization data.

[0119] In some embodiments, the algorithm mode in the configuration parameters is related to the type of the multi-mode circuit. For example, when the multi-mode circuit is an encryption circuit, the algorithm mode may be a secure hash algorithm. When the multi-mode circuit is an error correction coding circuit, the algorithm mode may be a logical shift algorithm.

[0120] In some embodiments, the control unit 1081 is configured to query the calculation result corresponding to the additional function service in response to sending the third command and receive feedback of the calculation result. Specifically, the processor reads the calculation result in the multi-mode circuit, and the control unit 1081 receives feedback of the processor on the calculation result.

[0121] Based on the above host and memory system, the present application embodiment also provides an electronic device, referring to Figure 7 , Figure 7 A schematic diagram of a command interaction situation in an electronic device provided in an embodiment of the present application; Figure 7As shown, according to a third aspect of an embodiment of the present application, an electronic device is provided, comprising: a host and a memory system coupled to the host; wherein the host is configured to: send a first command, the first command indicating a query of a state of a multi-mode circuit in the memory system; the memory system is configured to: in response to the first command, feedback the state of the multi-mode circuit; the host is further configured to: in response to feedback that the multi-mode circuit is in an idle state, send a second command, the second command at least including configuration parameters corresponding to an additional functional service provided by the multi-mode circuit when idle; the multi-mode circuit is configured to: in response to the second command, perform calculation processing on the data to be processed according to the requirements of the configuration parameters; the host is further configured to: send a third command, the third command indicating a query of a calculation result corresponding to the additional functional service; the memory system is further configured to: in response to the third command, feedback the calculation result.

[0122] The structure of the electronic device can refer to the relevant description in the above embodiments, which will not be repeated here.

[0123] It should be noted that Figure 1 The solid arrows in show the instruction interaction path in the electronic device when the multi-mode circuit provides the main function service. Figure 1 The dashed arrows in FIG. 1 show instruction interaction paths in the multi-mode circuit providing additional functional service electronic device.

[0124] In some embodiments, the multi-mode circuit 1062 includes at least one of the following: an encryption circuit, a decryption circuit, an error correction encoding circuit, an error correction decoding circuit, a data randomization encoding circuit, or a data randomization decoding circuit.

[0125] In some embodiments, the multi-mode circuit 1062 includes an encryption circuit; the main function service includes encrypting and encoding important data in the stored data to obtain verification data; the verification data is used to verify whether the important data has been tampered with; the additional function service includes providing a computing service of a secure hash algorithm for the data to be processed.

[0126] In some embodiments, the secure hash algorithm includes but is not limited to the SHA160 algorithm, the SHA256 algorithm, and the SHA512 algorithm.

[0127] In other embodiments, the additional functional services include providing computing services including but not limited to symmetric algorithms and asymmetric algorithms for the data to be processed.

[0128] Exemplarily, the multi-mode circuit 1062 includes an error correction coding circuit; the main functional service includes encoding the data to be stored to obtain verification data; the verification data is used to detect and correct possible errors during data transmission; the additional functional service includes providing computing services for logical operations on the data to be processed, wherein the logical operations include but are not limited to: exclusive OR (XOR) operation, AND (AND) operation, OR (OR) operation, NOT (NOT) operation, and logical shift operation.

[0129] In some embodiments, the host 108 is further configured to send data to be processed in response to the feedback of the idle state.

[0130] Exemplarily, the host 108 may send the data to be processed before, simultaneously with, or after sending the second command in response to feedback that the multi-mode circuit is in an idle state, that is, the timing of sending the data to be processed is not restricted and can be selected according to actual conditions.

[0131] In a specific implementation, the host 108 sends the data to be processed while sending the second command. In other words, the second command may include the data to be processed.

[0132] Figure 8 The present invention provides an electronic device operation method according to a fourth aspect of the present invention. Figure 7 and Figure 8 , the operating method of the electronic device specifically includes the following steps:

[0133] Step S10: The host in the electronic device sends a first command.

[0134] Step S20: the memory system in the electronic device responds to the first command and feeds back the state of the multi-mode circuit in the memory system; the first command indicates to query the state of the multi-mode circuit.

[0135] Step S30: the host sends a second command in response to the feedback that the multi-mode circuit in the memory system is in an idle state.

[0136] Step S40: the multi-mode circuit in the memory system responds to the second command and performs calculations on the data to be processed according to the requirements of the configuration parameters; the second command at least includes the configuration parameters corresponding to the additional functional services provided by the multi-mode circuit when idle.

[0137] Step S50: the host sends a third command, where the third command instructs to query the calculation result corresponding to the additional function service.

[0138] Step S60: the memory system responds to the third command and feeds back the calculation result.

[0139] In some embodiments, the first command and / or the second command are implemented through commands of a small computer system interface SCSI bus. The host and the memory system implement the transmission of the first command and / or the second command through the existing SCSI interface, which helps to simplify the structure, improve efficiency and reduce costs.

[0140] In some embodiments, the third command is transmitted through a read interface with a priority higher than a preset value; and the calculation result is fed back in the form of a task TASK.

[0141] Exemplarily, the priority of the read operation of querying the calculation result is set to be higher than a preset value. Therefore, the host and the memory system will receive the third command through the read interface with a priority higher than the preset value, and give priority to the transmission of the calculation result.

[0142] The task TASK mode allows the processor of the memory system to process other tasks in the background while executing a task, that is, the processor can process other tasks in the background while executing the task of querying the calculation result after receiving the third command, without having to wait for the calculation result to be queried before executing other tasks. In this way, the efficiency and responsiveness of the electronic device can be improved.

[0143] In some embodiments, the multi-mode circuit includes at least one of: an encryption circuit, a decryption circuit, an error correction encoding circuit, an error correction decoding circuit, a data randomization encoding circuit, or a data randomization decoding circuit.

[0144] In some embodiments, the multi-mode circuit 1062 includes an encryption circuit; the main function service includes encrypting and encoding important data in the stored data to obtain verification data; the verification data is used to verify whether the important data has been tampered with; the additional function service includes providing a computing service of a secure hash algorithm for the data to be processed.

[0145] In some embodiments, the secure hash algorithm includes but is not limited to the SHA160 algorithm, the SHA256 algorithm, and the SHA512 algorithm.

[0146] In other embodiments, the additional functional services include providing computing services including but not limited to symmetric algorithms and asymmetric algorithms for the data to be processed.

[0147] Exemplarily, the multi-mode circuit 1062 includes an error correction coding circuit; the main functional service includes encoding the data to be stored to obtain verification data; the verification data is used to detect and correct possible errors during data transmission; the additional functional service includes providing computing services for logical operations on the data to be processed, wherein the logical operations include but are not limited to: exclusive OR (XOR) operation, AND (AND) operation, OR (OR) operation, NOT (NOT) operation, and logical shift operation.

[0148] Fig. 9 A block diagram of a computer-readable storage medium provided for an embodiment of the present application. According to a fifth aspect of the present application, an embodiment of the present application provides a computer-readable storage medium, the computer-readable storage medium 800 storing a computer program 810, and the computer program 810 can implement the operation method of the electronic device in the above technical solution when executed by the processor. The operation method includes: a host in the electronic device sends a first command; a memory system in the electronic device responds to the first command and feeds back the state of the multi-mode circuit in the memory system; the first command indicates the query of the state of the multi-mode circuit; the host responds to the feedback that the multi-mode circuit in the memory system is in an idle state and sends a second command; the multi-mode circuit in the memory system responds to the second command and calculates and processes the data to be processed according to the requirements of the configuration parameters; the second command at least includes the configuration parameters corresponding to the additional function service provided by the multi-mode circuit when idle; the host sends a third command, the third command indicates the query of the calculation result corresponding to the additional function service; the memory system responds to the third command and feeds back the calculation result.

[0149] The methods disclosed in the method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0150] The features disclosed in several device embodiments provided in this application can be arbitrarily combined without conflict to obtain new device embodiments.

[0151] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0152] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the inventive concept of the present application, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A memory system, characterized in that: include: Memory device; The multi-mode circuit has data computing and processing capabilities and is configured to: provide a main function service when in a busy state, and provide an additional function service when in an idle state; the main function service includes implementing a normal access operation of data stored in the memory device, and the additional function service includes implementing a computing service other than the normal access operation of data stored in the memory device; A processor is coupled to the memory device and the multi-mode circuit and is configured to control the memory device and the multi-mode circuit.

2. The memory system according to claim 1, wherein: The multi-mode circuit includes at least one of the following: An encryption circuit, a decryption circuit, an error correction encoding circuit, an error correction decoding circuit, a data randomization encoding circuit or a data randomization decoding circuit.

3. The memory system according to claim 2, wherein: The multi-mode circuit includes an encryption circuit; The main function service includes encrypting and encoding important data in the stored data to obtain verification data; the verification data is used to verify whether the important data has been tampered with; The additional functional services include computing services that provide a secure hash algorithm for data to be processed.

4. The memory system according to any one of claims 1 to 3, characterized in that: The processor is configured to: receiving a first command, wherein the first command indicates to query a state of the multi-mode circuit; In response to the first command, feeding back a state of the multi-mode circuit; and In response to the multi-mode circuit being in an idle state, receiving a second command, the second command at least including a configuration parameter corresponding to the additional function service; The multi-mode circuit is configured to: In response to the second command, performing calculation processing according to requirements of the configuration parameters; The processor is further configured to: receiving a third command, wherein the third command instructs querying the calculation result; and In response to the third command, the calculation result is fed back.

5. The memory system according to claim 4, characterized in that: The processor is configured to: The first command and / or the second command is implemented through a command of a small computer system interface SCSI bus.

6. The memory system according to claim 4, characterized in that: The processor is configured to: receiving the third command through a read interface having a priority higher than a preset value; The calculation result is fed back in the form of a task TASK.

7. The memory system according to claim 1, wherein: The memory device comprises a three-dimensional NAND type memory.

8. A host, characterized in that: include: A host memory and a control unit coupled to the host memory; the control unit is configured to: Sending a first command, wherein the first command indicates to query a state of a multi-mode circuit in a memory system; receiving feedback of a state of the multi-mode circuit; In response to feedback that the multi-mode circuit in the memory system is in an idle state, sending a second command, wherein the second command at least includes configuration parameters corresponding to the additional functional service provided by the multi-mode circuit when idle; Sending a third command, wherein the third command instructs to query a calculation result corresponding to the additional function service; Feedback of the calculation result is received.

9. The host according to claim 8, characterized in that: The control unit is further configured to: In response to the feedback that the multi-mode circuit is in an idle state, data to be processed is sent.

10. An electronic device, characterized in that: include: A host and a memory system coupled to the host; wherein, The host is configured to: send a first command, wherein the first command indicates to query a state of the multi-mode circuit in the memory system; The memory system is configured to: in response to the first command, feedback the state of the multi-mode circuit; The host is further configured to: in response to feedback that the multi-mode circuit is in an idle state, send a second command, wherein the second command at least includes configuration parameters corresponding to the additional functional service provided by the multi-mode circuit when idle; The multi-mode circuit is configured to: in response to the second command, perform computational processing on the data to be processed according to the requirements of the configuration parameters; The host is further configured to: send a third command, wherein the third command indicates to query the calculation result corresponding to the additional function service; The memory system is further configured to: in response to the third command, feed back the calculation result.

11. The electronic device according to claim 10, characterized in that: The multi-mode circuit includes at least one of the following: An encryption circuit, a decryption circuit, an error correction encoding circuit, an error correction decoding circuit, a data randomization encoding circuit or a data randomization decoding circuit.

12. The electronic device according to claim 10, characterized in that: The host is also configured to: After responding to the feedback of the idle state, the data to be processed is sent.

13. A method for operating an electronic device, characterized in that: include: The host in the electronic device sends a first command; The memory system in the electronic device feeds back a state of a multi-mode circuit in the memory system in response to the first command; The first command indicates to query the state of the multi-mode circuit; The host sends a second command in response to feedback that the multi-mode circuit in the memory system is in an idle state; The multi-mode circuit in the memory system performs calculation processing on the data to be processed according to the requirements of the configuration parameters in response to the second command; the second command at least includes the configuration parameters corresponding to the additional functional service provided by the multi-mode circuit when idle; The host sends a third command, where the third command instructs to query a calculation result corresponding to the additional function service; The memory system feeds back the calculation result in response to the third command.

14. The operating method according to claim 13, characterized in that: The multi-mode circuit includes at least one of the following: An encryption circuit, a decryption circuit, an error correction encoding circuit, an error correction decoding circuit, a data randomization encoding circuit or a data randomization decoding circuit.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the operating method according to any one of claims 13 to 14 is performed.

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