Memory system and method of operating a memory system

Abstract

The present disclosure provides a memory system and a method of operating a memory system, the memory system being a memory system based on 3D NAND flash memory with high capacity and / or capable of high performance. The memory system includes memory planes, each of the memory planes including a plane core and a particular set of resources. For each of the plurality of memory planes, the technique provides a corresponding plane ready (PRDY) signal indicating a busy state or a ready state of the particular set of resources of the corresponding memory plane, and a corresponding plane in operation (PIO#) signal indicating an in-operation state or an idle state of a resource used by the plane core of the corresponding memory plane. Based on the state of one or more of the plurality of PRDY signals and the plurality of PIO# signals, the execution of a memory command for a memory plane of the plurality of memory planes and the issuance of the memory command by a controller are selectively allowed or denied.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to memory systems, and particularly to memories that support various types of memory operations. BACKGROUND

[0002] In recent years, memory arrays, such as non-volatile memory arrays, have become increasingly dense and can store relatively large amounts of data. Typically, a memory (e.g., a relatively high density memory) is divided into a plurality of physical segments, which can be referred to as memory planes. Thus, such a memory has a plurality of memory planes. Data stored in different planes can be unrelated (or can be related).

[0003] A challenge in such multi-plane memories is to provide overlapping access to different planes to a host. However, conventional memory operation command protocols typically prohibit issuing new embedded operation commands to non-operating planes, e.g., until a current embedded operation is completed or operating in the background in the operating plane. SUMMARY

[0004] The present disclosure describes a memory technology (system) that supports multiple memory planes. Each memory plane includes a plane core and a corresponding set of specific resources, each of the memory planes operable to (i) perform foreground operations using at least one of the corresponding set of specific resources of the corresponding memory plane and resources of the plane core of the corresponding memory plane and (ii) perform background operations using resources of the plane core of the corresponding memory plane. The memory further includes an input / output (I / O) interface to receive memory commands from a host addressed to one or more of the multiple memory planes, a state control circuit to generate a state bit corresponding to each of the multiple memory planes, the state bit indicating (i) one of a busy state and a ready state of the set of specific resources used by the foreground operations of the corresponding memory plane and (ii) one of an in-operation state and an idle state of the resources of the plane core of the corresponding memory plane, and a control circuit operably coupled with the I / O interface, the state control circuit, and the multiple memory planes to perform memory operations using the multiple memory planes. In performing memory operations using one or more of the multiple memory planes, the control circuit generates the plurality of state bits corresponding to each of the multiple memory planes in the state control circuit. Further, the control circuit performs or denies performing memory operations of a received memory command in response to a combination of the received memory command and the plurality of state bits in the state control circuit, including performing or denying performing a first type of memory command dependent on a combination of the busy state and the ready state and the in-operation state and the idle state of all of the multiple memory planes and performing or denying performing a second type of memory command addressed to a specific memory plane independent of a combination of the busy state and the ready state and the in-operation state and the idle state of the memory planes of the multiple memory planes other than the specific memory plane.

[0005] Further, according to the present disclosure, the foreground operations include operations involving at least one of (i) the plane core of each memory plane that controls the set of specific resources of each memory plane and (ii) the resources of the plane core of each memory plane and the background operations (i) include operations involving the resources of the plane core of each memory plane and (ii) do not include operations involving the plane core of each memory plane that controls the set of specific resources of each memory plane of the multiple memory planes.

[0006] According to the present disclosure, the particular set of resources for each memory plane is a set of caches or particular registers for each memory plane such that foreground operations prevent the host from accessing the caches or particular registers of each of the plurality of memory planes and background operations do not prevent the host from accessing the caches or particular registers of each of the plurality of memory planes, wherein the caches or particular registers are not controlled by each plane core of each memory plane.

[0007] Further, according to the present disclosure, the overlapping operation period is a period in which a new memory command is received by the control circuit while an existing background operation of a previous memory command is being performed, and the control circuit is configured such that during the overlapping operation period and when the new memory command has a higher priority than the previous memory command, the existing background operation is suspended to allow a foreground operation of the new memory command, and the suspended background operation is resumed after the foreground operation of the new memory command is completed.

[0008] According to the present disclosure, the new memory command having a higher priority can be a memory command that does not include a background operation.

[0009] Additionally, according to the present disclosure, the overlapping operation period can be a period in which a new memory command is received by the control circuit while an existing background operation of a previous memory command is being performed, and the control circuit can be configured such that during the overlapping operation period and when the new memory command does not have a higher priority than the previous memory command, a foreground operation of the new memory command is started after the existing background operation is completed.

[0010] According to the present disclosure, the first type of memory command is for a first selected type of operation, the first type of memory command is received by the control circuit to perform the first selected type of operation when: (i) a busy state and a ready state of the particular set of resources used by the foreground operation in each of the plurality of memory planes are both in ready; (ii) an in-operation state and an idle state of the resources of each plane core are both in operation according to another first type of memory command; and (iii) the first selected type of operation is capable of being performed with an existing background operation.

[0011] According to the present disclosure, the second type of memory command is for a second type of operation for a target memory plane, the second type of memory command is received by the control circuit to perform the second type of operation when: (i) a busy state and a ready state of the particular set of resources used by the foreground operation in each of the plurality of memory planes include the ready state in the particular set of resources of the target memory plane; and (ii) an in-operation state and an idle state of the resources of each plane core include the idle state in the resources of the plane core of the target memory plane.

[0012] Further, according to the present disclosure, the second type of memory command is for a second selected type of operation for the target memory plane, the second type of memory command accepted by the control circuit to perform the second selected type of operation when: (i) the busy state and the ready state of a particular set of resources used by foreground operations in each of the plurality of memory planes includes the ready state in the particular set of resources of the target memory plane (ii) the in-operation state and the idle state of a resource of a plane core in the target memory plane is in operation according to another second type of memory command; and (iii) the second selected type of operation is capable of being performed with existing background operations.

[0013] Further, according to the present disclosure, the second type of memory command is for a second selected type of operation for the target memory plane, the second type of memory command accepted by the control circuit to perform the second selected type of operation when: (i) the busy state and the ready state of a particular set of resources used by foreground operations in each of the plurality of memory planes includes the ready state in the particular set of resources of the target memory plane (ii) the in-operation state and the idle state of a resource of a plane core in the target memory plane is in operation according to a first type of memory command; and (iii) the second selected type of operation is capable of being performed with existing background operations.

[0014] According to the present disclosure, the first type of memory command is a synchronous chip operation (SCO) and the second type of memory command is an asynchronous independent plane operation (AIPO).

[0015] According to the present disclosure, the memory command includes a reset plane command for the target memory plane, the reset plane command accepted for execution by the control circuit when the in-operation state and the idle state of a resource of a plane core in the target memory plane is in operation according to the second type of memory command, such that a second type of operation in progress of the plane core of the target memory plane is aborted.

[0016] Further, according to the present disclosure, the memory command includes a command accepted by the control circuit to perform an occupancy of a target memory plane of the plurality of memory planes when: the busy state and the ready state includes the ready state for a particular set of resources for the plurality of memory planes, and the in-operation state and the idle state includes the in-operation state for a resource of a plane core for the plurality of memory planes.

[0017] According to the present disclosure, the plane core of one of the memory planes can be a 3D NAND flash memory.

[0018] Further, according to the present disclosure, a plane core of one of the memory planes can be at least one of a memory unit storing data, an error free memory unit including an ECC circuit to correct data, a computation in memory (CIM) unit configured to perform a data computation function, and a memory unit configured to execute an in memory search (IMS) command.

[0019] According to the present disclosure, the memory system can be configured to perform an operation occupying a target memory plane, during a first execution phase of the operation, the memory system can be configured to set busy and ready states of the target memory plane to busy and in-operation and idle states of the target memory plane to in-operation for foreground operations, regardless of busy and ready states and in-operation and idle states of a plurality of memory planes other than the target memory plane, and during a second execution phase of the operation, the memory system can be configured to change the busy and ready states of the target memory plane to ready and keep the in-operation and idle states of the target memory plane to in-operation for background operations, regardless of the busy and ready states and in-operation and idle states of the plurality of memory planes other than the target memory plane.

[0020] Further, according to the present disclosure, during a pre-processing operation period of the operation occupying the target memory plane occurring before the first execution phase and the second execution phase, the busy and ready states of each of the plurality of memory planes can be set to busy and the in-operation and idle states of each of the plurality of memory planes to in-operation.

[0021] According to the present disclosure, a method of operating a memory system is provided, wherein the memory system includes a plurality of memory planes, each memory plane including a plane core and a corresponding set of specific resources, each of the memory planes operable to (i) perform foreground operations with the set of specific resources of the corresponding memory plane and (ii) perform background operations without the set of resources of the corresponding memory plane. The method includes generating, for each of the plurality of memory planes, (i) a corresponding first status signal indicative of a busy or ready state of the set of specific resources used by the foreground operations of the corresponding memory plane, and (ii) a corresponding second status signal indicative of an in-operation or idle state of the plane core of the corresponding memory plane.

[0022] Further, in accordance with the present disclosure, the method includes selectively allowing execution or denying execution of a memory command for a memory plane of the plurality of memory planes based on a state of one or more of the plurality of first status signals and the second status signal.

[0023] Other aspects and advantages of the present application can become apparent from the following drawings, detailed description, and application claims. BRIEF DESCRIPTION OF DRAWINGS

[0024] FIG. 1A A simplified block diagram of a data processing system having a multi-plane memory device as described herein.

[0025] FIG. 1B A simplified block diagram of an integrated circuit device having a plurality of planes with multi-bit status.

[0026] FIG. 2A An example SCO operation to access data from memory arrays of two memory planes is shown.

[0027] FIG. 2B An example first type of SCO operation is shown.

[0028] FIG. 3A An example AIPO operation to access data from memory arrays of two memory planes is shown.

[0029] FIG. 3B An example AIPO operation is shown.

[0030] FIG. 4 An example memory system in which background memory operations and foreground memory operations can be performed is shown.

[0031] FIG. 5 Example memory plane busy status signals (PxRDY) and example memory plane in-operation status signals (PxIO#) for various memory planes are shown symbolically.

[0032] FIG. 6A An example timing diagram showing memory plane busy status signals and memory plane in-operation status signals in response to receiving an AIPO command, where execution of the AIPO command includes a command pre-processing period during which all planes are in a busy (in-operation) state.

[0033] FIG. 6B An example timing diagram showing memory plane busy status signals and memory plane in-operation status signals in response to receiving an AIPO command, where execution of the AIPO command does not have any command pre-processing period during which all planes are in a busy (in-operation) state.

[0034] FIG. 7 An example timing diagram showing the plane busy status signal and the plane in operation status signal in response to receiving a SCO command.

[0035] FIG. 8A Another example timing diagram showing the issuance of an AIPO memory command to an idle plane while another in-operation plane has a pending background operation, where the AIPO memory command causes a command pre-processing period. FIG. 8A

[0036] FIG. 8B Another example timing diagram showing the issuance of an AIPO memory command to an idle plane while another in-operation plane has a pending background operation, where the AIPO memory command does not cause any command pre-processing period. FIG. 8B

[0037] FIG. 9A Another example timing diagram showing the issuance of an AIPO memory command to a plane that has a pending background operation. FIG. 9B

[0038] FIG. 10 A timing diagram showing the issuance of a SCO memory command and the resulting SCO background operation.

[0039] FIG. 11 An example timing diagram showing a pending SCO background operation and the issuance of an AIPO command and the issuance of a SCO command.

[0040] FIG. 12 A table showing an overview of the use of PxRDY and PxIO# for various memory operations.

[0041] FIG. 13 A configuration (e.g., cycle type) of a reset plane command is shown.

[0042] FIG. 14A Another example timing diagram showing the issuance of an AIPO memory command to a memory plane that does not have a pending background operation, while one or more other memory planes can have a pending AIPO background operation. FIG. 14B

[0043] Another example timing diagram showing the issuance of an AIPO memory command to a memory plane that does not have a pending background operation, while one or more other memory planes can have a pending AIPO background operation. FIG. 15A FIG. 15B Another example timing diagram showing various example scenarios for the issuance of an AIPO command.

[0044] FIG. 16A A timing diagram showing an example of a SCO command.

[0045] FIG. 16B Another timing diagram showing an example of a SCO command. ​​​​

[0046] FIG. 17 A timing diagram illustrating other examples of SCO commands is shown, and also illustrating that some AIPO memory commands can not be issued while a plane is executing a SCO background operation.

[0047] FIG. 18A and FIG. 18B A timing diagram illustrating other examples of SCO commands is shown, and also illustrating that some AIPO memory commands can be issued and executed concurrently with a plane executing a SCO background operation.

[0048] FIG. 19A , FIG. 19B , FIG. 19C and FIG. 19D An example timing diagram showing the plane busy status signal PxRDY of the plane P0 through plane P3 in response to receiving commands of each category and the plane operation in status signal PxIO# of the plane P0 through plane P3 is shown.

[0049] FIG. 20 An example showing a second SCO command being issued during the operation of a first SCO command is shown.

[0050] FIG. 21 An example showing an AIPO command that can be issued by the host and accepted at the memory device that pauses the operation of a previous SCO command is shown.

[0051] FIG. 22 Command acceptance parameters and status signals for a sequence of AIPO commands addressing different planes are shown.

[0052] FIG. 23 Command acceptance parameters and status signals for a sequence of AIPO commands with overlapping operations are shown.

[0053] FIG. 24 Command acceptance parameters and status signals for a sequence of AIPO commands invoking a foreground operation with a first phase affecting multiple planes are shown.

[0054] FIG. 25 Command acceptance parameters and status signals for a sequence of AIPO commands invoking a background operation with a first phase affecting multiple planes are shown.

[0055] FIG. 26 Command acceptance parameters and status signals for a sequence of SCO commands invoking a foreground operation are shown.

[0056] FIG. 27 Command acceptance parameters and status signals for a sequence of SCO commands invoking a background operation are shown.

[0057] FIG. 28 Command acceptance parameters and status signals for a sequence of SCO commands followed by an AIPO operation are shown.

[0058] FIG. 29 A flowchart to illustrate control logic on an integrated circuit memory device to accept or reject commands and to update status signals as described herein.

[0059] FIG. 30 A flowchart to illustrate an example of logic executed by a memory controller to issue commands in dependence on status signals as described herein.

[0060] FIG. 31 A flowchart to illustrate example logic to accept or reject SCO commands and AIPO commands.

[0061] REFERENCE NUMERALS

[0062] 10: source device

[0063] 11, 12, 60: bus signal lines

[0064] 15, 16, 17, 18, 19, 20, 140: state control circuitry

[0065] 50: integrated circuit memory device

[0066] 51: multi-plane NAND flash memory

[0067] 52: bus interface

[0068] 55, 56, 57, 58: planes

[0069] 65: ΔR / B (I / I) line

[0070] 66, CE#: chip enable line

[0071] 70: controller logic

[0072] 71: state machine

[0073] 72: multi-bit plane state control circuitry / register

[0074] 73, 117: command decoder

[0075] 74: notification circuitry

[0076] 100: memory system

[0077] 101: memory

[0078] 102a, 102b, 102c, 102d,..., 102N, Pa ~ Pd: memory planes

[0079] 103a, 103b,..., 103N: plane core

[0080] 104a, 104b, 104c, 104d: memory array

[0081] 112a, 112b,..., 112N: cache

[0082] 116, 118: I / O interface

[0083] 119: communication link

[0084] 120: control circuit

[0085] 130: host

[0086] 604a, 604b, 804, 904, 1104a, 1404a, 1404b, 1504a, 1504b, 1504c, 1604a, 1704b, 1804b, 1808b: AIPO command

[0087] 704a, 704b, 1004, 1104b, 1604b, 1604c, 1604d, 1704a, 1704c, 1804a, 1808a: SCO command

[0088] 1400a, 1400b, 1500a, 1500b, 1600a, 1600b, 1700, 1800a, 1800b: timing diagram

[0089] 1190: table

[0090] 2900, 2901, 2902, 2903, 2910, 2911, 2912, 2913, 2920, 2922, 2923, 3000, 3001, 3002, 3003, 3010, 3020, 3021, 3022, 3023, 3024, 3050: step

[0091] 3100, 3102, 3104, 3106, 3108, 3110, 3112, 3114, 3118, 3120, 3122: operation

[0092] CLK: clock

[0093] I / O BUS1, I / O BUS2: bus

[0094] I / O[7:0]: data line

[0095] NAND 1, NAND 2,..., NAND m, NAND n: multi-plane memory device

[0096] OP1, OP2, OP3, OP4, OP5, OP6: operation

[0097] PaIO#, PbIO#, PcIO#, PdIO#, PNIO#, PxIO#: status signals in memory plane operation

[0098] PaRDY, PbRDY, PcRDY, PdRDY, PNRDY, PxRDY: memory plane busy status signals

[0099] P0IO#, P1IO#, P0RDY, P1RDY: status bits

[0100] RE#: read enable

[0101] tO, tl, t2, t3, t4, t5, t6, t7, t8, t9, t601a, t601b, t602a, t603a, t603b, t604a, t604b, t702, t706, t708, t802a, t802b, t803a, t902a, t902b, t903a, tlOOl, tl002, tl003, tl 104, tl402a, tl402b, tl403a, tl501a, tl502a, tl503a, tl504a, tl505a, tl506a, tl507a, tl501b, 1503b, 1504b, 1506b, tl601a, tl602a, tl603a, tl604a, tl605a, tl605al, tl606a, tl607a, tl70l, tl702, tl703, tl704, tl801a, tl802a, tl803a, tl804a, tl806a, tl80lb, tl802b, tl803b, tl806b: times DETAILED DESCRIPTION

[0102] A detailed description of embodiments of the application is provided with reference to the drawings.

[0103] FIG. 1A A diagram of a data processing system, such as a memory system, having a communication network with a bus topology is provided to provide an example of a data processing system in which the technology can be deployed. The system includes a source device 10 (e.g., a host in communication with a memory device) having a bus master interface for a plurality of bus I / O BUS1 and bus I / O BUS2, each of the buses including a set of bus signal lines 11, 12. The device can be a memory controller implementing, for example, a flash translation layer.

[0104] FIG. 1AThe system shown in FIG. 1 can be connected to a wide network that maintains a system data flow to and from the memory device. For example, the source device 10 can include a data port, such as a universal serial bus port, for connecting to an external computer.

[0105] The first set of multi-plane memory devices NAND 1, multi-plane memory device NAND 2,..., multi-plane memory device NAND n are disposed on the I / O BUS 1. The second set of multi-plane memory devices NAND 1, multi-plane memory device NAND 2,..., multi-plane memory device NAND m are disposed on the I / O BUS 2. The multi-plane memory devices NAND 1, multi-plane memory device NAND 2,..., multi-plane memory device NAND n include a bus controller interface to the bus signal lines on the I / O BUS 1. The multi-plane memory devices NAND 1, multi-plane memory device NAND 2,..., multi-plane memory device NAND n each have a state control circuit 15, state control circuit 16, state control circuit 17 to generate a plurality of state bits in the device for each memory plane or for at least one of the memory planes. The multi-plane memory devices NAND 1, multi-plane memory device NAND 2,..., multi-plane memory device NAND m include a bus controller interface to the bus signal lines on the I / O BUS 2. The multi-plane memory devices NAND 1, multi-plane memory device NAND 2,..., multi-plane memory device NAND m each have a state control circuit 18, state control circuit 19, state control circuit 20 to generate a plurality of state bits in the device for each memory plane or for at least one of the memory planes.

[0106] The bus signal lines on the I / O BUS 1 include a set of chip enable lines, labeled CE#, one chip enable line for each device NAND 1, device NAND 2,..., device NAND n in the first set. The bus signal lines on the I / O BUS 2 include a set of chip enable lines, labeled CE#, one chip enable line for each device NAND 1, device NAND 2,..., device NAND m in the second set.

[0107] The bus signal lines on I / O BUS1 include a set of ready / busy (in operation / idle) notification lines, labeled ΔR / B(I / I) lines, one ready / busy (in operation / idle) notification line for each device in the first set, NAND1, NAND 2,..., NAND n. The bus signal lines on I / O BUS2 include a set of ready / busy (in operation / idle) notification lines, labeled ΔR / B(I / I) lines, one ready / busy (in operation / idle) notification line for each device in the second set, NAND1, NAND 2,..., NAND m. In other embodiments, a set of devices on a given bus, such as the devices in the first set, NAND1, NAND 2,..., NAND n, have a notification pin connected to a shared single line on the bus, which can be identified as being generated by a particular device by, for example, being combined with a chip enable line.

[0108] In some examples, the device 10 can have only one connected multi-plane memory device.

[0109] The multi-plane NAND device, or at least one of them, includes a plurality of memory planes, where each memory plane includes: (i) a particular set of resources, such as a cache or scratchpad set, to support memory operations using the corresponding memory plane; and (ii) resources of a plane core to support memory operations using the corresponding memory plane.

[0110] The source device 10 includes logic implemented by circuitry, such as a programmed processor, programmable logic, or dedicated logic circuitry, or a combination thereof, to issue memory commands for the connected memory device. The logic to issue memory commands responds to expected ready / busy (in operation / idle) status of the resources of the particular set (plane core) of each of the plurality of memory planes. In addition, the source device includes logic to issue commands to read the status in the connected memory device to update the expected ready / busy (in operation / idle) status. The expected ready / busy (in operation / idle) status can be maintained by the logic by creating a table that is populated at the time a command is issued, which in some cases has information provided by the ready / busy (in operation / idle) notification pins.

[0111] In this example, source device 10 includes a bus interface that includes a plurality of lines for command, address, and data communication with a connected memory device, and an interface that includes a line for connection with a notification pin on the connected memory device to indicate a change in at least one current combination of a particular set of resources of a plurality of memory planes and a current ready / busy (active / idle) state of a plane core. In a system that includes a notification pin, the logic to issue a command to read status can respond to a signal on the notification pin. The results of the read of status can be used to update the expected ready / busy (active / idle) state at device 10.

[0112] Reference is made to FIG. 30 Examples of logic to issue commands in this setting are described. The techniques provided enable the use of a plurality of commands in a plurality of combinations of ready / busy (active / idle) states of planes in a multi-plane memory device, examples of which are described herein.

[0113] FIG. 1B A simplified block diagram of an integrated circuit memory device 50 that includes a multi-plane NAND memory (e.g., a multi-plane device that can include multiple cores for in-memory searching). Integrated circuit device 50 can be implemented on a single integrated circuit chip, or on multiple integrated circuit chips in a multi-chip package configuration. Integrated circuit memory device 50 in the example includes a multi-plane NAND flash memory 51. The memory has a plurality of planes (55, 56, 57, 58) labeled P[3:0]. Multi-plane NAND flash memory 51 is connected for data communication with a bus interface 52 or other type of input / output (I / O) circuit. Bus interface 52 can be, for example, a bus controller interface such as described with reference to FIG. 1A discussed. FIG. 1B Further shown is a host 130 (such as device 10 of FIG. 1A communicating with integrated circuit memory device 50 using a communication link 119. The operations performed by integrated circuit memory 50 and host 130 can be categorized as background operations and foreground operations that are discussed in detail below. FIG. 4

[0114] In this example, bus signal lines 60 include bus control signals such as clock CLK and read enable RE#. In addition, bus signal lines include data lines I / O[7:0]. In this illustration, there are eight data lines. In other embodiments, there can be a different number of data lines and different types and quantities of control signal lines to suit a particular bus system configuration. The bus can include other signal lines not shown, such as bus clock lines and bus power and ground lines.

[0115] ​The bus interface 52 is connected to controller logic 70 on the integrated circuit device 50. In this example, the controller logic 70 includes multi-bit plane status control circuitry 72 and command decoder 73.

[0116] The bus interface 52 includes pins or other connections for connection to the bus signal lines 60, to the chip enable CE# line 66, and to the AR / B (I / I) line 65 for ready / busy notification. The ready / busy notification is a signal generated in the notification circuitry 74 upon detecting a change in the combination of ready / busy status signals in the multi-bit plane status control circuitry 72. The bus signal lines 60, the chip enable CE# line 66, and the AR / B (I / I) line 65 can be part of the communications link 119. Additional information can be communicated between the integrated circuit memory device 50 and the host 130 using the communications link 119.

[0117] The bus interface 52 receives commands from the bus and applies them to the command decoder 73. The controller logic applies decoded command signals to the state machine 71, which operates. The state machine includes registers or other signal sources to indicate the state of the operation being performed, and includes circuitry to maintain state bits in the multi-bit plane status control circuitry 72. The state machine 71 can include multiple instances of state machines for particular operations, such as one instance for each memory plane.

[0118] The controller logic 70 includes operating circuitry, such as state machines and specialized circuitry, to perform memory operations in response to commands received at the bus interface 52. The multi-bit plane status control circuitry 72 includes more than one state bit in each of the multiple planes 55, plane 56, plane 57, plane 58. The combination of state bits for a particular plane in the multiple planes 55, plane 56, plane 57, plane 58 and for more than one and for all of the planes, together with the operation identified by a command received at the interface 52 and in some embodiments together with the type of operation currently being performed in the multiple planes, can be applied by the controller logic 70 to accept and reject commands received at the bus interface 52 for execution, examples of which are described herein.

[0119] More generally, FIG. 1BThe apparatus 50 is an example of a memory apparatus having an input / output (I / O) interface to receive data and memory commands addressed to one or more of a plurality of memory planes and to output data, a state control circuit, and a control circuit coupled operably with the I / O interface, the state control circuit, and the plurality of memory planes to perform memory operations (e.g., compute-in-memory (CIM) operations, search-in-memory (IMS) operations, etc.) using one or more of the plurality of memory planes. Even if not explicitly stated, all memory operations described herein can be operations including, for example, compute-in-memory (CIM) operations, search-in-memory (IMS) operations, etc. In performing memory operations using one or more of the plurality of memory planes, the control circuit generates a plurality of state bits in the state control circuit linked to each of the plurality of memory planes, the plurality of state bits linked to each of the memory planes indicating a particular set of resources of each of the plurality of memory planes and a plurality of different combinations of ready / busy (in operation / idle) states of the plane cores. Further, the control circuit performs or denies performing a memory operation of a received memory command in response to the received memory command and the combination of the plurality of state bits. In the state control circuit, including performing or denying performing a first type of memory command dependent on a combination of ready / busy (in operation / idle) states of all of the plurality of memory planes, and performing or denying performing a second type of memory command addressed to a particular memory plane and independent of a combination of ready / busy (in operation / idle) states of memory planes of the plurality of memory planes other than the particular memory plane.

[0120] Reference is made to FIG. 29 Examples of logic to receive and deny commands in this setting are described. The techniques provided enable the use of a variety of commands in a variety of combinations of ready / busy (in operation / idle) states of planes in a multi-plane memory apparatus, examples of which are described herein.

[0121] Synchronous chip operation (SCO) or parallel multi-plane operation

[0122] FIG. 2A An example synchronous chip operation (SCO) to access data from memory arrays 104b, 104d of two example memory planes 102b, 102d, respectively, is shown. In the example, the SCO operation is not limited to a particular memory plane or memory array and can occupy multiple (such as all) memory planes and / or memory arrays.

[0123] In FIG. 2AIn the example of FIG. 1, assume that four memory planes 102a,..., 102d (Pa to Pd) exist in a memory 101 (e.g., a multi-plane device that can include multiple cores for compute-in-memory (CIM) and search-in-memory (IMS)), which receives commands and data from a host (not shown), where memory array 104a of memory plane 102a can store data, memory array 104b of memory plane 102b can store data, memory array 104c of memory plane can store data, and memory array 104d of memory plane 102d can store data. The data stored by memory array 104a, memory array 104b, memory array 104c, and memory array 104d can be any appropriate type of data.

[0124] For example, from time to and according to operation OP1, data is being accessed from memory plane 102a, memory plane 102b, and memory plane 102d. At time ti and according to operation OP2, a request is issued to access data from memory plane 102a and memory plane 102c. However, FIG. 2A SCO is shown, where, for example, due to one or more shared resources in memory 101, an operation performed in one memory plane depends on the status of other memory planes. For example, if SCO is being performed in one memory plane, operations on one or more other planes cannot be performed. Until all internal operations are completed, the host cannot read data from the idle memory planes. After a SCO command is issued, the memory chip becomes busy and cannot accept new embedded operation commands during the busy period. Depending on the command, the memory chip will return to the ready state after the current embedded operation is completed or the cache is ready (idle) for data input / output for all planes. Only when the chip is ready and idle (i.e., all planes are idle) after SCO is completed, or the chip is ready and in operation (i.e., all planes are ready and in operation) in the case of SCO with background operations, the host can issue new embedded operation commands that can be performed by the memory chip. To determine whether to issue a command that invokes SCO, the host can check the chip (or plane) busy status PRDY and the chip (or plane) in operation status PIO#. Since SCO occupies multiple planes in parallel, SCO is also referred to as a parallel multiple plane operation. Operations OP1 and OP2 can be any type of memory operation (e.g., read, write, etc.).

[0125] Therefore, although operation OP2 is requesting access to data from memory plane 102a and memory plane 102c at time t1, the request cannot be executed immediately, for example, because SCO (e.g., accessing data) is currently being performed in memory plane 102a, memory plane 102b, and memory plane 102d according to operation OP1. Once the access to data according to operation OP1 is completed at time t2, the access to data from memory plane 102a and memory plane 102c according to operation OP2 begins at time t2.

[0126] FIG. 2B An example of SCO is shown. In this example, operations on each plane begin simultaneously, that is, they are synchronous.

[0127] Specifically, such as FIG. 2B As shown, starting at time t0, SCO OP1 (e.g., an operation of the same type) is executed in each of memory planes a, b, and d. Once OP1 is completed in memory planes a, b, and d, OP2 can be executed in, for example, memory planes a and c. Other types of SCO will be obvious to those skilled in the art.

[0128] Asynchronous Independent Plane Operations (AIPO) or Overlapping Independent Plane Operations

[0129] FIG. 3A An example of asynchronous independent plane operation (AIPO) is shown for accessing data from memory array 104a in memory plane 102a and memory array 104c in memory plane 102c. Similar to... FIG. 2A ,exist FIG. 3A In this example, assume four memory planes 102a, ..., 102d (Pa to Pd) exist in memory 101, where memory arrays 104a, 104b, 104c, and 104d store data. The data stored by memory arrays 104a, 104b, 104c, and 104d can be of any suitable type.

[0130] Data can be accessed from memory plane 102a at time t0 according to operation OP1. At time t1 according to operation OP2, a request can be issued to access data from memory array 104c of memory plane 102c. FIG. 3AAsynchronous independent plane operations (AIPOs) (also referred to herein as overlapped independent plane operations) are shown, in which operations can be performed in one memory plane without regard to or affecting the state of other memory planes. In AIPOs, each plane can start any operation at any time, as long as the selected plane is ready for the embedded operation command. Thus, AIPOs can be performed in a plane regardless of the state of other planes. That is, a host can issue an embedded operation command to a particular memory plane that can be performed by the memory, as long as the particular plane is ready (and regardless of the ready state of other planes). For AIPOs, the host can treat each plane as an independent memory unit, and the host checks the plane busy status PRDY and the plane operation in status PIO# for progress of operations in each plane. For example, if an AIPO operation is being performed in one memory plane, another AIPO operation on another memory plane can be performed in an overlapped manner. Thus, AIPO memory operations allow operations to be performed in more than one memory plane in an overlapped or at least partially simultaneous manner.

[0131] Thus, when a data request is made at time tl, the request is immediately performed, e.g., when an AIPO (e.g., an access data) is currently being performed in memory plane 102a. Thus, the access of data from memory plane 102c starts at time tl, as shown in FIG. 3A Thus, the host can access a non-busy plane (e.g., plane 102c) for new data access while another memory operation is still being performed in another busy plane (e.g., plane 102a).

[0132] FIG. 3B Example AIPO operations are shown. In the example, AIPO operations (OP1, OP2, OP3, OP4, OP5, and OP6) for different planes (memory plane a, memory plane b, memory plane c, and memory plane d) can start at different times (to, tl, t2, t3, t4, and t5). For example, OP1 starts in memory plane a at time to, OP2 starts in memory plane c at time tl, OP3 starts in memory plane b at time t2, OP4 starts in memory plane d at time t3, OP5 starts in memory plane a at time t4, and OP6 starts in memory plane b at time t5. As shown. The AIPO operations are asynchronous in nature.

[0133] Memory embedded operation protocol supporting both SCO operations and AIPO operations

[0134] As will be discussed in more detail later herein, in embodiments, the techniques described herein support both SCO operations and AIPO operations.

[0135] Background memory operations and foreground memory operations

[0136] FIG. 4 An example memory system 100 is shown in order to explain the difference between background memory operations and foreground memory operations that are performed. The memory system 100 can be, for example, a plurality of planar devices that can include a plurality of cores for compute-in-memory (CIM) and search-in-memory (IMS), and can include a fault-free chip enabled such as by ECC circuitry. Any memory system described herein can be the same type of memory system as the memory system 100. An IMS operation or command allows a host to input target data for a data search, and the memory system 100 can search for matching or highly matching data in the target data region and then further report the data locations to the host. One application of the IMS operation or command can include facial recognition.

[0137] Before describing FIG. 4 background operations, the overall architecture of the memory system 100 shown in both FIG. 4 and FIG. 5 will be described. The memory system 100 can include a memory system 101 that includes a plurality of memory planes 102a memory plane 102b,..., memory plane 102N (similar to the integrated memory device 50 of FIG. 1B ).

[0138] Elements referred to herein with a common reference numeral followed by a number or letter can be referred to individually by the reference numeral common. For example, the memory plane 102a, memory plane 102b,..., memory plane 102N can be referred to collectively and generally as the memory planes 102 in the plural (or as the memory planes 102 (a-N)), and as the memory plane 102 in the singular.

[0139] The memory 101 can be distinct from another integrated circuit that includes the host 130. In another embodiment, the host 130 and the memory 101 are on the same single IC chip or multi-chip package.

[0140] The memory 101 can be of any appropriate type, such as non-volatile NAND memory, non-volatile NOR memory, or the like. In an example, the memory 101 is a three-dimensional (3D) memory that includes vertically stacked memory cells in individual planes. As an example, the memory 101 can be a NAND flash memory.

[0141] Each memory plane 102 (memory plane 102a, memory plane 102b,..., memory plane 102N) includes a corresponding plane core 103 (plane core 103a, plane core 103b,..., plane core 103N). Each plane core 103 can be a memory unit to store data, a faultless memory unit that includes ECC circuitry to correct data, a CIM unit to perform data computation functions, a memory unit that can perform in-memory searches, etc. Each plane core 103 is in communication with each cache 112 (cache 112a, cache 112b,..., cache 112N). The caches 112, which can be cache memory or scratchpad sets, are in communication with the I / O interface 116. Each cache 112 can store data from the host 130 or each plane core 103. The stored data can be raw data or computed data from the memory array. When the caches 112 are scratchpad sets, the scratchpad sets can be scratchpad groups that store results from operations such as IMS results or CIM results. Each cache 112 can be referred to as a particular resource set.

[0142] If a particular resource set (e.g., cache 112a, which can be a cache memory or a scratchpad set) is being controlled by a corresponding plane core (e.g., plane core 103a), the host 130 cannot access the memory plane (e.g., memory plane 102a). This can be referred to as a foreground operation period during which the memory plane is busy (e.g., cache 112a is controlled by plane core 103a and plane core 103a is in operation). If a particular resource set is not being controlled by a corresponding plane core, the memory plane is ready (e.g., a background operation period or an idle period). In other words, the busy state and ready state of a memory plane is designated by whether a corresponding plane core is controlling a particular resource set of a corresponding plane. If a particular resource set is being controlled, the memory plane is busy, and if a particular resource set is not being controlled, the memory plane is ready. If a plane core is in operation, the in operation / idle state of a corresponding memory plane is “in operation” (foreground and / or background operation period), otherwise, the state of a corresponding memory plane is idle (idle period).

[0143] In this example, the memory plane is configured with two sets of state indicators. In other embodiments, there can be more than two sets of state indicators, where each state indicator can be one or more bits.

[0144] The memory 101 also includes one or more status control circuits 140, e.g., to generate one or more status signals for each plane (plane x, for a memory having N planes, x can be from 0 to N-1), such as a plane busy status (PxRDY), a plane in operation status (PxIO#), etc., as will be discussed later herein. For each memory plane (e.g., memory plane 102a), the plane busy status (PxRDY) indicates busy (0) when the particular set of resources (e.g., corresponding cache 112a) is controlled by the corresponding plane core (e.g., plane core 103a), and indicates ready (1) when the particular set of resources is not controlled by the corresponding plane core. When the memory plane is busy, the host 130 cannot access the memory plane (e.g., during foreground operation periods). When the memory plane is ready (1), the host 130 can access the memory plane (e.g., during background operation periods or idle periods). In addition, for each memory plane (e.g., memory plane 102a), the in operation status (PxIO#) indicates in operation (0) when each plane core (e.g., plane core 103a) is in operation (foreground operation period or background operation period), and indicates idle (1) when the plane core is not in operation.

[0145] The memory 101 can also include one or more hardware notification pins dedicated to outputting the status of one or more signals.

[0146] The memory 101 also includes an input / output (I / O) interface 116 coupled to the caches 112a,..., 112N (also referred to as the particular set of resources). The individual caches 112 receive data from and write data to the corresponding plane core 103 from / to the I / O interface 116.

[0147] In an example, the host 130 generates and transmits memory commands to the memory 101, stores data to and receives data from the memory 101. For example, the host can be a memory controller implementing a flash translation layer.

[0148] In an example, the memory 101 communicates with the host 130, e.g., via a communication link 119. The communication link 119 can be any suitable communication link, such as a link over a wired connection. The host 130 includes an I / O interface 118 coupled to the I / O interface 116 of the memory 101 via the communication link 119. Thus, the host 130 stores data to and reads data from the memory array of a memory plane via the I / O interface 118 associated with the memory plane, the communication link 119, the I / O interface 116, the corresponding cache 112, and the corresponding page buffer 108.

[0149] In an embodiment, the memory 101 also includes control circuitry 120 that controls the operation of the various aspects of the memory 101. In an embodiment, the control circuitry 120 issues various memory state commands, as will be discussed later herein.

[0150] In this example, the memory 101 includes a command decoder 117 that communicates with the I / O interface 116. The command decoder 117 decodes commands received at the I / O interface in conjunction with the state control circuitry 140. The command decoder 117 signals the control circuitry 120, which provides the circuitry for performing the operation identified by the command.

[0151] The memory 101 has many other components, which are not shown for purposes of clarity of illustration and so as not to obscure the description of the present disclosure.

[0152] As previously mentioned, the memory system 100 can perform background memory operations and foreground memory operations.

[0153] Background memory operations (also referred to as background operations) are those memory operations (of the memory 101 of the memory system 100) during the execution of which selected memory commands can be accepted while the set of resources (cache 112) is not being controlled by the corresponding plane core. In other words, even though the corresponding plane core 103 can be performing a background operation, the host 130 can access or issue new commands to the memory plane 102 during the background operation (e.g., while the background operation is being performed). For example, the host 130 can provide new commands to the cache 112 during the background operation. Also, for example, selected memory commands (operations) can be accepted while PxRDY is ready (1) even though a background operation is still being performed and the corresponding plane core is in operation. Once the background operation is complete, any memory command can be accepted. During the background operation, since the particular set of resources (e.g., cache 112) is not being controlled by the plane core, PxRDY indicates ready (1) and since the plane core 103 is busy, PXIO# indicates in operation (0).

[0154] Foreground memory operations (also referred to as foreground operations) are those memory operations (of the memory 101) during which, since the set of resources (cache 112) is being controlled by the plane core 103 (e.g., PxRDY = busy (0)) and since the plane core is in operation (PxIO# = in operation (0)), only system management commands can be accepted. During the foreground operation, the host 130 cannot access or issue new commands to the memory plane 102 except for system management commands. For example, during the foreground operation, the cache 112 cannot be accessed by the host 130 since the cache 112 can be occupied by the foreground operation. System management commands can be issued at any time.

[0155] FIG. 5 An example memory plane busy status signal (PxRDY) and an example memory plane operation in status signal (PxIO#) are illustratively shown for various memory planes. FIG. 5 All other reference elements are the same as FIG. 4 with reference elements of

[0156] Acceptance / rejection of the first set of commands (or first commands) depends on operations of all memory planes 102, and acceptance / rejection of the second set of commands (or second commands) depends on operations of the target memory plane. Based on the fact that the memory system 100 can be aware of ongoing operations being conducted or performed thereon, commands can be accepted or rejected according to the following rules: (i) both SCO (type 1) commands and AIPO (type 2) commands can be accepted if there are no operations on any plane core 103 (i.e., all operation / busy status signals = idle); (ii) selected SCO commands can be accepted at all memory planes are ready, or selected AIPO commands (without background operations) can be accepted to the memory planes identified as ready, if SCO operations are still in progress (all operation / busy status signals = busy); and (iii) any AIPO command can be accepted for idle plane cores (operation / busy status = idle for the target plane core), selected AIPO commands can be accepted for ready memory planes with busy plane cores, and all SCO commands are rejected, if AIPO operations are still in progress (operation / busy status signal = busy for at least one plane core).

[0157] Categories of memory commands and memory operations

[0158] Table 1 below herein shows various example memory commands that can be implemented by the memory system 100 discussed throughout this disclosure, as well as their corresponding types and categories.

[0159] Table 1

[0160]

[0161] The first row of Table 1 lists a sequence number corresponding to various memory commands. The second row of Table 1 lists the memory commands. The third row of Table 1 indicates the operation type, such as whether the memory command is an AIPO or an SCO. For example, a cache read random memory command (e.g., which can be used to read data from a cache) is an AIPO memory command.

[0162] The fourth row of Table 1 indicates whether the memory command contains, requires, and / or causes a background operation. If the operation is identified as "no background operation," the operation does not contain any background operation (but it does contain a foreground operation). For example, during an operation that is "no background operation" (e.g., a foreground operation), new command acceptance is not allowed (except for system management commands) during the foreground operation, the busy status signal PxRDY indicates busy, and the in-operation status signal PxIO# indicates in-operation. If the operation is identified as "background operation," the operation contains a background operation. For example, during an operation that is "background operation" (e.g., a foreground operation), new command acceptance is not allowed (except for system management commands) during the foreground operation, the busy status signal PxRDY indicates busy, and the in-operation status signal PxIO# indicates in-operation, then after the foreground operation is completed, for example, new command acceptance is allowed, the busy status signal PxRDY indicates ready, but the in-operation status signal PxIO# indicates in-operation.

[0163] The fifth row of Table 1 classifies each memory command into a corresponding one of five possible categories. The last column of Table 1 identifies the possible categories. For example, category 1 refers to an SCO memory command that has no (e.g., does not contain) background operation, category 2 refers to an SCO memory command that has (e.g., contains) background operation, category 3 refers to a system management command, category 4 refers to an AIPO memory command that has no (e.g., does not contain) background operation, and category 5 refers to an AIPO memory command that has (e.g., contains) background operation.

[0164] For example, in the case that a background operation of a cache read operation is in progress: (i) a cache read random command can be issued / accepted, (ii) a cache read end random command can be issued / accepted, and (iii) a system management command (e.g., a reset plane command) can be issued / accepted. Also, for example, in the case that a background operation of a cache program operation is in progress: (i) a page program command can be issued / accepted, (ii) a cache program command can be issued / accepted, and (iii) a system management command (e.g., a reset command or a reset LUN command) can be issued / accepted.

[0165] Memory plane busy status signal (PxRDY) and memory plane in-operation status signal (PxIO#)

[0166] In an embodiment, various planes of the memory 101 (or the control circuit 120) issue various status signals, for example, to indicate whether a first set of resources and a second set of resources in a corresponding memory plane 102 are ready to perform a new memory operation, or are busy performing a current memory operation and cannot accept a new memory operation.

[0167] One such status signal is a memory plane busy status signal (PxRDY) issued for each memory plane Px, where "x" in Px is an index of the corresponding memory plane. For example, for memory plane 102a, the memory plane busy status signal is PaRDY; for memory plane 102b, the memory plane busy status signal is PbRDY; for memory plane 102N, the memory plane busy status signal is PNRDY, and so on. In general, the signal PxRDY indicates whether the memory plane 102x is in a busy state or a ready state, as will be discussed in greater detail later herein.

[0168] For example, when the PxRDY signal indicates that the memory plane is in a busy state (e.g., value 0), the plane cannot be accessed (while a foreground operation in the plane is in progress), and when the PxRDY signal indicates that the memory plane is not in a busy state (e.g., in a ready state; indicated by value 1), the plane can be accessed and receive new commands (no foreground operation in the plane is in progress). In other words, when a foreground operation is being executed, the PxRDY signal will indicate that the particular plane is in a busy state (e.g., value 0), and when a foreground operation is not being executed, the PxRDY signal will indicate that the particular plane is in a ready state (e.g., value 1).

[0169] Another such status signal is a memory plane operation-in-progress status signal (PxIO#) issued for each memory plane, where "x" in PxIO# is an index of the corresponding memory plane. For example, for memory plane 102a, the plane operation-in-progress status signal is PaIO#; for memory plane 102b, the plane operation-in-progress status signal is PbIO#; for memory plane 102N, the plane operation-in-progress status signal is PNIO#, and so on. In general, the signal PxIO# indicates whether the memory plane is in operation or in idle. For example, when the PxIO# signal indicates that the memory plane is in operation (e.g., value 0), there is a foreground operation or a background operation in the selected plane in progress, and when the PxIO# signal indicates that the memory plane is in idle (e.g., not in operation; value 1), there is no operation in the memory plane in progress.

[0170] Whether a particular memory plane can receive and execute a new memory command at any given time is based on the PxRDY and / or PxIO# of the particular memory plane, as well as the PxRDY and / or PxIO# of various other memory planes.

[0171] FIG. 5The memory plane busy status signals (PxRDY) and the memory plane in operation status signals (PxIO#) are shown symbolically for various memory planes 102 of the memory 101 of the system 100. This is merely an example of a memory 101 providing the status signals PxRDY and PxIO#. As shown, each memory plane has a corresponding PxIO# signal and a PxARDY signal. It is noted that in an example, the control circuit 120 or another suitable component of the memory plane 102 or the memory 101 issues the PxRDY signal and the PxIO# signal for the memory plane 102.

[0172] The memory plane busy status signals (PxRDY) can also be referred to simply as plane status signals, and the memory plane in operation status signals (PxIO#) are also referred to simply as plane operation status signals.

[0173] In an example, the bits representing the status signals PxRDY and PxIO# can be generated by the status control circuit 140.

[0174] In general, if a background operation in the memory plane 102x is currently being performed (where a background operation has been discussed previously herein, for example, with respect to FIG. 4 The PxIO# status signal is in the in operation state, indicated by, for example, PxIO# being 0, because the background operation in the memory plane 102x means that the memory plane 102x is involved in the background operation. Otherwise, if the memory plane 102x is not experiencing any operation (e.g., any background operation), the corresponding PxIO# status signal is in the idle state, indicated by, for example, PxIO# being 1.

[0175] Thus, for the memory plane 102x:

[0176] PxIO# = 0 -> indicates that the memory plane 102x is in the in operation state because either a foreground operation or a background operation is being performed in the plane; and

[0177] PxIO# = 1 -> indicates that the memory plane 102x is in the idle state because no foreground operation or background operation is being performed in the plane.

[0178] For the memory plane 102x:

[0179] PxRDY = 0 -> indicates that the memory plane 102x is in the busy state, indicating that the memory plane cannot be accessed while a foreground operation is being performed in the plane, and thus cannot accept new commands while the foreground operation is being performed; and

[0180] PxRDY = 1 indicates that the memory plane 102x is in the ready state, meaning that no foreground operation is being performed in the plane, so the memory plane can be accessed and a new command can be accepted.

[0181] SCO memory commands and AIPO memory commands that do not include a background operation (see Table 1) can be executed in certain scenarios, which are discussed in more detail below with reference to FIG. 12 The scenarios include: PxRDY = busy (0); and PxIO# = in operation (0). This configuration does not include: (i) PxRDY = busy (0); PxIO# = idle (1); and (ii) PxRDY = ready (1); PxIO# = in operation (0).

[0182] SCO memory commands and AIPO memory commands that include a background operation (see, e.g., Table 1) can be executed in different state signal scenarios, which are discussed in more detail below with reference to FIG. 12 The scenarios include: (i) PxRDY = busy (0); PxIO# = in operation (0); and (ii) PxRDY = ready (1); PxIO# = in operation (0). These two configurations do not include: (i) PxRDY = busy (0); PxIO# = idle (1).

[0183] SCO memory commands and AIPO memory commands that can be operated in an overlapping period of a background operation can be executed in the scenario of PxRDY = busy (0) and PxIO# = in operation (0). The overlapping operation period can start when a first new command is accepted by the chip during a background operation, and it ends without pending operations (suspended or waiting operations). During the overlapping operation period, at least one pending operation is queued for waiting. If the pending operation has a higher priority, the ongoing operation is suspended to execute the high-priority operation (see FIG. 21 ), and will resume after all high-priority operations are completed. Otherwise, the pending operation is executed after the current operation is completed (see FIG. 20 ).

[0184] When no background operation is in progress (i.e., for a particular plane, PxRDY = PxIO# = ready / idle) and an AIPO command can be issued by the host to the particular plane and accepted at the memory device.

[0185] When no background operation is in progress in a particular plane (i.e., for a particular plane, PxRDY = PxIO# = 1 or ready / idle), the host 130 can issue an AIPO command to a non-busy particular plane that can be executed. That is, when PxRDY = PxIO# = 1, the host 130 can issue an AIPO command to the memory plane 102x, and the AIPO command can be accepted by the memory plane 102x.

[0186] After an AIPO command is issued to a specific plane (e.g., plane 102a), there are one or more possible options for executing the AIPO command: for example FIG. 6A Option A shown, and FIG. 6B Option B is shown. FIG. 6A Option A or FIG. 6B Option B is selected for implementation-specific purposes and can be chosen based on the circuit design of memory 101.

[0187] FIG. 6A Option A, as shown, transitions the ready state of all planes to a busy state for a short time period (PxRDY = 0 for x = a, ..., N) to process commands. This "short time period" is also referred to herein as the "command preprocessing period," which is the first execution phase of the AIPO command. After this first phase, the busy state of unselected planes (e.g., planes to which the AIPO command was not issued) represents the current state of the unselected planes and becomes independent of the selected planes. Therefore, after time t602a at the end of the command preprocessing period, for the selected or busy plane Pa to which the AIPO command was issued, PaRDY = 0, and for all other unselected and non-busy memory planes, PbRDY, PcRDY, and PdRDY = 1. The length of the command preprocessing period is implementation-specific, such as the design of memory-based circuits and other implementation details.

[0188] FIG. 6A An example timing diagram is shown in response to the plane status signal and the plane operation status signal received from the AIPO command 604a, wherein the execution of the AIPO command 604a includes a command preprocessing period during which all planes are either busy or in operation. It should be noted that in FIG. 6A In timing diagrams and various other graphs, dashed rectangles correspond to associated signals that are busy (or in operation), while unshaded rectangles correspond to associated signals that are ready (i.e., not busy) (or idle), such as... FIG. 6A As shown in the legend section. In FIG. 6A In this example, four memory planes are assumed to be 102a, 102b, 102c, and 102d, but any different number of memory planes may exist. Therefore, four plane state signals PaRDY, PbRDY, PcRDY, and PdRDY are shown, along with four array state signals PaIO#, PbIO#, PcIO#, and PdIO#. FIG. 6AIn the example shown in FIG. 6A, prior to time t601a, all signals PaRDY, PbRDY, PcRDY, PdRDY, PaIO#, PbIO#, PcIO#, and PdIO# are in the ready (idle) state.

[0189] At t601a, an AIPO command 604a for plane 102a is received. At t601a, the plane busy and plane in operation state signals for the selected plane (e.g., plane 102a) are changed to busy (operation) (PxRDY and PxIO# are changed from 1 to 0), and the plane ready and plane in operation state signals for the other unselected planes (e.g., planes 102b, 102c, and 102d) are not affected. FIG. 6A In the example shown in FIG. 6A, immediately after receiving the AIPO command 604a for plane 102a, from time t601a to time t602a (which is referred to as the command pre-processing period or the first phase of the execution cycle of the AIPO command 604a), all plane state signals are changed to busy and the plane operation in state signals are changed to operation.

[0190] Subsequently, at time t602a (e.g., upon issuance of the AIPO command 604a for memory plane 102a), the plane busy and plane operation in state signals for planes 102b, 102c, and 102d are changed to ready (idle). After time t602a, PaRDY and PaIO# continue to be busy (operation). Thus, the memory plane 102a containing the corresponding memory array 104a is executing the AIPO command 604a. At time t603a, the memory plane 102a becomes ready to accept a new command, and PaRDY becomes ready. The time period between time t602a and time t603a is also referred to as the second phase of the execution cycle of the AIPO command 604a. Note that background operations for the AIPO command 604a can still be in progress in the memory plane 102a, and thus, PaIO# is still in operation. Eventually, the background operations for the AIPO command 604a end at time t604a, and the array state signal PaIO# now transitions from operation to idle. The time period between time t603a and time t604a is also referred to as the AIPO background operation phase or the third phase of the execution cycle of the AIPO command 604a, while only the background operations of the AIPO command 604a are being executed.

[0191] FIG. 6B Option B shown in FIG. 6B: In this option, the plane busy and plane operation in state for the selected plane (e.g., for which the AIPO command is issued) are changed to busy (operation) (PxRDY and PxIO# are changed from 1 to 0), and the plane ready and plane operation in state for the other unselected planes are not affected. Thus, unlike Option A discussed above with respect to FIG. 6A, Option B does not have a command pre-processing period. FIG. 6A FIG. 6B ​Another example timing diagram showing the response of the plane status signals and the plane operation-in signals to receiving the AIPO command 604b, where the execution of the AIPO command 604b does not have any command pre-processing period during which all planes are in the busy state. In contrast to the example of FIG. 6A , in the example of FIG. 6B , only the selected plane for which the AIPO command 604b is issued has its plane status signal and plane operation-in signal (i.e., PaRDY and PaIO#) transition to busy (operation-in), and the signals of all other planes remain ready. Thus, from t601b to t603b, which is the first phase of the execution period of the AIPO command 604b, PaRDY is in busy. From t601b to t604b (e.g., as also discussed with respect to FIG. 6A , which is the AIPO background operation phase or the second phase of the execution period of the AIPO command 604b, PaIO# is in operation-in.

[0192] Thus, comparing FIG. 6A to FIG. 6B , in FIG. 6A , all plane busy signals and plane operation-in signals are in busy (operation-in) for a short period of time after the AIPO command 604a is issued (i.e., during the command pre-processing period); whereas in FIG. 6B , only the selected plane busy signal and plane operation-in status signal become busy after the AIPO command 604b is issued. Thus, FIG. 6B higher operation efficiency is achieved compared to FIG. 6A , as in FIG. 6B , the unselected planes are always available. However, the timing diagram implementing FIG. 6B requires more complex circuitry in the memory 101, for example, compared to the case of FIG. 6A . Thus, whether the timing diagrams of FIG. 7 and FIG. 6A are implemented is specific to the design of the memory 101.

[0193] In the case where no background operation is in progress (i.e., PxIO# is idle for all planes) and a SCO command is issued for a particular plane

[0194] In an example, the host 130 can issue a SCO command to the memory 101 when all planes are idle (e.g., PxIO# = 1 for all planes). After the SCO command is issued, all planes become busy (PxRDY = PxIO# = busy (operation-in) for all planes), and no other command can be issued by the host 130 and accepted at the memory device 101 until all planes become ready (PxRDY = ready for all planes).

[0195] FIG. 6A An example timing diagram showing the plane busy status signals and the plane in operation status signals in response to receiving the SCO command is shown. In this example, similar to FIG. 16A , assume that in response to the AIPO command for plane 102a at time t601a, PaRDY is busy from t601a to t603a, PaIO# is in operation from t601a to t604a, and the plane busy status signals and the plane in operation status signals for the other planes are busy (in operation) from t601a to t602a, e.g., for reasons discussed with respect to FIG. 8A .

[0196] Assume that a SCO command 704a for plane 102c is issued between t602a and t603a. Since at this time at least one plane is not ready (e.g., PaRDY is busy), the SCO command 704a for plane 102c is declared invalid, since the host 130 can only issue a SCO command to the memory 101 when all planes are ready for a new command and there is no AIPO background operation.

[0197] Assume that a SCO command 704b for plane 102d is issued after time t604a (e.g., at time t702). Since all planes are now ready (idle) and there is no background operation in progress, the SCO command 704b for plane 102d is executed. From time t702, all plane busy status signals and plane in operation status signals transition to the busy state. The plane ready status remains busy from time t702 to time t706, where the time period between time t702 and time t706 is also referred to as the “SCO foreground operation phase,” “plane occupancy period,” or “first phase.”

[0198] In an example, during the plane occupancy period, the SCO occupies the resources of all memory planes (or occupies the common resources of the memory planes), so that no other operation can be executed - thus, the PxRDY of all planes is busy during this period. In an example, during the plane occupancy period, the PxRDY of all planes is busy and all planes are shown as occupied to prevent any command input until the memory 101 is ready for the next command. Note that any AIPO (or SCO) command issued during the plane occupancy period is declared invalid (as also discussed later in this document with respect to FIG. 8A .

[0199] At time t706, the cache (e.g., non-background) operation associated with the SCO command 704b for plane 102d can complete, and thus, the plane busy status signal can be ready for all planes from time t706 (e.g., for x = a,..., d, PxRDY = ready). However, the all plane operation in status signal for all planes can still be busy (e.g., for x = a,..., d, PxIO# = busy) while a background operation can be in progress in the selected plane 102d. At time t708, the SCO command 704b for plane 102d can complete, and thus, the all plane operation in status signal for all planes becomes idle (e.g., for x = a,..., d, PxIO# = idle).

[0200] Thus, during the time period between time t706 and time t708, the plane operation in status signal is in operation for all planes while the plane busy status signal is ready for all planes. This period of time is referred to herein as the SCO background operation phase or the second phase of the execution period of the SCO command.

[0201] When a background operation is in progress for at least one plane (i.e., PxIO# = operation in) and an AIPO command is issued for a particular plane that does not have a background operation in progress

[0202] Assuming a background operation is in progress for at least one plane, such as plane 102a, i.e., for that plane, PaIO# = 0 (e.g., operation in). One or more other planes, such as at least plane 102b, do not have a background operation in progress (e.g., PbRDY = PbIO# = 1 or ready (idle)). That is, one or more other planes, such as at least plane 102b, are idle planes or ready. In this scenario, the host 130 can issue an AIPO command to an idle plane.

[0203] FIG. 8A An example timing diagram is shown depicting the issuance of an AIPO memory command to an idle plane while another operation in plane has a background operation in progress, where FIG. 8B The AIPO memory command of FIG. 8BIn this case, only prior to time t802a, background operations are in progress in plane 102a (i.e., PaIO# = In-Op) and the other planes are ready (e.g., PyRDY = PyIO# = Ready (Idle), where y = b, c, d). At time t802a, an AIPO command 804 for plane 102b is issued by host 130. Thus, from t802a to t803a, the PxRDY and PxIO# for all planes (where x = a,..., d) become busy (In-Op) for a short time period (i.e., a command pre-processing period). After the command pre-processing period (discussed with respect to FIG. 6), PaRDY, PcRDY, PdRDY, PcIO# and PdIO# transition to Ready (Idle). Due to the execution of AIPO command 804 for plane 102b, PbRDY and PbIO# remain busy (In-Op). PaIO# remains In-Op due to the execution of the previous AIPO command for plane 102a.

[0204] FIG. 8B Another example timing diagram is shown depicting the issuance of an AIPO memory command to an idle plane while another plane has an in-progress background operation, where FIG. 8A the AIPO memory command does not cause any command pre-processing period c FIG. 8B is similar to FIG. 8B the difference between these two figures is that in FIG. 6B after the issuance of AIPO command 804 for plane 102b at time t802b, only the signals of plane 102b become busy. Thus, FIG. 9A there is no command pre-processing period. Accordingly, the signals corresponding to the unselected planes do not become busy (In-Op), as also discussed with respect to FIG. 9A .

[0205] When an AIPO background operation is in progress in a particular plane (i.e., PxRDY = Ready and PxIO# = In-Op) and an AIPO command is issued for the particular plane having an in-progress background operation

[0206] Assuming a background operation is in progress for at least one plane, such as plane 102a, i.e., for that plane, PaRDY = 1 (e.g., Ready) and PaIO# = 0 (e.g., In-Op). In this scenario, host 130 can issue selected (rather than all) AIPO commands to the plane having a background operation.

[0207] FIG. 6A An example timing diagram is shown depicting the issuance of an AIPO memory command to a plane having an in-progress background operation. For example, in FIG. 9BIn this case, only prior to time 902a, background operations are in progress in plane 102a (i.e., PaRDY = ready, PaIO# = in operation), and the other planes are ready (e.g., PyRDY = PyIO# = ready (idle), where y = b, c, d). At time 902a, an AIPO command 904 for plane 102a is issued by host 130. Thus, from time t902a to time t903a, PxRDY and PxIO# (where x = a,..., d) become busy (in operation) for a short time period (i.e., a command pre-processing period). After the short time period (as discussed with respect to FIG. 9B FIG. 6), PbRDY, PcRDY, PdRDY, PbIO#, PcIO#, and PdIO# transition to ready (idle). Due to the execution of AIPO command 904 for plane 102a, PaRDY and PaIO# remain busy (in operation).

[0208] FIG. 9A Another example timing diagram depicting issuing an AIPO memory command to a plane with a background operation in progress is shown. FIG. 9B Similar to FIG. 9B the difference between these two figures is that in FIG. 6B the case, only the signals of plane 102a become busy (in operation) after AIPO command 904 for plane 102a is issued at time t902b (e.g., FIG. 9A without a command pre-processing period). The signals corresponding to the unselected planes do not become busy for a short time period, as also discussed with respect to FIG. 9B FIG. 6.

[0209] It should be noted that in FIG. 9A and FIG. 9B only some selected types of AIPO memory commands can be allowed to keep plane 102a busy prior to time t902a. Examples of some such selected AIPO memory commands include a cache read random command. For example, a cache read random command is a selected AIPO memory command that can be accepted during a background operation period of a cache read (random) operation. Thus, FIG. 9A and FIG. 9B AIPO command 904 can be, for example, a cache read random command.

[0210] However, there are some other example AIPO memory commands that cannot be issued to a plane with a background operation in progress. For example, a page read command is an AIPO memory command that is not acceptable during a background operation period of a cache read (random) operation (i.e., it can only be executed when there is no existing background operation in progress). Thus, FIG. 10 and FIG. 7The AIPO command 904 is not available for e.g. page read commands.

[0211] There are some commands that can be issued by the host at any time and accepted at the memory device (e.g. system management commands, see Table 1). One example of such a command is a reset command, which can be issued by the host at any time and accepted at the memory device to terminate ongoing operations in one or more planes.

[0212] SCO and AIPO background operations and execution of SCO background operations

[0213] FIG. 7 A timing diagram depicting the issuance of a SCO memory command and the resulting SCO background operation is shown. For example, at time t1001, a SCO command 1004 for plane 102a is issued by the host 130. The PxRDY signals for all planes become busy between time period t1001 and time period t1002 (also referred to herein as the first phase of the plane occupancy period or execution period of the SCO memory command (see FIG. 7 )). Phase 1 can include a SCO foreground operation (phase) in which the plane core is performing an operation involving the cache. In phase 1, since the cache is busy and the host cannot read / write data in / from the cache, PRDY and PIO# = 0 (busy, operation in progress). After phase 1, the cache is free and the host can read / write data in / from the cache, so PRDY returns to 1 and PIO# remains 0. Thus, after time t1002, the PxRDY signals for all planes transition to the ready state. However, the plane operation in progress status signals PxIO# for all planes remain operation in progress until the SCO is completed at t1003, e.g. as discussed with respect to FIG. 10 . As also discussed with respect to FIG. 6A , the time period between time t1002 and time t1003 is referred to as the background operation phase, or phase 2, in which the host can read / write from / to the cache.

[0214] It is noted that during the SCO background operation phase of a SCO memory command, the PxIO# for all planes are in operation, as shown in FIG. 6A . In contrast, for AIPO, the corresponding AIPO background operation phase (see FIG. 6B ) only keeps the PxIO# for the selected plane (i.e. for which the AIPO has been issued) in operation, as shown in FIG. 10 and FIG. 6A .

[0215] Thus, SCO background operations are associated with SCO memory commands, and any such operation will occupy all planes (i.e., for all planes, PxIO# = operation), as shown in FIG. 6B By contrast, AIPO background operations are associated with AIPO memory commands, and any such operation will occupy a particular plane (i.e., for a particular plane, PxIO# = operation), as shown in FIG. 11 and FIG. 10 .

[0216] At a SCO background operation is in progress (i.e., for all planes, PxRDY = ready and PxIO# = operation) and (i) an AIPO command is issued (which becomes invalid) and (ii) an SCO command is issued

[0217] FIG. 10 shows an example timing diagram depicting a SCO background operation in progress (see FIG. 11 , i.e., for all planes, PxRDY = ready and PxIO# = operation) as well as the issuance of an AIPO command 1104a and the issuance of an SCO command 1104b.

[0218] It is noted that when a SCO background operation is in progress (see FIG. 11 for further discussion of SCO background operations), the host 130 can only issue selected operation commands. For example, when a SCO background operation is in progress, the host 130 can not issue an AIPO command 1104a of a selected type (other AIPO commands of selected types can be issued, as discussed below), and thus, FIG. 11 the AIPO command 1104a of is declared invalid. This shows an example of a method in which a second type of memory command (e.g., an AIPO command) is received by a memory while the memory is executing a first type of memory command (e.g., an SCO command) that is simultaneously occupying multiple planes; and in response to receiving the second type of memory command during execution of the first type of memory command, execution of the second type of memory command is denied. However, when a SCO background operation is in progress, the host 130 can effectively issue an SCO command 1104b at t1004, as shown in FIG. 10 . As shown in FIG. 12 , the status of the various signals after time t1104 has been discussed with respect to FIG. 11 .

[0219] Overview of Memory Plane Ready State Signal (PxRDY) and Memory Array Ready State Signal (PxIO#)

[0220] Reference is made to FIG. 11Table 1190 in the Appendix, in an embodiment, the host 130 can check the plane busy status signal PxRDY and the plane operation in status signal PxIO# for an operation.

[0221] If there are no ongoing operations in any plane of the memory 101 (all PxRDY and PxIO# = 1), the host 130 can issue any command to the chip.

[0222] If there is an ongoing AIPO operation in the memory 101, the host 130 must check the PxRDY and PxIO# of the selected plane. If the selected plane is idle (PxRDY and PxIO# = 1, where 102x is the selected plane), the host can issue any AIPO command to the selected plane. If the selected plane is busy and in operation (PxRDY and PxIO# = 0, where 102x is the selected plane), the command issued by the host 130 will not be executed. If the selected plane is ready but there is a background operation (i.e., PxRDY = 1 and PxIO# = 0, where 102x is the selected plane), the host 130 can issue the selected AIPO command to the selected plane.

[0223] If there is an ongoing SCO operation in the chip, the host 130 must check the PxRDY and PxIO# of the selected plane. If the selected plane is busy and in operation (i.e., PxRDY and PxIO# = 0, where 102x is the selected plane), the host can not issue any command that will be accepted by the selected plane. If the selected plane is ready but there is a background operation (PxRDY = 1 and PxIO# = 0, where 102x is the selected plane), the host can only issue the selected SCO command or AIPO command (not all SCO commands or AIPO commands) to the selected plane.

[0224] In an embodiment, SCO system management commands can be issued by the host at any time and accepted at the memory device. AIPO system management commands can not be issued when there is an ongoing background SCO operation, but AIPO system management commands can be issued by the host and accepted at the memory device when there is an ongoing AIPO operation.

[0225] Table 1190 summarizes the use of the PxRDY status signal and the PxIO# status signal for various memory operations, some of which are discussed above.

[0226] As previously discussed herein, each plane has its own ready status - PxRDY and PxIO#. Thus, the ready status of an individual memory plane includes two status bits, one for each of PxRDY and PxIO#.

[0227] PxRDY specifies whether a plane is ready to execute the next command input. For a given memory plane, if PxRDY is busy (PxRDY = 0), then this plane can not receive other commands. On the other hand, if PxRDY is ready (PxRDY = 1), then this plane can selectively receive new commands (or can not receive new commands) based on the command type and other state signals of other planes.

[0228] In an example, when all planes are ready (idle) (all PxRDY = 1 and PxIO# = 1), the memory 101 can receive a SCO operation command, as previously discussed herein.

[0229] In an example, when a selected particular plane is ready (PxRDY = 1) and the plane is not under a SCO background operation (e.g., see FIG. 11 , where the AIPO operation command 1104a is invalid), the memory 101 can receive an AIPO operation command for the particular plane.

[0230] When a plane is under a SCO background operation (e.g., for all planes, PxRDY = 1 and PxIO# = 0, see FIG. 13 ), only limited or selected types of new commands can be received. An AIPO operation command can not be included in such limited or selected types of commands (e.g., see FIG. 13 , where the AIPO operation command 1104a is invalid).

[0231] As discussed, PxIO# provides in-plane operation status of a corresponding memory operation. If PxIO# is in operation (PxIO# = 0) for a particular plane, then the memory operation of this plane is still in progress. If PxIO# is idle (PxIO# = 1) for a particular plane, then the plane is not under any operation.

[0232] Reset Plane Command

[0233] A "reset plane" command can be supported by the memory 101, where the reset plane command will abort any AIPOs being executed in the selected plane that issued the reset plane command. FIG. 14A The configuration (e.g., cycle type) of the reset plane command is shown. As FIG. 14BAs shown in FIG. 13, the reset plane command includes a command cycle followed by one or more (e.g., three) address cycles, where the addresses included in the address cycles indicate one or more addresses (e.g., column addresses) of the memory plane to be reset. In an example, after the memory 101 receives this command, the memory 101 aborts any AIPO being performed in the memory plane identified by the addresses in the address cycles. The reset plane command can be issued by the host and accepted by the memory device when the PxRDY status signal and the PxIO# status signal indicate a busy state, in the case of an ongoing AIPO operation, but not in the case of an ongoing SOC operation. The plane reset command can also be issued during a foreground operating period or a background operating period.

[0234] AIPO memory commands issued to memory planes that do not have an ongoing background operation (other planes can have AIPO background operations)

[0235] FIG. 14A and FIG. 6A Timing diagrams 1400a and 1400b, respectively, are shown depicting the scenario of AIPO memory commands issued to a memory plane that does not have an ongoing background operation while one or more other memory planes can have an ongoing AIPO background operation.

[0236] In the example of FIG. 14, FIG. 14A At time t1402a, an AIPO command 1404a for plane 102b is issued. Prior to time t1402a, PaRDY is busy and PaIO# is in operation, indicating that an AIPO is being performed in plane 102a. The AIPO command 1404a is issued to a non-busy plane, such as plane 102b, where PbRDY = ready at the time the AIPO command 1404a is issued. In an example, the AIPO command 1404a can be any of the appropriate AIPO commands listed in Table 1 discussed previously, such as a page read operation.

[0237] As discussed previously with respect to FIG. 14B In the example of FIG. 14, FIG. 14A After the AIPO command 1404a is issued, all planes become busy for a short period of time (e.g., between time t1402a and time t1403a), which is the command pre-processing period. After the command pre-processing period, the PxRDY and PxIO# of plane 102c and plane 102d become ready (idle). The memory plane 102b processes the AIPO command 1404a command starting at time t1403a. Plane 102a remains busy due to the ongoing operation that started prior to time 1402a.

[0238] In this embodiment, new commands are not allowed to be issued via host 130 during the command preprocessing period. As discussed, after the command preprocessing period, the plane busy state signals of planes 102c and 102d are switched back to the ready state.

[0239] FIG. 14A Alternative embodiments are shown (e.g., they may be...) FIG. 14B Alternatives to the embodiments shown). For example, in FIG. 14B In this context, there exists a command preprocessing period immediately following the issuance of AIPO command 1404a, during which all planes become busy (e.g., for x = a, ..., d, PxRDY and PxIO#). In contrast, FIG. 14A This command does not have a preprocessing period. For example, in FIG. 14B In this embodiment, only the selected plane (to which AIPO command 1404b is issued by at time t1402b) becomes busy from time t1402b. Other unselected planes (e.g., plane 102c, plane 102d) remain ready—that is, the PcRDY status signal, PdRDY status signal, PcIO# status signal, and PdIO# status signal are not affected by AIPO command 1404b, and these status signals remain available.

[0240] In the example, FIG. 14A The embodiment is more FIG. 14A The embodiments are relatively easier to use for circuit implementation (e.g. because...) FIG. 15A The embodiments have a relatively simpler command interface. However, in FIG. 15B There may be a slight performance loss in the embodiment because the host 130 needs to wait during the command preprocessing period, during which no new commands issued by the host 130 will be executed.

[0241] Other examples of AIPO memory commands

[0242] If an AIPO background operation is in progress in a specific plane (such as the first plane, where PxRDY = Ready and PxIO# = In Operation for the first plane), then an AIPO command (such as a page read or cache read command) may be issued by the host to another plane (such as the second plane) that does not have any background operation (for the second plane, PxRDY = PxIO# = Ready (Idle)) and accepted at the memory device.

[0243] If an AIPO background operation is in progress in a particular plane, such as the first plane where for the first plane, PxRDY = ready and PxIO# = operating, only selected AIPO commands, such as cache read commands, can be issued by the host to the first plane with the background operation and accepted at the memory device. For example, with reference to Table 1 discussed previously herein, a cache read random command is an AIPO command that is allowed during a background operation period.

[0244] There can be other AIPO memory commands, such as page read commands, that are not allowed to be issued to a plane with an ongoing AIPO background operation. The type of commands that can be issued by the host and accepted at the memory device during an AIPO background operation can depend on the particular implementation of the memory device.

[0245] If an AIPO background operation is in progress, SCO commands (e.g., block erase commands) are not allowed.

[0246] FIG. 15A and FIG. 15B Timing diagram 1500a and timing diagram 1500b respectively show various example scenarios depicting the issuance of AIPO commands. It should be noted that, FIG. 15A shows a scenario where an AIPO command is followed by a command pre-processing period, while FIG. 6A does not have a command pre-processing period.

[0247] With reference to FIG. 15B Prior to time t1501a, none of the planes are busy (i.e., for all planes, PxRDY = PxIO# = idle). At time t1501a, an AIPO command 1504a is issued for plane 102a. Thus, there is a command pre-processing period between time t1501a and time t1502a during which all planes are busy (i.e., for all planes, PxRDY = PxIO# = operating).

[0248] At time t1502a, plane 102b, plane 102c, and plane 102d transition to ready (idle). At time t1503a, plane 102a becomes ready (e.g., as discussed with respect to t603a of FIG. 15A ).

[0249] At t1504a, the host 130 issues another AIPO command 1804b for plane 102b. Similar to the previous discussion, there is a command pre-processing period between time t1504a and time t1505a during which all planes are busy (i.e., for all planes, PxRDY = PxIO# = busy (in operation)). At time t1505a, plane 102a, plane 102c, and plane 102d are ready (i.e., PaRDY = PcRDY = PdRDY = ready), but a background operation is still in progress in plane 102a for execution of AIPO command 1504a.

[0250] At t1506a, the host 130 issues another AIPO command 1504c for plane 102a. Similar to the previous discussion, there is a command pre-processing period between time t1506a and time t1507a during which all planes are busy (i.e., for all planes, PxRDY = PxIO# = busy (in operation)). At time t1507a, plane 102c and plane 102d are ready (i.e., PcRDY = PdRDY = ready (idle)), but operations are still in progress in plane 102a and plane 102b for execution of AIPO command 1504c and AIPO command 1504b, respectively.

[0251] Thus, as previously discussed, if an AIPO background operation is in progress in a particular plane (such as the first plane for which PxRDY = ready and PxIO# = in operation), an AIPO command (such as a page read or cache read command) can be issued by the host to another plane (such as the second plane for which PxRDY = PxIO# = ready (idle)) that does not have any background operations and accepted at the memory device. AIPO command 1504b for plane 102b issued at time t1504a is an example of such an AIPO command.

[0252] As previously discussed, if an AIPO background operation is in progress in a specific plane (such as the first plane, where PxRDY = Ready and PxIO# = In Operation for the first plane), then only the selected AIPO command (such as a cache read random command from Table 1 discussed earlier herein or another category 5 command) can be issued by the host to the first plane with the background operation and accepted at the memory device. For example, at time t1506a, an AIPO command 1504c is issued for plane 102a while plane 102a is still undergoing an AIPO background operation (i.e., PaRDY = Ready, PaIO# = In Operation). Therefore, AIPO command 1504c can be a cache read random command from Table 1 or another category 5 command, but not a page read from Table 1 or another category 4 command.

[0253] FIG. 15A The timing diagram 1500b is partially similar to FIG. 15B Timing diagram 1500a. The difference between these two timing diagrams is... FIG. 6B The timing diagram 1500a includes the command preprocessing period. FIG. 15B Timing diagram 1500b does not have the command preprocessing period. For example, similar to FIG. 15A , FIG. 6B The timing diagram 1500b does not have a command preprocessing period. Based on... FIG. 15B and FIG. 15B The argument FIG. 15A The timing diagram 1500b will be obvious to those skilled in the art. FIG. 16A Includes time t1501b, time 1503b, time 1504b, and time 1506b, which are related to FIG. 6B The corresponding time in the text is similar.

[0254] Other examples of SCO memory commands

[0255] If no background operations are in progress, SCO commands (e.g., page programming commands or block erase commands) can be issued by the host and received at the memory device only when all planes are ready (idle) (i.e., for all planes, PxRDY = PxIO# = ready (idle)). After the SCO command is issued, all planes will become busy (operating) (i.e., for all planes, PxRDY = PxIO# = busy (operating)).

[0256] FIG. 16AA timing diagram 1600a depicting an example of a SCO command is shown. At t1601a, an AIPO command 1604a for plane 102a is issued. This is followed by a command pre-processing period between time t1601a and time t1602a (but in another example, such a command pre-processing period can not exist, as discussed with respect to FIG. 6A ). Thus, after time t1602a, PaRDY = PaIO# = busy (in operation), and all other status signals are ready. At time t1604a, execution of the AIPO command 1604a for plane 102a is completed, and both PaRDY and PaIO# become ready (idle) at time t1604a. Note that although in this example of FIG. 16A , both PaRDY and PaIO# become ready (idle) at the same time, PaIO# can become idle after PaRDY becomes ready, as seen in FIG. 7 .

[0257] Also as shown in FIG. 16A , at time t1603a (e.g., which is between time t1602a and time t1604a), a SCO command 1604b for plane 102b is issued. Since not all planes are ready at time t1603a (e.g., at time t1603a PaRDY = busy), the SCO command 1604b for plane 102b is invalid, and is not executed by memory 101.

[0258] After all planes are ready (idle) from time t1604a, another SCO command 1604c for plane 102b is issued at time t1605a. Note that at this time, all planes are ready. Thus, the SCO command 1604c is valid, and is executed from time t1605a.

[0259] As discussed with respect to FIG. 16A , in FIG. 16B , once the SCO command 1604c is issued, all planes will become busy (in operation) during a plane occupancy period, e.g., between time t1605a and time t1606a (i.e., for x = a,..., d, PxRDY = PxIO# = busy (in operation)). At t1606a (i.e., after the plane occupancy period ends), all planes transition to ready (i.e., for x = a,..., d, PxRDY = ready), but the SCO background operation is in progress in all planes (i.e., for x = a,..., d, PxIO# = operation). Finally, at time t1607a, the SCO background operation is completed, and for x = a,..., d, PxIO# = idle.

[0260] It is noted that between time t1605a and time t1606a, during the plane occupancy period, all planes are depicted as busy (i.e., for x = a,..., d, PxRDY = busy), but the SCO command 1604c is for a specific plane 102b. That is, although planes 102a, 102c, 102d can not actively participate in the SCO command 1604c, planes 102a, 102c, 102d are still depicted as being busy or in operation to avoid any command entry until memory 101 is ready for the next command. Thus, the time period between time t1605a and time t1606a, when the planes are depicted as occupied, is also referred to herein as a plane occupancy period to avoid any command entry until memory 101 is ready for the next command.

[0261] It is noted that any AIPO (or SCO) operation issued during the plane occupancy period is declared invalid. For example, in FIG. 16B , an AIPO command 1604d for a plane is issued at time t1605al, which is during the plane occupancy period. Thus, this command is declared invalid.

[0262] FIG. 16A Another timing diagram 1600b depicting examples of SCO commands is shown.

[0263] FIG. 16A Timing diagram 1600b of FIG. 16 is partially similar to timing diagram 1600a of FIG. 15. FIG. 16B The difference between these two timing diagrams is that FIG. 6B Timing diagram 1600a of FIG. 15 includes a command pre-processing period, FIG. 16B Timing diagram 1600b of FIG. 16 does not have the command pre-processing period. For example, similar to FIG. 16A , FIG. 6B Timing diagram 1600b of FIG. 16 does not have the command pre-processing period. Based on the discussion regarding FIG. 16B and FIG. 17 Timing diagram 1600b of FIG. 16 will be apparent to those skilled in the art. FIG. 16B

[0264] FIG. 18A ​A timing diagram 1700 depicting other examples of SCO commands is shown, and also depicts that some AIPO memory commands can not be issued while a plane is executing a SCO background operation. In timing diagram 1700, a SCO command 1704a for plane 102a is issued at time t1701, whereby all planes become busy (in operation) during the previously discussed plane occupancy period, which occurs between time t1701 and time t1702. At time t1702, for x = a,..., d, PxlRDY transitions to ready, i.e., all planes become ready. Note that the SCO background operation is still in progress after time t1702, and thus, for x = a,..., d, PxlO# = in operation.

[0265] At time t1703 (e.g., while the SCO background operation is still in progress), an AIPO command 1704b for plane 102b is issued. Note that if the SCO background operation is in progress, then memory 101 can not be able to execute AIPO memory commands, such as page read commands. Thus, AIPO command 1704b for plane 102b is invalid.

[0266] However, if the SCO background operation is in progress, then memory 101 can be able to execute selected SCO memory commands, such as the cache program command of Table 1 or another category 2 SCO command previously discussed herein. Note that if the SCO background operation is in progress, then category 1 SCO commands can not be validly received and executed.

[0267] For example, at time t1704 (e.g., while the SCO background operation is still in progress), a SCO command 1704c (such as the cache program command of Table 1 or another category 2 SCO command) for plane 102b is issued. This command is valid, and is executed by memory 101. For example, during the corresponding plane occupancy period beginning at time t1704, all planes become busy (in operation). The portion of the timing diagram after time t1704 is similar to the portion discussed with respect to FIG. 18B with respect to the portion discussed, and thus, is not discussed in further detail.

[0268] FIG. 18A and FIG. 18B Timing diagrams 1800a and 1800b depicting other examples of SCO commands are shown, and also depict that some AIPO memory commands can be issued and executed concurrently with a plane executing a SCO background operation.

[0269] Note that, FIG. 17 and FIG. 17 A scenario opposite to that of FIG. 18A is shown. For example, in FIG. 18BIn the case of the AIPO command 1704b, the plane is not allowed to be performing a SCO background operation. In contrast, in the case of the AIPO command 1804b, the plane is allowed to be performing a SCO background operation. FIG. 17 In the case of the AIPO command 1704b, the plane is not allowed to be performing a SCO background operation. In contrast, in the case of the AIPO command 1804b, the plane is allowed to be performing a SCO background operation. FIG. 18A In the case of the AIPO command 1704b, the plane is not allowed to be performing a SCO background operation. In contrast, in the case of the AIPO command 1804b, the plane is allowed to be performing a SCO background operation.

[0270] The circuitry within the memory 101 implementing the scenario of FIG. 18B may be different than the circuitry within the memory 101 implementing the scenario of FIG. 17 and FIG. 18A Thus, whether or not the AIPO memory command is allowed while the plane is performing a SCO background operation is implementation specific - based on the design of the memory 101. When the plane is performing a SCO background operation, the memory 101 can support selectively allowing (or disallowing) AIPO memory commands.

[0271] In another example, the AIPO command 1704b of FIG. 18A is different than the AIPO command 1804 of FIG. 17 Thus, the AIPO command 1804b of FIG. 6A (e.g., category 4 command of Table 1) is allowed while the AIPO command 1704b of FIG. 18B (e.g., category 5 command of Table 1) is disallowed.

[0272] In timing diagram 1800a, a SCO command 1804a is issued for plane 102a at time t1801a, whereby all planes become busy during the plane occupancy period previously discussed, which occurs between time t1801a and time t1802a. At time t1802a, PXRDY transitions to ready for x = a,..., d, i.e., all planes become ready. Note that the SCO background operation is still in progress after time t1802a, and thus, PIO# = operation in progress for x = a,..., d.

[0273] At time t1803a (e.g., while the SCO background operation is still in progress), an AIPO command 1804b is issued for plane 102b. In the case of the AIPO command 1804b of FIG. 18A (e.g., category 4 command of Table 1) is allowed while the AIPO command 1704b of FIG. 18A (e.g., category 5 command of Table 1) is disallowed. Thus, the AIPO command 1804b for plane 102b is allowed. Depending on the implementation of the memory system, a page read command can or can not be issued / accepted during the cache program background operation period. A page read command cannot be issued during the cache read background operation.

[0274] Thus, from time 1803a, all planes become busy during the command pre-processing period until time t1804a, after which plane 102a, plane 102c, plane 102d become available. Note that a SCO background operation is in progress in all planes, e.g., to execute SCO command 1804a for plane 102a. At time t1806a, plane 102b is ready (e.g., PbRDY), e.g., as discussed with respect to FIG. 18B time t603a. Note that a SCO background operation can still be in progress in all planes after time t1806a.

[0275] FIG. 6B Timing diagram 1800b is partially similar to timing diagram 1800a of FIG. 18B The difference between these two timing diagrams is that timing diagram 1800a of FIG. 18A includes a command pre-processing period, FIG. 6B Timing diagram 1800b of FIG. 18B , FIG. 18B does not have a command pre-processing period. Based on the discussion with respect to FIGS. 19A-19D and FIGS. 19A-19D Timing diagram 1800b of FIG. 19A will be apparent to those skilled in the art. FIG. 19B includes SCO command 1808a for plane 102a, AIPO command 1808b for plane 102b, and times t1801b, t1802b, t1803b, and t1806b.

[0276] FIG. 19C An example timing diagram showing the plane busy state signals P0-P3xRDY and the plane in operation state signals P0-P3xIO# of planes P0-P3 in response to receiving a category of commands that can be implemented in various embodiments is shown. Note that in the timing diagrams of FIG. 19D as in the previous figures, a dashed rectangle corresponds to the associated signal being busy, and an unshaded rectangle corresponds to the associated signal being ready (i.e., not busy), as shown in the legend.

[0277] FIG. 20 The timing of the state signals of a SCO command (category 1 in Table 1) to be executed without a background operation is illustrated. Upon receiving the SCO command for plane P0, all state signals are in the ready (idle) state. During execution of the command, all state signals are in the busy (in operation) state until the command is completed. The plane busy state signals and the plane in operation state signals of all planes are in the busy (in operation) state during the operation period.

[0278] FIG. 21 The timing of the state signals for a SCO command (as in category 2 of Table 1) to be executed with background operations is illustrated, which has two operational periods. Upon receiving a SCO command for plane PO, all state signals are in the ready (idle) state. After receiving the command, the plane busy state signals for all planes transition to the busy state during a busy period and transition to the ready state at the end of the busy period (this busy period is part of the plane occupancy period, which can include both the foreground and background operational periods of the SCO command). During the background operational period, the plane in operation state signal remains in the in operation state during a long interval after the end of the busy period.

[0279] FIG. 22 The timing of the state signals for an AIPO command (as in category 4 of Table 1) to be executed without background operations is illustrated, which has two operational phases. Upon receiving an AIPO command for plane PO, all state signals are in the ready (idle) state. After receiving the command, the plane busy state signals for all planes transition to the busy state. In addition, after receiving the command, the plane in operation state signals for all planes transition to the in operation state. At the end of the command processing interval (command pre-processing period), the plane busy signal and the plane in operation signal for the unselected planes transition to the ready (idle) state. The plane busy state signal and the plane in operation state signal for the selected plane PO remain busy (in operation) during the operation interval.

[0280] FIG. 23The timing of the status signals for an AIPO command (e.g., category 5 of Table 1) that can be executed with a background operation is shown, which has three operation phases, including: a command processing phase, where all plane busy status signals and plane operation in status signals are busy (in operation); a data transfer phase, where for unselected planes, the plane busy status signals and plane operation in status signals are ready (idle), and the plane busy status signals and plane operation in status signals for the selected plane remain busy (in operation); and a background operation phase, where the plane busy status signal for the selected plane transitions to ready and the plane operation in status signal for the selected plane remains in operation until completion. Upon receiving an AIPO command for plane PO, all status signals are in the ready (idle) state. After receiving the command, the plane busy status signals for all planes transition to the busy state. Also, after receiving the command, the plane operation in status signals for all planes transition to the in operation state. At the end of the cache operation interval, the plane busy status signal for the selected plane PO transitions to the ready state. However, the plane operation in status signal for the selected plane remains in operation for a longer operation interval. The plane busy status signals for unselected planes and the plane operation in status signals for unselected planes transition to the ready (idle) state at the end of the command processing interval.

[0281] FIG. 22 An example of issuing a second SCO command during the operation of a first SCO command is shown. After issuing SCO command 1, the chip becomes busy only in phase 1 (all PxRDY = 0), then the chip returns to ready (all PxRDY = 1) after phase 1 is complete. A new SCO command 2 can be issued by the host and accepted at the memory device, even though phase 2 for the previous command is still in progress. However, the second SCO operation does not start until the first command operation is finished, so it still satisfies the SCO criteria. In other words, there is an "overlapping operation" period during which the second SCO operation does not start until the first command operation is finished.

[0282] FIG. 23 Another example of an AIPO command that can be issued by the host and accepted at the memory device, which suspends the operation of a previous SCO command, is shown. After issuing SCO command 1, the chip becomes busy only in phase 1 (all PxRDY = 0), then the chip returns to ready (all PxRDY = 1) after phase 1 is complete. A new AIPO command 2 can be issued by the host and accepted at the memory device, even though phase 2 for the previous command is still in progress. In this case, there is an overlapping operation period in which the previous operation is suspended to perform the new command and automatically resumes the old operation after the new operation is complete. This can be a special case that applies when one command has a higher priority than the other command.

[0283] Various example configurations that can be supported by embodiments of the plane busy status signal and the plane operation in progress status signal are described herein. One example can be characterized as follows:

[0284] 1. If there is no background operation (PxRDY = PxIO# = 1).

[0285] i. If the selected plane is ready (idle) (PxRDY = PxIO# = 1), then for the selected plane, an AIPO command (including "with" and "without" background operation AIPO commands) can be issued by the host and accepted at the memory device.

[0286] ii If all planes are ready (idle) (PxRDY = PxIO# = 1), then a SCO command (including "with" and "without" background operation SCO commands) can be issued by the host and accepted at the memory device.

[0287] 2. If there is a background operation (PxRDY = 1 and PxIO# = 0).

[0288] i. If the background operation is a "with" background operation AIPO operation for the selected plane, then for the selected plane, the selected AIPO command can be issued by the host and accepted at the memory device.

[0289] ii. If the background operation is a "with" background operation AIPO operation for an unselected plane, then for the selected plane, an AIPO command (including "with" and "without" background operation AIPO commands) can be issued by the host and accepted at the memory device.

[0290] iii. If the background operation is a "with" background operation SCO operation, then the selected SCO or AIPO command can be issued by the host and accepted at the memory device.

[0291] iv. Note that the selected command referred to here does not only a "with" (SCO / AIPO) command, it can also include a "without" (SCO / AIPO) command.

[0292] 3. If the selected plane is busy (in operation) (PxRDY = PxIO# = 0), then an AIPO or SCO command cannot be issued by the host to the selected plane and accepted at the memory device.

[0293] Thus, in some configurations, "with" and "without" background operation commands can be issued by the host and accepted at the memory device when there is no background operation in progress (PxRDY = PxIO# = 1).

[0294] Further, the selected commands can be issued by the host during background operations (PxRDY = I and PxIO# = 0) and accepted at the memory device, including commands that are not "with" background operation commands.

[0295] The techniques described herein include a chip device (e.g., a memory system described herein) having multiple planes that support synchronous chip commands for type 1 operations (operations of a first type, selecting operations of a first type, commands of a first type, etc.) and asynchronous independent commands for type 2 operations (operations of a second type, selecting operations of a second type, commands of a second type, etc.). Example commands include commands to continue or abort read operations and write operations of a memory array.

[0296] Type 1 commands select one or more planes for a type 1 operation. Type 2 commands select only one plane for a type 2 operation.

[0297] Both type 1 operations and type 2 operations include foreground operations, some of which include additional background operations.

[0298] Type 1 operations can be synchronous chip operations SCO, in which only one operation is performed at a time for one or more selected planes, and the operation starts and ends simultaneously for all selected planes. Type 2 operations can be asynchronous plane operations AIPO, in which the operation for each plane is performed asynchronously and independently from the operations for other planes.

[0299] In examples described herein, each plane provides one ready busy status signal PxRDY to indicate when the plane is ready for a next command, and another idle status signal PxIO# to indicate when there is no ongoing operation. For type 1 operations, since it is a chip-based operation, all planes including both operating (busy) planes and idle (ready) planes have the same status signals for both PxRDY (busy / read) and PxIO# (operating / idle). For type 2 operations, except for the first phase of the foreground operation period for some embodiments, the plane busy status signal PxRDY and the plane operating status signal PIO# of one plane are independent from the status of another plane.

[0300] Type 2 operations can be Asynchronous Plane Operations (AIPO) in which the operations for each plane are performed asynchronously and independently of the operations for other planes. Type 2 operations can have a first embodiment that performs only foreground operations and a second embodiment that performs background operations. Type 2 operations start after the chip receives a Type 2 command sequence with one selected plane (target plane). Type 2 operations start with a foreground operation in the selected plane, and during the foreground operation period, for the selected plane, the plane busy status signal PxRDY is set to busy and the plane in operation status signal PxIO# is set to in operation (see FIG. 22 and FIG. 23 ). After the foreground operation is completed, some operations are completed and the plane busy status signal PxRDY returns to ready and the plane in operation status signal PxIO# returns to idle ( FIG. 23 ). Some operations continue with a background operation, PxRDY returns to ready and PxIO# remains in operation ( FIG. 22 ). After the background operation is completed, PxIO# returns to idle.

[0301] While a Type 2 operation is in progress for a selected plane, new Type 2 commands are allowed to be issued to unselected planes ( FIG. 23 ). New Type 2 commands are prohibited from being issued to the selected plane during the foreground operation period of the selected plane (PxRDY is busy). Selected Type 2 commands are allowed to be issued for the selected plane during the background operation period of the selected plane (PxRDY is ready but PIO# is in operation) ( FIG. 22 ). In FIG. 23 , the overlapping operation period is the portion of the period between t4 and t6. During the overlapping operation period, both PRDY and PIO# are busy.

[0302] FIG. 24 is a diagram that shows in the upper portion of the diagram the logic for accepting and rejecting commands for planes P0 through P3, and in the lower portion of the diagram the ready / busy (idle / in operation) status of the status bit PxRDY and the status bit PxIO# for the case where a Type 2 command (AIPO) for plane P0 is received at time t0 that does not include a background operation, and a second Type 2 command for P1 is received at time t1 that does not include a background operation. Prior to time t0, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command. At time t0, the device starts a foreground operation in plane P0, and sets the status bit P0RDY and the status bit P0IO# for plane P0 to the busy (in operation) state. The status bits for planes P1 through P3 remain in the ready (idle) state.

[0303] Between time tO and time tl, the logic for accepting and rejecting commands can accept other type 2 commands for planes PI through P3. No commands will be accepted for plane PO. Type 1 commands will be rejected during this interval.

[0304] At time tl, a second type 2 command is received for plane PI. The device accepts the command and starts a foreground operation in plane PI. In addition, the device sets the status bit PI RDY and the status bit PI IO# of plane PI to the busy (in operation) state. The status bits of planes P2 through P3 remain in the ready (idle) state. The status bits of plane PO remain in the busy (in operation) state corresponding to the execution of the foreground operation of the first command. No commands will be accepted for plane PO or plane PI. Type 1 commands will be rejected during this interval.

[0305] At time t2, the foreground operation of the first command completes and the status bits PO RDY and PO IO# of plane PO change to the ready (idle) state, allowing type 2 commands for plane PO. The foreground operation of the second command completes at a later time, and the status bits and the logic for accepting and rejecting commands change in a similar manner as described for the first command.

[0306] FIG. 25 To summarize, the figure shows in the upper portion of the figure the logic for accepting and rejecting commands for planes PO through P3, and in the lower portion of the figure the ready / busy (idle / in operation) states of the status bits Px RDY and Px IO# for the following cases: receiving at time tO a type 2 command for plane PO that includes both a foreground operation and a background operation (AIPO), receiving at time tl a second type 2 command for PI that includes both a foreground operation and a background operation, receiving at time t4 a third type 2 command for PO that includes both a foreground operation and a background operation. Prior to time tO, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command.

[0307] At time tO, the device starts a foreground operation in plane PO, and sets the status bits PO RDY and PO IO# of plane PO to the busy (in operation) state. The background operation starts at the start of or during the operation of PO IO# in the operation state. The status bits of planes PI through P3 remain in the ready (idle) state. The device cannot accept new commands for plane PO. The device can accept new type 2 commands for planes PI through P3.

[0308] At time t1, the device starts foreground operation in plane P1, and sets the status bit P1RDY and the status bit P1IO# of plane P1 to busy (in operation) state. The background operation starts at or during the busy state of P1IO#. The status bits of plane P2 and plane P3 remain in ready (idle) state. The status bits of P0 remain unchanged. The device cannot accept new commands for plane P0 or plane P1. The device can accept new type 2 commands for plane P2 and plane P3.

[0309] At time t2, the foreground operation in plane P0 is completed, and the P0RDY status bit changes to ready state. The status bits of plane P1 to plane P3 remain unchanged. At this time, the device can accept selected type 2 commands for plane P0.

[0310] At time t3, the foreground operation in plane P1 is completed, and the P1RDY status bit changes to ready state. The status bits of plane P0, plane P2, and plane P3 remain unchanged. At this time, the device can accept selected type 2 commands for plane P1.

[0311] At time t4, a third type 2 command for plane P0 is received. The device starts an overlapping operation period, in which the foreground operation of P0 is on hold until the background operation of the first type 2 command for plane P0 is completed, and sets the status bit P0RDY and the status bit P0IO# of plane P0 to busy (in operation) state. In this example, the background operation of the first type 2 command for plane P0 is not yet completed. Therefore, there is an overlap between the operation order of the first command and the third command. The foreground operation of the third command starts during the busy state of P0RDY when the memory operation performed according to the first command releases the resource. The status bits of plane P2 and plane P3 remain in ready (idle) state. The status bits of P1 remain unchanged. The device cannot accept new commands for plane P0. The device can accept selected type 2 commands for plane P1. The device can accept new type 2 commands for plane P2 and plane P3.

[0312] At time t5, the background operation in plane P1 is completed, and the P1IO# status bit changes to ready state. The status bits of plane P0, plane P2, and plane P3 remain unchanged. At this time, the device can accept type 2 commands for plane P1.

[0313] At time t6, the foreground operation performed in response to the third command in plane P0 is complete and the P0RDY status bit changes to the ready state. The status bits for planes P1, P2, and P3 remain unchanged. At this time, the device can accept a select type 2 command for plane P0 and type 2 commands for planes P1, P2, and P3. The background operation performed in response to the third command continues until it is complete, at which time (not shown in the figure) the P0IO# status bit will change to the idle state.

[0314] In the embodiments described with reference to FIG. 24 and FIG. 25 In the embodiments described with reference to

[0315] FIG. 26 and FIG. 27 represents the logic for accepting and rejecting commands and for setting and resetting the status signals of type 2 commands, where the foreground operation is performed in a manner that requires the status of unselected planes to be changed to the busy (in operation) state during the first phase of the operation of the command.

[0316] FIG. 28 is a diagram that shows in the upper portion of the diagram the logic for accepting and rejecting commands for planes P0 through P3 and in the lower portion the ready / busy (idle / in operation) states of the status bits PxRDY and the status bits PxIO# for the following cases: a type 2 command for plane P0 (AIPO) is received at time t0 that does not contain a background operation and a second type 2 command for P1 is received at time t2 that does not contain a background operation. Prior to time t0, all of the status bits are in the ready (idle) state and the control logic on the memory device can accept any type of command. At time t0, the device starts a foreground operation in plane P0 and sets the status bits PxRDY and the status bits PxIO# for planes P0 through P3 to the busy (in operation) state.

[0317] At time t1, the first phase of the operation of the command for plane P0 is complete and the status bits for planes P1 through P3 change to the ready (idle) state.

[0318] Between time t0 and time t1, the logic for accepting and rejecting commands rejects all commands.

[0319] At time tl, the logic can accept other type 2 commands for planes PI through P3. No commands will be accepted for plane PO. During this interval, type 1 commands will be rejected.

[0320] At time t2, a second type 2 command is received for plane PI. The device accepts the command and starts at the foreground operation in plane PI. In addition, the device sets the status bits PxRDY and PxIO# for planes P2 and P3 to the busy (in operation) state. The status bit for plane PO remains in the busy (in operation) state corresponding to the execution of the foreground operation of the first command. No commands will be accepted for plane PO, plane PI, plane P2, or plane P3.

[0321] At time t3, the first phase of the operation of the command for plane PI is complete and the status bits for planes P2 and P3 change to the ready (idle) state. The status bit for plane PO remains unchanged due to the ongoing operation.

[0322] Between time t2 and time t3, the logic for accepting and rejecting commands rejects all commands.

[0323] At time t3, the logic can accept other type 2 commands for planes P2 and P3. No commands will be accepted for planes PO through PI. During this interval, type 1 commands will be rejected.

[0324] At time t4, the foreground operation of the first command is complete and the status bits PO RDY and P0IO# for plane PO change to the ready (idle) state, allowing type 2 commands to be accepted for plane PO. The foreground operation of the second command is complete at a later time and the status bits and the logic for accepting and rejecting commands change in a similar manner as described for the first command.

[0325] FIG. 29 To illustrate, it shows in the upper portion of the figure the logic for accepting and rejecting commands for planes PO through P3 and in the lower portion of the figure the ready / busy (idle / in operation) states of the status bits PxRDY and PxIO# for the following cases: a type 2 command for plane PO (AIPO) containing two foreground operations and a background operation is received at time to, a second type 2 command for PI containing two foreground operations and a background operation is received at time t2, a third type 2 command for PO containing two foreground operations and a background operation is received at time t6. Prior to time to, all status bits are in the ready (idle) state and the control logic on the memory device can accept any type of command.

[0326] At time tO, the device starts a foreground operation in plane P0, and sets all plane status bits PxRDY and status bits PxIO# to busy (in operation) state. The background operation starts at or during the start of P0IO#'s in operation state. The device cannot accept new commands for planes P0 through P3.

[0327] At time t1, the first phase of the operation of the command for plane P0 is complete, and the status bits of planes P1 through P3 change to ready (idle) state.

[0328] Between time tO and time t1, the logic for accepting and rejecting commands rejects all commands.

[0329] At time t1, the logic can accept other type 2 commands for planes P1 through P3. No commands for plane P0 will be accepted. Type 1 commands will be rejected during this interval.

[0330] At time t2, the device starts a foreground operation in plane P1 in response to a second command for plane P1, and sets the status bits of planes P1 through P3 to busy (in operation) state. The background operation starts at or during the start of P1IO#'s in operation state. The status bits of P0 remain unchanged. The device cannot accept new commands for plane P0, plane P1, plane P2, or plane P3.

[0331] At time t3, the first phase of the operation of the command for plane P1 is complete, and the status bits of planes P2 and P3 change to ready (idle) state.

[0332] Between time t2 and time t3, the logic for accepting and rejecting commands rejects all commands.

[0333] At time t3, the logic can accept other type 2 commands for planes P2 and P3. No commands for planes P0 and P1 will be accepted. Type 1 commands will be rejected during this interval.

[0334] At time t4, the foreground operation in plane P0 is complete, and the P0RDY status bit changes to ready state. The status bits of planes P1 through P3 remain unchanged. At this time, the device can accept select type 2 commands for plane P0.

[0335] At time t5, the foreground operation in plane P1 is complete, and the P1RDY status bit changes to ready state. The status bits of planes P0, P2, and P3 remain unchanged. At this time, the device can accept select type 2 commands for planes P0 and P1.

[0336] At time t6, a third type 2 command for plane P0 is received. The device starts an overlap operation period in which foreground operations for P0 are on hold until the background operation for the first type 2 command for plane P0 is completed, and the status bits for planes P0 through P4 are set to busy (in operation) state. In this example, the background operation for the first type 2 command for plane P0 and the background operation for the second type 2 command for plane P1 are not completed. Thus, there is an overlap between the background operations for the first and third commands for plane P0. The operation for the third command is started during the busy state of P0RDY when the memory operation performed in accordance with the first command frees up resources. The device cannot accept new commands for planes P0 through P3.

[0337] At time t7, the first phase of the operation for the third command for plane P0 is completed, and the status bits for planes P2 through P3 change to ready (idle) state. The P1IO# status bit for plane P1 remains in operation due to the background operation performed in response to the second command. Between time t6 and time t7, the logic for accepting and rejecting commands rejects all commands.

[0338] At time t7, the logic can accept other type 2 commands for planes P2 and P3. A select type 2 command for plane P1 can be accepted. No command for plane P0 will be accepted. Type 1 commands will be rejected during this interval.

[0339] At time t8, the foreground operation performed in response to the third command in plane P0 is completed, and the P0RDY status bit changes to ready state. The status bits for planes P1, P2, and P3 remain unchanged. At this point, the device can accept select type 2 commands for planes P0 and P1, and all type 2 commands for planes P2 and P3. The background operation performed in response to the third command continues until it is completed, at which point (not shown in the figure) the P0IO# status bit will change to idle state.

[0340] At time t9, the background operation in plane P1 is completed, and the P1IO# status bit changes to idle state. The status bits for planes P0, P2, and P3 remain unchanged. At this point, the device can accept type 2 commands for planes P1, P2, and P3. Only select type 2 commands for plane P0 are accepted.

[0341] FIG. 1BFor the figure, it shows in the upper part of the figure the logic for accepting and rejecting commands for planes P0 to P3, and in the lower part of the figure the ready / busy (idle / in operation) status of the status bit PxRDY and the status bit PxIO# for the following case: receiving a sequence of type 1 commands without background operations. At time tO a first type 1 command (SCO command) for plane P0 and plane P1 is received, and at time t2 a second type 1 command for plane P2 is received. Before time tO, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command. At time tO, the device starts operation and sets the status bit PxRDY and the status bit PxIO# of all planes P0 to P3 to the busy (in operation) state.

[0342] At time t1, the operation of the first command is completed, and the status bit PxRDY and the status bit PxIO# of all planes P0 to P3 are in the ready (idle) state. Between time tO and time t1, the logic for accepting and rejecting commands can reject all commands.

[0343] At time t2, a second type 1 command for plane P2 without background operations is received. The device accepts the command and starts a foreground operation in plane P2. In addition, the device sets the status bit PxRDY and the status bit PxIO# of all planes P0 to P3 to the busy (in operation) state. During the interval after time t2, all commands will be rejected until the status bits change.

[0344] FIG. 29 For the figure, it shows in the upper part of the figure the logic for accepting and rejecting commands for planes P0 to P3, and in the lower part of the figure the ready / busy (idle / in operation) status of the status bit PxRDY and the status bit PxIO# for the following case: receiving a sequence of type 1 commands without background operations. At time tO a first type 1 command (SCO command) for plane P0 and plane P1 is received, and at time t2 a second type 1 command for plane P1 is received. Before time tO, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command. At time tO, the device starts operation and sets the status bit PxRDY and the status bit PxIO# of all planes P0 to P3 to the busy (in operation) state.

[0345] At time t1, the foreground operation of the first command is completed and the status bits PxRDY of all planes P0 to P3 are in the ready state, while the status bits PxIO# of all planes P0 to P3 remain in the operation in progress state while the background operation is being performed. Between time t0 and time t1, the logic for accepting and rejecting commands can reject all commands.

[0346] At time t2, a second type 1 command without a background operation is received for plane P1. The device accepts the command and starts an overlapping operation period, where the foreground operation of the second command remains until the background operation of the first command is completed. In addition, the device sets the status bits PxRDY and the status bits PxIO# of all planes P0 to P3 to the busy (operation in progress) state. Between time t1 and time t2, the logic for accepting and rejecting commands can allow selected commands.

[0347] At time t3, the foreground operation of the second command is completed. Also in this example, the background operation of the first command is completed before time t3, allowing the status bits PxRDY and the status bits PxIO# of all planes P0 to P3 to return to the ready (idle) state at time t3. During the interval between time t2 and time t3, all commands will be rejected.

[0348] FIG. 30 To summarize, it shows in the upper portion of the figure the logic for accepting and rejecting commands for planes P0 to P3, and in the lower portion of the figure the ready / busy (idle / operation in progress) states of the status bits PxRDY and the status bits PxIO# for the following case: a sequence of type 1 (e.g., SCO) commands and type 2 (e.g., AIPO) commands is received. At time t0, a first type 1 command (SCO command) with a background operation is received for planes P0 and P1, and at time t2, a second type 2 command without a background operation is received for plane P2. Prior to time t0, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command. At time t0, the device starts operation and sets the status bits PxRDY and the status bits PxIO# of all planes P0 to P3 to the busy (operation in progress) state.

[0349] At time t1, the foreground operation of the first command is completed and the status bits PxRDY of all planes P0 to P3 are changed to the ready (idle) state, while the status bits PxIO# of all planes P0 to P3 remain in the busy (operation in progress) state while the background operation is being performed. Between time t0 and time t1, the logic for accepting and rejecting commands can reject all commands.

[0350] At time t2, a second type 2 command for plane PI is received that does not have a background operation. Between time tl and time t2, the logic for accepting and rejecting commands can allow a select command. The received command is one of the select commands allowed by this combination of state bits and current operations. The device accepts the command and starts an overlapping operation period where the background operation of the first command is suspended and the foreground operation of the second command is started, since this foreground operation has higher priority than the suspended background operation. The state bit PI RDY for plane 1 changes to the busy state. The state bits PxRDY for plane PO, plane P2, and plane P3 remain in the ready state. The state bits PxIO# for all planes PO through P3 remain in the in operation state while the background operation of the first command is executing.

[0351] At time t3, the foreground operation of the second command is completed and the background operation of the first command is automatically resumed. The state bit PI RDY for plane PI changes to the ready state. The state bits PxRDY for plane PO, plane P2, and plane P3 remain in the ready state. The state bits PxIO# for all planes PO through P3 remain in the in operation state while the background operation of the first command is executing. During the interval between time t2 and time t3, only select type 2 commands for planes PO, P2, and P3 will be accepted.

[0352] In this example, the background operation of the first command continues to time t4, allowing the state bits PxRDY and the state bits PxIO# for all planes PO through P3 to return to the ready (idle) state at time t4. During the interval between time t2 and time t3, all commands for plane PI will be rejected.

[0353] FIG. 1A To illustrate the flow of logic performed by the control logic in a system similar to the system mentioned above FIG. 31 A flowchart of the logic performed by the control logic in a system similar to the system mentioned above

[0354] If the command is valid (e.g., accepted) at step 2903, the logic sets the plane status and operation / busy bits (e.g., PxRDY and PxIO#) to busy and busy (2910) and initiates a foreground operation for the command (2911). The timing of the initiation of the foreground operation and the setting of the status bits can be reversed, or they can be performed concurrently.

[0355] In conjunction with the foreground operation, the logic determines whether the foreground operation is complete at step 2912. If the operation is not complete, the algorithm waits for completion. If the operation is complete, the logic sets the plane status bit (e.g., PxRDY) to ready (2913). The timing of the initiation of the background operation and the setting of the status bits can be reversed, or they can be performed concurrently.

[0356] At step 2923, a determination is made as to whether the background operation can begin. If the background operation cannot begin, step 2923 sets the busy / idle status to idle. If the background operation can begin (determined in step 2923), the background operation begins in step 2920. In conjunction with the background operation, the logic determines whether the background operation is complete at step 2922. If the operation is not complete, the algorithm waits for completion. If the operation is complete, the logic sets the busy / idle status bit to idle (e.g., PxIO#) (2923).

[0357] More generally, FIG. 31 For an example of a method of operating a memory including a plurality of memory planes, each of the plurality of memory planes includes a particular set of resources to store data from / to the corresponding memory plane. The method includes generating, for each of the plurality of memory planes: (i) a corresponding first status signal indicative of a busy status or a ready status of the particular set of resources in the corresponding memory plane; and (ii) a corresponding second status signal indicative of a busy status or a ready status of the corresponding memory plane. Further, the method can include selectively allowing or denying execution of a memory command for a memory plane of the plurality of memory planes based on the status of one or more of the plurality of first status signals and second status signals.

[0358] FIG. 12 For a flowchart of logic performed by a host device or source device, examples of which are described above with respect to FIG. 12are described. In this example, the program executed by the logic begins after a request for a memory read / write operation is received from an external system source (3000). The logic then translates the request into the target plane / device and memory command format required by the connected multi-plane memory device under its control (3001). Next, the translated command is added to the command queue to be sent to the connected memory device (3002). The logic determines the status of the target device for the queue top command (3003). The status of the target device can be maintained by the source node as expected status data, which is stored in memory accessible to the logic (3050). The expected status data can be updated using commands to read the status from various connected devices, as well as using local information about commands that have been issued. From the status of the target device and the queue top command, the logic determines if the command and status are a valid combination (3020). If so, the logic can issue the command (3021). If it is not a valid combination, the logic can issue a read status command for the target device (3024). In response to the read status command, the current status of the target device is returned. This information can be used to maintain the expected status data (3050). In addition, this information can be used at step 3020 to determine if the command and status bits returned by the read status command form a valid combination.

[0359] After the command is issued, in some embodiments, the host logic can check the ready / busy (in operation / idle) notification pin on the target device (3022) (if used in the target device). The logic determines if a change notification has been asserted at step 3023. If a change notification has been asserted, the logic can make the next command in the queue the queue top (3010), and return to step 3003. In addition, the expected status data can be updated. If a change notification has not been asserted, the logic can issue a read status command for the target device (3024). In response to the read status command as discussed above, the current status of the target device is returned. This information can be used to maintain the expected status data (3050). In addition, this information can be used at step 3020 to determine if the command and status bits returned by the read status command form a valid combination.

[0360] While the source device or host is performing memory system operations, the logic can continue to complete the commands in the queue.

[0361] ​ A flowchart showing example logic for accepting or rejecting SCO commands and AIPO commands is shown. In particular, ​ The logic is shown starting at operation 3100 (e.g., the control circuit can receive a memory command for execution). At operation 3102, a determination is made as to whether the new memory command is a SCO command or an AIPO command. The SCO command path will be described first, and the AIPO command path will be described second.

[0362] If the new memory command is a SCO command operation, 3104 will determine if the chip is idle (e.g., PxIO# = Ready for all memory planes on the chip). If operation 3104 determines YES, the SCO command will be accepted for execution in operation 3112. If operation 3104 determines NO, operation 3106 will determine if the chip is ready (e.g., PxRDY = Ready for all memory planes on the chip). If operation 3106 determines NO, operation 3114 will reject the SCO command. If operation 3106 determines YES, operation 3108 will determine if the SCO command contains a background operation. If operation 3108 determines NO, operation 3114 will reject the SCO command. If operation 3108 determines YES, operation 3110 will determine if the SCO command is a selected command that can be executed, e.g., with an existing background operation (see ​ and the description of examples thereof). If operation 3110 determines NO, operation 3114 will reject the SCO command. If operation 3110 determines YES, operation 3112 will accept the SCO command for execution. After operations 3112 and 3114, the process will end until a new memory command is received.

[0363] If the new memory command is an AIPO command operation, 3118 will determine if the target plane of the chip is idle (e.g., PxIO# = Ready for the target plane). If operation 3118 determines YES, the AIPO command will be accepted for execution in operation 3112. If operation 3118 determines NO, operation 3120 will determine if the target plane of the chip is ready (e.g., PxRDY = Ready for the particular target plane). If operation 3120 determines NO, operation 3114 will reject the AIPO command. If operation 3120 determines YES, operation 3122 will determine if the AIPO command is a selected command that can be executed, e.g., with an existing background operation (see ​ and the description of examples thereof). If operation 3122 determines NO, operation 3114 will reject the AIPO command. If operation 3122 determines YES, operation 3112 will accept the AIPO command for execution. After operations 3112 and 3114, the process will end until a new memory command is received.

[0364] A number of flow diagrams illustrating logic performed by a memory controller or by a memory device are described herein. The logic can be implemented using a processor programmed with a computer program stored in memory accessible to the computer system, and can be executed by the processor, by special purpose logic hardware, including field programmable integrated circuits, and by a combination of special purpose logic hardware and computer programs. Through all the flow diagrams herein, it will be understood that many of the steps can be combined, executed in parallel, or in a different sequence without affecting the functionality achieved. In some cases, as will be appreciated by those skilled in the art, reordering steps will achieve the same result as long as certain other changes are also made. In other cases, as will be appreciated by those skilled in the art, reordering steps will achieve the same result as long as certain conditions are met. Moreover, it will be appreciated that the flow diagrams herein are only meant to illustrate the steps relevant to understanding the present application, and it will be understood that a large number of additional steps for achieving other functionality can be performed before, after, and in between the steps illustrated.

[0365] While the application has been disclosed in connection with the preferred embodiments and examples described above, it should be understood that it is capable of further modifications and that this application is intended to cover any variations which fall within the spirit or the scope of the following claims.

Claims

1. A memory system, comprising: Multiple memory planes, each memory plane comprising a specific resource set and a plane core, each memory plane being operable to perform a foreground operation using at least one of the resources of the specific resource set corresponding to the memory plane and the resources of the plane core corresponding to the memory plane, and to perform a background operation using the resources of the plane core corresponding to the memory plane; the specific resource set of each memory plane is a collection of caches or temporary registers for each memory plane; The resources of the plane core are used to support memory operations using the corresponding memory plane; An input / output I / O interface for a host to receive memory commands from one or more memory planes of the plurality of memory planes, which are self-addressable. A state control circuit generates a state bit corresponding to each of the plurality of memory planes, the state bit indicating one of a busy state and a ready state of the particular set of resources used by the foreground operation of the corresponding memory plane, and one of an operational state and an idle state of the resources of the plane core of the corresponding memory plane. as well as Control circuitry is operably coupled to the I / O interface, the state control circuitry, and the plurality of memory planes to perform memory operations using the plurality of memory planes; When performing memory operations using one or more of the plurality of memory planes, the control circuit generates multiple state bits in the state control circuit corresponding to each of the plurality of memory planes; and The control circuit, in response to a received memory command and a combination of the plurality of state bits in the state control circuit, performs or rejects a memory operation of the received memory command, comprising: performing or rejecting a first type of memory command, which depends on a combination of the busy state and the ready state and the operating state and the idle state of all of the plurality of memory planes; and performing or rejecting a second type of memory command addressing to a specific memory plane, which is only related to a combination of the busy state and the ready state and the operating state and the idle state of the memory planes other than the specific memory plane among the plurality of memory planes.

2. The memory system according to claim 1, The foreground operations include operations involving at least one of the following: controlling the plane core of each memory plane corresponding to the specific resource set of each memory plane; and the resources of the plane core of each memory plane. The background operations mentioned therein include operations relating to the resources of the plane core of each memory plane, but do not include operations relating to the plane core of each memory plane that control the specific resource set of each memory plane.

3. The memory system according to claim 2, The specific resource set of each memory plane causes the foreground operation to prevent the host from accessing the cache or temporary register of each of the plurality of memory planes, and The background operation does not prevent the host from accessing the cache or temporary memory of each of the plurality of memory planes, wherein the cache or temporary memory is not controlled by each of the plane cores of each memory plane.

4. The memory system of claim 1, wherein the first type of memory command is used for a first type of operation, and the control circuit accepts the first type of memory command to execute the first type of operation in response to the following: the busy state and the ready state of the specific resource set used by the foreground operation in each of the plurality of memory planes are both ready; and the operating state and the idle state of the resources of each plane core are both idle.

5. The memory system of claim 1, wherein the first type of memory command is used for a first selection type of operation, and the control circuit accepts the first type of memory command to execute the first selection type of operation when: the busy state and the ready state of the specific resource set used by the foreground operation in each of the plurality of memory planes are both ready; the operating state and the idle state of the resources of each plane core are both operating according to another first type of memory command; and the first selection type of operation can be executed together with an existing background operation.

6. The memory system according to claim 1, The overlapping operation period is the time during which the control circuit receives a new memory command while an existing background operation that was executing a previous memory command is in progress. The control circuitry is configured such that during the overlapping operation period and when the new memory command has a higher priority than the previous memory command, the existing background operation is paused to allow foreground operation of the new memory command to be processed, and the paused background operation is resumed after the foreground operation of the new memory command is completed.

7. The memory system of claim 6, wherein the new memory command having the higher priority is a memory command that does not include background operations.

8. The memory system according to claim 1, The overlapping operation period is the time during which the control circuit receives a new memory command while an existing background operation that was executing a previous memory command is in progress. The control circuitry is configured such that during the overlapping operation period, and when the new memory command does not have a higher priority than the previous memory command, the foreground operation of the new memory command begins after the existing background operation has been completed.

9. The memory system of claim 1, wherein the second type of memory command is for a second type of operation on a target memory plane, and the control circuit accepts the second type of memory command to execute the second type of operation when: the busy state and the ready state of the specific resource set used by the foreground operation in each of the plurality of memory planes include the ready state of the specific resource set of the target memory plane; and the operating state and the idle state of the resources of each plane core include the idle state of the resources of the plane core of the target memory plane.

10. The memory system of claim 1, wherein the second type of memory command is used for a second selection type of operation on a target memory plane, and the control circuit accepts the second type of memory command to execute the second selection type of operation when: the busy state and the ready state of the specific resource set used by the foreground operation in each of the plurality of memory planes include the ready state of the specific resource set of the target memory plane; the operating state and the idle state of the resources of the plane core in the target memory plane are in operation according to another second type of memory command; and the second selection type of operation can be executed together with an existing background operation.

11. The memory system of claim 1, wherein the second type of memory command is used for a second selection type of operation for a target memory plane, and the control circuit accepts the second type of memory command to execute the second selection type of operation when: the busy state and the ready state of the specific resource set used by the foreground operation in each of the plurality of memory planes include the ready state of the specific resource set of the target memory plane; the operating state and the idle state of the resources of the plane core in the target memory plane are in operation according to the first type of memory command; and the second selection type of operation can be executed together with an existing background operation.

12. The memory system according to claim 1, wherein, The first type of memory command is a synchronous chip operation, and the second type of memory command is an asynchronous independent plane operation.

13. The memory system of claim 1, wherein the memory command includes a reset plane command for a target memory plane, wherein the reset plane command is received by the control circuit for execution when the operational state and the idle state of the resources of the plane core in the target memory plane are operational according to the second type of memory command, such that the ongoing second type of operation of the target memory plane is aborted.

14. The memory system of claim 1, wherein the core of one of the memory planes is a 3D NAND flash memory.

15. The memory system of claim 1, wherein the core of one of the memory planes is at least one of the following: a memory cell for storing data; an error-free memory cell including ECC circuitry to correct the data; a memory-in-memory computing unit configured to perform data calculation functions; and a memory cell configured to execute a memory-in-memory search command.

16. The memory system according to claim 1, wherein: The memory system is configured to perform operations that occupy the target memory plane; and During the first execution phase of the operation, the memory system is configured to set the busy state and the ready state of the target memory plane to busy and the operating state and the idle state of the target memory plane to operating for the foreground operation, regardless of the busy state, the ready state, the operating state, and the idle state of the plurality of memory planes other than the target memory plane.

17. The memory system of claim 16, wherein during the second execution phase of the operation, the memory system is configured to change the busy state and the ready state of the target memory plane to ready for background operations and maintain the operating state and the idle state of the target memory plane as operating, regardless of the busy state and the ready state, the operating state and the idle state of the plurality of memory planes other than the target memory plane.

18. The memory system of claim 17, wherein during a preprocessing operation period of the operation occupying the target memory plane that occurs prior to the first execution phase and the second execution phase, the busy state and the ready state of each of the plurality of memory planes are set to busy, and the operating state and the idle state of each of the plurality of memory planes are set to operating.

19. A method of operating a memory system as claimed in any one of claims 1 to 18, the memory system comprising a plurality of memory planes, each memory plane including a plane core and a corresponding specific resource set, each memory plane operable to perform a foreground operation using the specific resource set of the corresponding memory plane and to perform a background operation in the absence of the specific resource set of the corresponding memory plane, the method comprising: For each of the plurality of memory planes, a corresponding first state signal is generated indicating the busy or ready state of the specific resource set used by the foreground operation of the corresponding memory plane, and a corresponding second state signal indicating the operational or idle state of the plane core of the corresponding memory plane.

20. The method of operating a memory system according to claim 19, further comprising: Based on the state of one or more of the first and second state signals, memory commands for memory planes in the plurality of memory planes are selectively allowed or denied.

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