Flash memory controller and method of performing cache flush operations

Abstract

A flash memory controller and a method of performing a cache erase operation are disclosed. The flash memory controller includes a first interface circuit and a processor. The first interface circuit is coupled to a flash memory to transmit data and commands. The processor is coupled to the first interface circuit to access the flash memory. The processor controls the first interface circuit to transmit a first command sequence and a second command sequence to the flash memory. The first command sequence includes a first command and a second command. In response to the transmission of the second command, the flash memory performs an erase operation and transmits the second command sequence to the flash memory when an array ready bit is in a non-ready state. The present application can perform related operations that use a bus while performing an erase operation to improve transmission efficiency.

Description

Technical Field

[0001] This application relates to a memory device, and more particularly to a flash memory controller and a method for performing a cache erase operation. Background Technology

[0002] The memory device includes a flash memory controller and flash memory. The flash memory controller controls the operation of the memory device and accesses the flash memory, while the flash memory stores data. During an erase operation, the bus (BUS) between the flash memory controller and the flash memory is idle. That is, no operations that would use the BUS, such as data transfer or command sending, are performed during this time. This causes the flash memory controller to remain in a waiting state until the erase operation is complete, failing to fully utilize its computing power and resources, resulting in reduced overall system performance and wasted resources. Summary of the Invention

[0003] To address the problems of the prior art, the purpose of this application is to provide a flash memory controller and a method for performing cache erase operations, which can perform related operations using the BUS while performing the erase operation to improve transmission efficiency.

[0004] In a first aspect, this application provides a flash memory controller for controlling a flash memory, the flash memory controller comprising: a first interface circuit and a processor. The first interface circuit is coupled to the flash memory to transmit data and commands. The processor is coupled to the first interface circuit to access the flash memory through the first interface circuit. The processor controls the first interface circuit to transmit a first command sequence and a second command sequence to the flash memory. The first command sequence includes a first command and a second command, the first command being used to instruct the flash memory to receive address information, and in response to the transmission of the second command, the flash memory performing an erase operation corresponding to the address information, and transmitting the second command sequence to the flash memory when an array ready bit is in a non-ready state.

[0005] In some embodiments, when the array ready bit of the flash memory is set to a value of 0, it represents the non-ready state, and when it is set to a value of 1, it represents the ready state.

[0006] In some embodiments, in response to the transmission of the second command, a ready bit of the flash memory and the array ready bit are set to 0, and after a first busy period, the ready bit is set to 1 and the array ready bit is set to 0.

[0007] In some embodiments, before transmitting the first command sequence, the processor controls the first interface circuit to transmit a setting feature command sequence to the flash memory, the setting feature command sequence being configured to enable the flash memory controller to transmit the second command sequence to the flash memory when the array ready bit is in the non-ready state.

[0008] In some embodiments, the second command sequence includes the same command as the first command sequence, and during the timing interval of the flash memory processing operations corresponding to the first command sequence and the second command sequence, the array ready bits are all maintained in the non-ready state.

[0009] In some embodiments, the second command sequence is used to instruct the flash memory to perform a read operation, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bits are all maintained in the non-ready state.

[0010] In some embodiments, the second command sequence is used to instruct the flash memory to perform a write operation, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bits are all maintained in the non-ready state.

[0011] Secondly, this application also provides a method for performing a cache erase operation in a flash memory controller, wherein the flash memory controller is coupled to the flash memory to transmit data and commands, the method comprising: transmitting a first command sequence to the flash memory, wherein the first command sequence includes a first command and a second command, the first command being used to instruct the flash memory to receive address information; in response to the transmission of the second command, the flash memory performing an erase operation corresponding to the address information, and transmitting a second command sequence to the flash memory when an array ready bit is in a non-ready state.

[0012] In some embodiments, when the array ready bit of the flash memory is set to a value of 0, it represents the non-ready state, and when it is set to a value of 1, it represents the ready state.

[0013] In some embodiments, before transmitting the first command sequence, the method further includes: transmitting a setting feature command sequence to the flash memory, and in response to the transmission of the setting feature command sequence, enabling the flash memory controller to transmit the second command sequence to the flash memory when the array ready bit is in the non-ready state.

[0014] In some embodiments, the second command sequence includes the same command as the first command sequence, and during the timing interval of the flash memory processing operations corresponding to the first command sequence and the second command sequence, the array ready bits are all maintained in the non-ready state.

[0015] In some embodiments, the second command sequence is used to instruct the flash memory to perform a read operation, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bits are all maintained in the non-ready state.

[0016] In some embodiments, the second command sequence is used to instruct the flash memory to perform a write operation, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bits are all maintained in the non-ready state.

[0017] Thirdly, this application also provides a method for performing a cache erase operation in flash memory, comprising: receiving a first command sequence, and in response to receiving a first command of the first command sequence, receiving corresponding address information; in response to receiving a second command in the first command sequence, performing an erase operation corresponding to the address information and setting an array ready bit to a non-ready state; and receiving a second command sequence while the array ready bit is in the non-ready state.

[0018] In some embodiments, the array ready bit is set to a value of 0 to represent the non-ready state, and is set to a value of 1 to represent a ready state.

[0019] In some embodiments, before receiving the first command sequence, the method further includes: receiving a setting feature command sequence, and in response to receiving the feature command sequence, enabling the flash memory to receive the second command sequence when the array ready bit is in the non-ready state.

[0020] In some embodiments, the second command sequence includes the same command as the first command sequence, and during the timing interval of the flash memory processing operations corresponding to the first command sequence and the second command sequence, the array ready bits are all maintained in the non-ready state.

[0021] In some embodiments, the second command sequence is used to instruct the flash memory to perform a read operation, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bits are all maintained in the non-ready state.

[0022] In some embodiments, the second command sequence is used to instruct the flash memory to perform a write operation, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bits are all maintained in the non-ready state.

[0023] Compared to existing technologies, this application provides a flash memory controller and a method for performing cache erase operations, which receives another command sequence or data while performing the erase operation. Therefore, it avoids having to wait for the erase operation to complete before performing operations that utilize the BUS, thereby improving transmission efficiency. Attached Figure Description

[0024] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0025] Figure 1 A schematic diagram of a memory device according to an embodiment of the present invention is shown.

[0026] Figure 2 A schematic diagram of a flash memory according to an embodiment of the present invention is shown.

[0027] Figure 3 This diagram shows the timing of the cache erasure operation performed according to the first embodiment of the present invention.

[0028] Figure 4A This diagram illustrates a set feature command sequence based on a cache erase operation according to an embodiment of the present invention.

[0029] Figure 4B A schematic diagram showing a sequence of setting features for enabling cache erase operation according to an embodiment of the present invention.

[0030] Figure 4C A schematic diagram showing a sequence of setting features for disabling cache erase operation according to an embodiment of the present invention.

[0031] Figure 5 This diagram shows the timing of the cache erasure operation according to the second embodiment of the present invention.

[0032] Figure 6 This diagram shows the timing of the cache erasure operation according to the third embodiment of the present invention.

[0033] Figure 7 This diagram shows the timing of the cache erasure operation according to the fourth embodiment of the present invention.

[0034] Figure 8 A flowchart illustrating a method for performing a cache erase operation in a flash memory controller according to an embodiment of the present invention is shown.

[0035] Figure 9 A flowchart illustrating a method for performing a cache erase operation in flash memory according to an embodiment of the present invention is shown. Detailed Implementation

[0036] Exemplary embodiments of this application will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein. Rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0037] Please refer to Figure 1 This diagram illustrates a memory device according to an embodiment of the present invention. The memory device 10 includes a flash memory controller 100 and flash memory 200. The flash memory controller 100 controls the operation of the memory device 10 and accesses the flash memory 200, and the flash memory 200 stores data. The memory device 10 may include, but is not limited to, solid-state drives (SSDs) and various types of embedded memory devices, such as embedded memory devices conforming to the Peripheral Component Interconnect Express (PCIe) standard.

[0038] like Figure 1 As shown, the flash memory controller 100 may include a first interface circuit 110, a second interface circuit 120, a processor 130, a buffer 140, and a read-only memory 150. The flash memory controller 100 is coupled to the flash memory 200 via the first interface circuit 110 to transmit data and commands. Furthermore, the flash memory controller 100 can communicate with a host device via the second interface circuit 120. The processor 130 is electrically coupled to the first interface circuit 110, the second interface circuit 120, the buffer 140, and the read-only memory 150. The buffer 140 may be implemented using random access memory (RAM). For example, the buffer 140 may be static random access memory (SRAM), but the invention is not limited thereto. The read-only memory 150 is used to store program code 151.

[0039] In some embodiments, the flash memory controller 100, which executes program code 151 via processor 130, can perform various control operations using its internal components, such as controlling access to the flash memory 200 via first interface circuit 110, communicating with the host device via second interface circuit 120, and performing necessary buffering operations via buffer 140. For example, the host device can transmit a host command and its corresponding logical address to the flash memory controller 100. The processor 130 of the flash memory controller 100 receives the host command and logical address via second interface circuit 120, converts the host command into a memory operation command, and further controls the flash memory 200 to perform read and / or write (also known as program) operations on memory cells (e.g., data pages) at certain physical addresses in the flash memory 200 via first interface circuit 110. The physical address corresponds to the logical address. First interface circuit 110 may include an encoder and a decoder. The encoder is used to encode the data written to the flash memory 200 to generate the corresponding check code, while the decoder is used to decode the data received from the flash memory 200.

[0040] In some embodiments, the host device may include a processor and a power supply circuit coupled to each other. The processor may be used to control the operation of the host device, while the power supply circuit may be used to provide power to the processor and the memory device 10, and to output one or more drive voltages to the memory device 10. The memory device 10 may be used to provide storage space to the host device, and to obtain one or more drive voltages from the host device as power to the memory device 10. The host device mentioned herein may include, but is not limited to, mobile devices, wearable devices, tablet computers, and personal computers such as desktop computers and laptop computers.

[0041] In some embodiments, the second interface circuit 120 of the flash controller 100 may conform to a specific communication standard, such as the Serial Advanced Technology Attachment (Serial ATA or SATA) standard, the Peripheral Component Interconnect (PCI) standard, the PCIe standard, the Universal Flash Storage (UFS) standard, etc., and may communicate according to the specific communication standard, for example, to perform communication between the host device and the memory device 10, wherein the host device may include a corresponding transmission interface circuit conforming to the specific communication standard to perform communication between the host device and the memory device 10.

[0042] In this embodiment, the flash memory 200 is NAND flash memory. Accordingly, the first interface circuit 110 of the flash memory controller 100 communicates with the flash memory 200 using a communication protocol compatible with Open NAND Flash Interface (ONFI). For example, the flash memory controller 100 can translate requests from the host device into commands for the flash memory 200 according to the ONFI protocol, wherein the commands are selected from the ONFI command set.

[0043] Please refer to Figure 2 The diagram shows a schematic of a flash memory according to an embodiment of the present invention. The flash memory 200 includes an input / output (I / O) control circuit 201, a logic control circuit 202, an address register 203, a status register 204, a command register 205, a memory cell array 206, a row decoder 207, a column decoder 208, a data register 209, and a ready / busy (R / B) control circuit 210.

[0044] The I / O control circuit 201 sends and receives, for example, 8-bit wide input / output signals (I / Ox) with the flash memory controller 100. For example, the I / O control circuit 201 may receive an input / output signal (I / Ox) containing write data from the flash memory controller 100 and transmit it to the data register 209. Furthermore, the I / O control circuit 201 may send read data transmitted from the data register 209 as an input / output signal (I / Ox) to the flash memory controller 100.

[0045] The logic control circuit 202 receives various control signals from the flash memory controller 100 to control the I / O control circuit 201. These control signals include, for example, a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. The logic control circuit 202 controls the overall operation of the flash memory 200. Specifically, based on commands transmitted from the command register 205, the logic control circuit 202 controls the row decoder 207, column decoder 208, data register 209, etc., thereby performing data write operations, read operations, etc.

[0046] Address register 203 receives address information from I / O control circuit 201 and holds the address information. Furthermore, address register 203 transmits the column address signal and row address signal contained in the address information to row decoder 207, column decoder 208, and data register 209, respectively. Status register 204 transmits the status information to I / O control circuit 201 according to the instruction of logic control circuit 202. Command register 205 receives commands from I / O control circuit 201 and holds the commands. Furthermore, command register 205 transmits the commands to logic control circuit 202.

[0047] The memory cell array 206 has multiple blocks. A block is a collection of multiple non-volatile memory cells associated with bit lines and word lines, where each memory cell can store multiple bits of data using an MLC (Multi-Level Cell) approach. Each block contains multiple pages. A page is the smallest unit of programming; that is, a page is the smallest unit for writing or reading data. A block is the smallest unit for erasing operations. An erasing operation must be performed before a write operation is performed on the flash memory 200 because a write operation can only change a memory cell from "1" to "0", while an erasing operation sets all memory cells to 1.

[0048] The logic control circuit 202 can receive control signals to check the state of the memory cell array 206 and provide the result of the state check to the status register 204. Please refer to Table 1, which illustrates the various state values ​​in the status register 204.

[0049] Table 1:

[0050]

[0051] FAIL: If the SR[0] bit is 1, it indicates that the previous command failed. If the SR[0] bit is 0, it indicates that the previous command succeeded. In one embodiment, the SR[0] bit is only valid during programming or erasing operations.

[0052] FAILC: If the SR[1] bit is 1, it means that the command before the previous command failed (the command before that). If the SR[1] bit is 0, it means that the command before the previous command succeeded. The SR[1] bit is only valid in programming cache operations.

[0053] SR[2]-SR[4]VSP: Defined and used by the product developer.

[0054] ARDY: If the SR[5] bit (i.e., the array ready bit) is 1, it means that there is no array operation in progress. If the SR[5] bit is 0, it means that a command is being executed (RDY is cleared to 0), or an array operation is in progress. If overlapped multi-plane operations or cache commands are not supported, the SR[5] bit will not be used.

[0055] RDY: If the SR[6] bit (i.e., the ready bit) is 1, it indicates that the logical unit (LUN) or plane address of another command is ready, and all other bits in the status value are valid. If the SR[6] bit is 0, it indicates that the previous command sent has not yet been executed, and the SR[5] bit is invalid and should be ignored by the host device. The SR[6] bit affects the value of the signal R / B#. That is, the signal R / B# reflects whether the LUN on the memory cell array 206 is busy. When a cache operation is in progress, the SR[6] bit indicates whether another command can be accepted, while RDY indicates whether the previous operation has been completed.

[0056] WP_n: If SR[7] bit is 1, it means the device is not in write-protected mode. If SR[7] bit is 0, it means the device is in write-protected mode. Regardless of the value of SR[6] bit, SR[7] bit is always valid.

[0057] The row decoder 207 and column decoder 208 select the bit lines and word lines corresponding to the target memory cells to be read and written. Furthermore, the row decoder 207 and column decoder 208 apply the required voltages to the selected / unselected bit lines and word lines respectively.

[0058] Data register 209 outputs data read from memory cell array 206 to flash memory controller 100 via I / O control circuit 201. Furthermore, data register 209 transmits write data received from flash memory controller 100 via I / O control circuit 201 to memory cell array 206.

[0059] The R / B control circuit 210 generates a ready / busy signal R / B# based on the operating state of the logic control circuit 202 and sends the signal to the flash memory controller 100. The ready / busy signal R / B# notifies the flash memory controller 100 whether the flash memory 200 is in a ready or busy state. A ready state is a state where commands from the flash memory controller 100 can be accepted, while a busy state is a state where commands from the flash memory controller 100 cannot be accepted. Furthermore, the ready / busy signal R / B# is generated by the R / B control circuit 210 controlling the switching on / off of the transistors connected to its output. For example, the ready / busy signal R / B# is set to a low level (busy state) when the flash memory 200 performs operations such as reading data, and is set to a high level (ready state) when the operations are completed.

[0060] Ideally (for high transmission efficiency), the bus (BUS) between the flash memory controller 100 and the flash memory should be transmitting commands or data. However, in the prior art, the BUS is idle when an erase operation is performed. That is, no operations that use the BUS, such as data transmission or command sending, are performed. This causes the flash memory controller to be in a waiting state until the erase operation is completed, failing to fully utilize its computing power and resources. In this application, by performing a cache erase operation, operations that use the BUS are performed simultaneously with the erase operation, thereby improving transmission efficiency. The specific implementation of this application is described below.

[0061] Please refer to Figure 3 The diagram shows a timing diagram of the cache erase operation performed according to the first embodiment of the present invention, including example waveforms of the ready bit SR[6] and the array ready bit SR[5]. It should be understood that the cache erase operation in this embodiment is performed by the memory device 10 described above. Specifically, the first interface circuit 110 of the flash memory controller 100 is coupled to the flash memory 200 to transmit data and commands. Furthermore, the processor 130 of the flash memory controller 100 is coupled to the first interface circuit 110 to access the flash memory 200 through the first interface circuit 110. In this embodiment, the processor 130 controls the first interface circuit 110 to transmit the first command sequence 301 and the second command sequence 302 to the flash memory 200.

[0062] like Figure 3As shown, the first command sequence 301 of this application is used to indicate an erase operation, including commands 60h and 86h. The transmission of the first command sequence 301 is as follows: The processor 130 of the flash memory controller 100 controls the first interface circuit 110 to sequentially send an erase command (i.e., the first command) such as 60h, address information ALE (e.g., block address information of a plane (e.g., the m-th plane), and a confirmation command (i.e., the second command) such as 86h to the flash memory 200. The block address information can be used to indicate the block address of the n-th block of the m-th plane (but is not limited to this). The input of the first command 60h allows the flash memory 200 to recognize the start of the erase operation, and the first command 60h is used to instruct the flash memory 200 to receive the address information ALE. When the first command 60h is received, the flash memory 200 can know and confirm that the information following the first command 60h includes the block address information of the block in the m-th plane. Furthermore, in response to the transmission of the second command 86h, the flash memory 200 begins to perform the erase operation on the block corresponding to the address information ALE. It should be noted that the second command number in this embodiment is optional; for example, it can be any command number in the ONFI command set reserved area, such as 76h, 82h, 86h, etc. This embodiment uses command 86h as an example.

[0063] like Figure 3 As shown, in response to the transmission of the second command 86h of the first command sequence 301, the ready bit SR[6] and the array ready bit SR[5] of the flash memory 200 are set to 0. As described above, when the ready bit SR[6] and the array ready bit SR[5] of the flash memory are set to the value 0, it represents a non-ready state, and when they are set to the value 1, it represents a ready state. Then, after the first busy period tW1, the ready bit SR[6] becomes 1, indicating that the flash memory 200 can start receiving another command. Therefore, when the ready bit SR[6] is 1, the processor 130 immediately transmits the second command sequence 302 to the flash memory 200. That is, when the processor 130 controls the first interface circuit 110 to transmit the second command sequence 302 to the flash memory 200, the ready bit SR[6] of the flash memory 200 is set to 1 and the array ready bit SR[5] is set to 0 (i.e., in a non-ready state). It should be understood that, since the flash memory 200 is still performing the erase operation at this time, the second command sequence 302 is transmitted to the corresponding registers, such as the command register 205, the address register 203, etc.

[0064] like Figure 3As shown, in this embodiment, the second command sequence 302 contains the same commands as the first command sequence 301, but the address information ALE is different. For example, the address information ALE of the second command sequence 302 can be used to indicate the block address of another block in the m-th plane or another plane. That is, after the erase operation corresponding to the first command sequence 301 ends, the flash memory immediately performs another erase operation corresponding to the second command sequence 302 to perform the erase operation on the corresponding other block.

[0065] like Figure 3 As shown, in response to the transmission of the second command 86h in the second command sequence 302, the ready bit SR[6] of the flash memory 200 is set to 0. Then, after the second busy period tW2, the ready bit SR[6] becomes 1. That is, in some embodiments, the flash memory 200 may begin to receive another command at this time, but is not limited to this.

[0066] like Figure 3 As shown, tBERS represents the block erase period. During the timing interval (tBERS_1+tBERS_2) of the flash memory 200 processing the operations corresponding to the first command sequence 301 and the second command sequence 302, the array ready bit SR[5] remains in the non-ready state. After the flash memory 200 finishes executing the operations corresponding to the first command sequence 301 and the second command sequence 302 (after the period tBERS_1+tBERS_2), the array ready bit SR[5] of the flash memory 200 becomes 1, indicating that there is no array operation in progress.

[0067] It should be understood that in some embodiments, the success of the erase operation can be determined by reading the data in the status register of the flash memory 200. If the erase is successful, data can be rewritten to the flash memory 200. If the erase is unsuccessful, an erase command can be issued again to erase the erroneous data in the flash memory 200 until the erase is successful. For example, after transmitting the second command sequence 302, the flash memory controller 100 can further transmit a status read command 70h to the flash memory 200. The flash memory 200 responds to the status read command 70h by sending its status to the flash memory controller 100. At this time, the status value of the SR[0] bit in the status register is read to confirm whether the erase operation has failed. When the SR[0] bit is 0, it indicates that the erase operation has been successfully completed. However, when the SR[0] bit is 1, it indicates that the erase operation has failed.

[0068] In this embodiment, by replacing the traditional erase confirmation command D0h with command 86h in the first command sequence 301, the flash memory 200 can receive the second command sequence 302 while performing the erase operation. Therefore, it avoids having to wait for the erase operation to complete before performing operations that utilize the BUS, thereby improving transmission efficiency. For example, in the case of performing two erase operations, this embodiment reduces the transmission time of one command sequence compared to the prior art (because the transmission of the second command sequence 302 and the execution of the erase operation are performed in parallel).

[0069] The above description uses the example of replacing the traditional erase confirmation command D0h with command 86h to achieve parallel execution of the transmission and erase operations of the second command sequence 302, but it is not limited to this. For example, the operating mode of the memory device 10 can be changed by setting a feature command. Specifically, please refer to... Figure 4A This diagram illustrates a set feature command sequence based on a cache erase operation according to an embodiment of the present invention. Figure 4A As shown, before transmitting the command sequence instructing the execution of an erase operation (such as the first command sequence), the processor 130 controls the first interface circuit 110 to transmit a setting feature command sequence 400 to the flash memory 200. The setting feature command is a command used to set various parameters of the flash memory 200. If the setting feature command is set in the command register, the parameter data sent from the flash memory controller 100 after the setting feature command will be set in various registers.

[0070] like Figure 4A As shown, the transmission of the setting feature command sequence 400 is as follows. First, the flash memory controller 100 transmits a setting feature command (e.g., EFh) to the flash memory 200. The command EFh is used to instruct the flash memory 200 to change parameters. Next, the flash memory controller 100 transmits address information EFh to the flash memory 200. The address information EFh specifies the address corresponding to the parameter to be changed. Then, the flash memory controller 100 outputs setting data P1-P4 to the flash memory 200 in multiple cycles. Here, the output setting data P1-P4 is equivalent to the data of the parameter to be changed. When the flash memory 200 receives the feature command sequence 400, it begins setting features and changes the operating mode of the flash memory 200. In this embodiment, the flash memory controller 100 can use the setting feature command to set the cache erase operation of the flash memory 200. Specifically, the setting feature command sequence is configured such that the flash memory controller 100 can transmit a second command sequence to the flash memory 200 when the array ready bit is in a non-ready state. In other words, the feature command sequence is configured to allow the flash memory 200 to receive a second command sequence while performing an erase operation.

[0071] It should be noted that in this embodiment, the first command sequence transmitted after the feature command sequence 400 is <60h-ALE-D0h>, that is, the first command is 60h and the second command is D0h. In some electronic products, the command for performing the erase operation is required to include D0h. In this case, by transmitting and enabling the above-mentioned feature command sequence 400, without changing the command sequence of the traditional erase operation (such as the first command sequence <60h-ALE-D0h>), it is achieved that the flash memory 200 can receive the second command sequence while performing the erase operation.

[0072] Please refer to Figure 4B and Figure 4C . Figure 4B A schematic diagram showing a sequence of setting features for enabling cache erase operations according to an embodiment of the present invention. Figure 4C A schematic diagram illustrating a setting feature command sequence for disabling a cache erase operation according to an embodiment of the present invention is shown. When the flash memory controller 100 or the flash memory 200 is powered on (or enabled), the processor 130 of the flash memory controller 100 can control the first interface circuit 110 to send setting feature command sequences 410 or 420 to the flash memory 200 to enable or disable the aforementioned cache erase operation of the flash memory 200 (receiving the second command sequence while performing the erase operation). Figure 4B As shown, in the setting feature command sequence 410 indicating the enable cache erase operation, the address information is, for example, 2Fh, and the setting data P1 is, for example, 00h. Also, as... Figure 4C As shown, in the setting feature command sequence 420 indicating the disabling of the cache erase operation, the address information is, for example, 2Fh, and the setting data P1 is, for example, 01h. It should be understood that the setting data P1 is used to indicate whether the aforementioned cache erase operation is enabled or disabled. When the setting data P1 is set to, for example, a logical bit of 0, the aforementioned cache erase operation can be enabled. When the setting data P11 is set to, for example, a logical bit of 1, the aforementioned cache erase operation is disabled. In this case, when performing a conventional erase operation with the command sequence <60h-ALE-D0h>, one must wait for the erase operation to complete before performing any operations that would utilize the BUS.

[0073] Please refer to Figure 5 The diagram shows a timing diagram of the cache erase operation performed according to a second embodiment of the present invention, with example waveforms of the ready bit SR[6] and the array ready bit SR[5]. In this embodiment, the processor 130 controls the first interface circuit 110 to transmit the first command sequence 501 and the second command sequence 502 to the flash memory 200.

[0074] like Figure 5As shown, the first command sequence 501 is used to indicate a multi-plane erase operation, including multiple first commands 60h and a second command 86h. The transmission of the first command sequence 501 is as follows: The processor 130 of the flash memory controller 100 controls the first interface circuit 110 to sequentially transmit the multiple first commands 60h. Furthermore, in each first command 60h, a corresponding address information ALE is transmitted. The address information ALE is used to indicate the block address of a block in the corresponding plane, such as the m-th plane, n-th plane, o-th plane, and p-th plane. After transmitting the address information ALE of the last plane, the flash memory controller 100 transmits a confirmation command (i.e., the second command) such as 86h to the flash memory 200. In response to the transmission of the second command 86h, the flash memory 200 begins to perform a multi-plane erase operation on the blocks in the planes corresponding to the address information ALE. It should be noted that the second command number in this embodiment is optional. For example, it can be any command number in the ONFI command set reserved area, such as 76h, 82h, 86h, etc. This embodiment uses command 86h as an example.

[0075] like Figure 5 As shown, in response to the transmission of the second command 86h in the first command sequence 501, the ready bit SR[6] and the array ready bit SR[5] of the flash memory 200 are set to 0. Then, after the first busy period tW1, the ready bit SR[6] becomes 1, indicating that the flash memory 200 can start receiving another command. Therefore, when the ready bit SR[6] is 1, the processor 130 immediately transmits the second command sequence 502 to the flash memory 200. That is, when the processor 130 controls the first interface circuit 110 to transmit the second command sequence 502 to the flash memory 200, the ready bit SR[6] of the flash memory 200 is set to 1 and the array ready bit SR[5] is set to 0. It should be understood that since the flash memory 200 is still performing the erase operation at this time, the second command sequence 502 is transmitted to the corresponding registers, such as the command register 205, the address register 203, etc.

[0076] like Figure 5 As shown, in this embodiment, the second command sequence 502 is also used to instruct the execution of a multi-plane erase operation. That is, after the multi-plane erase operation corresponding to the first command sequence 501 ends, the flash memory immediately executes another plane erase operation corresponding to the second command sequence 502.

[0077] In this embodiment, in the first command sequence 501, by replacing the traditional erase confirmation command D0h with command 86h, the flash memory 200 can receive the second command sequence 502 while performing the erase operation. Therefore, it avoids having to wait for the erase operation to complete before performing operations that utilize the BUS, thereby improving transmission efficiency. It should be understood that the cache erase operation based on the second embodiment can also change the operating mode of the memory device 10 by setting a combination of feature commands and existing multi-plane erase command sequences, so as to achieve simultaneous multi-plane erase operation and BUS-related operations. On the other hand, the remaining features of the second embodiment are the same as those of the first embodiment and will not be described again here.

[0078] Please refer to Figure 6 The diagram shows a timing diagram of the cache erase operation performed according to a third embodiment of the present invention, showing example waveforms of the ready bit SR[6] and the array ready bit SR[5]. In this embodiment, the processor 130 controls the first interface circuit 110 to transmit the first command sequence 601 and the second command sequence 602 to the flash memory 200.

[0079] like Figure 6 As shown, the first command sequence 601 is used to instruct the execution of an erasure operation, including a first command 60h and a second command 86h. It should be understood that the first command sequence 601 of the third embodiment is the same as the first command sequence 301 of the first embodiment, and will not be described again here.

[0080] like Figure 6 As shown, in response to the transmission of the second command 86h in the first command sequence 601, the ready bit SR[6] and the array ready bit SR[5] of the flash memory 200 are set to 0. Then, after the first busy period tW1, the ready bit SR[6] becomes 1, indicating that the flash memory 200 can start receiving another command. Therefore, when the ready bit SR[6] is 1, the processor 130 immediately transmits the second command sequence 602 to the flash memory 200. That is, when the processor 130 controls the first interface circuit 110 to transmit the second command sequence 602 to the flash memory 200, the ready bit SR[6] of the flash memory 200 is set to 1 and the array ready bit SR[5] is set to 0. It should be understood that since the flash memory 200 is still performing the erase operation at this time, the second command sequence 602 is transmitted to the corresponding registers, such as the command register 205, the address register 203, etc.

[0081] like Figure 6As shown, in this embodiment, the second command sequence 602 is used to instruct the flash memory 200 to perform a write operation. The second command sequence 602 includes commands 80h and 10h. Specifically, the flash memory controller 100 transmits command 80h to the flash memory 200. Command 80h is a command instructing the flash memory 200 to receive address information ALE, i.e., an address receive command. Next, the flash memory controller 100 processor 130 also controls the first interface circuit 110 to transmit the address information ALE to the flash memory 200, and also sequentially transmits the storage data W_DATA to be written to the data register 209 of the flash memory 200. Finally, the flash memory controller 100 transmits command 10h to the flash memory 200. Command 10h is used to instruct the flash memory 200 to perform a write operation. After the erase operation corresponding to the first command sequence 601 ends, the flash memory 200 immediately performs the write operation corresponding to the second command sequence 602. During the write operation, the storage data W_DATA in the data register 209 is written to the page corresponding to the logical address in the flash memory 200 in page units. Figure 6 tPROG in the figure represents the period during which the write operation is performed. It should be noted that during the timing interval (tBERS+tPROG) of the flash memory 200 processing the operations corresponding to the first command sequence 601 and the second command sequence 602, the array ready bits SR[5] are all kept in the unready state.

[0082] In this embodiment, in the first command sequence 601, by replacing the traditional erase confirmation command D0h with command 86h, the flash memory 200 can receive the second command sequence 602 while performing the erase operation. Therefore, it avoids having to wait for the erase operation to complete before performing operations that use the BUS, thereby improving transmission efficiency. For example, in the case of performing one erase operation and one write operation consecutively, this embodiment reduces the transmission time of one command sequence and the written data compared to the prior art (because the transmission of the second command sequence 602 and the stored data W_DATA is performed in parallel with the erase operation). It should be understood that, based on the cache erase operation of the third embodiment, the operating mode of the memory device 10 can also be changed by setting a combination of feature commands and existing erase command sequences to achieve simultaneous execution of erase operations and related operations that use the BUS. On the other hand, the remaining features of the third embodiment are substantially the same as those of the first embodiment and will not be described in detail here.

[0083] Please refer to Figure 7 The diagram shows a timing diagram of the cache erase operation performed according to the fourth embodiment of the present invention, showing example waveforms of the ready bit SR[6] and the array ready bit SR[5]. In this embodiment, the processor 130 controls the first interface circuit 110 to transmit the first command sequence 701 and the second command sequence 702 to the flash memory 200.

[0084] like Figure 7 As shown, the first command sequence 701 is used to instruct the execution of an erasure operation, including a first command 60h and a second command 86h. It should be understood that the first command sequence 701 of the fourth embodiment is the same as the first command sequence 301 of the first embodiment, and will not be described again here.

[0085] like Figure 7 As shown, in response to the transmission of the second command 86h in the first command sequence 701, the ready bit SR[6] and the array ready bit SR[5] of the flash memory 200 are set to 0. Then, after the first busy period tW1, the ready bit SR[6] becomes 1, indicating that the flash memory 200 can start receiving another command. Therefore, when the ready bit SR[6] is 1, the processor 130 immediately transmits the second command sequence 702 to the flash memory 200. That is, when the processor 130 controls the first interface circuit 110 to transmit the second command sequence 702 to the flash memory 200, the ready bit SR[6] of the flash memory 200 is set to 1 and the array ready bit SR[5] is set to 0. It should be understood that since the flash memory 200 is still performing the erase operation at this time, the second command sequence 702 is transmitted to the corresponding registers, such as the command register 205, the address register 203, etc.

[0086] like Figure 7 As shown, in this embodiment, the second command sequence 702 is used to instruct the flash memory 200 to perform a read operation. The second command sequence 702 includes commands 00h and 30h. Specifically, the flash memory controller 100 transmits command 00h to the flash memory 200. Command 00h is a command instructing the flash memory 200 to receive address information ALE, i.e., an address receive command. The flash memory controller 100 processor 130 also controls the first interface circuit 110 to transmit the address information ALE to the flash memory 200, and then transmits command 30h to the flash memory 200. Command 30h is used to instruct the flash memory 200 to perform a read operation. After the erase operation corresponding to the first command sequence 701 ends, the flash memory 200 immediately performs the read operation corresponding to the second command sequence 702. During the read operation, the processor 130 immediately controls the first interface circuit 110 to receive the read storage data R_DATA from the flash memory 200. Specifically, the storage data R_DATA in the flash memory 200 is transmitted to the I / O control circuit 201 through the data register 209, and then to the flash memory controller 100. Figure 7 In this context, tR represents the period during which the read operation is performed. It should be noted that during the timing interval (tBERS+tR) of the flash memory 200 processing the operations corresponding to the first command sequence 701 and the second command sequence 702, the array ready bits SR[5] remain in the unready state.

[0087] In this embodiment, by replacing the traditional erase confirmation command D0h with command 86h in the first command sequence 701, the flash memory 200 can receive the second command sequence 702 while performing the erase operation. Therefore, it avoids having to wait for the erase operation to complete before performing operations that use the BUS, thereby improving transmission efficiency. For example, in the case of performing one erase operation and one read operation consecutively, this embodiment reduces the transmission time of one command sequence compared to the prior art (because the transmission of the second command sequence 702 is performed in parallel with the execution of the erase operation). It should be understood that, based on the cache erase operation of the fourth embodiment, the operating mode of the memory device 10 can also be changed by setting a combination of feature commands and existing erase command sequences to achieve simultaneous execution of erase operations and related operations that use the BUS. On the other hand, the remaining features of the fourth embodiment are substantially the same as those of the first embodiment and will not be described in detail here.

[0088] This application also provides a method for performing a cache erase operation in a flash memory controller. The flash memory controller is coupled to the flash memory to transmit data and commands. The flash memory controller and flash memory are as described above and will not be repeated here. Specifically, the microprocessor of the flash memory controller is typically configured to control the overall operation of the memory device. The microprocessor executes program code to perform all or part of the steps in the cache erase operation as described in the first to fourth embodiments above.

[0089] Please refer to Figure 8 This document illustrates a flowchart of a method for performing a cache erase operation in a flash memory controller according to an embodiment of the present invention. The cache erase operation includes at least steps S81 to S82. In step S81, a first command sequence is transmitted to the flash memory, wherein the first command sequence includes a first command and a second command, the first command being used to instruct the flash memory to receive address information. In step S82, in response to the transmission of the second command, the flash memory performs an erase operation corresponding to the address information, and while the array ready bits are in a non-ready state, the second command sequence is transmitted to the flash memory.

[0090] In some embodiments, when the array ready bit of the flash memory is set to the value 0, it represents a non-ready state, and when it is set to the value 1, it represents a ready state.

[0091] In some embodiments, before transmitting the first command sequence, the method further includes transmitting a setting feature command sequence to flash memory. In response to the transmission of the feature command sequence, the flash memory controller is enabled to transmit a second command sequence to flash memory when the array ready bit is in a non-ready state.

[0092] In some embodiments, the second command sequence contains the same commands as the first command sequence, and during the timing interval of the flash memory processing operations corresponding to the first and second command sequences, the array ready bits are all kept in the unready state.

[0093] In some embodiments, the second command sequence is used to instruct the flash memory to perform a read operation, and during the timing interval of the flash memory processing the operations corresponding to the first command sequence and the second command sequence, the array ready bits are all kept in a non-ready state.

[0094] In some embodiments, the second command sequence is used to instruct the flash memory to perform a write operation, and during the timing interval of the flash memory processing the operations corresponding to the first command sequence and the second command sequence, the array ready bits are all kept in a non-ready state.

[0095] This application also provides a method for performing a cache erase operation in a flash memory. A flash memory controller is coupled to the flash memory to transmit data and commands. The flash memory controller and flash memory are as described above and will not be repeated here. Specifically, the flash memory performs all or part of the steps in the cache erase operation as described in the first to fourth embodiments above.

[0096] Please refer to Figure 9 This diagram illustrates a flowchart of a method for performing a cache erase operation in flash memory according to an embodiment of the present invention. The cache erase operation includes at least steps S91 to S93. In step S91, a first command sequence is received, and in response to the receipt of the first command in the first command sequence, corresponding address information is received. In step S92, in response to the receipt of the second command in the first command sequence, an erase operation corresponding to the address information is performed, and the array ready bits are set to a non-ready state. In step S93, while the array ready bits are in a non-ready state, a second command sequence is received.

[0097] In some embodiments, the array ready bit is set to 0 to represent a non-ready state, and set to 1 to represent a ready state.

[0098] In some embodiments, before receiving the first command sequence, the method further includes: receiving a setting feature command sequence. In response to the receipt of the feature command sequence, the flash memory is enabled to receive a second command sequence when the array ready bits are in a non-ready state.

[0099] In some embodiments, the second command sequence contains the same commands as the first command sequence, and during the timing interval of the flash memory processing operations corresponding to the first and second command sequences, the array ready bits are all kept in the unready state.

[0100] In some embodiments, the second command sequence is used to instruct the flash memory to perform a read operation, and during the timing interval of the flash memory processing the operations corresponding to the first command sequence and the second command sequence, the array ready bits are all kept in the non-ready state.

[0101] In some embodiments, the second command sequence is used to instruct the flash memory to perform a write operation, and during the timing interval of the flash memory processing the operations corresponding to the first command sequence and the second command sequence, the array ready bits are all kept in a non-ready state.

[0102] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A flash memory controller for controlling a flash memory, the flash memory controller comprising: The flash memory controller comprises: a first interface circuit coupled to the flash memory to transmit data and commands; and a processor coupled to the first interface circuit to access the flash memory through the first interface circuit, wherein the processor controls the first interface circuit to transmit a first command sequence and a second command sequence to the flash memory; and wherein the first command sequence comprises a first command and a second command, the first command is to instruct the flash memory to receive address information, and in response to the transmission of the second command, the flash memory performs an erase operation corresponding to the address information, and when an array ready bit is in a non-ready state, the flash memory transmits the second command sequence to the flash memory, after the flash memory receives the second command sequence, the flash memory continues to perform the erase operation corresponding to the address information of the first command sequence; wherein before the transmission of the first command sequence, the processor controls the first interface circuit to transmit a set feature command sequence to the flash memory, the set feature command sequence is configured to enable the flash memory controller to transmit the second command sequence to the flash memory when the array ready bit is in the non-ready state.

2. The flash controller of claim 1, wherein, When the array ready bit of the flash memory is set to a value of 0, it represents the non-ready state, and when it is set to a value of 1, it represents the ready state.

3. The flash controller of claim 1, wherein, In response to the transmission of the second command, the ready bit and the array ready bit of the flash memory are set to 0, and after a first busy period, the ready bit is set to 1 and the array ready bit is set to 0.

4. The flash controller of claim 1, wherein, The second command sequence contains the same commands as the first command sequence, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bit is maintained in the non-ready state.

5. The flash controller of claim 1, wherein, The second command sequence is used to instruct the flash memory to perform a read operation, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bit is maintained in the non-ready state.

6. The flash controller of claim 1, wherein, The second command sequence is used to instruct the flash memory to perform a write operation, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bit is maintained in the non-ready state.

7. A method of performing a cache flush operation in a flash controller, the method comprising: The flash memory controller is coupled to a flash memory to transmit data and commands, the method comprises: transmitting a first command sequence to the flash memory, wherein the first command sequence comprises a first command and a second command, the first command is to instruct the flash memory to receive address information; and in response to the transmission of the second command, the flash memory performs an erase operation corresponding to the address information, and when an array ready bit is in a non-ready state, the flash memory transmits a second command sequence to the flash memory, after the flash memory receives the second command sequence, the flash memory continues to perform the erase operation corresponding to the address information of the first command sequence; wherein before the transmission of the first command sequence, the processor controls the first interface circuit to transmit a set feature command sequence to the flash memory, the set feature command sequence is configured to enable the flash memory controller to transmit the second command sequence to the flash memory when the array ready bit is in the non-ready state. When the array ready bit of the flash memory is set to a value of 0, it represents the non-ready state, and when it is set to a value of 1, it represents the ready state. In response to the transmission of the second command, the ready bit and the array ready bit of the flash memory are set to 0, and after a first busy period, the ready bit is set to 1 and the array ready bit is set to 0. The second command sequence contains the same commands as the first command sequence, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bit is maintained in the non-ready state. The second command sequence is used to instruct the flash memory to perform a read operation, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bit is maintained in the non-ready state. The second command sequence is used to instruct the flash memory to perform a write operation, and during the time interval in which the flash memory processes the operations corresponding to the first command sequence and the second command sequence, the array ready bit is maintained in the non-ready state. wherein before transmitting the first command sequence, the method further comprises transmitting a set feature command sequence to the flash memory, and in response to the transmission of the set feature command sequence, enabling the flash memory controller to transmit the second command sequence to the flash memory when the array ready bit is in the non-ready state.

8. The method of claim 7, wherein the cache flush operation is performed in a flash controller, and the cache flush operation is performed in response to a command from a host device. The array ready bit is set to a value of 0 to represent the non-ready state and is set to a value of 1 to represent a ready state.

9. The method of claim 7, wherein the cache flush operation is performed in a flash controller, and the cache flush operation is performed in response to a command from a host device. The second command sequence contains the same commands as the first command sequence, and the array ready bit is maintained in the non-ready state during a time interval in which the flash memory processes operations corresponding to the first command sequence and the second command sequence.

10. The method of claim 7, wherein the cache flush operation is performed in a flash controller, and the cache flush operation is performed in response to a command from a host device. The second command sequence is used to instruct the flash memory to perform a read operation, and the array ready bit is maintained in the non-ready state during a time interval in which the flash memory processes operations corresponding to the first command sequence and the second command sequence.

11. The method of claim 7, wherein the cache flush operation is performed in a flash controller, and the cache flush operation is performed in response to a command from a host device. The second command sequence is used to instruct the flash memory to perform a write operation, and the array ready bit is maintained in the non-ready state during a time interval in which the flash memory processes operations corresponding to the first command sequence and the second command sequence.

12. A method of performing a cache flush operation in a flash memory, the method comprising: Comprising: receiving a first command sequence, and in response to receiving a first command of the first command sequence, receiving corresponding address information; in response to receiving a second command of the first command sequence, performing an erase operation corresponding to the address information and setting an array ready bit to a non-ready state; and while the array ready bit is in the non-ready state, receiving a second command sequence, the flash memory continuing to perform the erase operation corresponding to the address information of the first command sequence after the flash memory receives the second command sequence; wherein before receiving the first command sequence, the method further comprises receiving a set feature command sequence, and in response to receiving the feature command sequence, enabling the flash memory to receive the second command sequence when the array ready bit is in the non-ready state.

13. The method of claim 12, wherein the cache flush operation is performed in a flash memory, and The array ready bit is set to a value of 0 to represent the non-ready state and is set to a value of 1 to represent a ready state.

14. The method for performing a cache erase operation in flash memory as described in claim 12, characterized in that, The second command sequence contains the same commands as the first command sequence, and the array ready bit is maintained in the non-ready state during a time interval in which the flash memory processes operations corresponding to the first command sequence and the second command sequence.

15. The method of claim 12, wherein the cache flush operation is performed in a flash memory, and the cache flush operation is performed in a non-volatile memory. 15 The second command sequence is used to instruct the flash memory to perform a read operation, and the array ready bit is maintained in the non-ready state during a time interval in which the flash memory processes operations corresponding to the first command sequence and the second command sequence.

16. The method of claim 12, wherein the cache flush operation is performed in a flash memory, and The second command sequence is used to instruct the flash memory to perform a write operation, and the array ready bit is maintained in the non-ready state during a time interval in which the flash memory processes operations corresponding to the first command sequence and the second command sequence.

Images