A directed acyclic graph-based instruction scheduling optimization method, device and compilation method

Abstract

The present invention provides an instruction scheduling optimization method based on a directed acyclic graph, comprising: initializing a directed acyclic graph, building a dependency relationship between instructions, and creating a node for each instruction; defining an instruction compounding strategy, using an instruction buffer to sequentially store instructions on the directed acyclic graph, and extracting each instruction type, selecting compoundable instructions in the instruction buffer as candidate instructions according to the defined instruction compounding strategy; performing instruction compounding on the selected candidate instructions, creating a new node for the compound instruction, deleting the predecessor instruction node, updating the directed edges on which the compound instruction has dependencies, and constructing a new directed acyclic graph; based on the updated directed acyclic graph, prioritizing scheduling of instructions on the critical path, and executing the instructions simultaneously. The present invention also provides an instruction scheduling optimization device and compilation method based on a directed acyclic graph, which are used in conjunction with the instruction scheduling optimization method.

Description

Technical Field

[0001] The present invention belongs to the technical field of compilers, and in particular relates to an instruction scheduling optimization method, device and compilation method based on a directed acyclic graph. Background Art

[0002] With the increasing complexity and diversity of instruction set architectures (ISAs) in modern processors, compiler optimization plays a vital role in improving processor performance. Instruction scheduling is a key aspect of compiler optimization, aiming to optimize the execution order of instructions to maximize the utilization of processor resources and reduce the number of clock cycles required to avoid data race conditions.

[0003] The DAG (Directed Acyclic Graph)-based table scheduling algorithm is a commonly used instruction scheduling algorithm in the GCC compiler, designed to represent the dependencies between instructions. While this method can significantly improve pipeline efficiency and reduce pipeline stalls caused by data dependencies, it is primarily based on static analysis and only considers direct dependencies between instructions, ignoring indirect dependencies between instructions. It also cannot adapt to dynamic changes at runtime. Furthermore, when processing a large number of instructions, it does not support instruction compounding, limiting its optimization effectiveness and making it impossible to fully schedule the order of instruction execution, resulting in certain limitations in the order of instruction execution.

[0004] Therefore, it is necessary to fully optimize its algorithm and improve the flexibility of instruction scheduling, thereby reducing the pause cycle during instruction execution and improving the execution efficiency of instructions. Summary of the Invention

[0005] The present invention provides an instruction scheduling optimization method based on a directed acyclic graph, which improves the flexibility of instruction scheduling through an instruction compounding method, and at the same time assists in an adaptive scheduling strategy. During the instruction execution process, the execution of instructions can be adjusted in real time, thereby improving the execution efficiency of instructions.

[0006] The present invention also provides an instruction scheduling optimization device and a compilation method based on a directed acyclic graph, which are used in conjunction with the instruction scheduling optimization method.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] In order to achieve one or part or all of the above-mentioned purposes or other purposes, a technical solution of the present invention provides an instruction scheduling optimization method based on a directed acyclic graph, including: initializing a directed acyclic graph, constructing a dependency relationship between instructions, creating a node for each instruction, and adding a weight value to the directed edge to represent the delay cycle of the instruction; defining an instruction compounding strategy, using an instruction buffer to store the instructions on the directed acyclic graph in sequence, and extracting each instruction type, and selecting the compoundable instructions in the instruction buffer as candidate instructions based on the defined instruction compounding strategy; performing instruction compounding on the selected candidate instructions, and creating a new node for the compound instruction, while deleting the predecessor instruction node, and updating the directed edge with which the compound instruction has dependencies, and constructing a new directed acyclic graph; based on the updated directed acyclic graph, giving priority to scheduling instructions on the critical path and executing the instructions at the same time.

[0009] The compounding strategy is to compound the current instruction with its predecessor instruction.

[0010] The compound strategy also includes: classifying instructions into load instructions, storage instructions, and fixed-point / floating-point operation instructions; when encountering load, fixed-point / floating-point operation, and fixed-point / floating-point operation type instructions, adopting a load-fixed-point / floating-point operation instruction compound mode; when encountering fixed-point / floating-point operation, fixed-point / floating-point operation, and storage type instructions, adopting a fixed-point / floating-point operation-fixed-point / floating-point operation instruction compound mode; when encountering floating-point multiplication and addition, floating-point division, and floating-point square root instructions, giving priority to compounding such instructions.

[0011] It also includes optimizing the compound strategy based on the dependency relationship, calculating the execution time of individual instructions with dependencies and the execution time of compound instructions after the instructions with dependencies are compounded, and calculating the ratio of the time cost reduced by the compound instructions to the time cost of individual execution of the instructions with dependencies as the compound benefit score; traversing the candidate instructions and selecting instruction pairs with high compound benefit scores for compounding.

[0012] The execution time of a single instruction with a dependency relationship is the sum of the delay cycle of the single instruction and the dependency delay time between the instructions; and the execution time of a compound instruction after the instructions with a dependency relationship are combined is the sum of the longest delay cycle of the instructions in the instruction pair and the compound overhead, where the compound overhead is the delay added by the hardware when executing the compound instruction.

[0013] Determining the dependency relationship between the instructions includes performing dependency analysis on the instructions in the directed acyclic graph, and the dependency analysis includes static dependency analysis and multi-level dependency analysis; the static dependency analysis includes defining the data structure of nodes and edges, identifying the direct data dependency relationship between instructions, and constructing a directed acyclic graph based on the direct dependency relationship; the multi-level dependency analysis includes capturing the direct dependency and indirect dependency relationship between instructions, and marking the indirect dependency relationship on the directed acyclic graph.

[0014] Instructions that do not have data competition hazards in the instruction buffer and can be compounded are selected as candidate instructions. There is no register conflict or operand address overlap between the compounded instructions.

[0015] During instruction scheduling, instructions with higher dependency depth are scheduled first: among instructions with direct dependencies, instructions with longer dependency chains are scheduled first. During instruction execution, weight values are dynamically assigned to instructions with higher latency, and the critical path of the directed acyclic graph is calculated in real time based on the weight values. During instruction scheduling, instructions on the critical path are scheduled first.

[0016] An adaptive scheduling strategy is used during instruction execution to dynamically monitor processor performance, collect processor performance data, and feed the data back to the scheduler. The scheduler adjusts the instruction execution order based on the fed-back processor performance data.

[0017] When an instruction takes too long to execute due to a cache miss, the scheduler executes the subsequent instruction in advance if the subsequent instruction does not depend on the cache miss instruction; when there are frequent pauses in the execution stage in the pipeline, the scheduler reschedules the instruction execution order.

[0018] Another technical solution of the present invention provides an instruction scheduling optimization device based on a directed acyclic graph, which performs instruction scheduling optimization based on the instruction scheduling optimization method based on a directed acyclic graph described above, and includes a data structure updater for updating the instruction structure and inter-instruction dependencies of the directed acyclic graph; a directed acyclic graph updater for updating the directed acyclic graph based on the update results of the data structure updater, combined with static dependency analysis, multi-level dependency analysis and instruction compound results; a function optimizer for supporting the generation function of the introduced compound instructions and the call of the adaptive scheduling strategy dynamic adjustment function; a compound instruction generator, including using a modified and extended compiler to generate compound instruction encoding, and modifying the extended processor architecture to support the operation of compound instructions; an optimization option generator, which updates the optimization option generator and starts the new optimization function after the function optimizer supports the optimization function.

[0019] Another technical solution of the present invention provides an instruction scheduling optimization compilation method based on a directed acyclic graph, which integrates the above-mentioned instruction scheduling optimization method based on a directed acyclic graph into the RISCV-GUN-TOOLCHAIN compilation suite, including the following steps: Step 1: Design a new data structure to represent the nodes and dependencies of the directed acyclic graph, and add the designed new data structure to the gcc / sched-int.h file; at the same time, add the updated directed acyclic graph function to the gcc / sched-deps.c file; Step 2: Write a function for compound instruction operations, generate a new compound instruction, and replace the original instruction in the DAG. Add new pattern detection logic and compound operations in the combine.cc file, and define a new compound instruction mode in the riscv.md file; integrate a performance monitoring mode in GCC to allow the collection of processor performance indicators when instructions are running, and use these indicators to adjust the execution order of instructions; modify the sched-deps.c and sched-rgn.c files, add the adaptive scheduling policy module code, and dynamically adjust the instruction execution order based on runtime performance feedback to optimize processor performance; Step 3: Extend the compiler according to the encoding format of the compound instruction so that the compiler can support the compilation of the compound instruction; expand and modify the corresponding decoding unit, control unit and execution unit of the processor so that the processor can correctly execute the compound instruction and output the correct result; Step 4: Extend the GCC compiler options and add the adaptive scheduling policy dynamic adjustment function and the compilation option of the instruction compound function in the gcc / opt.cc file.

[0020] Compared with the prior art, the beneficial effects of the present invention mainly include: the instruction scheduling optimization method, device and compilation method based on directed acyclic graph proposed by the present invention integrate multi-level dependency analysis and compound instruction methods to construct a directed acyclic graph; the compound method supports the combination of load instructions, storage instructions, and fixed-point / floating-point operation instructions; and the compound instruction generation adopts a compound strategy of compounding with the predecessor node. The use of an adaptive scheduling strategy in the scheduling process can effectively improve the flexibility of instruction scheduling and the performance of the processor, reduce the pause cycle of instruction execution, and improve the execution efficiency of instructions.

[0021] In order to make the above and other objects, features and advantages of the present invention more clearly understood, preferred embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 This is a flow chart of the instruction scheduling algorithm specified in the present invention.

[0024] Figure 2 Schematic diagram of the optimized DAG of the present invention.

[0025] Figure 3 It is an integrated schematic diagram of the instruction scheduling method of the present invention.

[0026] Figure 4 Schematic diagram of the instruction scheduling optimization device of the present invention DETAILED DESCRIPTION

[0027] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0028] Example 1

[0029] Embodiment 1 provides an instruction scheduling optimization method based on a directed acyclic graph, including: initializing a directed acyclic graph, building a dependency relationship between instructions, creating a node for each instruction, and adding a weight value to the directed edge to represent the delay cycle of the instruction; defining an instruction compounding strategy, using an instruction buffer to sequentially store instructions on the directed acyclic graph, and extracting each instruction type, selecting compoundable instructions in the instruction buffer as candidate instructions according to the defined instruction compounding strategy; performing instruction compounding on the selected candidate instructions, creating a new node for the compound instruction, deleting the predecessor instruction node, and updating the directed edge on which the compound instruction has dependencies, and constructing a new directed acyclic graph; based on the updated directed acyclic graph, giving priority to scheduling instructions on the critical path and executing the instructions at the same time. The present invention can refine the directed acyclic graph by analyzing the dependency relationship between instructions, and compound the instructions at the same time, thereby improving the throughput and execution efficiency of the instructions.

[0030] The following is an explanation of the specific implementation process of the solution of this embodiment 1 with reference to the accompanying drawings. Figure 1 as well as Figure 2 The instruction scheduling optimization method based on a directed acyclic graph of the first embodiment includes the following steps:

[0031] Step 1: Optimize the DAG graph (directed acyclic graph)

[0032] Step 1-1: Initialize the DAG graph, build the dependency relationships between instructions, and create a node for each instruction. The node is used to represent the instruction, and the dependency depth of the instruction is marked on the node. At the same time, weight values are attached to the directed edges to represent the delay cycle of the instruction, and then the critical path in the DAG graph is calculated (the critical path of the DAG graph is mainly calculated to find the longest path from the starting point to the end point. The total execution time of all tasks on this path determines the shortest completion time of the entire project. The operation time on the critical path refers to the sum of the weight values attached to the directed edges on this path). Initialize the dependency relationships between instructions in the basic block.

[0033] Step 1-2: Analyze the dependencies between instructions. This includes static dependency analysis and multi-level dependency analysis. Static dependency analysis involves performing static data flow analysis to identify direct data dependencies between instructions. Static dependency analysis primarily identifies the immediate predecessor and successor instructions (i.e., dependencies) of each instruction. After static data analysis is complete, a preliminary DAG is constructed based on the dependencies.

[0034] After constructing the preliminary DAG graph, a multi-level dependency analysis method is used to capture the deep dependencies between instructions, including direct dependencies and indirect dependencies (dependencies that span one or more instructions. For example, if an addition instruction depends on the result of the previous instruction, then the previous instruction is the direct dependent instruction of the addition instruction. If a subsequent calculation instruction depends on the result of the addition instruction, then the previous instruction is the indirect dependent instruction of the subsequent calculation instruction). This method solves the bottleneck of static dependency analysis and establishes a more refined dependency graph relationship.

[0035] Steps 1-3: Perform instruction compounding. Before compounding, a compounding strategy must be defined. The compounding strategy used is to compound with predecessor instructions, prioritizing the current instruction and its predecessor instructions. The goal of this compounding is to improve instruction execution efficiency by reducing the number of instructions while ensuring that instruction dependencies are not broken. Instruction compounding can also reduce the execution cycle of instructions, thereby improving instruction execution efficiency.

[0036] When encountering specific instruction types, this application also provides a special compounding strategy. Specifically, instructions are classified into load instructions, store instructions, and fixed-point / floating-point operation types. Therefore, the following three compound modes can be defined: load-fixed-point / floating-point operation, fixed-point / floating-point-fixed-point / floating-point operation, and fixed-point / floating-point operation-store.

[0037] When encountering load, fixed-point / floating-point operation, or fixed-point / floating-point operation type, the "load-fixed-point / floating-point operation" compound mode is used to compound the load instruction with the fixed-point / floating-point operation;

[0038] When encountering fixed-point / floating-point operations, fixed-point / floating-point operations, and storage types, the composite mode of "fixed-point / floating-point operations-fixed-point / floating-point operations" is adopted;

[0039] Floating-point multiplication and addition, floating-point division, and floating-point square root instructions have longer cycles and are likely to become instructions on the critical path. When such instructions can be compounded, give priority to compounding them.

[0040] The specific instruction compounding process is as follows:

[0041] 1-3-1: Select candidate instructions and use an instruction buffer to sequentially store some instructions in the DAG (for example, sequentially fetch the first dozen instructions). Extract the type of each instruction and determine whether it belongs to the load, fixed-point / floating-point operation, or store instruction category.

[0042] Based on the compounding strategy defined above and the dependencies between instructions, compoundable instructions with no data hazards in the instruction buffer are selected as candidate instructions. These instructions need to conform to the defined compounding mode and ensure that there are no conflicts in registers and no overlapping operand addresses.

[0043] 1-3-2: Based on the analysis results of the compound strategy, the candidate instructions are compounded. After the compound operation, a new node is created for the compound instruction, and the predecessor instruction node is deleted. At the same time, the dependent directed edges related to the compound instruction are updated to reduce unnecessary dependency chains.

[0044] After the compound operation is executed, a compound instruction that performs multiple operations in the same cycle will be generated. In the DAG graph, the compound instruction is processed as a single unit, which reduces the length of the dependency chain and the dependency complexity between instructions, thereby improving the instruction throughput and overall execution efficiency.

[0045] As an optional approach, when selecting candidate instructions for compounding based on a compounding strategy, the compounding strategy can be optimized. Specifically, a machine learning algorithm (decision tree) is used to train a model to predict compound returns. The instruction type, critical path length, directed edge weight, and node weight are used as inputs, and the compound return score is used as output. The formula for calculating the selected features of the compound return score is as follows (using instructions I1 and I2 as examples):

[0046] 1) Cost of executing a single instruction:

[0047] Cs=L(I1)+L(I2)+D(I1,I2);

[0048] Where L(I): delay cycle of instruction I;

[0049] D(I1, I2): dependency delay between instruction I1 and instruction I2;

[0050] 2) Compound instruction execution cost

[0051] Cf=Max(L(I1), L(I2))+composite overhead;

[0052] Compound overhead: refers to the delay added by the hardware to execute compound instructions (assuming it is 0.5 cycles).

[0053] 3) Calculate compound returns

[0054] Compound return = (Cs-Cf) / Cs.

[0055] Traverse the candidate instructions and prioritize the instruction pairs with the highest scores for compounding.

[0056] 1-3-3: Build a new DAG graph. Based on the results of the comprehensive analysis of static dependencies, multi-level dependencies, and compound instructions, create a new node for the compound instruction. At the same time, update the current instruction node to the compound instruction node, delete the predecessor node, adjust the weight value, update the dependency depth between instructions, reduce unnecessary dependency chains, and build a new DAG graph.

[0057] Step 2: Instruction Scheduling

[0058] During the instruction scheduling process, instructions with higher dependency depth are scheduled first to ensure that instructions on the critical path are scheduled first, making the processor execution more efficient and reducing the impact of the critical path on the overall processor performance.

[0059] Dependency depth includes static and dynamic dependency depth. Static dependency depth refers to the length of the data chain between instructions; the longer the length, the higher the depth. Dynamic dependency depth primarily considers runtime factors and dynamically adjusts dependency weights. For example, increasing the weight of high-latency multiplication and division instructions will prioritize scheduling paths with increased weight.

[0060] Step 3: Instruction Execution

[0061] Step 3-1: During the instruction execution process, an adaptive scheduling strategy is used to monitor the processor's performance indicators in real time, mainly the cache hit rate and the number of pipeline pauses. The monitored data is fed back to the scheduler. The scheduler dynamically adjusts the instruction scheduling order based on the performance feedback and optimizes the subsequent scheduling process.

[0062] Specifically: When it is found that a certain instruction takes too long to execute due to a cache miss, and there are some subsequent instructions that do not depend on the result of this instruction, the scheduler will execute these subsequent instructions in advance to make full use of the processor's resources and avoid the processor being idle. If it is found that the pipeline frequently pauses at a certain execution stage, the scheduler will reschedule the order of instruction execution to minimize the number and time of pipeline pauses, thereby improving the overall execution efficiency and performance of the processor.

[0063] Step 3-2: Loop scheduling execution

[0064] Instructions in the scheduler are scheduled and executed step by step until all instructions are executed.

[0065] Example 2

[0066] The second embodiment provides an instruction scheduling optimization compilation method based on a directed acyclic graph. The second embodiment integrates the optimized scheduling method in the first embodiment into the RISCV-GNU-TOOLCHAIN compilation suite. Figure 3 , the specific steps are as follows:

[0067] Step 1: Modify the GCC source code

[0068] Step 1-1: Define a new data structure

[0069] GCC uses GIMPLE and RTL as intermediate representations to optimize the code, so the data structure is expanded at these stages to build a DAG graph of instructions and to store information about the new DAG graph.

[0070] The gcc / sched-int.h file mainly defines the internal data structures related to instruction scheduling. It redefines new data structures to represent the relationship between DAG nodes and dependencies, so that they correspond to the nodes and dependencies of the updated DAG graph.

[0071] Step 1-2: Build a DAG graph

[0072] The gcc / sched-deps.c file is responsible for generating the DAG graph.

[0073] Add the updated DAG graph functions to the gcc / sched-deps.c file to ensure that they can be used normally during the GCC optimization phase.

[0074] Step 2: Update and optimize features

[0075] Step 2-1: Compound Instructions

[0076] Based on the compounding strategy for predecessor instructions, we extend GCC's instruction pattern detection mechanism and compound instruction implementation to find instructions that can be compounded in the DAG. We write functions to operate on compound instructions, generate new compound instructions, and replace the original instructions in the DAG.

[0077] Add new mode detection logic and compound operations in the combine.cc file, and define new compound instruction modes in the riscv.md file.

[0078] Step 2-2: Adaptive adjustment strategy

[0079] A performance monitoring mode is integrated into GCC, which allows you to collect processor performance metrics such as cache hit rate, pipeline stall count, etc. when instructions are executed. These metrics can be used to adjust the scheduling strategy during compilation.

[0080] Modify the sched-deps.c and sched-rgn.c files and add the adaptive scheduling policy module code. Based on runtime performance feedback, the instruction scheduling order is dynamically adjusted to optimize performance.

[0081] Step 3: Adding a Compound Instruction

[0082] The compiler and processor do not natively support compound instructions. Compound instructions must be formatted and encoded based on their type, including the instruction's opcode, function code, and register information. Note that when the compound instruction mode is "fixed-point / floating-point-fixed-point / floating-point" mode, three registers are required, requiring the original instruction format to be readjusted for instruction encoding.

[0083] The compiler is extended according to the encoding format of the compound instruction in the compiler, so that the compiler can support the compilation of the compound instruction and can normally enable the instruction scheduling function after the compound instruction is added.

[0084] Modifications and extensions are made to the corresponding decoding unit, control unit, and execution unit of the processor so that the processor can correctly execute the compound instruction and output the correct result.

[0085] Adding instructions to the compiler and the processor is a conventional technique in the art, which is not the invention of this application and will not be described in detail here.

[0086] Step 4: Integrate compiler optimization options

[0087] To enable the new optimization features, you need to extend the GCC compiler options and add compiler options that control the adaptive scheduling and instruction compounding features in the gcc / opt.cc file.

[0088] Example 3

[0089] Example 3 provides an instruction scheduling optimization device based on a directed acyclic graph, see Figure 4 , including a data structure updater, which updates the instruction structure and inter-instruction dependencies of the directed acyclic graph;

[0090] The directed acyclic graph updater updates the directed acyclic graph based on the update results of the data structure updater, while combining static dependency analysis, multi-level dependency analysis, and instruction compound results;

[0091] Function optimizer, used to support the generation of introduced compound instructions and the call of the adaptive scheduling policy dynamic adjustment function;

[0092] A compound instruction generator, including modifying the compiler and the processor, using the modified and extended compiler to generate compound instruction encoding and modifying the extended processor architecture to support the operation of the compound instruction;

[0093] Optimization option generator, after the function optimizer supports the optimization function, update the optimization option generator and enable the new optimization function.

[0094] The above is a detailed introduction to the instruction scheduling optimization method, device and compilation method based on a directed acyclic graph provided by the present invention. Specific examples are used herein to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A directed acyclic graph-based instruction scheduling optimization compilation method, characterized in that: Integrate the directed acyclic graph-based instruction scheduling optimization method into the RISCV-GUN-TOOLCHAIN compilation suite; The instruction scheduling optimization method based on the directed acyclic graph includes: initializing the directed acyclic graph, building the dependency relationship between instructions, creating a node for each instruction, and adding a weight value to the directed edge to represent the delay cycle of the instruction; An instruction compounding strategy is defined, and an instruction buffer is used to sequentially store instructions on a directed acyclic graph, and each instruction type is extracted, and instructions that can be compounded in the instruction buffer are selected as candidate instructions according to the defined instruction compounding strategy; Perform instruction compounding on the selected candidate instructions, create new nodes for the compound instructions, delete the predecessor instruction nodes, update the directed edges that the compound instructions have dependencies on, and construct a new directed acyclic graph; based on the updated directed acyclic graph, prioritize the instructions on the critical path and execute them simultaneously; Integration into the RISCV-GUN-TOOLCHAIN compilation suite includes the following steps: Step 1: Design a new data structure to represent the nodes and dependencies of the directed acyclic graph. Add the designed new data structure to the gcc / sched-int.h file. Also, add the updated directed acyclic graph functions to the gcc / sched-deps.c file. Step 2: Write a function for compound instruction operations, generate new compound instructions, and replace the original instructions in the DAG. Add new pattern detection logic and compound operations in the combine.cc file, and define the new compound instruction pattern in the riscv.md file. Integrate a performance monitoring mode into GCC, which allows collecting processor performance metrics as instructions are executed and using these metrics to adjust the execution order of instructions; Modify the sched-deps.c and sched-rgn.c files and add the adaptive scheduling policy module code. This will dynamically adjust the instruction scheduling order based on runtime performance feedback to optimize performance. Step 3: Expand the compiler according to the encoding format of the compound instruction so that the compiler can support the compilation of the compound instruction; Expand and modify the corresponding decoding unit, control unit, and execution unit of the processor so that the processor can correctly execute compound instructions and output correct results; Step 4: Expand the GCC compiler options and add the compilation options for the adaptive scheduling policy dynamic adjustment function and the instruction compound function in the gcc / opt.cc file.

2. The instruction scheduling optimization compilation method based on directed acyclic graph according to claim 1, characterized in that: The compounding strategy is to compound the current instruction with its predecessor instruction.

3. The instruction scheduling optimization compilation method based on directed acyclic graph according to claim 2, characterized in that: The composite strategy further includes: classifying instructions into load instructions, store instructions, and fixed-point / floating-point operation instructions; When encountering load, fixed-point / floating-point operation, fixed-point / floating-point operation type instructions, the load-fixed-point / floating-point operation instruction composite mode is used; When encountering fixed-point / floating-point operations, fixed-point / floating-point operations, and storage type instructions, the fixed-point / floating-point-fixed-point / floating-point operation instruction composite mode is used; When encountering floating-point multiplication and addition, floating-point division, and floating-point square root instructions, these instructions are compounded first.

4. The instruction scheduling optimization compilation method based on directed acyclic graph according to claim 1, characterized in that: It also includes optimizing the compound strategy based on the dependency relationship, calculating the execution time of the individual instructions with dependency relationships and the execution time of the compound instructions after the instructions with dependency relationships are compounded, and calculating the ratio of the time cost reduced by the compound instructions to the time cost of the individual execution of the dependent instructions as the compound benefit score; Traverse the candidate instructions and select instruction pairs with high compound benefit scores for compounding.

5. The instruction scheduling optimization compilation method based on directed acyclic graph according to claim 4, characterized in that: The execution time of a dependent instruction is the sum of the delay cycle of the independent instruction and the dependency delay time between the instructions. The execution time of the compound instruction after compounding the instructions with dependency relationship is the sum of the longest delay cycle of the instructions in the instruction pair and the compound overhead, where the compound overhead is the delay added by the hardware executing the compound instruction.

6. The instruction scheduling optimization compilation method based on directed acyclic graph according to claim 1, characterized in that: Determining the dependency relationship between the instructions includes performing dependency analysis on the instructions in the directed acyclic graph, wherein the dependency analysis includes static dependency analysis and multi-level dependency analysis; The static dependency analysis includes defining the data structure of nodes and edges, identifying the direct data dependency between instructions, and constructing a directed acyclic graph based on the direct dependency; The multi-level dependency analysis includes capturing direct dependencies and indirect dependencies between instructions, and marking the indirect dependencies on a directed acyclic graph.

7. The instruction scheduling optimization compilation method based on directed acyclic graph according to claim 1, characterized in that: Instructions that do not have data competition hazards in the instruction buffer and can be compounded are selected as candidate instructions. There is no register conflict or operand address overlap between the compounded instructions.

8. The instruction scheduling optimization compilation method based on directed acyclic graph according to claim 6, characterized in that: During instruction scheduling, instructions with higher dependency depth are scheduled first: among instructions with direct dependencies, instructions with longer dependency chains are scheduled first; During the execution of instructions, weight values are dynamically assigned to instructions with higher latency, and the critical path of the directed acyclic graph is calculated in real time based on the weight values. During the instruction scheduling process, instructions on the critical path are scheduled first.

9. The instruction scheduling optimization compilation method based on directed acyclic graph according to claim 1, characterized in that: An adaptive scheduling strategy is used during instruction execution to dynamically monitor processor performance, collect processor performance data, and feed the data back to the scheduler. The scheduler adjusts the instruction execution order based on the fed-back processor performance data.

10. The instruction scheduling optimization compilation method based on directed acyclic graph according to claim 9, characterized in that: When an instruction takes too long to execute due to a cache miss, the scheduler executes the subsequent instruction in advance if the subsequent instruction does not depend on the instruction that missed the cache; When there are frequent pauses in the execution stage of the pipeline, the scheduler reschedules the instruction execution order.

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