Hardware network card for virtual machine program and logic circuit module configuration method

Abstract

The invention provides a hardware network card for a virtual machine program and a logic circuit module configuration method, and relates to the technical field of virtual machines, the hardware network card comprises one or more virtual machine program logic circuit modules, at least one network interface and at least one universal connection interface, and the hardware network card for the virtual machine program is formed by the one or more virtual machine program logic circuit modules, the at least one network interface and the at least one universal connection interface; the network interface sends the received network packet to a corresponding virtual machine program logic circuit module; the virtual machine program logic circuit module is used for processing the network packet; when a network packet of the virtual machine program logic circuit module needs to be transmitted to a host, the network packet is sent to the host and the hardware network card through the general connection interface, so that adjustment can be performed in a manner of unloading virtual machine hardware of the host according to the requirements of individual virtual machine program functions, and the hardware network card is relatively flexible and suitable for various scenes.

Description

Technical Field

[0001] The present application relates to the field of virtual machine technology, and in particular to a method for configuring a hardware network card and a logic circuit module for a virtual machine program. Background Art

[0002] A virtual machine is a computer program or system that simulates the hardware operating environment of a physical computer through software, allowing multiple operating systems to run simultaneously on the same hardware network card. Virtual machines have functions such as cross-platform operation, application isolation, and rapid deployment. Therefore, the configuration of the virtual machine program is of great significance to the data processing function of the hardware network card.

[0003] In the related art, some network equipment platforms can adjust the virtual machine program on the hardware to complete the subsequent network packet and other related data processing. However, in the related art, the unified adjustment of the virtual machine program is too rigid and not applicable to a variety of scenarios. Summary of the invention

[0004] The embodiment of the present application provides a method for configuring a hardware network card and a logic circuit module for a virtual machine program, so as to achieve the effect of flexible adjustment of the virtual machine program to be applicable to a variety of scenarios.

[0005] In a first aspect, an embodiment of the present application provides a hardware network card for a virtual machine program, comprising: one or more virtual machine program logic circuit modules, at least one network interface, and at least one universal connection interface;

[0006] Wherein, the one or more virtual machine program logic circuit modules are respectively communicatively connected with the network interface;

[0007] The network interface is used to receive or send network packets;

[0008] The one or more virtual machine program logic circuit modules are respectively communicatively connected to the universal connection interface;

[0009] The universal connection interface is connected to the host for communication; wherein the host includes one or more virtual machines, and the virtual machine program logic circuit module is obtained according to the virtual machine program configuration of each virtual machine;

[0010] The network interface sends the received network packet to the corresponding virtual machine program logic circuit module;

[0011] The virtual machine program logic circuit module processes the network packet;

[0012] When the network packet of the virtual machine program logic circuit module needs to be transmitted to the host, it is sent to the host through the universal connection interface.

[0013] In a possible implementation, it also includes: a local memory end and one or more virtual machine program key value query circuit modules; wherein the local memory end is respectively communicated with the one or more virtual machine program key value query circuit modules; each virtual machine program key value query circuit module is communicated with the corresponding virtual machine program logic circuit module; the network interface sends the received network packet to the corresponding virtual machine program logic circuit module; the virtual machine program logic circuit module processes the network packet; the virtual machine program logic circuit module sends the network packet to the corresponding virtual machine program key value query circuit module; the virtual machine program key value query circuit module sends the network packet to the local memory end; the local memory end stores the network packet; when the virtual machine program logic circuit module needs to pass the network packet to the host, the local memory end is accessed through the corresponding virtual machine program key value query circuit module to send the network packet to the host through the universal connection interface.

[0014] In a possible implementation, it also includes: one or more efficiency meters, wherein each efficiency meter is configured in a corresponding virtual machine program logic circuit module; each efficiency meter obtains the measured throughput of the corresponding virtual machine program logic circuit module for network packets within a preset time; determines the total throughput based on each measured throughput, and determines whether the total throughput is less than the throughput threshold; if the total throughput is less than the throughput threshold, continues to supplement additional virtual machine program logic circuit modules; if the total throughput is not less than the preset throughput, stops supplementing additional virtual machine program logic circuit modules.

[0015] In a second aspect, an embodiment of the present application provides a method for configuring a virtual machine program logic circuit module, which is used to configure a virtual machine program logic circuit module in a hardware network card as described in the first aspect; the method includes: obtaining the code of the virtual machine program of any virtual machine of the host; converting the code of the virtual machine program into the bytecode of the virtual machine program according to a virtual machine compiler; parsing the bytecode of the virtual machine program according to a bytecode parser to obtain the circuit code of the virtual machine program; converting the circuit code of the virtual machine program into the virtual machine program logic circuit module according to a field programmable gate array.

[0016] In a possible implementation, the bytecode of the virtual machine program is parsed according to the bytecode parser to obtain the circuit code of the virtual machine program, including: parsing the bytecode of the virtual machine program according to the bytecode parser to determine the instruction unit required for the bytecode of the virtual machine program; determining the circuit code of the virtual machine program according to the instruction unit. In a possible implementation, the instruction unit includes instructions and instruction execution functions, and the circuit code of the virtual machine program includes instruction decoding circuit code and instruction execution circuit code; accordingly, the bytecode of the virtual machine program is parsed according to the bytecode parser to determine the instruction unit required for the bytecode of the virtual machine program, including: parsing the bytecode of the virtual machine program according to the bytecode parser to determine the instructions and instruction execution functions required for the bytecode of the virtual machine program; accordingly, determining the circuit code of the virtual machine program according to the instruction unit includes: determining the instruction decoding circuit code of the virtual machine program according to the instruction; determining the instruction execution circuit code of the virtual machine program according to the instruction execution function.

[0017] In a possible implementation, converting the circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array includes: converting the instruction decoding circuit code and the instruction execution circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array.

[0018] In a possible implementation, the virtual machine compiler includes a compilation front end and a compilation back end; accordingly, converting the code of the virtual machine program into the bytecode of the virtual machine program according to the virtual machine compiler includes: converting the code of the virtual machine program into the bytecode of the virtual machine program according to the compiler front end, the compiler back end and preset parameters.

[0019] In a possible implementation manner, the circuit code of the virtual machine program is a preset hardware language or a configuration file.

[0020] In a possible implementation, the hardware network card further includes: one or more virtual machine program key value query circuit modules; the method includes: obtaining one or more pre-generated storage key value pairs of virtual machine programs; and converting the one or more pre-generated storage key value pairs of virtual machine programs into corresponding one or more virtual machine program key value query circuit modules according to a field programmable gate array.

[0021] In a possible implementation, the process of generating the storage key-value pair of the virtual machine program includes: obtaining any storage key value; and declaring the storage key value according to a preset language program to obtain the storage key-value pair of the virtual machine program.

[0022] In a possible implementation, after converting the storage key-value pairs of the one or more pre-generated virtual machine programs into corresponding one or more virtual machine program key value query circuit modules according to the field programmable gate array, it also includes: the host sending the initial storage key value to the universal connection interface; the universal connection interface sending the initial storage key value to the one or more virtual machine program key value query circuit modules, so that the one or more virtual machine program key value query circuit modules complete initialization.

[0023] In a third aspect, an embodiment of the present application provides an electronic device, including: a memory and a processor;

[0024] The memory stores computer-executable instructions;

[0025] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the above second aspect and / or various possible implementations of the second aspect.

[0026] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the above second aspect and / or various possible implementations of the second aspect.

[0027] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the above second aspect and / or various possible implementation methods of the second aspect.

[0028] The embodiment of the present application provides a method for configuring a hardware network card and logic circuit module for a virtual machine program. A hardware network card for a virtual machine program is formed by one or more virtual machine program logic circuit modules, at least one network interface, and at least one universal connection interface. The network interface sends the received network packet to the corresponding virtual machine program logic circuit module. The virtual machine program logic circuit module processes the network packet. When the network packet of the virtual machine program logic circuit module needs to be transmitted to the host, it is sent to the host through the universal connection interface, so that it can be adjusted according to the needs of individual virtual machine program functions by unloading the host's virtual machine hardware. It is more flexible and suitable for a variety of scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0030] Figure 1 A schematic diagram of the structure of a hardware network card for a virtual machine program provided in an embodiment of the present application Figure 1 ;

[0031] Figure 2 A flowchart of a method for configuring a virtual machine program logic circuit module provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of the structure of a hardware network card for a virtual machine program provided in an embodiment of the present application Figure 2 ;

[0033] Figure 4 A flowchart of a method for configuring a virtual machine program key value query circuit module provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of the structure of a hardware network card for a virtual machine program provided in an embodiment of the present application Figure 3 ;

[0035] Figure 6 A schematic diagram of the structure of a virtual machine program logic circuit module configuration device provided in an embodiment of the present application;

[0036] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0037] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0038] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0039] A virtual machine is a simulated version of a physical computer. It simulates the hardware operating environment of a physical computer through software, allowing multiple operating systems to run simultaneously on the same hardware network card. Virtual machines have functions such as cross-platform operation, application isolation, and rapid deployment. Therefore, the configuration of the virtual machine program is of great significance to the data processing function of the hardware network card.

[0040] In the related art, some network equipment platforms can adjust the virtual machine program on the hardware to complete the subsequent network packet and other related data processing. However, in the related art, the unified adjustment of the virtual machine program is too rigid and not applicable to a variety of scenarios.

[0041] In order to solve the above technical problems, the embodiments of the present application propose the following technical concepts: the inventor considers a hardware network card for a virtual machine program constructed by one or more virtual machine program logic circuit modules, at least one network interface and at least one universal connection interface, and based on the network interface, sends the received network packet to the corresponding virtual machine program logic circuit module so that the virtual machine program logic circuit module processes the network packet, and when the network packet of the virtual machine program logic circuit module needs to be transmitted to the host, it is sent to the host using the universal connection interface, so that it can be adjusted according to the needs of individual virtual machine program functions by unloading the host's virtual machine hardware, which is more flexible and suitable for a variety of scenarios.

[0042] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0043] Figure 1 A schematic diagram of the structure of a hardware network card for a virtual machine program provided in an embodiment of the present application Figure 1 .

[0044] like Figure 1 , a hardware network card for a virtual machine program includes: one or more virtual machine program logic circuit modules 101, at least one network interface 102 and at least one universal connection interface 103.

[0045] Among them, one or more virtual machine program logic circuit modules 101 are respectively communicatively connected with the network interface 102 .

[0046] In this embodiment, the virtual machine is an eBPF virtual machine, but may also be other virtual machines.

[0047] Among them, eBPF is the extended Berkeley packet filter.

[0048] In this embodiment, the virtual machine program logic circuit module 101 is an eBPF RISC circuit.

[0049] Among them, eBPF RISC is a reduced instruction set computer for the extended Berkeley packet filter.

[0050] In this embodiment, the network interface 102 is a Network Interface.

[0051] The network interface 102 is used to receive or send network packets.

[0052] One or more virtual machine program logic circuit modules 101 are respectively communicatively connected to the universal connection interface 103 .

[0053] In this embodiment, the universal connection interface 103 is a PCIe Interface.

[0054] The universal connection interface 103 is connected to the host 20 for communication; the host 20 includes one or more virtual machines, and the virtual machine program logic circuit module 101 is obtained according to the virtual machine program configuration of each virtual machine.

[0055] In this embodiment, the virtual machine currently has ≥100 instructions. In hardware circuit design, the more instructions there are, the larger the area of ​​the "instruction decoder" and "arithmetic logic unit" circuit logic, and the slower the circuit speed (clock). However, most virtual machine programs will not use all 100 instructions. According to observation, most of them only use the most common 30% of instructions.

[0056] The network interface 102 sends the received network packet to the corresponding virtual machine program logic circuit module 101 .

[0057] The virtual machine program logic circuit module 101 processes the network packets.

[0058] In this embodiment, the network packets are processed, including: packet loss processing of the network packets, forwarding processing of the network packets after address modification, original transmission processing of the network packets and other processing.

[0059] When the network packet of the virtual machine program logic circuit module 101 needs to be transmitted to the host 20 , it is sent to the host 20 through the universal connection interface 103 .

[0060] The hardware network card for the virtual machine program provided in this embodiment is composed of one or more virtual machine program logic circuit modules, at least one network interface and at least one universal connection interface. The network interface sends the received network packet to the corresponding virtual machine program logic circuit module. The virtual machine program logic circuit module processes the network packet. When the network packet of the virtual machine program logic circuit module needs to be transmitted to the host, it is sent to the host through the universal connection interface, so that it can be adjusted according to the needs of individual virtual machine program functions by unloading the host's virtual machine hardware. It is more flexible and suitable for a variety of scenarios.

[0061] Figure 2 This is a flowchart of a method for configuring a virtual machine program logic circuit module provided in an embodiment of the present application. The execution subject of this embodiment may be Figure 1 The hardware network card used for the virtual machine program in the embodiment shown is not particularly limited in this embodiment. Figure 2 As shown, the method includes:

[0062] S201: Obtain the code of a virtual machine program of any virtual machine of the host.

[0063] In this embodiment, the code of the virtual machine program may be C language code or other code.

[0064] The virtual machine may be an eBPF virtual machine.

[0065] Among them, the virtual machine program can be an eBPF virtual machine program.

[0066] S202: Convert the code of the virtual machine program into bytecode of the virtual machine program according to the virtual machine compiler.

[0067] In this embodiment, the virtual machine compiler includes a compiler front end and a compiler back end; accordingly, step S202 specifically includes: converting the code of the virtual machine program into the bytecode of the virtual machine program according to the compiler front end, the compiler back end and preset parameters.

[0068] In this embodiment, the compiler front end is clang; the compiler back end is LLVM; and the preset parameter is -targetbpf.

[0069] Among them, clang is a lightweight compiler for C, C++, and Objective-C; LLVM is a framework system for building compilers.

[0070] In this embodiment, the bytecode of the virtual machine program is eBPF bytecode.

[0071] Among them, eBPF bytecode is the bytecode of the extended Berkeley packet filter.

[0072] For example, any eBPF bytecode is as follows:

[0073] { 0x28, 0, 0, 0x0000000c}, { 0x15, 0, 3, 0x00000800}, { 0x30, 0, 0, 0x00000017}, { 0x15, 0, 1, 0x00000011}, { 0x6, 0, 0, 0x00040000}, { 0x6, 0,0, 0x00000000}

[0074] Among them, {0x15, 0, 3, 0x00000800} is opcode (0x15 instruction), dst_reg (r0), src_reg (r3), offset / immediate (0x00000800)

[0075] S203: Parse the bytecode of the virtual machine program according to the bytecode parser to obtain the circuit code of the virtual machine program.

[0076] In this embodiment, the circuit code of the virtual machine program is a preset hardware language or configuration file.

[0077] The preset hardware language may be any one of Verilog, VHDL or SystemVerilog RTL, or other hardware languages.

[0078] Specifically, step S203 includes:

[0079] S2031: Parse the bytecode of the virtual machine program according to the bytecode parser to determine the instruction unit required by the bytecode of the virtual machine program.

[0080] In this embodiment, the instruction unit includes instructions and instruction execution functions; accordingly, step S2031 is specifically: parsing the bytecode of the virtual machine program according to the bytecode parser to determine the instructions and instruction execution functions required by the bytecode of the virtual machine program.

[0081] In this embodiment, the bytecode parser is a bytecode parser.

[0082] The bytecode parser can be implemented in any software language, such as C language, Java or other software languages.

[0083] In addition, the corresponding register may also be determined according to step S2031.

[0084] S2032: Determine the circuit code of the virtual machine program according to the instruction unit.

[0085] In this embodiment, the circuit code of the virtual machine program includes an instruction decoding circuit code and an instruction execution circuit code; accordingly, step S2032 specifically includes:

[0086] S20321: Determine the instruction decoding circuit code of the virtual machine program according to the instruction.

[0087] Specifically, an instruction is fetched through an Instruction Fetch action, and an Instruction Decode action is performed according to the instruction to determine the instruction decoding circuit code of the virtual machine program.

[0088] S20322: Determine the instruction execution circuit code of the virtual machine program according to the instruction execution function.

[0089] S204: Converting the circuit code of the virtual machine program into a virtual machine program logic circuit module according to the field programmable gate array.

[0090] Specifically, step S204 is as follows: according to the field programmable gate array, the instruction decoding circuit code and the instruction execution circuit code of the virtual machine program are converted into a virtual machine program logic circuit module.

[0091] In this embodiment, the field programmable gate array is an FPGA.

[0092] Specifically, an Execution action is performed according to the field programmable gate array to convert the instruction decoding circuit code and the instruction execution circuit code of the virtual machine program into a virtual machine program logic circuit module.

[0093] Exemplarily, the arithmetic logic unit in the instruction may be addition, subtraction, left shift, right shift, NOT, AND, OR and other arithmetic logic.

[0094] In addition, the virtual machine program logic circuit module can also perform Memory Read / Write (read and write memory) actions and Write Back (update cache) actions.

[0095] The virtual machine program logic circuit module configuration method provided in the present embodiment obtains the code of the virtual machine program of any virtual machine of the host; converts the code of the virtual machine program into the bytecode of the virtual machine program according to the virtual machine compiler; parses the bytecode of the virtual machine program according to the bytecode parser to obtain the circuit code of the virtual machine program; converts the circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array, and parses the bytecode of the virtual machine program by the bytecode parser to determine the virtual machine program logic circuit module, so that it can be adjusted according to the needs of individual virtual machine program functions in the future, which is more flexible and suitable for a variety of scenarios.

[0096] In addition, the bytecode of the virtual machine program is parsed according to the bytecode parser to determine the instruction unit required by the bytecode of the virtual machine program; the circuit code of the virtual machine program is determined according to the instruction unit, so that a virtual machine program logic circuit module with optimized area and speed can be obtained to realize virtual machine hardware acceleration.

[0097] Figure 3 A schematic diagram of the structure of a hardware network card for a virtual machine program provided in an embodiment of the present application Figure 2 .exist Figure 1 Based on the embodiment of the present invention, the hardware network card for the virtual machine program further includes: a local memory terminal 104 and one or more virtual machine program key value query circuit modules 105;

[0098] The local memory terminal 104 is respectively connected to one or more virtual machine program key value query circuit modules 105 for communication.

[0099] In this embodiment, the virtual machine program key value query circuit module 105 is a KVS BPF Map circuit.

[0100] The BPF Map uses the memory of the host 20 to store the BPF Map data.

[0101] Among them, the KVS BPF Map circuit converts the software BPF Map into high-speed hardware, and the Map access speed can be increased by 10 to 20 times.

[0102] Among them, KVS is a special type of computer storage used in some very high-speed search programs.

[0103] Among them, BPF Map stores key-value pairs.

[0104] Each virtual machine program key value query circuit module 105 is communicatively connected with the corresponding virtual machine program logic circuit module 101 .

[0105] In this embodiment, the discussion about the virtual machine program logic circuit module 101 has been Figure 1 The corresponding embodiments have been described and will not be repeated here.

[0106] The network interface 102 sends the received network packet to the corresponding virtual machine program logic circuit module 101 .

[0107] In this embodiment, the discussion about the network interface 102 has been Figure 1 The corresponding embodiments have been described and will not be repeated here.

[0108] The virtual machine program logic circuit module 101 processes the network packets.

[0109] In this embodiment, the discussion on processing network packets has been Figure 1 The corresponding embodiments have been described and will not be repeated here.

[0110] The virtual machine program logic circuit module 101 sends the network packet to the corresponding virtual machine program key value query circuit module 105 .

[0111] The virtual machine program key value query circuit module 105 sends the network packet to the local memory end 104 .

[0112] The local memory terminal 104 stores the network packets.

[0113] When the virtual machine program logic circuit module 101 needs to transmit a network packet to the host 20 , the corresponding virtual machine program key value query circuit module 105 accesses the local memory terminal 104 to send the network packet to the host 20 through the universal connection interface 103 .

[0114] The hardware network card for virtual machine programs provided in this embodiment adds a local memory terminal and one or more virtual machine program key value query circuit modules; sends the received network packet to the corresponding virtual machine program logic circuit module through the network interface; the virtual machine program logic circuit module processes the network packet; the virtual machine program logic circuit module sends the network packet to the corresponding virtual machine program key value query circuit module; the virtual machine program key value query circuit module sends the network packet to the local memory terminal; the local memory terminal stores the network packet; when the virtual machine program logic circuit module needs to pass the network packet to the host, the local memory terminal is accessed through the corresponding virtual machine program key value query circuit module to send the network packet to the host through the universal connection interface. By adding the local memory terminal and the virtual machine program key value query circuit module, the read and write speed of the hardware network card is improved.

[0115] Figure 4This is a flowchart of a method for configuring a virtual machine program key value query circuit module provided in an embodiment of the present application. The execution subject of this embodiment may be Figure 3 The hardware network card used for the virtual machine program in the embodiment shown is not particularly limited in this embodiment. Figure 4 As shown, the method includes:

[0116] S301: Obtain storage key-value pairs of one or more pre-generated virtual machine programs.

[0117] In this embodiment, the process of generating the storage key-value pair of the virtual machine program specifically includes:

[0118] S3011: Get any storage key value.

[0119] S3012: Declare the storage key value according to the preset language program to obtain the storage key value pair of the virtual machine program.

[0120] In this embodiment, the preset language program may be a C language program or other language programs.

[0121] Specifically, the storage key value is declared in a Key / Value manner according to the C language program to obtain the storage key-value pair of the virtual machine program.

[0122] For example, the Key / Value is "port0" / 3003, "port2" / 1234, which means that the key "port0" is used to determine the corresponding value to obtain 3003, that is, the port 0 of the network port is 3003 at this time.

[0123] Among them, the storage key-value pairs of the virtual machine program can be reflected in the Struct structure.

[0124] S302: Convert one or more pre-generated storage key-value pairs of virtual machine programs into corresponding one or more virtual machine program key-value query circuit modules according to the field programmable gate array.

[0125] In this embodiment, after step S302, steps a to b are further included:

[0126] Step a: The host sends the initial storage key value to the general connection interface.

[0127] Step b: The general connection interface sends the initial storage key value to one or more virtual machine program key value query circuit modules, so that the one or more virtual machine program key value query circuit modules complete initialization.

[0128] In addition, the storage key value for updating can be sent to one or more virtual machine program key value query circuit modules via the universal connection interface according to a preset period, so that the one or more virtual machine program key value query circuit modules complete the update.

[0129] The preset period may be 1 day, 1 week or other periods.

[0130] The virtual machine program key value query circuit module configuration method provided in this embodiment obtains one or more pre-generated storage key value pairs of virtual machine programs; converts the one or more pre-generated storage key value pairs of virtual machine programs into corresponding one or more virtual machine program key value query circuit modules according to the field programmable gate array, thereby laying a foundation for improving the read and write speed of the subsequent hardware network card.

[0131] Figure 5 A schematic diagram of the structure of a hardware network card for a virtual machine program provided in an embodiment of the present application Figure 3 ,exist Figure 1 Based on the embodiment of the present invention, the hardware network card for the virtual machine program further includes: one or more performance detectors, wherein each performance detector is configured in the corresponding virtual machine program logic circuit module 101.

[0132] Each performance meter obtains the measured throughput of the network packets by the corresponding virtual machine program logic circuit module 101 within a preset time.

[0133] In this embodiment, the preset time may be any one of 1 day, 2 days or 3 days, or other time.

[0134] In this embodiment, the throughput is throughput.

[0135] The total throughput is determined according to each measured throughput, and it is determined whether the total throughput is less than a throughput threshold.

[0136] In this embodiment, the throughput threshold is Threshold, which can be set to any value among 0.9, 2.0 or 3.0, or can be determined to be other values.

[0137] If the total throughput is less than the throughput threshold, then the additional virtual machine program logic circuit modules continue to be supplemented; if the total throughput is not less than the preset throughput, then the additional virtual machine program logic circuit modules are stopped from being supplemented.

[0138] In addition, if the total throughput is not less than the preset throughput, the replenishment of the additional virtual machine program logic circuit module is stopped, and a new hardware network card is replaced to continue replenishing the additional virtual machine program logic circuit module.

[0139] The hardware network card for virtual machine programs provided in this embodiment adds one or more efficiency meters, wherein each efficiency meter is configured in a corresponding virtual machine program logic circuit module; through each efficiency meter, the measured throughput of the corresponding virtual machine program logic circuit module for network packets within a preset time is obtained; the total throughput is determined according to each measured throughput, and it is determined whether the total throughput is less than the throughput threshold; if the total throughput is less than the throughput threshold, additional virtual machine program logic circuit modules continue to be supplemented; if the total throughput is not less than the preset throughput, the supplement of additional virtual machine program logic circuit modules is stopped, so that the operation of the hardware network card can be regularly controlled to ensure the efficient operation of the hardware network card.

[0140] Figure 6 A schematic diagram of the structure of a virtual machine program logic circuit module configuration device provided in an embodiment of the present application, such as Figure 6 As shown, the virtual machine program logic circuit module configuration device provided in this embodiment includes: a first acquisition module 601, a first conversion module 602, a parsing module 603 and a conversion module 604.

[0141] A first acquisition module 601 is used to acquire the code of a virtual machine program of any virtual machine of the host;

[0142] A first conversion module 602, configured to convert the code of the virtual machine program into the bytecode of the virtual machine program according to the virtual machine compiler;

[0143] A parsing module 603, used for parsing the bytecode of the virtual machine program according to a bytecode parser to obtain a circuit code of the virtual machine program;

[0144] The conversion module 604 is used to convert the circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array.

[0145] In a possible design, the parsing module 603 specifically includes:

[0146] A parsing unit, configured to parse the bytecode of the virtual machine program according to the bytecode parser to determine the instruction unit required by the bytecode of the virtual machine program;

[0147] A determination unit is used to determine the circuit code of the virtual machine program according to the instruction unit.

[0148] In a possible design, the instruction unit includes instructions and instruction execution functions, and the circuit code of the virtual machine program includes instruction decoding circuit code and instruction execution circuit code; accordingly, the parsing unit is specifically used to: parse the bytecode of the virtual machine program according to the bytecode parser to determine the instructions and instruction execution functions required by the bytecode of the virtual machine program;

[0149] Accordingly, the determining unit specifically includes:

[0150] A first determining unit, configured to determine the instruction decoding circuit code of the virtual machine program according to the instruction;

[0151] The second determining unit is used to determine the instruction execution circuit code of the virtual machine program according to the instruction execution function.

[0152] In a possible design, the conversion module 604 is specifically used to: convert the instruction decoding circuit code and the instruction execution circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array.

[0153] In a possible design, the virtual machine compiler includes a compilation front end and a compilation back end; accordingly, the first conversion module 602 is specifically used to: convert the code of the virtual machine program into the bytecode of the virtual machine program according to the compiler front end, the compiler back end and preset parameters.

[0154] In a possible design, the circuit code of the virtual machine program is a preset hardware language or configuration file.

[0155] In a possible design, the hardware network card further includes: one or more virtual machine program key value query circuit modules; the device further includes:

[0156] A second acquisition module, used to acquire storage key-value pairs of one or more pre-generated virtual machine programs;

[0157] The second conversion module is used to convert the storage key-value pairs of the one or more pre-generated virtual machine programs into corresponding one or more virtual machine program key-value query circuit modules according to the field programmable gate array.

[0158] In one possible design, the device further includes:

[0159] A third acquisition module is used to obtain any storage key value;

[0160] The declaration module is used to declare the storage key value according to a preset language program to obtain a storage key value pair of the virtual machine program.

[0161] In one possible design, the device further includes:

[0162] A first sending module, used for the host, to send the initial storage key value to the universal connection interface;

[0163] The second sending module is used for the universal connection interface to send the initial storage key value to one or more virtual machine program key value query circuit modules, so that the one or more virtual machine program key value query circuit modules complete initialization.

[0164] The virtual machine program logic circuit module configuration device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and this embodiment will not be described in detail here.

[0165] Figure 7 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 7 As shown, the electronic device provided in this embodiment includes: at least one processor 701 and a memory 702. Optionally, the device further includes a communication component 703. The processor 701, the memory 702 and the communication component 703 are connected via a bus.

[0166] In a specific implementation process, at least one processor 701 executes the computer-executable instructions stored in the memory 702, so that at least one processor 701 executes the above method.

[0167] The specific implementation process of the processor 701 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0168] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the application may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0169] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk storage.

[0170] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0171] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0172] An embodiment of the present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0173] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0174] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0175] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0176] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0177] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0178] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program codes.

[0179] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0180] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application, are not limited to the precise structures described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A hardware network card for a virtual machine program, characterized in that: include: One or more virtual machine program logic circuit modules, at least one network interface and at least one universal connection interface; Wherein, the one or more virtual machine program logic circuit modules are respectively communicatively connected with the network interface; The network interface is used to receive or send network packets; The one or more virtual machine program logic circuit modules are respectively communicatively connected to the universal connection interface; The universal connection interface is connected to the host for communication; wherein the host includes one or more virtual machines, and the virtual machine program logic circuit module is obtained according to the virtual machine program configuration of each virtual machine; The network interface sends the received network packet to the corresponding virtual machine program logic circuit module; The virtual machine program logic circuit module processes the network packet; When the network packet of the virtual machine program logic circuit module needs to be transmitted to the host, it is sent to the host through the universal connection interface.

2. The hardware network card according to claim 1, characterized in that: Also includes: A local memory terminal and one or more virtual machine program key value query circuit modules; Wherein, the local memory end is respectively connected to the one or more virtual machine program key value query circuit modules for communication; Each virtual machine program key value query circuit module is communicatively connected with the corresponding virtual machine program logic circuit module; The network interface sends the received network packet to the corresponding virtual machine program logic circuit module; The virtual machine program logic circuit module processes the network packet; The virtual machine program logic circuit module sends the network packet to the corresponding virtual machine program key value query circuit module; The virtual machine program key value query circuit module sends the network packet to the local memory end; The local memory end stores the network packets; When the virtual machine program logic circuit module needs to transmit the network packet to the host, the local memory end is accessed through the corresponding virtual machine program key value query circuit module to send the network packet to the host through the universal connection interface.

3. The hardware network card according to claim 1 or 2, characterized in that: Also includes: One or more performance measurement devices, wherein each performance measurement device is configured in a corresponding virtual machine program logic circuit module; Each efficiency meter obtains the measured throughput of the network packets by the corresponding virtual machine program logic circuit module within a preset time; Determine a total throughput according to each measured throughput, and determine whether the total throughput is less than a throughput threshold; If the total throughput is less than the throughput threshold, continue to add additional virtual machine program logic circuit modules; If the total throughput is not less than the preset throughput, the replenishment of additional virtual machine program logic circuit modules is stopped.

4. A method for configuring a virtual machine program logic circuit module, characterized in that: Used to configure the virtual machine program logic circuit module in the hardware network card as claimed in claim 1; the method comprises: Obtain the code of a virtual machine program of any virtual machine of the host; Converting the code of the virtual machine program into the bytecode of the virtual machine program according to the virtual machine compiler; Parsing the bytecode of the virtual machine program according to the bytecode parser to obtain the circuit code of the virtual machine program; The circuit code of the virtual machine program is converted into the virtual machine program logic circuit module according to the field programmable gate array.

5. The method according to claim 4, characterized in that The step of parsing the bytecode of the virtual machine program according to the bytecode parser to obtain the circuit code of the virtual machine program includes: Parsing the bytecode of the virtual machine program according to the bytecode parser to determine the instruction unit required by the bytecode of the virtual machine program; The circuit code of the virtual machine program is determined according to the instruction unit.

6. The method according to claim 5, characterized in that The instruction unit includes instructions and instruction execution functions, and the circuit code of the virtual machine program includes instruction decoding circuit code and instruction execution circuit code; Accordingly, parsing the bytecode of the virtual machine program according to the bytecode parser to determine the instruction unit required by the bytecode of the virtual machine program includes: Parsing the bytecode of the virtual machine program according to the bytecode parser to determine the instructions and instruction execution functions required by the bytecode of the virtual machine program; Accordingly, the determining the circuit code of the virtual machine program according to the instruction unit includes: Determine the instruction decoding circuit code of the virtual machine program according to the instruction; The instruction execution circuit code of the virtual machine program is determined according to the instruction execution function.

7. The method according to claim 6, characterized in that The converting the circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array includes: According to the field programmable gate array, the instruction decoding circuit code and the instruction execution circuit code of the virtual machine program are converted into the virtual machine program logic circuit module.

8. The method according to claim 4, characterized in that The virtual machine compiler includes a compilation front end and a compilation back end; Accordingly, converting the code of the virtual machine program into the bytecode of the virtual machine program according to the virtual machine compiler includes: The code of the virtual machine program is converted into the bytecode of the virtual machine program according to the compiler front end, the compiler back end and preset parameters.

9. The method according to any one of claims 4 to 8, characterized in that: The circuit code of the virtual machine program is a preset hardware language or a configuration file.

10. The method according to claim 4, characterized in that The hardware network card also includes: one or more virtual machine program key value query circuit modules; The method comprises: Obtaining storage key-value pairs of one or more pre-generated virtual machine programs; The one or more pre-generated storage key-value pairs of the virtual machine programs are converted into corresponding one or more virtual machine program key-value query circuit modules according to the field programmable gate array.

11. The method according to claim 10, characterized in that The process of generating the storage key-value pair of the virtual machine program includes: Get any storage key value; The storage key value is declared according to a preset language program to obtain a storage key value pair of the virtual machine program.

12. The method according to claim 10 or 11, characterized in that: After converting the one or more pre-generated virtual machine program storage key-value pairs into corresponding one or more virtual machine program key-value query circuit modules according to the field programmable gate array, the method further includes: The host sends the initial storage key value to the universal connection interface; The universal connection interface sends the initial storage key value to one or more virtual machine program key value query circuit modules, so that the one or more virtual machine program key value query circuit modules complete initialization.

13. An electronic device, characterized in that: include: Memory and processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the virtual machine program logic circuit module configuration method according to any one of claims 4 to 11.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the virtual machine program logic circuit module configuration method according to any one of claims 4 to 11.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method for configuring a virtual machine program logic circuit module is implemented as described in any one of claims 4 to 11.

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