A real-time debugging method and device for monitoring internal signals of an FPGA

Abstract

The present invention provides a real-time debugging method for monitoring internal signals of an FPGA, which includes creating a VIO core and embedding it into a user circuit; the host computer inputs instructions to the user circuit through a JTAG interface, and the JTAG control module of the VIO core receives the instructions, stores and analyzes the instructions, and inputs the instructions to an instruction parsing module according to the instruction analysis result for instruction splitting and latching operations; the instruction splitting result is sent to a control information processing module for execution, and according to the instruction execution result, an enable signal, a VIO core instruction, and parameters of an output instruction are sent to an execution module for execution; after the execution module completes the corresponding work, the JTAG interface status continues to jump backward, and each module does not act during the transmission process. When the JTAG enters the signal sending state, an output arbitration module sends the sampling result to the JTAG interface for output. The present invention also provides a real-time debugging device for monitoring internal signals of an FPGA.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and particularly relates to a real-time debugging method and device for monitoring internal signals of an FPGA. Background Art

[0002] A field programmable gate array (FPGA) is a large-scale programmable device, which solves the deficiencies of custom circuits. Users can describe the required functions through a hardware description language, then compile the description language into a bitstream file through software, and finally implement the configuration of the FPGA. The field programmable gate array (FPGA) has the advantages of being programmable, reconfigurable, and easy to use, and is widely used in various fields.

[0003] The complete design process of an FPGA (field programmable gate array) includes main steps such as circuit design and input, functional simulation, synthesis, implementation, placement and routing, board-level verification, and debugging.

[0004] In the prior art, when designing an FPGA, users need to add or modify excitation signals during board-level verification and debugging, and even increase the board-level IO interfaces. After modification, the project needs to be re-performed with logic synthesis, routing, placement, timing analysis, and generation of a bitstream. With the continuous expansion of the FPGA scale and the continuous enrichment of internal resources, the circuit modules developed by engineers are gradually becoming large, and the above process will increase the complexity of debugging and bring a great time cost.

[0005] Therefore, it is necessary to develop a new real-time debugging method and device that can monitor internal signals of an FPGA, which can drive and monitor internal signals of the FPGA in real time without recompiling the code and reconfiguring the FPGA, so as to improve the debugging efficiency. Summary of the Invention

[0006] The present invention provides a real-time debugging method and device for monitoring internal signals of an FPGA, which can embed virtual input and output interfaces in a user circuit, allowing users to drive and monitor internal signals of the FPGA in real time through a user interface, without recompiling the code and reconfiguring the FPGA, improving the user design ability and debugging efficiency.

[0007] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one or part or all of the above purposes or other purposes, a real-time debugging method for monitoring internal signals of an FPGA provided by a technical solution of the present invention includes creating a VIO core and embedding it into a user circuit; the host computer inputs instructions to the user circuit through a JTAG interface, and the JTAG control module of the VIO core receives the instructions, stores and analyzes the instructions, and inputs the instructions to an instruction parsing module according to the instruction analysis result for instruction splitting and latching operations; the instruction splitting result is sent to a control information processing module for execution, and an enable signal, a VIO core instruction, and parameters of an output instruction are sent to an execution module for execution according to the instruction execution result; after the execution module completes the corresponding work, the JTAG interface status continues to jump backward, and each module does not operate during the transmission process. When the JTAG enters the signal sending state, an output arbitration module sends the sampling result to the JTAG interface for output. Compared with the prior art, the present invention embeds a virtual input / output interface in the user circuit. The bit width and quantity of the interface are customized by the user, allowing the user to drive and monitor the internal signals of the FPGA in real time through a user interface without recompiling the code and reconfiguring the FPGA, improving the user design ability and debugging efficiency.

[0009] Integrate, place and route the generated VIO core with the user circuit, generate a user circuit with VIO function, and configure the generated bitstream file into the FPGA.

[0010] Create a VIO core in the user interface and embed it into the user circuit. After creating the VIO core, corresponding register transfer level code is generated.

[0011] After the VIO core receives an instruction, when it judges that the latched value of the instruction is the corresponding synchronization header, the enable signal of the VIO core is pulled high and distributed to the input instruction parsing module and the execution module.

[0012] The execution module includes a VIO signal input monitoring module and a VIO signal output monitoring module; the VIO signal input monitoring module is used for input signal refresh instructions; the VIO signal output monitoring module is used for executing output signal refresh instructions, output signal distribution instructions, and output signal reset instructions.

[0013] When multiple VIO cores embedded in the user circuit are instantiated simultaneously, the output arbitration module arbitrates the output order, polls the VIO windows that need to upload data to the JTAG interface, and uploads the data of the next VIO window after the data upload of the previous VIO window is completed; if there is no data to upload, it is skipped until all VIO windows have been polled.

[0014] According to the debugging requirements of the user, any of the VIO cores can be instantiated multiple times. Each instantiation will generate a new window on the host computer, and the output data of all windows on the host computer is polled and output by the output arbitration module.

[0015] A real-time debugging device for monitoring internal signals of an FPGA provided by another technical solution of the present invention includes: a VIO core embedded in a user circuit, where the VIO core is provided with a JTAG status module and a JTAG control module. The JTAG status module and the JTAG control module receive signals input through a JTAG interface and input the processing results into an input instruction parsing module; the input instruction parsing module is used for splitting and latching input instructions; a VIO function control module, including a control information processing module that receives the split result output by the input instruction parsing module and an execution module responsible for executing instructions; an output arbitration module. The VIO core communicates with a JTAG output interface through an output arbitration polling module, and when the JTAG enters a signal sending state, the output of the execution module is sent to the JTAG interface.

[0016] The control information processing module determines the specific execution instruction of the VIO core and sends relevant enable signals, VIO instructions, and parameters of output instructions to the execution module; the execution module includes a VIO signal input monitoring module and a VIO signal output monitoring module; the VIO signal input monitoring module is used for input signal refresh instructions; the VIO signal output monitoring module is used for executing output signal refresh instructions, output signal sending instructions, and output signal reset instructions.

[0017] When the VIO signal input monitoring module receives an input signal refresh instruction, it samples the target circuit connected to the VIO signal input monitoring module and processes and sends the sampling result to the output arbitration module.

[0018] When the VIO signal output monitoring module receives an output signal refresh, it samples the target circuit connected to the VIO signal output monitoring module, processes the sampling result, and sends it to the output arbitration module; when the VIO signal output monitoring module receives an output signal sending instruction, it sends the output parameters set by the user interface to the user circuit to drive the target circuit connected to the user circuit; when the VIO signal output monitoring module receives an output reset instruction, the VIO signal output monitoring module will send the default value generated by setting the VIO core to the user circuit.

[0019] When the multiple VIO cores are embedded in the user circuit, the output arbitration module arbitrates the output order of the multiple VIO cores.

[0020] The number of input signal ports of the VIO signal input monitoring module and the number of output signal ports of the VIO signal output monitoring module support multiple groups, and the bit width range of each group of signals is 1-32 bits.

[0021] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. The VIO core of the present invention can be used for debugging and fault reproduction, which is efficient and flexible in use. At the same time, it can drive and monitor the user circuit in real time, with configurable parameters and simple use. Moreover, there is no need to perform logic synthesis and layout and wiring multiple times, which can greatly reduce the time cost and improve the efficiency of debugging and fault reproduction.

[0022] 2. The user circuit embedded with the VIO core in the present invention can set the number of channels and the signal bit width, and can operate multiple-bit signals simultaneously during use. Different VIO cores can be instantiated and used at the same time, and the same VIO core also supports multiple instantiations.

[0023] 3. The VIO core circuit structure in the present invention is flexible, and it can share the JTAG interface with other functional circuits during use and poll the JTAG interface to communicate with the host computer.

[0024] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. Brief Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for use in the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0026] Figure 1 It is a design diagram of the real-time debugging device for monitoring internal signals of the FPGA of the present invention. Detailed Embodiments

[0027] Regarding the foregoing and other technical contents, features, and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, or back, etc., are only references to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0028] Embodiment 1

[0029] Embodiment 1 provides a real-time debugging method for monitoring internal signals of an FPGA, including creating a VIO core (here, the VIO (Virtual Input Output) core is a virtual input-output core, mainly used to monitor and drive internal FPGA signals in real time), and embedding it into the user circuit. The host computer inputs instructions to the user circuit through the JTAG interface. The JTAG control module of the VIO core receives the instructions, stores and analyzes the instructions, and inputs the instructions to the instruction parsing module according to the instruction analysis result for instruction splitting and latching operations; the instruction splitting result is sent to the control information processing module for execution, and the enable signal, VIO core instruction, and parameters of the output instruction are sent to the execution module for execution according to the instruction execution result; after the execution module completes the corresponding work, the JTAG interface status continues to jump backward, and each module does not act during the transfer process. When the JTAG enters the signal sending state, the output arbitration module sends the sampling result to the JTAG interface for output.

[0030] The following is a specific explanation of the technical solution of the present invention:

[0031] The created VIO core is embedded into the user circuit. The specific embedding strategy can refer to Figure 1 the design diagram of the real-time debugging device for monitoring internal signals of the FPGA; multiple VIO cores can be set and can be embedded into the user circuit together with other functional circuits. The VIO cores and other functional circuits share the JTAG interface for data input and output. For the convenience of user operation, the user can operate the user interface to create a VIO core. When creating the VIO core, the corresponding register transfer level code of the VIO core will be generated. After creating the VIO core, the generated VIO core is synthesized, placed and routed with the user circuit, and a user circuit with VIO function is generated, and the generated bitstream file is configured into the FPGA.

[0032] The user directly operates the user interface, and the host computer sends corresponding instructions to the user circuit through the JTAG. After the VIO core in the user circuit receives the instructions, it stores the instructions. When it is judged that the latched value of the instruction is the corresponding synchronization header, the VIO core enable signal is pulled high and distributed to the input instruction parsing module and the execution module.

[0033] The input instruction parsing module will split and latch the instructions input by the JTAG, and at the same time send the splitting result to the control information processing module. The control information processing module judges the specific execution instructions of the VIO core and sends the relevant enable signals, VIO instructions, and specific parameters of the output instructions to each subsequent execution module.

[0034] The execution module includes a VIO signal input monitoring module and a VIO signal output monitoring module; the VIO signal input monitoring module is used to input a signal refresh instruction. When the VIO signal input monitoring module receives the input signal refresh instruction, it samples the target circuit connected to the VIO signal input monitoring module and processes and sends the sampling result to the output arbitration module for selection and output;

[0035] The VIO signal output monitoring module is used to execute an output signal refresh instruction, an output signal sending instruction, and an output signal reset instruction. When the VIO signal output monitoring module receives an output signal refresh, it samples the target circuit connected to the VIO signal output monitoring module, processes the sampling result, and sends it to the output arbitration module; when the VIO signal output monitoring module receives an output signal sending instruction, it sends the output parameters set by the user interface to the user circuit to drive the target circuit connected to the user circuit; when the VIO signal output monitoring module receives an output reset instruction, the VIO signal output monitoring module will send the default value generated by setting the VIO kernel to the user circuit.

[0036] After the execution module finishes the corresponding work, the JTAG interface status will continue to jump backward. During the signal transmission process, each module does not operate. When the JTAG enters the signal sending state, the output arbitration module will send the sampling result to the JTAG interface.

[0037] As an implementation method, when multiple VIO kernels are embedded in the user circuit in Embodiment 1 and are instantiated (configured) simultaneously, the output arbitration module arbitrates the output order, polls the VIO windows that need to upload data to the JTAG interface, and uploads the data of the next VIO window after the data upload of the previous VIO window is completed; if there is no data to upload, it will be skipped, and the above operation steps will be looped until all VIO windows have been polled.

[0038] As an implementation method, any VIO kernel in Embodiment 1 can be instantiated multiple times according to the user's debugging needs. Any VIO kernel can be instantiated (configured) multiple times, and each instantiation will generate a new window on the host computer. The output data of all windows on the host computer is polled and output by the output arbitration module.

[0039] Through the method in Embodiment 1, the characteristics of real-time monitoring / driving of the target circuit are realized by adding VIO kernels (virtual input / output circuits). At the same time, the technical solution of this embodiment supports the simultaneous use of multiple windows, supports the characteristics of multi-channel and multi-bit signal operation of the user circuit, supports the characteristics of being compatible with other functional circuits, and can reproduce the faults of multi-parameter circuits, which can save the time of logic synthesis and layout and wiring.

[0040] Embodiment 2

[0041] Embodiment 2 provides a real-time debugging device for monitoring internal signals of an FPGA, including: a VIO core embedded in a user circuit, where the VIO core is provided with a JTAG status module and a JTAG control module. The JTAG status module and the JTAG control module receive signals input through the JTAG interface and input the processing results into an input instruction parsing module; the input instruction parsing module is used for splitting and latching input instructions; there is also a VIO function control module, which includes a control information processing module that receives the splitting result output by the input instruction parsing module and an execution module responsible for instruction execution; and an output arbitration module. The VIO core communicates with the JTAG output interface through the output arbitration polling module, and when the JTAG enters the signal sending state, the output of the execution module is sent to the JTAG interface.

[0042] The following will specifically describe the real-time debugging device for monitoring internal signals of an FPGA in this Embodiment 2 with reference to the attached Figure 1 For the real-time debugging device for monitoring internal signals of an FPGA in this Embodiment 2:

[0043] Refer to Figure 1 , the real-time debugging device for monitoring internal signals of the present invention includes creating a VIO core embedded in a user circuit. The VIO core includes a JTAG status module and a JTAG control module. The JTAG status module and the JTAG control module receive signals input through the JTAG interface. The input signals include user monitoring signals and user clock signals, and the processing results are input into an input instruction parsing module.

[0044] The input instruction parsing module is used for splitting and latching input instructions. The input instruction parsing module generates control information containing the splitting result by splitting the instructions, and this control information is sent to the VIO function control module. Specifically, the VIO function control module includes a control information processing module that directly receives the control information and an execution module responsible for instruction execution.

[0045] The control information processing module determines the specific execution instructions of the VIO core and sends relevant enable signals, VIO instructions, and parameters of the output instructions to the execution module.

[0046] The execution module includes a VIO signal input monitoring module and a VIO signal output monitoring module. The VIO signal input monitoring module is used for input signal refresh instructions. After the VIO signal input monitoring module receives the input signal refresh instruction, it samples the target circuit connected to the VIO signal input monitoring module and processes the sampling result (that is, the Refresh_input value generated in Figure 1 ) and sends it to the output arbitration module;

[0047] The VIO signal output monitoring module is used to execute the output signal refresh instruction, the output signal distribution instruction, and the output signal reset instruction. When the VIO signal output monitoring module receives the output signal refresh, it samples the target circuit connected to the VIO signal output monitoring module, processes the sampling result (that is, Figure 1 the refresh output value Refresh_ontput output to the JTAG interface in

[0048] and then sends it to the output arbitration module;

[0049] When the VIO signal output monitoring module receives the output signal distribution instruction, it sends the output signal value commit_output_valuse set by the user interface to the user circuit to drive the connected target circuit;

[0050] And the output arbitration module. The VIO kernel communicates with the JTAG output interface through the output arbitration polling module, and when the JTAG enters the signal sending state, it sends the output of the execution module to the JTAG interface.

[0051] Since the VIO module communicates with the JTAG interface through the output arbitration module polling, it can be used in combination with other functional circuits using the JTAG interface, leaving room for adding new IP cores later.

[0052] As an implementation, when multiple VIO cores are embedded in the user circuit, the output arbitration module arbitrates the output order of multiple VIO cores.

[0053] As an implementation, the number of input signal ports of the VIO signal input monitoring module and the number of output signal ports of the VIO signal output monitoring module support multiple groups, and the bit width range of each group of signals is 1-32 bits.

[0054] The above has introduced in detail a real-time debugging method and device for monitoring internal signals of an FPGA. Specific examples are used in this article to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A real-time debugging method for monitoring internal signals of FPGA, characterized in that: This includes creating a VIO kernel and embedding it into the user circuit; The host computer inputs instructions to the user circuit through the JTAG interface, and the JTAG control module of the VIO core receives the instructions, stores and analyzes the instructions, and inputs the instructions to the instruction parsing module for instruction splitting and latching operations according to the instruction analysis results; The instruction splitting result is sent to the control information processing module for execution, and according to the instruction execution result, the enable signal, VIO kernel instruction, and output instruction parameters are sent to the execution module for execution; The execution module includes a VIO signal input monitoring module and a VIO signal output monitoring module; the VIO signal input monitoring module is used to input a signal to execute a refresh instruction; the VIO signal output monitoring module is used to execute an output signal refresh instruction, an output signal sending instruction, and an output signal reset instruction; After the execution module completes the corresponding work, the JTAG interface state continues to jump backwards. During the transmission process, each module does not act. When JTAG enters the signal sending state, the output arbitration module sends the sampling result to the JTAG interface for output; When multiple VIO cores embedded in the user circuit are instantiated at the same time, the output arbitration module arbitrates the output order, polls the VIO windows of the JTAG interface that need to upload data, and uploads the data of the next VIO window after the data upload of the next VIO window is completed; if there is no uploaded data, it is skipped until all VIO windows have been polled.

2. A real-time debugging method for monitoring FPGA internal signals according to claim 1, characterized in that: The generated VIO core is integrated with the user circuit, and layout and routing are performed to generate a user circuit with a VIO function; a plurality of VIO cores are provided and embedded into the user circuit together with other functional circuits, and the VIO cores and the VIO cores and other functional circuits use a JTAG interface to input and output data; When creating a VIO kernel, a register transfer level code corresponding to the VIO kernel is generated, and a bit stream file corresponding to the generated transfer level code is configured into the FPGA.

3. A real-time debugging method for monitoring FPGA internal signals according to claim 1, characterized in that: A VIO kernel is created in the user interface and embedded into the user circuit. After the VIO kernel is created, the corresponding register transfer level code is generated.

4. A real-time debugging method for monitoring FPGA internal signals according to claim 1, characterized in that: After the VIO core receives the instruction, when it is determined that the latch value of the instruction is the corresponding synchronization header, the VIO core enable signal is pulled high and distributed to the input instruction parsing module and the execution module.

5. A real-time debugging method for monitoring FPGA internal signals according to claim 1, characterized in that: According to the debugging requirements of the user, any of the VIO cores can be instantiated multiple times, and each instantiation will generate a new window on the host computer. All window output data of the host computer are polled and output by the output arbitration module.

6. A real-time debugging device for monitoring internal signals of FPGA, characterized in that: include: A VIO core embedded in the user circuit, wherein the VIO core is provided with a JTAG status module and a JTAG control module, wherein the JTAG status module and the JTAG control module receive signals input through the JTAG interface and input processing results to the input instruction parsing module; The input instruction parsing module is used for splitting and latching the input instructions; A VIO function control module, including a control information processing module for receiving the splitting result output by the input instruction parsing module and an execution module responsible for instruction execution; The control information processing module determines the specific execution instruction of the VIO kernel, and sends the relevant enable signal, VIO instruction and output instruction parameters to the execution module; the execution module includes a VIO signal input monitoring module and a VIO signal output monitoring module; the VIO signal input monitoring module is used for input signal refresh instruction; the VIO signal output monitoring module is used for executing output signal refresh instruction, output signal sending instruction and output signal reset instruction; When the VIO signal output monitoring module receives an output signal refresh, it samples the target circuit connected to the VIO signal output monitoring module, and sends the sampling result to the output arbitration module after processing; when the VIO signal output monitoring module receives an output signal sending instruction, it sends the output parameters set by the user interface to the user circuit, and drives the target circuit connected to the user circuit; when the VIO signal output monitoring module receives an output reset instruction, the VIO signal output monitoring module sends the default value generated by the VIO core to the user circuit; An output arbitration module, wherein the VIO core communicates with the JTAG output interface through the output arbitration polling module, and when the JTAG enters a signal sending state, the output of the execution module is sent to the JTAG interface; When multiple VIO cores are embedded in the user circuit, the output arbitration module arbitrates the output sequence of the multiple VIO cores.

7. A real-time debugging device for monitoring internal signals of FPGA according to claim 6, characterized in that: When the VIO signal input monitoring module receives an input signal refresh instruction, it samples the target circuit connected to the VIO signal input monitoring module, and processes and sends the sampling result to the output arbitration module.

8. A real-time debugging device for monitoring internal signals of FPGA according to claim 6, characterized in that: When the multiple VIO cores are embedded in the user circuit, the output arbitration module arbitrates the output sequence of the multiple VIO cores.

9. A real-time debugging device for monitoring internal signals of FPGA according to claim 6, characterized in that: The number of input signal ports of the VIO signal input monitoring module and the number of output signal ports of the VIO signal output monitoring module support multiple groups, and the bit width range of each group of signals is 1-32 bits.

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