Method, processor and system for implementing RISC-V architecture to run X86 instruction set through hardware

Abstract

The present invention discloses a method, processor and system for implementing RISC-V architecture running X86 instruction set by hardware, the method comprising judging whether there is an equivalent RISC-V standard instruction replacing X86 instruction, if so, determining that X86 instruction and equivalent RISC-V standard instruction are first and second instructions respectively; if not, judging whether there is a non-equivalent RISC-V standard instruction replacing X86 instruction, if so, judging whether the execution efficiency of non-equivalent RISC-V standard instruction meets preset requirements, if so, determining that X86 instruction and non-equivalent RISC-V standard instruction are third and fourth instructions respectively; if not, determining RISC-V custom instruction replacing X86 instruction, and determining that X86 instruction and RISC-V custom instruction are fifth and sixth instructions respectively; obtaining instruction processing result corresponding to second, fourth or sixth instruction as output with first, third or fifth instruction as input and storing it in a hardware device. The present invention can realize RISC-V architecture running X86 instruction set quickly and efficiently.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, processor and system for implementing a RISC-V architecture to run an X86 instruction set through hardware. Background Art

[0002] Instruction Set Architecture (ISA), also known as instruction set or instruction set system, is the part of computer architecture related to programming. It defines the instruction set and data types that the CPU can execute, and is a complete definition of the interface between software and hardware. ISA not only includes basic data types, instruction sets, registers, addressing modes, but also involves storage systems, interrupts, exception handling, external I / O and other aspects.

[0003] ISA has a significant impact on computer performance because it determines how and how efficiently a computer executes instructions. Specifically, ISA defines the set of all instructions that a computer can execute. Each instruction specifies what operation the computer performs, the address space where the operands are stored, and the type of operands. Therefore, ISA is the bridge between software and hardware in computer architecture, which enables software developers to write programs that are compatible with specific hardware architectures.

[0004] Common instruction set architecture types include X86, ARM, and RISC-V. Among them, X86 is a widely used instruction set architecture, which was originally introduced by Intel and became the dominant architecture in the field of personal computers (PCs). It has a complex instruction set and variable-length instruction encoding, suitable for high-performance computing and general computing. RISC-V is an open instruction set architecture that is simple, scalable, and customizable. It is an instruction set architecture that has emerged in recent years and is widely used in various fields, including embedded systems, the Internet of Things, high-performance computing, etc.

[0005] Currently, the ecosystem of Microsoft's Windows operating system is still the most complete architecture in application environments such as laptops, desktops and workstations. However, limited by the WinTel (Windows-Intel) architecture, the chances of Windows directly supporting RISC-V are slim at present and in the foreseeable future, which greatly limits the market development of RISC-V. Existing technical solutions are to run Windows or Windows applications by running virtual machines on other systems or using software translation, but the performance will be greatly reduced.

[0006] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0007] The purpose of the present invention is to provide a method, processor and system for implementing the RISC-V architecture to run the X86 instruction set through hardware, which can quickly and efficiently implement the RISC-V architecture to run the X86 instruction set.

[0008] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0009] A method for implementing a RISC-V architecture to run an X86 instruction set through hardware, comprising the following steps:

[0010] For any X86 instruction in the target X86 instruction set;

[0011] Determine whether there is an equivalent RISC-V standard instruction that replaces the X86 instruction, the function of the equivalent RISC-V standard instruction is consistent with the function of the X86 instruction and the difference in execution efficiency between the two is within a preset range, and if so, determine that the X86 instruction is the first instruction, and determine that the equivalent RISC-V standard instruction is the second instruction;

[0012] If not, determining whether there is a non-equivalent RISC-V standard instruction that replaces the X86 instruction; if so, determining whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement; if so, determining that the X86 instruction is the third instruction, and determining that the non-equivalent RISC-V standard instruction is the fourth instruction;

[0013] If not satisfied, determining a RISC-V custom instruction to replace the X86 instruction, determining the X86 instruction to be the fifth instruction, and determining the RISC-V custom instruction to be the sixth instruction;

[0014] A necessary condition for using RISC-V instructions to replace X86 instructions is that the functions of RISC-V instructions are consistent with those of X86 instructions. The present invention further divides RISC-V standard instructions into equivalent RISC-V standard instructions and non-equivalent RISC-V standard instructions based on the difference in execution efficiency of RISC-V standard instructions replacing corresponding X86 instructions, that is, RISC-V standard instructions include the equivalent RISC-V standard instructions and the non-equivalent RISC-V standard instructions. If the execution efficiency of a RISC-V standard instruction is the same as the execution efficiency of an X86 instruction, If the two are consistent or close (the difference in execution efficiency between the two is within a preset range) or the execution efficiency of the RISC-V standard instruction is better, the RISC-V standard instruction is determined to be the equivalent RISC-V standard and the equivalent RISC-V standard is used to directly replace the X86 instruction; if the execution efficiency of a RISC-V standard instruction is far different from that of the X86 instruction (the difference in execution efficiency between the two is not within a preset range), it is necessary to further determine whether the execution efficiency of the RISC-V standard instruction can meet the application requirements. If so, the RISC-V standard instruction is used to replace the X86 instruction, otherwise the RISC-V custom instruction is used to replace the X86 instruction;

[0015] Based on the above steps, the instruction processing result is obtained and stored in a hardware device, and the instruction processing result includes:

[0016] Taking the first instruction as input, the second instruction as output;

[0017] Taking the third instruction as input, the fourth instruction as output;

[0018] The fifth instruction is taken as input, and the sixth instruction is taken as output.

[0019] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes the following steps:

[0020] For any X86 instruction in the target X86 instruction set;

[0021] If there is no equivalent RISC-V standard instruction to replace the X86 instruction, and there is no non-equivalent RISC-V standard instruction to replace the X86 instruction;

[0022] Then determine the RISC-V custom instruction that replaces the X86 instruction, determine the X86 instruction as the fifth instruction, and determine the RISC-V custom instruction as the sixth instruction.

[0023] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes the following steps:

[0024] A RISC-V custom instruction operation module is pre-designed, and the efficiency of the RISC-V custom instruction operation module in running the sixth instruction is greater than the efficiency of the RISC-V standard instruction operation module in running the sixth instruction;

[0025] Configure the RISC-V custom instruction operation module to run the sixth instruction.

[0026] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the RISC-V custom instruction operation module includes a data cache unit, a register unit and an operation unit, wherein the number of the register unit and the operation unit are both multiple and the two are electrically connected in a one-to-one correspondence to form an operator, and multiple operators are connected in series to form an operator group;

[0027] The output end of the data cache unit is electrically connected to the input end of the operator group, and the output end of the operator group is electrically connected to the input end of the data cache unit.

[0028] Further, according to any one of the technical solutions or a combination of multiple technical solutions mentioned above, the output end of each of the operators is electrically connected to the input end of the data cache unit.

[0029] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the RISC-V custom instruction operation module is also configured to run the second instruction and / or the fourth instruction.

[0030] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, any X86 instruction in the target X86 instruction set is traversed, and the instruction processing result is obtained, and the instruction processing result includes a first instruction set, a second instruction set, a third instruction set, a fourth instruction set, a fifth instruction set and a sixth instruction set;

[0031] The first instruction set includes one or more of the first instructions, the second instruction set includes one or more of the second instructions, and the second instructions correspond to the first instructions one by one;

[0032] The third instruction set includes one or more third instructions, the fourth instruction set includes one or more fourth instructions, and the fourth instructions correspond to the third instructions one by one;

[0033] The fifth instruction set includes one or more fifth instructions, the sixth instruction set includes one or more sixth instructions, and the sixth instructions correspond one to one with the fifth instructions.

[0034] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, whether the execution efficiency of the non-equivalent RISC-V standard instructions meets the preset requirements is determined by the following method:

[0035] Determine the execution duration of the X86 instruction and determine it as the first duration;

[0036] Determine the execution duration of the non-equivalent RISC-V standard instruction and determine it as the second duration;

[0037] Whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements is determined according to the second time length and the first time length.

[0038] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, judging whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements according to the second time length and the first time length includes:

[0039] Calculate the difference between the second duration and the first duration to obtain a duration difference, wherein the duration difference=the second duration-the first duration;

[0040] If the duration difference is less than a preset duration difference threshold, then the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements; otherwise, it does not meet the requirements.

[0041] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, judging whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements according to the second time length and the first time length includes:

[0042] Calculate the difference between the second duration and the first duration to obtain a duration difference, wherein the duration difference=the second duration-the first duration;

[0043] Calculate the ratio of the execution efficiency of the non-equivalent RISC-V standard instruction to the execution efficiency of the X86 instruction to obtain an execution efficiency ratio, where the execution efficiency ratio=(the duration difference / the first duration)×100%;

[0044] If the execution efficiency ratio is less than the preset ratio threshold, whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements; otherwise, it does not meet the requirements.

[0045] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, whether the execution efficiency of the non-equivalent RISC-V standard instructions meets the preset requirements is determined by the following method:

[0046] Determine the execution duration of the X86 instruction and determine it as the first duration;

[0047] If the first duration is less than a preset duration threshold, the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements.

[0048] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the first instruction is configured with a first tag, the second instruction is configured with a second tag, and the second tag has a corresponding relationship with the first tag;

[0049] The third instruction is configured with a third tag, the fourth instruction is configured with a fourth tag, and the fourth tag has a corresponding relationship with the third tag;

[0050] The fifth instruction is configured with a fifth tag, the sixth instruction is configured with a sixth tag, and the sixth tag has a corresponding relationship with the fifth tag.

[0051] Further, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes configuring a code stream operation optimization module, wherein the code stream operation optimization module is configured to monitor a RISC-V instruction code stream, wherein the RISC-V instruction code stream includes one or more of the second instruction, the fourth instruction, and the sixth instruction;

[0052] The code stream operation optimization module is also configured to adjust the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream.

[0053] According to another aspect of the present invention, the present invention provides a processor for running an X86 instruction set through a hardware-implemented RISC-V architecture, wherein the processor is configured to retrieve instruction processing results pre-stored in a hardware device, and replace X86 instructions with RISC-V instructions according to the instruction processing results, wherein the instruction processing results are obtained based on a method for running an X86 instruction set through a hardware-implemented RISC-V architecture as described in any one of the above technical solutions or a combination of multiple technical solutions.

[0054] According to another aspect of the present invention, the present invention provides a computer system, which is configured to implement a RISC-V architecture to run an X86 instruction set based on the method described in any one of the above technical solutions or a combination of multiple technical solutions.

[0055] The beneficial effects brought by the technical solution provided by the present invention are as follows:

[0056] a. The present invention obtains instruction processing results, stores the instruction processing results in a hardware device, and performs real-time translation of X86 instructions to RISC-V through hardware. This allows designers to maintain the original RISC-V design as much as possible, without the need for software translation, simulation software or hardware, or the use of an operating system virtual machine. The RISC-V processor can directly support the running of the X86 instruction set and the Windows operating system, without the need for software translation or compilation software optimization, thereby avoiding the occurrence of more instruction codes caused by instruction translation. Therefore, the method provided by the present invention can effectively improve the performance and compatibility of the RISC-V architecture running the X86 instruction set;

[0057] b. The present invention can compensate for the overhead caused by replacing X86 CISC instructions with RISC-V instruction sequences through RISC-V custom instructions and RISC-V custom instruction operation modules, and can also reduce the complexity of allowing RISC-V architecture to support Intel AVX and SIMD type instructions, and further improve the efficiency and performance of RISC-V architecture running X86 instruction set;

[0058] c. The present invention configures a code stream operation optimization module, uses the code stream operation optimization module to monitor one or more of the second instruction, the fourth instruction and the sixth instruction, and adjusts and allocates the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream composed of one or more of the second instruction, the fourth instruction and the sixth instruction, so that subsequent instruction operation modules can be processed in parallel as much as possible, which may reduce the code stream waiting time, thereby improving the instruction operation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0060] Figure 1 A selection flow chart for translating X86 instructions into RISC-V instructions provided for an exemplary embodiment of the present invention;

[0061] Figure 2 A schematic flow chart of a method for implementing a RISC-V architecture to run an X86 instruction set through hardware provided by an exemplary embodiment of the present invention;

[0062] Figure 3A selection flow chart for translating AVX512 instructions into RISC-V instructions provided for an exemplary embodiment of the present invention;

[0063] Figure 4 A schematic diagram of a typical five-stage processing flow of a processor provided for an exemplary embodiment of the present invention;

[0064] Figure 5 A schematic diagram of the architecture of a RISC-V processor provided for an exemplary embodiment of the present invention;

[0065] Figure 6 A schematic diagram of the architecture of a front-end processing module provided for an exemplary embodiment of the present invention;

[0066] Figure 7 It is a schematic diagram of the architecture of a RISC-V instruction operation module in the prior art;

[0067] Figure 8 A schematic diagram of the architecture of a RISC-V custom instruction operation module provided for an exemplary embodiment of the present invention;

[0068] Fig. 9 A schematic diagram of the dependency relationship between instructions in a machine code stream of a RISC-V instruction provided as an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0069] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0070] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0071] The instruction set architecture (ISA) is an indispensable part of computer architecture. It defines the computer's instruction format, instruction type, and data type, and has an important impact on computer performance. With the growing global demand for independent and controllable chips and the growing demand in the fields of the Internet of Things and edge computing, the instruction set architecture is showing the following development trends:

[0072] Open source and customizability: The rise of open source instruction set architectures such as RISC-V allows designers to tailor and customize them according to specific application requirements, thus better adapting to different application scenarios;

[0073] High performance and low power consumption: With the continuous advancement of technology, future instruction set architectures will pay more attention to the balance between high performance and low power consumption to meet the growing computing needs;

[0074] Multi-architecture fusion: In order to adapt to the application requirements of different fields, future computer systems may adopt a fusion solution of multiple instruction set architectures to achieve higher performance and flexibility.

[0075] Based on this, this application proposes a method, processor and system for implementing RISC-V architecture to run X86 instruction set through hardware, which can quickly and efficiently implement RISC-V architecture to run X86 instruction set, in line with the development trend of instruction set architecture towards open source and customizability, high performance and low power consumption, and multi-architecture integration.

[0076] In one embodiment of the present invention, a method for implementing the RISC-V architecture to run the X86 instruction set through hardware is provided. Figure 1 and Figure 2 , the method comprises the following steps:

[0077] For any X86 instruction in the target X86 instruction set;

[0078] Determine whether there is an equivalent RISC-V standard instruction that replaces the X86 instruction, the function of the equivalent RISC-V standard instruction is consistent with the function of the X86 instruction and the difference in execution efficiency between the two is within a preset range, and if so, determine that the X86 instruction is the first instruction, and determine that the equivalent RISC-V standard instruction is the second instruction;

[0079] If not, determining whether there is a non-equivalent RISC-V standard instruction that replaces the X86 instruction; if so, determining whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement; if so, determining that the X86 instruction is the third instruction, and determining that the non-equivalent RISC-V standard instruction is the fourth instruction;

[0080] If not satisfied, determining a RISC-V custom instruction to replace the X86 instruction, determining the X86 instruction to be the fifth instruction, and determining the RISC-V custom instruction to be the sixth instruction;

[0081] Based on the above steps, the instruction processing result is obtained and stored in a hardware device, and the instruction processing result includes:

[0082] Taking the first instruction as input, the second instruction as output;

[0083] Taking the third instruction as input, the fourth instruction as output;

[0084] The fifth instruction is taken as input, and the sixth instruction is taken as output.

[0085] Based on the above method of implementing the RISC-V architecture to run the X86 instruction set through hardware, the instruction processing result is obtained, and the instruction processing result is configured as a processing module stored in a hardware device, which allows designers to quickly design a new solution in an integrated manner (based on the processing module, a solution for running the corresponding X86 instruction set based on the RISC-V architecture can be quickly implemented). Under the premise of maintaining the original RISC-V design as much as possible, the RISC-V processor does not need to rely on software translation, simulation software or hardware, or the virtual machine of the operating system, and can directly support the X86 instruction set and directly run the Windows operating system, so that the RISC-V architecture processor can efficiently run Windows and the application software above.

[0086] The above method proposed by the present invention, while maintaining the original RISC-V architecture, the processor dynamically converts the machine code stream of the X86 instruction into a single machine code or a sequence of machine codes of the corresponding RISC-V instruction in a timely manner (hereinafter referred to as equivalent translation), and sends it to the computing unit in the RISC-V processor for operation. During the operation, there is no need to use software to translate the X86 instructions in advance, nor is there any need to use any virtual machine instructions or virtual machine mode to cooperate with processing to realize the RISC-V architecture to run the X86 instruction set. Therefore, the method provided by the present invention can effectively improve the performance and compatibility of the RISC-V architecture running the X86 instruction set.

[0087] In this embodiment, if Figure 1 and Figure 2 As shown, any X86 instruction in the target X86 instruction set is traversed to obtain the instruction processing result, and the instruction processing result includes a first instruction set, a second instruction set, a third instruction set, a fourth instruction set, a fifth instruction set and a sixth instruction set.

[0088] Among them, the first instruction set includes one or more of the first instructions, the second instruction set includes one or more of the second instructions, and the second instructions correspond to the first instructions one-to-one; the third instruction set includes one or more of the third instructions, the fourth instruction set includes one or more of the fourth instructions, and the fourth instructions correspond to the third instructions one-to-one; the fifth instruction set includes one or more of the fifth instructions, the sixth instruction set includes one or more of the sixth instructions, and the sixth instructions correspond to the fifth instructions one-to-one. After determining the first instruction set, the second instruction set, the third instruction set, the fourth instruction set, the fifth instruction set, and the sixth instruction set, any X86 instruction in the target X86 instruction set can be directly translated into a corresponding RISC-V instruction by looking up a table.

[0089] Preferably, the first instruction is configured with a first tag, the second instruction is configured with a second tag, and the second tag has a corresponding relationship with the first tag; the third instruction is configured with a third tag, the fourth instruction is configured with a fourth tag, and the fourth tag has a corresponding relationship with the third tag; the fifth instruction is configured with a fifth tag, the sixth instruction is configured with a sixth tag, and the sixth tag has a corresponding relationship with the fifth tag. By setting the tags, the efficiency of equivalently translating X86 instructions into corresponding RISC-V instructions can be further improved. For example, the first instruction configured with the first tag only needs to search for the corresponding RISC-V instruction in multiple second instructions configured with the second tag, and there is no need to search for the corresponding RISC-V instruction in the second instruction set, the fourth instruction set, and the sixth instruction set.

[0090] In one embodiment of the present invention, a method for implementing a RISC-V architecture to run an X86 instruction set through hardware is provided, such as Figure 1 and Figure 2 As shown, the method further comprises the following steps:

[0091] For any X86 instruction in the target X86 instruction set;

[0092] If there is no equivalent RISC-V standard instruction to replace the X86 instruction, and there is no non-equivalent RISC-V standard instruction to replace the X86 instruction;

[0093] Then determine the RISC-V custom instruction that replaces the X86 instruction, determine the X86 instruction as the fifth instruction, and determine the RISC-V custom instruction as the sixth instruction.

[0094] The method provided by the present invention implements the method of running the X86 instruction set through the RISC-V architecture through hardware. In addition to the RISC-V standard instruction set, the RISC-V instruction set architecture can also customize the characteristics of instructions / instruction sets. In the design selection process of translating X86 instructions into RISC-V instructions, if there is inefficiency caused by instruction translation, or there are no existing RISC-V standard instructions to replace the X86 instructions, the RISC-V instructions are customized to replace the X86 instructions.

[0095] It should be noted that, in any of the above embodiments, there are multiple implementation methods for determining the RISC-V custom instructions that replace the X86 instructions. Specifically, the RISC-V custom instructions can be implemented by hardware or by software. The present invention does not limit the specific method for determining the RISC-V custom instructions that replace the X86 instructions, as long as the function of the newly determined / defined RISC-V custom instructions is consistent with the function of the X86 instructions, and the performance (usually execution efficiency) of the RISC-V custom instructions meets expectations.

[0096] Among them, determining the RISC-V custom instructions that replace the X86 instructions through hardware implementation includes modifying the hardware description file, such as adding the implementation of the RISC-V custom instructions that are consistent with the functions of the X86 instructions in the hardware description file (usually a .v file) of the RISC-V core. Generally, it is necessary to modify the instruction decoding part and the execution part to support the new instruction format and opcode so that it can correctly parse and execute the custom instructions; and use tools such as Quartus for hardware synthesis and implementation, generate .pof files, etc., for configuring hardware devices such as FPGAs, so as to solidify the hardware logic of the custom instructions into the hardware.

[0097] Using software, the RISC-V instructions that replace X86 instructions are determined through binary compilation (compiler) and other technologies, including defining new custom instructions and their operation logic to define RISC-V custom instructions; regenerating opcode macro definitions, defining new opcode macros in header files for use in assembly code, such as #define DOT_OPCODE0x6B; modifying the GNU tool chain to support new custom instructions, usually including modifying the assembler, linker and compiler; finally testing the RISC-V custom instructions, by writing test programs to verify whether the functions of the new RISC-V custom instructions are consistent with the target X86 instructions, and verifying the performance of the RISC-V custom instructions, to ensure the correctness and performance of the RISC-V custom instructions meet expectations.

[0098] See also Figure 3For example, the AVX-512 instruction set in the Intel X86 processor has an instruction width extended to 512 bits, and can perform 32 double-precision or 64 single-precision floating-point (FP) operations in each clock cycle. It is specifically designed for application scenarios with large-scale computing requirements such as image / audio and video processing, data analysis, scientific computing, data encryption and compression, and deep learning. Figure 3 The dotted line in the figure indicates the process line that is not selected after the judgment. At present, there is no equivalent RISC-V standard instruction with the same function as the AVX-512 instruction and close execution efficiency. Therefore, it is judged that there is no equivalent RISC-V standard instruction that can replace the AVX-512 instruction. The AVX-512 instruction can be translated by the RISC-V "V" standard vector extension (Standard Extension for Vector Operations), so it is judged that there is a non-equivalent RISC-V standard instruction to replace the AVX-512 instruction. However, the operation efficiency of using non-equivalent RISC-V standard instructions to translate AVX-512 instructions cannot meet the requirements. Because if non-equivalent RISC-V standard instructions are used to translate AVX-512 instructions, loop processing will be required, and the running speed will be slowed down if the memory address alignment (Memory Alignment) is not aligned. Therefore, a lot of RISC-V instructions will be required to complete an X86 instruction, which will also lead to low performance of the RISC-V architecture running the AVX-512 instruction set. Therefore, in this application, RISC-V custom instructions are used to replace AVX-512 instructions. Preferably, it is further determined whether the operating efficiency of using RISC-V custom instructions to replace AVX-512 instructions can meet the requirements. If it cannot meet the requirements, a custom instruction operation unit is added to improve the operating efficiency of the translated RISC-V instructions. In addition, if V-standard extended instructions are not supported, the RISC-V architecture cannot be supported to run the AVX-512 instruction set by instruction translation. Therefore, using RISC-V custom instructions to replace AVX-512 instructions is the preferred solution.

[0099] In each of the above embodiments, there are multiple ways to determine whether the execution efficiency of the non-equivalent RISC-V standard instructions meets the preset requirements.

[0100] The first method is to determine the execution time of the X86 instruction and determine it as the first time, determine the execution time of the non-equivalent RISC-V standard instruction and determine it as the second time; and judge whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements according to the second time and the first time. Specifically, the difference between the second time and the first time is calculated to obtain the time difference, and the time difference = the second time - the first time; if the time difference is less than the preset time difference threshold, then the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements; otherwise, it does not meet.

[0101] The second method is to determine the execution time of the X86 instruction and determine it as the first time, determine the execution time of the non-equivalent RISC-V standard instruction and determine it as the second time; and judge whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements according to the second time and the first time. Calculate the difference between the second time and the first time to obtain the time difference, and the time difference = the second time - the first time. Calculate the ratio of the execution efficiency of the non-equivalent RISC-V standard instruction to the execution efficiency of the X86 instruction to obtain the execution efficiency ratio, and the execution efficiency ratio = (the time difference / the first time) × 100%. If the execution efficiency ratio is less than the preset ratio threshold, then the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements; otherwise, it does not meet.

[0102] The third method is to determine the execution time of the X86 instruction and determine it as the first time; if the first time is less than a preset time threshold, the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements.

[0103] It should be noted that the above three judgment methods are exemplary descriptions, and the present invention does not limit the method of judging whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements to only the three judgment methods listed above.

[0104] In order to further improve the efficiency and performance of running the X86 instruction set through the hardware implementation of the RISC-V architecture, in one embodiment of the present invention, Figure 8 As shown, the method also includes pre-designing a RISC-V custom instruction operation module, the efficiency of the RISC-V custom instruction operation module in running the sixth instruction is greater than the efficiency of the RISC-V standard instruction operation module in running the sixth instruction; and configuring the RISC-V custom instruction operation module to run the sixth instruction.

[0105] The RISC-V custom instruction operation module includes a data cache unit, a register unit and an operation unit, wherein the number of the register unit and the operation unit are both multiple and the two are electrically connected in a one-to-one correspondence to form an operator, and multiple operators are connected in series to form an operator group. The output end of the data cache unit is electrically connected to the input end of the operator group, and the output end of the operator group is electrically connected to the input end of the data cache unit. More preferably, the output end of each operator is also electrically connected to the input end of the data cache unit. The present invention utilizes the RISC-V custom instruction set and the corresponding RISC-V custom instruction operation module to support the X86 special instruction set or SIMD instructions required by Windows, thereby improving the performance and compatibility of RISC-V running the X86 instruction set. It should be noted that the specific architecture of the RISC-V custom instruction operation module is not limited to the embodiment of the present invention. Figure 8 The one shown here may also have other settings, as long as it can run RISC-V custom instructions and improve the running efficiency of RISC-V custom instructions.

[0106] Taking the matrix operation of the 512-bit operation unit required by the AVX-512 instruction set as an example, the existing RISC-V instruction operation module is as follows Figure 7 As shown, it has only one set of 64-bit operation units 603 (operators or multipliers). When it is necessary to operate matrix data, it needs to pass through the operation unit 603 and register 1 601 and register 2 602 for multiple times, and the result of each operation is stored back to the data cache 604 so that it can be operated again through the register and operation unit next time, so the operation efficiency is low. However, if the method provided by the present application is adopted, Figure 8 The RISC-V custom instruction operation module shown includes 4 register units and 4 operation units electrically connected in a one-to-one correspondence, and each register unit includes two operators or multipliers, such as Figure 8As shown, the four register units include a first register unit, a second register unit, a third register unit and a fourth register unit, the first register unit includes a first register 701 and a second register 702, the second register unit includes a third register 703 and a fourth register 704, the third register unit includes a fifth register 705 and a sixth register 706, the fourth register unit includes a seventh register 707 and an eighth register 708, and the four operation units include a first operation unit 709 to a fourth operation unit 712. For example, four matrix operations are required, and the RISC-V instruction operation module provided in the present application is used. The operation result of the first operation unit 709 is directly output to the second register unit and the second operation unit 710 is used to perform the second matrix operation, the operation result of the second operation unit 710 is directly output to the third register unit and the third operation unit 711 is used to perform the third matrix operation, the operation result of the third operation unit 711 is directly output to the fourth register unit and the fourth operation unit 712 is used to perform the fourth matrix operation to obtain the final operation result and transmit it to the data cache unit 713. It is not necessary as Figure 7 The RISC-V instruction operation module shown transmits the operation results obtained by each operation unit to the data cache unit and sends them to the operation unit again for the next operation. Therefore, the RISC-V instruction operation module provided by the present invention can effectively improve the operation efficiency and performance of RISC-V instructions.

[0107] In addition, by electrically connecting the output end of each of the arithmetic units to the input end of the data cache unit, as shown in FIG. Figure 8 The RISC-V custom instruction operation module shown is configured with 4 operation units. When processing three matrix operations, the operation result obtained by the third operation unit 711 can be directly output to the data cache unit 713 without passing through the fourth operation unit 712 and its corresponding register group. Therefore, the operation efficiency of the RISC-V instruction can be further improved.

[0108] The method provided by the present invention can use custom RISC-V instructions and RISC-V custom instruction operation modules to supplement the overhead caused by replacing X86 CISC instructions with RISC-V instruction sequences, and can also reduce the complexity of allowing the RISC-V architecture to support Intel AVX and SIMD (Single Instruction Multiple Data) and other types of instructions. For example: an instruction set unique to the INTEL X86 processor, such as the AVX instruction set or the SIMD instruction set. It should be noted that the RISC-V custom instruction operation module can also be configured to run the second instruction and the fourth instruction.

[0109] In one embodiment of the present invention, the method for implementing the RISC-V architecture to run the X86 instruction set through hardware further includes configuring a code stream operation optimization module, the code stream operation optimization module is configured to monitor the RISC-V instruction code stream, the RISC-V instruction code stream includes one or more of the second instruction, the fourth instruction and the sixth instruction. Preferably, the second instruction, the fourth instruction and the sixth instruction are all input into the code stream operation optimization module, and the code stream operation optimization module is configured to adjust and allocate the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream.

[0110] The typical five-level processing flow of a processor is as follows Figure 4 As shown, one of the purposes of the present invention is to obtain a front-end processing module that can be quickly imported into a processor or a front-end processing module that can be called by a processor based on the above design method, so as to minimize the changes in the original design.

[0111] In one embodiment of the present invention, based on the instruction processing results in the above embodiment, a front-end processing module for implementing the RISC-V architecture to run the X86 instruction set through hardware is provided, such as Figure 5 As shown, the front-end processing module has the function of an instruction reading unit, and the binary code stream of the X86 instruction is input into the input end of the front-end processing module. The front-end processing module directly translates the X86 instruction into a RISC-V binary code stream and sends it to the back-end decoder.

[0112] Specifically, the architecture of the front-end processing module 210 is as follows: Figure 6 As shown, it includes an input terminal 211, an X86 instruction decoder 212, a RISC-V instruction generation unit 213 and an output terminal 214. The input terminal 211 is configured with an input terminal temporary storage unit, so that the front-end processing module 210 can read and cache X86 instructions in advance through its input terminal, thereby reducing the waiting time and delay caused by cache miss.

[0113] The X86 instructions read and cached via the input terminal 211 are further output to the X86 instruction decoder 212, and the X86 instruction decoder 212 decodes the X86 instructions and outputs them to the RISC-V instruction generation unit 213. The RISC-V instruction generation unit 213 directly translates the decoded X86 instructions into corresponding RISC-V instructions based on the method for implementing the RISC-V architecture to run the X86 instruction set through hardware provided in the above embodiment.

[0114] When designing the equivalent translation function of the RISC-V instruction generation unit 213, one or a sequence of instructions in the RISC-V standard instructions can be selected to complete, or a RISC-V custom instruction can be used for translation. In order to maximize the use of the computing units derived from the custom instructions, the custom instructions can be classified into different custom instruction sets according to their characteristics and the custom computing units they use. The selection logic of the equivalent translation is as follows: Figure 1 and Figure 2 Taking the above X86 AVX-512 instruction as an example, the translation options are as follows Figure 3 The result of the selection is used to determine what kind of corresponding RISC-V instruction machine code stream combination the RISC-V instruction generation unit 213 should generate.

[0115] A more efficient way is to pre-store instruction processing results of X86 instructions corresponding to RISC-V instructions in the RISC-V instruction generation unit 213, and the instruction processing results include a first instruction set, a second instruction set, a third instruction set, a fourth instruction set, a fifth instruction set and a sixth instruction set.

[0116] Among them, the first instruction set includes one or more of the first instructions, the second instruction set includes one or more of the second instructions, and the second instructions correspond to the first instructions one-to-one; the third instruction set includes one or more of the third instructions, the fourth instruction set includes one or more of the fourth instructions, and the fourth instructions correspond to the third instructions one-to-one; the fifth instruction set includes one or more of the fifth instructions, the sixth instruction set includes one or more of the sixth instructions, and the sixth instructions correspond to the fifth instructions one-to-one. After determining the first instruction set, the second instruction set, the third instruction set, the fourth instruction set, the fifth instruction set, and the sixth instruction set, any X86 instruction in the target X86 instruction set can be directly translated into a corresponding RISC-V instruction by looking up a table.

[0117] Preferably, the first instruction is configured with a first tag, the second instruction is configured with a second tag, and the second tag has a corresponding relationship with the first tag; the third instruction is configured with a third tag, the fourth instruction is configured with a fourth tag, and the fourth tag has a corresponding relationship with the third tag; the fifth instruction is configured with a fifth tag, the sixth instruction is configured with a sixth tag, and the sixth tag has a corresponding relationship with the fifth tag. By setting the tags, the efficiency of equivalently translating X86 instructions into corresponding RISC-V instructions can be further improved. For example, the first instruction configured with the first tag only needs to search for the corresponding RISC-V instruction in multiple second instructions configured with the second tag, and does not need to search for the corresponding RISC-V instruction in the second instruction set, the fourth instruction set, and the sixth instruction set. It should be noted that the instruction processing result can be obtained by the method provided in any of the above embodiments to implement the RISC-V architecture running the X86 instruction set through hardware, or it can be obtained by other means.

[0118] The output end 214 is configured with a corresponding output end buffer area, and the machine code of the RISC-V instruction obtained by translating the X86 instruction is temporarily stored in the output end buffer area of ​​the front-end processing module in the form of an output queue.

[0119] In order to maintain the original design integrity of the RISC-V processor to the greatest extent and reduce the resource investment in design integration, the result of the front-end processing module 210 provided in this embodiment will be sent to the RISC-V decoder 220 in the machine code of the RISC-V instruction instead of microcode, so that the RISC-V processor can minimize the function of integrating translation and exert the modular effect.

[0120] By configuring the front-end processing module 210 provided in this embodiment in a RISC-V processor, the RISC-V processor can realize the function of directly reading the binary code stream of X86, directly translating it into the binary code stream of RISC-V and sending it to the back-end RISC-V decoder.

[0121] In addition, the method and front-end processing module proposed by the present invention are combined with an arithmetic unit (ALU) that provides the computing functions required by custom instructions. Custom instructions combined with an external arithmetic unit module can simplify instruction translation and improve performance.

[0122] At present, each design company needs to invest a lot of resources to study the method of running X86 instructions based on the RISC-V architecture. By using the method and front-end processing module provided by this application and taking advantage of the open source characteristics of RISC-V, design sharing or authorization can be carried out in a standardized manner. Each design company can integrate the design in a modular manner through authorization, thereby reducing the investment of duplicate R&D resources and accelerating the speed of product launch. The method provided by the present invention has a driving effect on establishing the standardization of X86 translation to RISC-V instructions and reducing the investment of duplicate resources.

[0123] Therefore, in one embodiment of the present invention, a processor that implements the RISC-V architecture and runs the X86 instruction set through hardware is also provided. The architecture of the processor is as follows Figure 5 As shown, it includes a front-end processing module 210, a RISC-V decoder 220, a code stream operation optimization module 230, a RISC-V standard instruction operation module 240, a RISC-V custom instruction operation module 250 and a storage management module 260.

[0124] The front-end processing module 210 is a front-end processing module as described in the embodiment of the front-end processing module for implementing the RISC-V architecture to run the X86 instruction set through hardware, and is configured to directly translate the X86 instructions into corresponding RISC-V instructions and output them to the RISC-V decoder 220. The RISC-V instructions include equivalent RISC-V standard instructions, non-equivalent RISC-V standard instructions, and RISC-V custom instructions that replace the X86 instructions.

[0125] The RISC-V decoder 220 decodes the input RISC-V instructions and outputs the decoded RISC-V instructions to the code stream operation optimization module 230. In order to improve the execution efficiency of the translated RISC-V instruction code stream, the code stream operation optimization module 230 is set at the output end of the RISC-V decoder 220. And the code stream operation optimization module 230 is electrically connected to the front-end processing module 210, and the code stream operation optimization module 230 is configured to read the RISC-V instructions temporarily stored at the output end of the front-end processing module 210, and calculate the resource relevance of the execution process and the dependency between each operation by monitoring / checking the code stream temporarily stored in the output end of the front-end processing module in advance, and optimize the execution order and output order of the allocated instructions.

[0126] More preferably, the microprocessor unit 231 (Micro Controler Module, MCU), cache and register 232 built into the processor are used to appropriately arrange the corresponding instructions in the code stream to run in advance, increase parallel processing, and improve the utilization of computing resources by reducing the congestion of subsequent computing units, thereby improving execution efficiency. Among them, the microprocessor unit 231 and the cache and register 232 can be integrated in the code stream operation optimization module 230, or can be set outside the code stream operation optimization module 230 and electrically connected to the code stream operation optimization module 230, thereby realizing the function of the code stream operation optimization module to adjust and allocate the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream.

[0127] After the code stream operation optimization module 230 adjusts and allocates the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream, the RISC-V standard instructions will be transmitted in sequence to the RISC-V standard instruction operation module 240; the RISC-V custom instructions will be transmitted in sequence to the RISC-V custom instruction operation module 250. The RISC-V standard instruction operation module 240 and the RISC-V custom instruction operation module 250 respectively process and operate the RISC-V instructions they receive, and transmit the operation results to the storage management module 260 for storage, and the storage management module 260 includes registers and memory.

[0128] The above-mentioned storage management module 260 is electrically connected to the micro-processing unit 231, and uses the micro-processing unit 231 to process part or all of the instructions in the instruction stream code in advance, or optimize the corresponding instructions and store them in the cache and register 232. After the instruction operation is completed, the storage management module 260 receives the corresponding instruction operation result, and the terminal register and memory, i.e., the storage management module 260, notifies the micro-processing unit 231 to release the resources occupied by the cache and register 232.

[0129] In the present invention, instruction translation is performed in real time by hardware, and no software is required to implement translation or compiler software (compiler) for optimization, so it is possible to avoid the result of instruction translation causing more instruction codes. In addition, since the output of the front-end processing module provided by the present invention is RISC-V machine code, rather than microcode, the code stream operation optimization module is used in conjunction with the code stream operation optimization module to check the code stream pre-stored in the output queue at the output end of the front-end processing module, so that the subsequent RISC-V operation module can be processed in parallel as much as possible, which may reduce the waiting time of the code stream and improve performance. The following is an explanation through a specific embodiment.

[0130] In a specific embodiment of the present invention, a machine code stream translated into RISC-V instructions is represented in RISC-V assembly language as shown in Table 1. To simplify the description, only the adder and storage management functions in the operation unit are used, and the operation of the adder requires one clock cycle, and the use of storage management to do cache reading requires two clock cycles. If it is run sequentially, it takes eight clock cycles as shown in Table 2 to complete.

[0131] However, based on the dependencies of registers and instructions, we can establish Fig. 9 The code stream operation optimization module 230 is configured to perform operation optimization based on the dependency relationship between various operation and storage instructions, execute instruction 4 in advance, and instructions 5 and 6 can also be processed in parallel in advance, and the timing of sending instructions to the computing unit is adjusted to obtain new instruction operation results as shown in Table 3. Considering that instruction 5 requires two clocks to complete, the new operation can be completed in six clock cycles, compared with the original eight clock cycles, which effectively improves the instruction operation efficiency.

[0132]

[0133]

[0134]

[0135] In one embodiment of the present invention, a front-end processing module for implementing the RISC-V architecture to run the X86 instruction set through hardware is provided. In this embodiment, the front-end processing module further includes a RISC-V decoder 220 and a code stream operation optimization module 230 based on the above-mentioned front-end processing module embodiment, that is, in this embodiment, the RISC-V decoder 220 and the code stream operation optimization module 230 described in the above-mentioned front-end processing module embodiment are integrated into the front-end processing module. Furthermore, the RISC-V custom instruction operation module 250 can also be integrated into the front-end processing module.

[0136] In one embodiment of the present invention, a processor is provided, wherein the processor is configured to retrieve instruction processing results pre-stored in a hardware device, and replace X86 instructions with RISC-V instructions according to the instruction processing results, wherein the instruction processing results are obtained based on the method of implementing the RISC-V architecture to run the X86 instruction set through hardware as described in any one of the above embodiments or a combination of multiple embodiments.

[0137] In one embodiment of the present invention, a computer system is provided, wherein the computer system is configured to implement a RISC-V architecture running an X86 instruction set based on a method of implementing a RISC-V architecture running an X86 instruction set through hardware as described in any one of the above embodiments or a combination of multiple embodiments.

[0138] It should be noted that the processor, computer system and front-end processing module embodiments provided by the present invention are the same as the inventive concept of the above-mentioned method embodiment for implementing the RISC-V architecture to run the X86 instruction set through hardware. The entire content of the method embodiment for implementing the RISC-V architecture to run the X86 instruction set through hardware is incorporated into the processor, computer system and front-end processing module embodiments by introduction.

[0139] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0140] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A method for implementing RISC-V architecture to run X86 instruction set through hardware, characterized in that: The following steps are involved: For any X86 instruction in the target X86 instruction set; Determine whether there is an equivalent RISC-V standard instruction that replaces the X86 instruction, the function of the equivalent RISC-V standard instruction is consistent with the function of the X86 instruction and the difference in execution efficiency between the two is within a preset range, and if so, determine that the X86 instruction is the first instruction, and determine that the equivalent RISC-V standard instruction is the second instruction; If not, determining whether there is a non-equivalent RISC-V standard instruction that replaces the X86 instruction; if so, determining whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement; if so, determining that the X86 instruction is the third instruction, and determining that the non-equivalent RISC-V standard instruction is the fourth instruction; If not satisfied, determining a RISC-V custom instruction to replace the X86 instruction, determining the X86 instruction to be the fifth instruction, and determining the RISC-V custom instruction to be the sixth instruction; Based on the above steps, the instruction processing result is obtained and stored in a hardware device, and the instruction processing result includes: Taking the first instruction as input, the second instruction as output; Taking the third instruction as input, the fourth instruction as output; The fifth instruction is taken as input, and the sixth instruction is taken as output.

2. The method for implementing RISC-V architecture to run X86 instruction set through hardware according to claim 1, characterized in that: The following steps are also included: For any X86 instruction in the target X86 instruction set; If there is no equivalent RISC-V standard instruction to replace the X86 instruction, and there is no non-equivalent RISC-V standard instruction to replace the X86 instruction; Then determine the RISC-V custom instruction that replaces the X86 instruction, determine the X86 instruction as the fifth instruction, and determine the RISC-V custom instruction as the sixth instruction.

3. The method for implementing RISC-V architecture to run X86 instruction set through hardware according to claim 1 or 2, characterized in that: The following steps are also included: A RISC-V custom instruction operation module is pre-designed, and the efficiency of the RISC-V custom instruction operation module in running the sixth instruction is greater than the efficiency of the RISC-V standard instruction operation module in running the sixth instruction; Configure the RISC-V custom instruction operation module to run the sixth instruction.

4. The method for implementing RISC-V architecture to run X86 instruction set through hardware according to claim 3, characterized in that: The RISC-V custom instruction operation module includes a data cache unit, a register unit and an operation unit, wherein the number of the register unit and the operation unit are both multiple and the two are electrically connected in a one-to-one correspondence to form an operator, and multiple operators are connected in series to form an operator group; The output end of the data cache unit is electrically connected to the input end of the operator group, and the output end of the operator group is electrically connected to the input end of the data cache unit.

5. The method for implementing RISC-V architecture to run X86 instruction set through hardware according to claim 4, characterized in that: The output end of each of the arithmetic units is electrically connected to the input end of the data cache unit.

6. The method of implementing RISC-V architecture to run X86 instruction set through hardware according to claim 3, characterized in that: The RISC-V custom instruction operation module is also configured to run the second instruction and / or the fourth instruction.

7. The method for implementing RISC-V architecture to run X86 instruction set through hardware according to claim 1 or 2, characterized in that: Traversing any X86 instruction in the target X86 instruction set, and obtaining the instruction processing result, wherein the instruction processing result includes a first instruction set, a second instruction set, a third instruction set, a fourth instruction set, a fifth instruction set, and a sixth instruction set; The first instruction set includes one or more of the first instructions, the second instruction set includes one or more of the second instructions, and the second instructions correspond to the first instructions one by one; The third instruction set includes one or more third instructions, the fourth instruction set includes one or more fourth instructions, and the fourth instructions correspond to the third instructions one by one; The fifth instruction set includes one or more fifth instructions, the sixth instruction set includes one or more sixth instructions, and the sixth instructions correspond one to one with the fifth instructions.

8. The method of implementing RISC-V architecture to run X86 instruction set through hardware according to claim 1, characterized in that: Whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements is determined in the following manner: Determine the execution duration of the X86 instruction and determine it as the first duration; Determine the execution duration of the non-equivalent RISC-V standard instruction and determine it as the second duration; Whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements is determined according to the second time length and the first time length.

9. The method for implementing RISC-V architecture to run X86 instruction set through hardware according to claim 8, characterized in that: Judging whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement according to the second time length and the first time length includes: Calculate the difference between the second duration and the first duration to obtain a duration difference, wherein the duration difference=the second duration-the first duration; If the duration difference is less than a preset duration difference threshold, then the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements; otherwise, it does not meet the requirements.

10. The method for implementing RISC-V architecture to run X86 instruction set through hardware according to claim 8, characterized in that: Judging whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement according to the second duration and the first duration includes: Calculate the difference between the second duration and the first duration to obtain a duration difference, wherein the duration difference=the second duration-the first duration; Calculate the ratio of the execution efficiency of the non-equivalent RISC-V standard instruction to the execution efficiency of the X86 instruction to obtain an execution efficiency ratio, where the execution efficiency ratio=(the duration difference / the first duration)×100%; If the execution efficiency ratio is less than the preset ratio threshold, whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements; otherwise, it does not meet the requirements.

11. The method for implementing RISC-V architecture to run X86 instruction set through hardware according to claim 1, characterized in that: Whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements is determined in the following manner: Determine the execution duration of the X86 instruction and determine it as the first duration; If the first duration is less than a preset duration threshold, the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements.

12. The method of implementing RISC-V architecture to run X86 instruction set through hardware according to claim 1, characterized in that: The first instruction is configured with a first tag, the second instruction is configured with a second tag, and the second tag has a corresponding relationship with the first tag; The third instruction is configured with a third tag, the fourth instruction is configured with a fourth tag, and the fourth tag has a corresponding relationship with the third tag; The fifth instruction is configured with a fifth tag, the sixth instruction is configured with a sixth tag, and the sixth tag has a corresponding relationship with the fifth tag.

13. The method of implementing RISC-V architecture to run X86 instruction set through hardware according to claim 1, characterized in that: Also included is a configuration code stream operation optimization module, wherein the code stream operation optimization module is configured to monitor a RISC-V instruction code stream, wherein the RISC-V instruction code stream includes one or more of the second instruction, the fourth instruction, and the sixth instruction; The code stream operation optimization module is also configured to adjust the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream.

14. A processor that implements RISC-V architecture and runs X86 instruction set through hardware, characterized in that: The processor is configured to retrieve instruction processing results pre-stored in a hardware device, and replace X86 instructions with RISC-V instructions according to the instruction processing results, wherein the instruction processing results are obtained based on the method of implementing the RISC-V architecture to run the X86 instruction set through hardware as described in claim 1.

15. A computer system, characterized in that: The computer system is configured to implement the RISC-V architecture and run the X86 instruction set based on the method described in any one of claims 1 to 13.

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