A new energy station electromagnetic transient model conversion method and related device

Abstract

The application discloses a new energy station electromagnetic transient model conversion method and related device, in the simulator, the FPGA model file or CPU model file selected by the user is acquired, for the FPGA model file, based on the preset FPGA model conversion strategy, the model elements in the model file to be converted are converted, and the FPGA model file based on the preset format is generated, for the CPU model file, based on the preset CPU model conversion strategy, the model elements in the model file to be converted are converted, and the CPU model file based on the preset format is generated. The technical problem that the prior art needs to manually remodel a plurality of device models under a hardware-in-the-loop simulation platform when combining device models of different manufacturers into a new energy station overall model, the workload is large, and the efficiency of batch new energy station grid connection detection business is reduced is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electromagnetic transient simulation, in particular to a new energy station electromagnetic transient model conversion method and related device. BACKGROUND

[0002] There are many electromagnetic transient simulation platforms used in electrical engineering, such as RTDS, RT-LAB, MATLAB, PSCAD, etc. These platforms all have corresponding new energy station hardware-in-the-loop modeling and simulation solutions, and occupy a considerable market share among users. However, these platforms are in a relationship of competitors with each other, and the models and engineering configuration files used by the platforms are not universal. When different manufacturers' device models need to be combined into a new energy station overall model, it is often necessary to manually re-model a plurality of device models under a kind of hardware-in-the-loop simulation platform to unify the model and engineering configuration file format, which is a large amount of work and reduces the efficiency of batch new energy station grid connection detection business. SUMMARY

[0003] The present application provides a new energy station electromagnetic transient model conversion method and related device, which solves the technical problem that the prior art needs to manually re-model a plurality of device models under a kind of hardware-in-the-loop simulation platform when different manufacturers' device models are combined into a new energy station overall model, which is a large amount of work and reduces the efficiency of batch new energy station grid connection detection business.

[0004] Therefore, the first aspect of the present application provides a new energy station electromagnetic transient model conversion method, comprising the following steps:

[0005] S1, obtaining a user-selected model file to be converted in a simulator, the model file to be converted is an FPGA model file or a CPU model file, the FPGA model file is a circuit model file running in an FPGA, and the CPU model file is a circuit model file running in a CPU;

[0006] S2, if the model file to be converted is an FPGA model file, converting the model elements in the model file to be converted based on a preset FPGA model conversion strategy to generate an FPGA model file based on a preset format;

[0007] S3, if the model file to be converted is a CPU model file, converting the model elements in the model file to be converted based on a preset CPU model conversion strategy to generate a CPU model file based on the preset format.

[0008] Optionally, step S2 comprises:

[0009] S21, if the model file to be converted is an FPGA model file, it is determined whether there is an AC voltage source, an AC current source or a DC voltage source in the model file to be converted, if yes, the AC voltage source, the AC current source and the DC voltage source are replaced by a controlled source form, and the step S22 is jumped to, if not, no adjustment is made, and the step S22 is jumped to;

[0010] S22, it is determined whether there is an annotated element in the model file to be converted, if yes, the annotated element is deleted, and the step S23 is jumped to, if not, no adjustment is made, and the step S23 is jumped to;

[0011] S23, all electrical ports of electrical elements in the model file to be converted are searched, and a state that the electrical ports are connected to electrical elements other than themselves is searched, when a suspended electrical port of an electrical element is searched, an entire branch where the suspended electrical port is located is indexed by the electrical element, the entire branch is deleted, and after all electrical elements are traversed, the step S24 is jumped to;

[0012] S24, control signal ports of all electrical elements in the model file to be converted are searched, Inport elements are added to each port in sequence and are automatically numbered, measurement signal ports of all electrical elements in the model file to be converted are searched, Outport elements are added to each port in sequence and are automatically numbered, and the step S25 is jumped to;

[0013] S25, a model attribute of the model file to be converted is searched, an m file defining model parameters is extracted, each parameter name and a corresponding parameter value in the m file are stored in a preset format, and the step S26 is jumped to;

[0014] S26, it is determined whether there is a parameter defined by an algorithm in the model file to be converted, if yes, an actual value of the parameter calculated according to the algorithm is obtained, the actual value is assigned to an original parameter value position, and an FPGA model file based on the preset format is obtained, if not, the FPGA model file based on the preset format is directly obtained.

[0015] Optionally, in the step S25, the storing of each parameter name and the corresponding parameter value in the m file in the preset format comprises:

[0016] It is determined whether the parameter value corresponding to each parameter name in the m file is a parameter that needs to be calculated by using parameters other than itself, if yes, the parameter value of the parameter that needs to be calculated is calculated first, and then each parameter name and the corresponding parameter value are stored in the preset format, if not, each parameter name and the corresponding parameter value are directly stored in the preset format.

[0017] Optionally, the step S3 comprises:

[0018] S31, if the model file to be converted is a CPU model file, a three-phase voltage source in the model file to be converted is found, and step S32 is executed;

[0019] S32, taking the three-phase voltage source as a root node, branches of each element are found step by step downwards until the entire element tree connected is found, and step S33 is executed;

[0020] S33, the element tree is copied into a newly created model file, an SVG module in the newly created model file is found, the SVG module is replaced by a current source, and step S34 is executed;

[0021] S34, an FPGA model file based on an SVG module is newly created, model parameters of the FPGA model file based on the SVG module are set according to SVG module parameters in the CPU model file, IO signals of the FPGA model file based on the SVG module are mapped into the CPU model file, and step S35 is executed;

[0022] S35, IO interface configurations of the CPU model file are read from a simulator hardware-in-the-loop interface configuration file, a mapping relationship between analog and digital signals and IO interfaces is obtained, and step S36 is executed;

[0023] S36, the mapping relationship between the analog and digital signals and the IO interfaces is re-listed as a file in the preset format, elements recording the mapping relationship between the analog and digital signals and the IO interfaces are all deleted, and a CPU model file based on the preset format is obtained.

[0024] Optionally, in step S35, the mapping relationship between the analog and digital signals and the IO interfaces includes a mapping relationship between FPGA model file analog output signals based on the SVG module and IO interfaces, a mapping relationship between FPGA model file digital input signals based on the SVG module and IO interfaces, a mapping relationship between CPU model file analog output signals and IO interfaces, and a mapping relationship between CPU model file digital input signals and IO interfaces.

[0025] Optionally, in step S35, the mapping relationship between the FPGA model file analog output signals based on the SVG module and the IO interfaces is obtained by searching a channel tab of an Analog Output Mapping and Rescaling block Control Panel element in the CPU model file;

[0026] The mapping relationship between the digital quantity input signal of the FPGA model file based on the SVG module and the IO interface is obtained by searching the Gates object in the eHS CPU Block in the CPU model file;

[0027] The OpFcnCommonAnalogOut object in the CPU model file is taken as a parent node, a first complete element tree configuring the analog quantity output signal of the CPU model file is indexed, the first complete element tree is parsed, and the mapping relationship between the analog quantity output signal of the CPU model file and the IO interface is obtained.

[0028] The OpFcnCommonDigitalIn object in the CPU model file is taken as a parent node, a second complete element tree configuring the digital quantity input signal of the CPU model file is indexed, the second complete element tree is parsed, and the mapping relationship between the digital quantity input signal of the CPU model file and the IO interface is obtained.

[0029] Optionally, the preset format is a CSV format.

[0030] The second aspect of the present application provides a new energy station electromagnetic transient model conversion device, comprising the following modules:

[0031] The obtaining module is configured to obtain a user-selected model file to be converted in a simulator, the model file to be converted being an FPGA model file or a CPU model file, the FPGA model file being a circuit model file running in an FPGA, and the CPU model file being a circuit model file running in a CPU.

[0032] The FPGA model conversion module is configured to, if the model file to be converted is the FPGA model file, convert model elements in the model file to be converted based on a preset FPGA model conversion strategy, and generate an FPGA model file based on a preset format.

[0033] The CPU model conversion module is configured to, if the model file to be converted is the CPU model file, convert model elements in the model file to be converted based on a preset CPU model conversion strategy, and generate a CPU model file based on the preset format.

[0034] The third aspect of the present application provides a new energy station electromagnetic transient model conversion device, the device comprising a processor and a memory:

[0035] The memory is configured to store program code and transmit the program code to the processor.

[0036] The processor is configured to execute the new energy station electromagnetic transient model conversion method according to the instructions in the program code.

[0037] The fourth aspect of the present application provides a computer readable storage medium for storing program code, the program code being used to execute the new energy station electromagnetic transient model conversion method according to any one of the first aspect.

[0038] From the above technical solutions, the new energy station electromagnetic transient model conversion method provided by the present application has the following advantages:

[0039] The new energy station electromagnetic transient model conversion method provided by the present application obtains the FPGA model file or the CPU model file selected by the user in the simulator. For the FPGA model file, the model elements in the model file to be converted are converted based on a preset FPGA model conversion strategy, and an FPGA model file based on a preset format is generated. For the CPU model file, the model elements in the model file to be converted are converted based on a preset CPU model conversion strategy, and a CPU model file based on a preset format is generated. The new energy station electromagnetic transient model conversion method provided by the present application can batch convert simulation models provided by different manufacturers into a file format that can be used by the simulator, saving the workload of manually re-modeling and engineering configuration of the test personnel, improving the work efficiency of the new energy station grid connection test, and solving the technical problem that the prior art needs to manually re-model a plurality of device models under a hardware-in-the-loop simulation platform when combining device models of different manufacturers into a new energy station overall model, which is time-consuming and reduces the efficiency of batch new energy station grid connection detection business. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other related drawings according to these drawings without creative labor.

[0041] Figure 1 A flowchart of a new energy station electromagnetic transient model conversion method provided in an embodiment of the present application;

[0042] Figure 2 A flowchart of an FPGA model conversion strategy provided in an embodiment of the present application;

[0043] Figure 3 A schematic diagram of adding an Inport element provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of adding an Outport element provided in an embodiment of the present application is shown in FIG. 1.

[0045] Figure 5 A flowchart of a CPU model conversion strategy provided in an embodiment of the present application is shown in FIG. 2.

[0046] Figure 6 A schematic diagram of replacing an SVG module with a current source provided in an embodiment of the present application is shown in FIG. 3.

[0047] Figure 7 A schematic diagram of obtaining a mapping relationship between an analog output signal of an SVG module-based FPGA model file and an IO interface provided in an embodiment of the present application is shown in FIG. 4.

[0048] Figure 8 A schematic diagram of obtaining a mapping relationship between an analog output signal of an SVG module-based FPGA model file and an IO interface provided in an embodiment of the present application is shown in FIG. 5.

[0049] Figure 9 A schematic diagram of obtaining a mapping relationship between an analog output signal of a CPU model file and an IO interface provided in an embodiment of the present application is shown in FIG. 6.

[0050] Figure 10 A schematic diagram of obtaining a mapping relationship between a digital input signal of a CPU model file and an IO interface provided in an embodiment of the present application is shown in FIG. 7.

[0051] Figure 11 A structural schematic diagram of a new energy station electromagnetic transient model conversion device provided in an embodiment of the present application is shown in FIG. 8.

[0052] Figure 12 A structural schematic diagram of a new energy station electromagnetic transient model conversion device provided in an embodiment of the present application is shown in FIG. 9. DETAILED DESCRIPTION

[0053] In order to make the personnel in the technical field better understand the present application scheme, the technical scheme in the embodiment of the present application will be described clearly and completely below in combination with the drawings in the embodiment of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor are within the scope of protection of the present application.

[0054] For the convenience of understanding, please refer to Figure 1 The present application provides an embodiment of a new energy station electromagnetic transient model conversion method, which comprises the following steps:

[0055] Step S1, obtaining a user-selected model file to be converted in the simulator, the model file to be converted being an FPGA model file or a CPU model file, the FPGA model file being a circuit model file running in an FPGA, and the CPU model file being a circuit model file running in a CPU.

[0056] It should be noted that in the electromagnetic transient simulation of the new energy station, part of the circuit model runs in the FPGA chip, and part of the circuit model runs in the CPU chip. Specifically, the MMC (Modular Multilevel Converter) model runs in the FPGA chip, and the circuit model other than the MMC model runs in the CPU chip. The circuit model in the FPGA chip and the circuit model in the CPU chip are associated according to the source file. In the embodiment of the present application, the user first selects the model file to be converted and the saved path of the converted file in the simulator. After the user sends a start conversion instruction to the simulator, the simulator can obtain the user-selected model file to be converted, and identify whether the user-selected model file to be converted is an FPGA model file or a CPU model file.

[0057] Step S2, if the model file to be converted is an FPGA model file, converting the model elements in the model file to be converted based on a preset FPGA model conversion strategy, to generate an FPGA model file in a preset format.

[0058] It should be noted that the simulator is preset with an FPGA model conversion strategy, which is used to convert the FPGA model file of other platforms (such as the RT-LAB platform) into an FPGA model file in a preset format that can be used by the simulator.

[0059] In one embodiment, as shown in FIG. 2, the preset FPGA model conversion strategy specifically includes the following steps: Figure 2

[0060] Step S21, if the model file to be converted is an FPGA model file, searching whether there is an alternating voltage source, an alternating current source or a direct current voltage source in the model file to be converted. If yes, replacing the alternating voltage source, the alternating current source and the direct current voltage source with a controlled source form, and jumping to step S22. If not, no adjustment is made, and jumping to step S22.

[0061] ​It should be noted that after starting the model conversion, the simulator first checks whether there is an AC voltage source, an AC current source or a DC voltage source in the model file to be converted, and if so, replaces the AC voltage source, the AC current source and the DC voltage source with a controlled source form, i.e. if there is an AC voltage source, converts the AC voltage source into a corresponding controlled voltage source, if there is an AC current source, converts the AC current source into a corresponding controlled current source, and if there is a DC voltage source, converts the DC voltage source into a corresponding controlled current source.

[0062] Step S22, judge whether there is an annotated element in the model file to be converted, if yes, delete the annotated element, jump to step S23, if not, do not adjust, jump to step S23.

[0063] It should be noted that the annotated element is an isolated element, so the annotated element needs to be deleted.

[0064] Step S23, retrieve the state of all electrical ports of the electrical element in the model file to be converted and the electrical elements other than itself, when retrieving that there is a suspended electrical port electrical element, index the whole branch where the suspended electrical port electrical element is located through the suspended electrical port electrical element, delete the whole branch, and after traversing all electrical elements, jump to step S24.

[0065] It should be noted that all electrical ports of the electrical element in the canvas of the model file to be converted are retrieved to check whether they are connected to electrical elements other than themselves, when retrieving that there is a suspended electrical port electrical element, index the whole branch where the suspended electrical port electrical element is located through the suspended electrical port electrical element, delete the whole branch.

[0066] Step S24, retrieve the control signal port of all electrical elements in the model file to be converted, add an Inport element on each port in turn and automatically number, retrieve the measurement signal port of all electrical elements in the model file to be converted, add an Outport element on each port in turn and automatically number, jump to step S25.

[0067] It should be noted that the control signal port of all electrical elements in the model file to be converted is retrieved, an Inport element is added on each port in turn and automatically numbered, such as number 16 and number 17 as shown in Figure 3 The measurement signal port of all electrical elements in the model file to be converted is retrieved, an Outport element is added on each port in turn and automatically numbered, such as number 13, number 14 and number 15 as shown in Figure 4 .

[0068] Step S25: Retrieve the model attributes of the model file to be converted, extract the m file that defines the model parameters, save each parameter name and corresponding parameter value in the m file in a preset format, and proceed to step S26.

[0069] It should be noted that the process involves retrieving the Model Properties (model attributes) from the model file to be converted, extracting the m-files that define the model parameters, and saving the parameter names and corresponding values ​​in the m-files in a preset format (such as CSV). Specifically, when saving the parameter names and values ​​in the m-files, it checks whether any parameter names in the m-files require calculation from parameters other than themselves. If so, the parameter values ​​are calculated first (for example, if a parameter in the software is expressed as a*b / c, and the m-file shows a = 0.5, b = 0.2, c = 0.1, then the parameter will be converted to 10), and then the parameter names and corresponding values ​​are saved in the preset format. Otherwise, the parameter names and corresponding values ​​are directly saved in the preset format.

[0070] Step S26: Search the model file to be converted for parameters defined by formulas. If so, calculate the actual value of the parameter according to the formula and assign the actual value to the original parameter value position to obtain an FPGA model file based on a preset format. If not, directly obtain an FPGA model file based on a preset format.

[0071] It should be noted that the process checks whether there are parameters defined by formulas in the model file to be converted. If so, the actual value of the parameter will be calculated according to the formula (for example, if a parameter is expressed as "10*0.2 / 5" in the model, then the parameter will be converted to 0.4). The actual value will be assigned to the original parameter value position to obtain an FPGA model file based on a preset format. That is, the final FPGA model file based on the preset format is a file containing the FPGA model and the preset format of the recorded model parameters.

[0072] Step S3: If the model file to be converted is a CPU model file, then based on the preset CPU model conversion strategy, the model components in the model file to be converted are converted to generate a CPU model file based on the preset format.

[0073] It should be noted that the simulator has a preset CPU model conversion strategy, which is used to convert CPU model files from other platforms (such as the RT-LAB platform) into CPU model files in a preset format that the simulator can use.

[0074] In one embodiment, such as Figure 5 As shown, the preset CPU model conversion strategy specifically includes the following steps:

[0075] Step S31, if the model file to be converted is a CPU model file, a three-phase voltage source in the model file to be converted is found, and step S32 is executed.

[0076] It should be noted that if the model file to be converted is a CPU model file, a three-phase voltage source in the circuit model of the model file to be converted is searched.

[0077] Step S32, taking the three-phase voltage source as a root node, branches of each element are searched step by step downwards until the entire element tree connected is searched, and step S33 is executed.

[0078] Step S33, the element tree is copied into a newly created model file, an SVG module in the newly created model file is searched, and the SVG module is replaced by a current source, and step S34 is executed.

[0079] It should be noted that the element tree is copied into a newly created model file, an SVG (Static Var Generator) module in the newly created model file is searched, and the SVG module is replaced by a current source, as shown in FIG. 4. Figure 6

[0080] Step S34, an FPGA model file based on an SVG module is newly created, model parameters of the FPGA model file based on the SVG module are set according to SVG module parameters in the CPU model file, IO signals of the FPGA model file based on the SVG module are mapped into the CPU model file, and step S35 is executed.

[0081] It should be noted that an FPGA model file based on an SVG module is newly created in a simulator, model parameters of the newly created FPGA model file based on the SVG module are set according to SVG module parameters in a CPU model file (i.e., an original model file to be converted), and IO signals of the FPGA model file based on the SVG module are mapped into the CPU model file (i.e., the original model file to be converted).

[0082] Step S35, IO interface configurations of the CPU model file are read from a hardware-in-the-loop interface configuration file of the simulator, mapping relationships between analog / digital signals and IO interfaces are obtained, and step S36 is executed.

[0083] It should be noted that IO interface configurations of the CPU model file (i.e., an original model file to be converted) are read from a hardware-in-the-loop interface configuration file (i.e., a conf file of an RT-LAB platform) of a simulator, mapping relationships between analog / digital signals and IO interfaces in the CPU model file (i.e., the original model file to be converted) are obtained.

[0084] ​In one embodiment, the mapping relationship between the analog / digital signals and the IO interface includes a mapping relationship between the analog output signals of the SVG module-based FPGA model file and the IO interface, a mapping relationship between the digital input signals of the SVG module-based FPGA model file and the IO interface, a mapping relationship between the analog output signals of the CPU model file and the IO interface, and a mapping relationship between the digital input signals of the CPU model file and the IO interface. As shown in Figure 7 , the mapping relationship between the analog output signals of the SVG module-based FPGA model file and the IO interface is obtained by searching the channel tab of the Analog Output Mapping and Rescaling block Control Panel element in the CPU model file. As shown in Figure 8 , the mapping relationship between the digital input signals of the SVG module-based FPGA model file and the IO interface is obtained by searching the Gates object in the eHS CPU Block in the CPU model file. As shown in Figure 9 , the OpFcnCommonAnalogOut object in the CPU model file is taken as a parent node, the first complete element tree configuring the analog output signals of the CPU model file is indexed, the first complete element tree is parsed, and the mapping relationship between the analog output signals of the CPU model file and the IO interface is obtained. As shown in Figure 10 , the OpFcnCommonDigitalIn object in the CPU model file is taken as a parent node, the second complete element tree configuring the digital input signals of the CPU model file is indexed, the second complete element tree is parsed, and the mapping relationship between the digital input signals of the CPU model file and the IO interface is obtained.

[0085] In step S36, the mapping relationship between the analog / digital signals and the IO interface is re-listed as a file in a preset format, elements recording the mapping relationship between the analog / digital signals and the IO interface are all deleted, and a CPU model file based on the preset format is obtained.

[0086] It should be noted that the mapping relationship between the analog / digital signals and the IO interface obtained in step S35 is re-listed as a file in a preset format, and elements recording the mapping relationship between the analog / digital signals and the IO interface will cause an error when the simulator loads the model. Therefore, elements recording the mapping relationship between the analog / digital signals and the IO interface are all deleted, and a CPU model file based on the preset format is obtained. The file includes the SVG module-based FPGA model, the CPU model excluding the SVG module and not having various elements required for compiling by the original simulation platform (i.e., the RT-LAB platform), and the preset format file recording the mapping relationship between the analog / digital signals.

[0087] The new energy station electromagnetic transient model conversion method provided by the application obtains a user-selected FPGA model file or CPU model file in a simulator. For the FPGA model file, the model elements in the model file to be converted are converted based on a preset FPGA model conversion strategy to generate an FPGA model file based on a preset format. For the CPU model file, the model elements in the model file to be converted are converted based on a preset CPU model conversion strategy to generate a CPU model file based on a preset format. The new energy station electromagnetic transient model conversion method provided by the application can batch convert simulation models provided by different manufacturers into a file format available for the simulator, thereby saving the workload of test personnel in manually re-modeling and engineering configuration of projects, improving the work efficiency of new energy station grid connection testing, and solving the technical problem of the prior art that a large number of device models need to be manually re-modeled under a hardware-in-the-loop simulation platform when different manufacturers' device models are combined into a new energy station overall model, which is a large workload and reduces the efficiency of batch new energy station grid connection testing.

[0088] For ease of understanding, please refer to Figure 11 An embodiment of a new energy station electromagnetic transient model conversion device is provided in the application, which includes the following modules:

[0089] The obtaining module is configured to obtain a model file to be converted selected by a user in a simulator. The model file to be converted is an FPGA model file or a CPU model file. The FPGA model file is a circuit model file running in an FPGA, and the CPU model file is a circuit model file running in a CPU.

[0090] The FPGA model conversion module is configured to, if the model file to be converted is the FPGA model file, convert model elements in the model file to be converted based on a preset FPGA model conversion strategy to generate an FPGA model file based on a preset format.

[0091] The CPU model conversion module is configured to, if the model file to be converted is the CPU model file, convert model elements in the model file to be converted based on a preset CPU model conversion strategy to generate a CPU model file based on a preset format.

[0092] In one embodiment, the FPGA model conversion module is specifically configured to perform the following steps:

[0093] S21, if the model file to be converted is the FPGA model file, it is determined whether an alternating voltage source, an alternating current source or a direct current voltage source exists in the model file to be converted. If yes, the alternating voltage source, the alternating current source and the direct current voltage source are replaced with a controlled source form, and the process jumps to step S22. If not, no adjustment is made, and the process jumps to step S22.

[0094] S22, judge whether there is an annotated element in the model file to be converted, if yes, delete the annotated element, jump to step S23, if not, do not adjust, jump to step S23;

[0095] S23, search for the state of all electrical ports of the electrical element in the model file to be converted and connected to electrical elements other than itself, when a suspended electrical port is found, index the entire branch where the suspended electrical port is located through the suspended electrical port, delete the entire branch, and after traversing all electrical elements, jump to step S24;

[0096] S24, search for the control signal port of all electrical elements in the model file to be converted, add Inport element on each port in turn and automatically number, search for the measurement signal port of all electrical elements in the model file to be converted, add Outport element on each port in turn and automatically number, jump to step S25;

[0097] S25, search for the model attribute of the model file to be converted, extract the m file defining the model parameters, store each parameter name and the corresponding parameter value in the preset format, and jump to step S26;

[0098] S26, search for whether there is a parameter defined by an algorithm in the model file to be converted, if yes, calculate the actual value of the parameter according to the algorithm, assign the actual value to the original parameter value position, obtain the FPGA model file based on the preset format, if not, directly obtain the FPGA model file based on the preset format.

[0099] In one embodiment, in step S25, storing each parameter name and the corresponding parameter value in the preset format includes:

[0100] judging whether the parameter value corresponding to each parameter name in the m file exists a parameter that needs to be calculated through parameters other than itself, if yes, calculating the parameter value of the parameter that needs to be calculated first, and then storing each parameter name and the corresponding parameter value in the preset format, if not, directly storing each parameter name and the corresponding parameter value in the preset format.

[0101] In one embodiment, the CPU model conversion module is specifically configured to execute the following steps:

[0102] S31, if the model file to be converted is a CPU model file, find the three-phase voltage source in the model file to be converted, jump to step S32;

[0103] S32, take the three-phase voltage source as the root node, find the branches of each element step by step downward, until the entire element tree connected is found, jump to step S33;

[0104] S33, copy the element tree to the newly created model file, find the SVG module in the newly created model file, replace the SVG module with a current source, and jump to step S34;

[0105] S34, create an SVG module-based FPGA model file, set the model parameters of the SVG module-based FPGA model file according to the SVG module parameters in the CPU model file, map the IO signals of the SVG module-based FPGA model file to the CPU model file, and jump to step S35;

[0106] S35, read the IO interface configuration of the CPU model file from the hardware-in-the-loop interface configuration file of the simulator, obtain the mapping relationship between the analog / digital signals and the IO interface, and jump to step S36;

[0107] S36, recompile the mapping relationship between the analog / digital signals and the IO interface into a file in a preset format, delete all elements recording the mapping relationship between the analog / digital signals and the IO interface, and obtain a CPU model file based on the preset format.

[0108] In one embodiment, in step S35, the mapping relationship between the analog / digital signals and the IO interface includes the mapping relationship between the analog output signal of the SVG module-based FPGA model file and the IO interface, the mapping relationship between the digital input signal of the SVG module-based FPGA model file and the IO interface, the mapping relationship between the analog output signal of the CPU model file and the IO interface, and the mapping relationship between the digital input signal of the CPU model file and the IO interface.

[0109] The mapping relationship between the digital input signal of the SVG module-based FPGA model file and the IO interface is obtained by searching the Gates object in the eHS CPU Block in the CPU model file;

[0110] Taking the OpFcnCommonAnalogOut object in the CPU model file as the parent node, indexing to the first complete element tree configuring the analog output signal of the CPU model file, parsing the first complete element tree, and obtaining the mapping relationship between the analog output signal of the CPU model file and the IO interface;

[0111] Taking the OpFcnCommonDigitalIn object in the CPU model file as the parent node, indexing to the second complete element tree configuring the digital input signal of the CPU model file, parsing the second complete element tree, and obtaining the mapping relationship between the digital input signal of the CPU model file and the IO interface.

[0112] In one embodiment, the preset format is CSV format.

[0113] For the convenience of understanding, please refer to Figure 12 The application further provides an embodiment of a new energy station electromagnetic transient model conversion device, which comprises a processor and a memory:

[0114] The memory is used for storing program codes and transmitting the program codes to the processor.

[0115] The processor is used for executing any one of the foregoing various embodiments of the new energy station electromagnetic transient model conversion method according to the instructions in the program codes.

[0116] The application further provides an embodiment of a computer readable storage medium, which is used for storing program codes, and the program codes are used for executing any one of the foregoing various embodiments of the new energy station electromagnetic transient model conversion method.

[0117] The application further provides an embodiment of a computer program product comprising instructions, which, when running on a computer, causes the computer to execute any one of the foregoing various embodiments of the new energy station electromagnetic transient model conversion method.

[0118] The new energy station electromagnetic transient model conversion device, the equipment, the computer readable storage medium and the computer program product comprising instructions provided by the application are all used for executing the new energy station electromagnetic transient model conversion method provided by the application, and the principle and the technical effects obtained are the same as those of the new energy station electromagnetic transient model conversion method provided by the application, which will not be described here.

[0119] The terms "first", "second", and the like in the specification of the application are used to distinguish similar objects, and do not necessarily mean a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0120] The above-described embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalent replacements; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for converting electromagnetic transient models of new energy power plant stations, characterized in that, The method comprises the following steps: S1, obtaining a user-selected model file to be converted in a simulator, the model file to be converted being an FPGA model file or a CPU model file, the FPGA model file being a circuit model file running in an FPGA, and the CPU model file being a circuit model file running in a CPU; S2, if the model file to be converted is an FPGA model file, converting model elements in the model file to be converted based on a preset FPGA model conversion strategy to generate an FPGA model file based on a preset format; S3, if the model file to be converted is a CPU model file, converting model elements in the model file to be converted based on a preset CPU model conversion strategy to generate a CPU model file based on the preset format; Step S2 comprises: S21, if the model file to be converted is an FPGA model file, searching whether there is an alternating voltage source, an alternating current source or a direct current voltage source in the model file to be converted, if yes, replacing the alternating voltage source, the alternating current source and the direct current voltage source with a controlled source form, and jumping to step S22, if not, making no adjustment and jumping to step S22; S22, judging whether there is an annotated element in the model file to be converted, if yes, deleting the annotated element, and jumping to step S23, if not, making no adjustment and jumping to step S23; S23, searching all electrical ports of electrical elements in the model file to be converted and a state of being connected to electrical elements other than themselves, when a suspended electrical port of an electrical element is searched, indexing the suspended electrical port of the electrical element to a whole branch where the suspended electrical port is located, deleting the whole branch, and after all electrical elements are traversed, jumping to step S24; S24, searching control signal ports of all electrical elements in the model file to be converted, adding an Inport element on each port and automatically numbering, searching measurement signal ports of all electrical elements in the model file to be converted, adding an Outport element on each port and automatically numbering, and jumping to step S25; S25, searching model attributes of the model file to be converted, extracting an m file defining model parameters, storing each parameter name and a corresponding parameter value in the m file as a preset format, and jumping to step S26; S26, searching whether there is a parameter defined by an algorithm in the model file to be converted, if yes, calculating an actual value of the parameter according to the algorithm, assigning the actual value to an original parameter value position, and obtaining an FPGA model file based on the preset format, if not, directly obtaining the FPGA model file based on the preset format; Step S3 comprises: S31, if the model file to be converted is a CPU model file, finding a three-phase voltage source in the model file to be converted, and jumping to step S32; S32, taking the three-phase voltage source as a root node, finding branches of each element step by step downwards until the whole element tree connected is found, and jumping to step S33; S33, copy the element tree to a newly created model file, find an SVG module in the newly created model file, replace the SVG module with a current source, and jump to step S34; S34, create an SVG module-based FPGA model file, set model parameters of the SVG module-based FPGA model file according to SVG module parameters in the CPU model file, map IO signals of the SVG module-based FPGA model file to the CPU model file, and jump to step S35; S35, read IO interface configurations of the CPU model file from a simulator hardware-in-the-loop interface configuration file, obtain a mapping relationship between analog and digital signals and IO interfaces, and jump to step S36; S36, recompile the mapping relationship between the analog and digital signals and the IO interfaces into a file in the preset format, delete all elements recording the mapping relationship between the analog and digital signals and the IO interfaces, and obtain a CPU model file based on the preset format.

2. The method of claim 1, wherein, In step S25, the storage of each parameter name and the corresponding parameter value in the m file into the preset format includes: determining whether the parameter value corresponding to each parameter name in the m file exists a parameter that needs to be calculated through parameters other than itself, if yes, calculating the parameter value of the parameter that needs to be calculated first, and then storing each parameter name and the corresponding parameter value into the preset format, if not, directly storing each parameter name and the corresponding parameter value into the preset format.

3. The method of claim 1, wherein, In step S35, the mapping relationship between the analog and digital signals and the IO interfaces includes a mapping relationship between analog output signals of the SVG module-based FPGA model file and IO interfaces, a mapping relationship between digital input signals of the SVG module-based FPGA model file and IO interfaces, a mapping relationship between analog output signals of the CPU model file and IO interfaces, and a mapping relationship between digital input signals of the CPU model file and IO interfaces.

4. The method of claim 3, wherein, In step S35, the mapping relationship between the analog and digital signals and the IO interfaces includes a mapping relationship between analog output signals of the SVG module-based FPGA model file and IO interfaces, a mapping relationship between digital input signals of the SVG module-based FPGA model file and IO interfaces, a mapping relationship between analog output signals of the CPU model file and IO interfaces, and a mapping relationship between digital input signals of the CPU model file and IO interfaces. In step S35, the mapping relationship between the analog and digital signals and the IO interfaces includes a mapping relationship between analog output signals of the SVG module-based FPGA model file and IO interfaces, a mapping relationship between digital input signals of the SVG module-based FPGA model file and IO interfaces, a mapping relationship between analog output signals of the CPU model file and IO interfaces, and a mapping relationship between digital input signals of the CPU model file and IO interfaces. In step S35, the mapping relationship between the analog and digital signals and the IO interfaces includes a mapping relationship between analog output signals of the SVG module-based FPGA model file and IO interfaces, a mapping relationship between digital input signals of the SVG module-based FPGA model file and IO interfaces, a mapping relationship between analog output signals of the CPU model file and IO interfaces, and a mapping relationship between digital input signals of the CPU model file and IO interfaces. Using the OpFcnCommonDigitalIn object in the CPU model file as the parent node, index to the second complete component tree that configures the digital input signals of the CPU model file, parse the second complete component tree, and obtain the mapping relationship between the digital input signals of the CPU model file and the IO interface.

5. The method of claim 1-4, wherein, The preset format is CSV format.

6. A new energy plant electromagnetic transient model conversion device, characterized in that, Includes the following modules: The acquisition module is used to acquire the user-selected model file to be converted in the simulator. The model file to be converted is an FPGA model file or a CPU model file. The FPGA model file is a circuit model file running in an FPGA, and the CPU model file is a circuit model file running in a CPU. The FPGA model conversion module is used to convert the model components in the model file to be converted based on a preset FPGA model conversion strategy if the model file to be converted is an FPGA model file, thereby generating an FPGA model file based on a preset format. The CPU model conversion module is used to convert the model elements in the model file to be converted based on a preset CPU model conversion strategy if the model file to be converted is a CPU model file, thereby generating a CPU model file based on the preset format. The FPGA model conversion module is specifically used to perform the following steps: S21. If the model file to be converted is an FPGA model file, then check whether there is an AC voltage source, AC current source or DC voltage source in the model file to be converted. If so, replace the AC voltage source, AC current source and DC voltage source with a controlled source and jump to step S22. If not, do not make any adjustment and jump to step S22. S22. Determine whether there are any commented-out elements in the model file to be converted. If so, delete the commented-out elements and proceed to step S23. If not, do not make any adjustments and proceed to step S23. S23. Search for the connection status of all electrical ports of electrical components in the model file to be converted with electrical components other than themselves. When an electrical component with a floating electrical port is found, the entire branch where the electrical component with the floating electrical port is located is indexed through the electrical component with the floating electrical port. The entire branch is deleted. After traversing all electrical components, jump to step S24. S24. Search for the control signal ports of all electrical components in the model file to be converted, add Inport components to each port in sequence and automatically number them, search for the measurement signal ports of all electrical components in the model file to be converted, add Outport components to each port in sequence and automatically number them, and jump to step S25. S25. Retrieve the model attributes of the model file to be converted, extract the m file that defines the model parameters, save each parameter name and corresponding parameter value in the m file in a preset format, and proceed to step S26. S26, it is judged whether the parameter defined by the formula exists in the model file to be converted. If yes, the actual value of the parameter calculated according to the formula is assigned to the original parameter value position, and the FPGA model file based on the preset format is obtained. If no, the FPGA model file based on the preset format is directly obtained. The CPU model conversion module is specifically configured to perform the following steps: S31, if the model file to be converted is a CPU model file, a three-phase voltage source in the model file to be converted is found, and step S32 is jumped to; S32, the three-phase voltage source is taken as a root node, and branches of each element are found step by step downwards until the whole element tree connected is found, and step S33 is jumped to; S33, the element tree is copied into a newly created model file, an SVG module in the newly created model file is found, the SVG module is replaced by a current source, and step S34 is jumped to; S34, an FPGA model file based on an SVG module is newly created, model parameters of the FPGA model file based on the SVG module are set according to SVG module parameters in the CPU model file, IO signals of the FPGA model file based on the SVG module are mapped into the CPU model file, and step S35 is jumped to; S35, IO interface configurations of the CPU model file are read from a simulator hardware-in-the-loop interface configuration file, a mapping relationship between analog and digital signals and IO interfaces is obtained, and step S36 is jumped to; S36, the mapping relationship between the analog and digital signals and the IO interfaces is re-listed as a file in the preset format, elements recording the mapping relationship between the analog and digital signals and the IO interfaces are all deleted, and a CPU model file based on the preset format is obtained.

7. A new energy plant electromagnetic transient model conversion device, characterized in that, The device comprises a processor and a memory: The memory is used for storing program code and transmitting the program code to the processor; The processor is used for executing the new energy station electromagnetic transient model conversion method according to instructions in the program code.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium is used for storing program code, and the program code is used for executing the new energy station electromagnetic transient model conversion method. The computer readable storage medium is used for storing program code, and the program code is used for executing the new energy station electromagnetic transient model conversion method.

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