Multi-objective dual-level intelligent optimization method for semiconductor device processes

Abstract

The present invention proposes a multi-objective dual-layer intelligent optimization method for semiconductor device processes, which belongs to the field of semiconductor process design. The method includes two steps: upper-layer optimization and lower-layer optimization. The upper-layer optimization is oriented to the graphical process and optimizes the structural characteristics; the lower-layer optimization is oriented to the material processing process and optimizes the physical characteristics. After two layers of optimization, the electrical characteristics are simulated, which can better guide the optimization direction and reduce the simulation time. Among the individuals who meet the thresholds of various objectives and successfully simulate the electrical characteristics, the relationship between the objectives of the upper and lower layer optimizations and the final electrical characteristics objectives is judged to better adjust the preferences between different objectives in the hierarchical optimization. The present invention saves time costs and manual design costs by automating the optimization iteration of semiconductor device process optimization, and effectively improves the design efficiency of components.

Description

Technical Field

[0001] The present invention belongs to the fields of semiconductor device manufacturing process, simulation technology and intelligent optimization technology, and mainly relates to a multi-objective double-layer intelligent optimization method for semiconductor device process. Background Art

[0002] Semiconductor device manufacturing refers to the process of manufacturing various electronic components on silicon wafers or other semiconductor materials. This process includes multiple complex steps, such as lithography, etching, deposition, diffusion, ion implantation and annealing. Each step requires precise control of parameters to ensure the performance, reliability and consistency of the final product. With the development of technology, the manufacturing process continues to evolve towards smaller size, higher integration and lower power consumption, which has promoted the continued development of Moore's Law.

[0003] Simulation technology is a method of predicting and analyzing actual conditions through computer models. In semiconductor device manufacturing, simulation technology is widely used to design and optimize process flows. It can help engineers predict the impact of different process parameters on device performance before actual manufacturing, thereby reducing trial and error time. Simulation tools are usually based on physical equations and mathematical models, combined with experimental data for calibration to improve the accuracy of predictions.

[0004] Intelligent optimization technology refers to the use of artificial intelligence and machine learning algorithms to solve complex optimization problems. In the field of semiconductor device manufacturing, intelligent optimization technology can be used to automatically adjust process parameters. The key parameters around each link in semiconductor simulation will directly affect the performance of semiconductor devices. By combining with simulation technology, a large number of experiments and optimizations can be carried out in a virtual environment, thereby accelerating the development of new processes and the improvement of existing processes. Summary of the invention

[0005] The purpose of the present invention is to provide a multi-objective dual-layer intelligent optimization method for semiconductor device processes. A multi-objective optimization algorithm is used to adjust various parameters in the semiconductor manufacturing process by calling semiconductor simulation tools, and optimization is performed in two stages to meet design requirements in multiple target dimensions, effectively improving the efficiency of semiconductor component process optimization. The present invention focuses on the six steps of semiconductor lithography, etching, deposition, diffusion, ion implantation and annealing, and classifies lithography and etching as graphic processes from a process perspective, and classifies the remaining four process flows as material processing processes, and optimizes various process parameters in stages.

[0006] In order to realize the above technology, the present invention comprises the following steps:

[0007] S1: Initialize wafer parameters, perform wafer geometry modeling and material property settings: First, define the wafer geometry and size, such as the wafer diameter, thickness, and doping area; also define the physical and chemical properties of the wafer material, including the lattice constant, electron and hole mass, etc. in the wafer material;

[0008] S2: Execute the upper-level optimization algorithm to optimize the target structural characteristics: by changing the lithography process parameters and the etching process parameters, evaluate the resolution and uniformity of the wafer after the lithography and etching processes for multiple times, iteratively optimize the structural characteristics, and use the intelligent evolutionary algorithm to perform multi-objective optimization, which specifically includes the following steps:

[0009] S21: Select parameters in the photolithography process and the etching process as decision variables. The parameters in the photolithography process include the type and thickness of the photoresist, the exposure dose and exposure wavelength in the photolithography, the time spent on the exposure and the intensity during the exposure process, and the time and intensity spent on the development after the exposure. The etching process includes the type of etching gas used and the gas flow rate, the power and time during the etching process, and the pressure and temperature in the etching environment. The critical dimensions, line width roughness, and thickness uniformity of the wafer after the photolithography process and the etching process are selected as optimization targets for optimization;

[0010] Taking the minimization of multi-objective optimization problems as an example, a multi-objective optimization problem with m objectives and n decision variables can be defined as follows:

[0011]

[0012] in, Represents the value of the current individual in the dimensions of n decision variables; It represents the first target value. For the upper optimization process, Represents a set of lithography and etching parameters, Represents the simulation index of lithography and etching results.

[0013] In the current multi-objective optimization problem, individuals cannot necessarily be directly compared with each other. The optimal solution to the problem is composed of a set of Pareto optimal solutions, which are defined by the Pareto dominance relationship. and , if it satisfies:

[0014]

[0015] That is, in the case of m objective functions, for any i-th objective function , a feasible solution and Can guarantee , and there is also the jth objective function , a feasible solution and Can guarantee ,but Pareto dominance , recorded as If a solution is not dominated by any other feasible solution, it is called a non-dominated solution, and all non-dominated feasible solutions become a non-dominated solution set. The ideal result of the upper optimization process is a Pareto non-dominated solution set. , the corresponding lithography and etching target values ​​in P cannot dominate each other.

[0016] S22: Initialize the upper optimization algorithm, including randomly generating an initial solution, initializing the population size N, the dimension D of the decision space, the number of iterations T, and the number of elite solutions E that need to be saved, etc.;

[0017] S23: Start the simulator, initialize it according to the simulator configuration file and the initial population, and check whether the upper optimization algorithm and the simulator communicate well;

[0018] S24: The upper optimization algorithm sends the current population to the simulator, and the simulator calculates the target values ​​of each individual in the population on different targets through simulation. ;

[0019] S25: Taking the current population as the parent, generating a child population through the crossover operator and mutation operator optimized for the upper layer, the size of the child population is the same as that of the parent population;

[0020] S26: Calculate the target value of the offspring population , the calculation method is the same as S24;

[0021] S27: Use non-dominated sorting to select the environment, select the non-dominated solutions, and then use the preference weights to screen the non-dominated solutions. Under the same non-dominated level, give priority to the goals with high weights to get the best front. The solutions are used as the population for the next generation.

[0022] S3: Check whether the structural characteristics of the wafer optimized in step S2 meet the upper target threshold: if the target threshold is reached, proceed to step S4; if the target threshold is not reached, return to step S2 and perform another round of optimization, which specifically includes the following steps:

[0023] S31: Initialize the minimum value that each target in S2 needs to meet as the upper optimization target threshold;

[0024] S32: Perform structural characteristic test on all individuals in the current population. If there are individuals that meet the target threshold, they will be used as the initial individuals of S4. If there are no individuals that meet the target threshold, return to S2 and optimize again.

[0025] S4: Execute the lower-level optimization algorithm to optimize the target physical properties: by changing the deposition, ion implantation, diffusion and annealing process parameters, evaluate the wafer doping activation, lattice damage, surface concentration and doping junction depth of the annealed wafer multiple times, iteratively optimize the physical properties, and use the intelligent evolutionary algorithm to perform multi-objective optimization, which specifically includes the following steps:

[0026] S41: Select the parameters in the deposition process, ion implantation process, diffusion process and annealing process as the decision variables for the lower-level optimization. The parameters in the deposition process include the pressure and temperature of the deposition environment, the type and flow of the gas in the deposition process; the parameters in the ion implantation process include the type and dose of the implanted ions, the energy added to the ions during implantation and the implantation angle, and the density of the ion beam; the parameters in the diffusion process include the pressure and temperature of the diffusion environment, the type of impurities used for diffusion and the concentration of impurities; the parameters in the annealing process include the annealing time and temperature, and the atmosphere in the annealing process. The doping activation, lattice damage, surface concentration and doping junction depth evaluation results of the wafer after annealing are selected as the optimization targets for optimization.

[0027] S42: Initialize the lower-level optimization algorithm, and then randomly generate individuals in the lower-level optimization, where the individual decision variables regarding lithography and etching are defined by the individuals that meet the target threshold in S3, and define the initial population size N, the dimension D of the decision space, the number of iterations T, and the elite solution E that needs to be saved;

[0028] S43: Start the simulator, initialize it according to the simulator configuration file and the initial population, and check whether the lower-level optimization algorithm and the simulator communicate well;

[0029] S44: The lower optimization algorithm sends the current population to the simulator, and the simulator calculates the target values ​​of each individual in the population on different targets through simulation. ;

[0030] S45: Using the current population as the parent, a offspring population is generated through the crossover operator and mutation operator optimized for the upper layer, and the population size of the offspring population is the same as that of the parent population;

[0031] S46: Calculate target value of offspring population , the calculation method is the same as S44;

[0032] S47: Use non-dominated sorting to select the environment, pick out non-dominated solutions, and then use preference weights to screen the non-dominated solutions to obtain the top N solutions as the next generation population.

[0033] S5: Check whether the physical properties of the wafer after optimization in step S4 meet the lower target threshold: if the target threshold is reached, proceed to S6; if the target threshold is not reached, determine the degree of deviation from the target threshold. If the deviation is minor, return to S4 for another round of optimization. If the deviation is serious, return to S2 for another round of structural property optimization. Specifically, the following steps are included:

[0034] S51: Initialize the minimum value that each target in S4 needs to meet as the lower-level optimization target threshold;

[0035] S52: Physical property tests are performed on all individuals in the current population. If there are individuals that meet the target threshold, these individuals are sent to S6. If the number of targets that deviate from the target threshold is less than or equal to half, return to S4 for another round of optimization. If more than half of the targets deviate from the target threshold, return to S2 for another round of structural property optimization.

[0036] S6: Evaluate the electrical characteristics of the individuals that reach the lower target threshold in step S5, obtain the electrical characteristics of the wafer, and calculate the preference weight of each target, specifically including the following steps:

[0037] S61: Evaluate the electrical properties of the individuals that meet the target threshold in S5 to obtain their electrical properties;

[0038] S62: Integrate the structural, physical and electrical properties of these individuals, and calculate the preference weights of each objective in the upper and lower optimizations. is defined as follows:

[0039]

[0040] In the formula, represents the i-th structural or physical property of these individuals; Y represents the electrical properties of these individuals, It represents the absolute value of the Pearson correlation coefficient between the two. Specifically, it can be calculated according to the following formula:

[0041]

[0042] in, represents the mathematical expectation of the target, It represents the tolerance of the target.

[0043] S7: Determine whether the termination condition of the evolution is met. If the termination condition is not met, return to step S2. If the termination condition is met, end the evolution process.

[0044] S8: Output the parameters and objectives of the optimal solution.

[0045] Compared with the prior art, the present invention has the following beneficial technical effects:

[0046] 1) The method of the present invention can reduce the cost of semiconductor design and improve design efficiency: through simulation technology and meta-heuristic optimization algorithm, it can efficiently design semiconductor components that meet expectations, reducing manual design costs and unnecessary simulation calculations.

[0047] 2) The method of the present invention can simultaneously optimize multiple objectives and can optimize multiple conflicting performance indicators to obtain semiconductor components with better simulation results.

[0048] 3) The method of the present invention is highly generalizable and covers the key processes of component design: it is applicable to various types of designs and can be optimized for different manufacturing processes. It has broad application prospects and a large optimization range. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 An overall flow chart of a multi-objective dual-layer intelligent optimization method for a semiconductor device process provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the specific implementation methods of the present invention will be further described in detail below in conjunction with specific embodiments.

[0051] This embodiment describes in detail the process of MOS wafer process optimization. From the final simulation results, the optimization goal is to make the threshold voltage (TV) of the MOS wafer as high as possible while ensuring that the leakage current (LC) is as low as possible. In the upper-level optimization, the focus of the optimization of structural characteristics is on the resolution and uniformity of the wafer obtained after the lithography and etching steps. Specifically, the critical dimension (CD) should be as close to the design target value as possible, the line width roughness (LWR) should be as low as possible, and the thickness uniformity (TU) should be as high as possible. In the lower-level optimization, the focus of the optimization of physical properties is on the wafer doping activation, lattice damage, surface concentration and doping junction depth evaluation after annealing. Specifically, the activation rate (AR) should be as high as possible, the change in defect density (DD) should be as small as possible, and the surface concentration (SC) and junction depth (JD) should be as close to the design target value as possible.

[0052] Based on the above optimization requirements, this embodiment provides a multi-objective dual-layer intelligent optimization method for semiconductor device processes, and its process is as follows: Figure 1 As shown, the specific steps include:

[0053] S1: Initialize wafer parameters, perform wafer geometry modeling and material property settings: First, define the wafer geometry and size, such as the wafer diameter, thickness, and doping area; also define the physical and chemical properties of the wafer material, including the lattice constant, electron and hole mass, etc. in the wafer material;

[0054] S2: Execute the upper-level optimization algorithm to optimize the target structural characteristics: by changing the lithography process parameters and the etching process parameters, evaluate the resolution and uniformity of the wafer after the lithography and etching processes for multiple times, iteratively optimize the structural characteristics, and use the intelligent evolutionary algorithm to perform multi-objective optimization, which specifically includes the following steps:

[0055] S21: 14 parameters in the photolithography process and the etching process are selected as decision variables. The parameters in the photolithography process include the type (PTY) and thickness (PTH) of the photoresist, the exposure dose (ED) and exposure wavelength (EXW) in the photolithography, the time spent on exposure (EXT) and the intensity (EXI) during the exposure process, as well as the time (DT) and intensity (DI) spent on development after exposure. The etching process includes the type of etching gas used (EGT) and the gas flow rate (EGF), the power (EP) and time (ET) during the etching process, and the pressure (EP) and temperature (ET) in the etching environment. Critical dimension (CD), line width roughness (LWR) and thickness uniformity (TU) are selected as optimization targets;

[0056] According to the definition of solving the minimization multi-objective optimization problem, the above problem has a total of 3 objectives and 14 decision variables. The multi-objective optimization problem can be defined as follows:

[0057]

[0058] in, Represents critical dimension, which is indicated by the size of the component after photolithography and etching. The closer to the design value, the better. It stands for line width roughness, which is expressed by the tolerance of the lines after component lithography and etching. The smaller the better. Represents thickness uniformity, which is determined by the thickness tolerance of different positions of the component after photolithography. The smaller the better. For the upper layer optimization process, represents the value of the current individual in the above 14 decision variable dimensions; since the simulation index of lithography and etching results is not a minimization problem, Represents the objective function after adjusting the simulation index of lithography and etching results. In the current multi-objective optimization problem, two individuals may not be directly compared. The optimal solution of the problem is composed of a set of Pareto optimal solutions, and the Pareto optimal solution is defined by the Pareto dominance relationship. For feasible solutions and , if it satisfies:

[0059]

[0060] That is, in the case of m objective functions, for any i-th objective function , a feasible solution and Can guarantee , and there is also the jth objective function , a feasible solution and Can guarantee ,but Pareto dominance , recorded as If a solution is not dominated by any feasible solution, it is called a non-dominated solution, and all non-dominated feasible solutions become a non-dominated solution set. The ideal result of the upper optimization process is a Pareto non-dominated solution set. , the corresponding lithography and etching target values ​​in P cannot dominate each other.

[0061] S22: Initialize the upper optimization algorithm, including randomly generating an initial solution, initializing the population size N=100, the dimension of the decision space D=14, the number of iterations T=100 and the elite solutions E to be saved, where the upper limit of the number of elite solutions is 200;

[0062] S23: Start the simulator, initialize it according to the simulator configuration file and the initial population, and check whether the upper optimization algorithm and the simulator communicate well;

[0063] S24: The upper optimization algorithm sends the current population to the simulator, which calculates the target values ​​of the three targets for each individual in the population through simulation. ;

[0064] S25: Take the current population as the parent, and generate a child population by using the crossover operator and mutation operator designed for the upper layer optimization, where the probability of crossover is 0.2 and the probability of mutation is 0.1. The size of the child population is the same as that of the parent population.

[0065] S26: Calculate the target value of the offspring population , the calculation method is the same as S24;

[0066] S27: Use non-dominated sorting to select the environment, select the non-dominated solutions, and then use the preference weights to screen the non-dominated solutions. Under the same non-dominated level, give priority to the goals with higher weights to obtain the best front. The solutions are used as the population for the next generation;

[0067] S3: Check whether the structural characteristics of the wafer optimized in step S2 meet the upper target threshold: if the target threshold is reached, proceed to step S4; if the target threshold is not reached, return to step S2 and perform another round of optimization, which specifically includes the following steps:

[0068] S31: Initialize the minimum value that each target in S2 needs to meet as the upper target threshold, and the specific value is provided by relevant technical personnel according to the actual manufacturing situation;

[0069] S32: Perform structural characteristic test on all individuals in the current population. If there are individuals that meet the target threshold, they will be used as the initial individuals of S4. If there are no individuals that meet the target threshold, return to S2 and optimize again.

[0070] S4: Initialize the lower-level optimization algorithm to optimize the physical properties. By changing the deposition, ion implantation, diffusion and annealing process parameters, the wafer doping activation (DA), lattice damage (LD), surface concentration (SC) and doping junction depth (JD) of the wafer after annealing are evaluated multiple times. The intelligent evolutionary algorithm is used to optimize these four goals. Specifically, the following steps are included:

[0071] S41: 17 parameters in the deposition process, ion implantation process, diffusion process and annealing process are selected as decision variables for lower-level optimization. The parameters in the deposition process include the pressure and temperature of the deposition environment, the type and flow of gas in the deposition process; the parameters in the ion implantation process include the type and dose of the implanted ions, the energy added to the ions during implantation and the angle of implantation, and the density of the ion beam; the parameters in the diffusion process include the pressure and temperature of the diffusion environment, the type of impurities used for diffusion and the concentration of impurities; the parameters in the annealing process include the annealing time and temperature, and the atmosphere during the annealing process. The doping activation, lattice damage, surface concentration and doping junction depth evaluation results of the wafer after annealing are selected as the optimization targets for optimization;

[0072] According to the definition of solving the minimization multi-objective optimization problem, the lower-level optimization has a total of 4 objectives and 17 decision variables. The multi-objective optimization problem can be defined as follows:

[0073]

[0074] in represents wafer doping activation (DA), which is determined by the rate at which dopants are successfully activated into current-carrying electrons; stands for lattice damage (LD), which is determined by the local destruction of the lattice structure inside the semiconductor; represents the surface concentration (SC), which is determined by the amount of dopant per unit volume on the surface of the semiconductor material; It stands for junction doping depth (JD), which is determined by the distance from the semiconductor surface to the pn junction location inside the semiconductor.

[0075] For the lower layer optimization process, represents the value of the current individual in the above 17 decision variable dimensions; since the wafer doping activation, lattice damage, surface concentration and doping junction depth simulation indicators are not a minimization problem, Represents the objective function after adjusting the simulation index. In the current multi-objective optimization problem, two individuals may not be directly comparable. The optimal solution to the problem is composed of a set of Pareto optimal solutions, which are defined by the Pareto dominance relationship. and , if it satisfies:

[0076]

[0077] That is, in the case of m objective functions, for any i-th objective function , a feasible solution and Can guarantee , and there is also the jth objective function , a feasible solution and Can guarantee ,but Pareto dominance , recorded as If a solution is not dominated by any feasible solution, it is called a non-dominated solution, and all non-dominated feasible solutions become a non-dominated solution set. The ideal result of the upper optimization process is a Pareto non-dominated solution set. , the corresponding lithography and etching target values ​​in P cannot dominate each other.

[0078] S42: Initialize the lower-level optimization algorithm, and then randomly generate individuals in the lower-level optimization, where the decision variables of the individuals regarding lithography and etching are defined by the individuals that meet the target threshold in S3, and define the initial population size N=100, the dimension of the decision space D=17, the number of iterations T=100, and the elite solutions E that need to be saved, where the upper limit of the number of elite solutions is 200;

[0079] S43: Start the simulator, initialize it according to the simulator configuration file and the initial population, and check whether the lower-level optimization algorithm and the simulator communicate well;

[0080] S44: The lower optimization algorithm sends the current population to the simulator, and the simulator calculates the target values ​​of each individual in the population on different targets through simulation. ;

[0081] S45: Using the current population as the parent, a offspring population is generated through the crossover operator and mutation operator optimized for the upper layer, and the population size of the offspring population is the same as that of the parent population;

[0082] S46: Calculate target value of offspring population , the calculation method is the same as S44;

[0083] S47: Use non-dominated sorting to select the environment, select the non-dominated solutions, and then use the preference weights to screen the non-dominated solutions to obtain the top N solutions as the next generation population;

[0084] S5: Check whether the physical properties of the wafer after S4 optimization meet the lower target threshold. If they meet the target threshold, proceed to S6. If they do not meet the target threshold, determine the degree of deviation from the target threshold. If the degree of deviation from the target threshold is minor, return to S4 for another round of optimization. If the degree of deviation from the target threshold is serious, return to S2 for another round of structural property optimization. Specifically, the following steps are included:

[0085] S51: Initialize the minimum value that each target in S5 needs to meet as the lower-level target threshold that needs to be met;

[0086] S52: Perform physical property inspection on all individuals in the current population. If there are individuals that meet the target threshold, these individuals are sent to S6. If there are no individuals that meet the target threshold, check the degree of deviation from the target threshold. If the deviation from the target threshold is serious, return to S2. If the deviation from the target threshold is small, return to S4.

[0087] The degree of deviation from the target threshold is defined according to the number of targets that are not met; for example, if there are 4 lower-level optimization targets, and more than half (i.e., 3-4) of them deviate from the target threshold, it is considered a more serious situation and needs to return to S2 for upper-level optimization; otherwise, it is considered a less serious situation and needs to return to S4 for lower-level optimization.

[0088] S6: Evaluate the electrical characteristics of the results that meet the target threshold in S5, obtain the electrical characteristics of the wafer, simulate the threshold voltage (TV) and leakage current (LC) of the component, and calculate the preference weight of each target, which specifically includes the following steps:

[0089] S61: Evaluate the threshold voltage and leakage current of the individuals that meet the target threshold in S5 to obtain their electrical properties;

[0090] S62: Integrate the structural characteristics, physical characteristics and electrical characteristics of these individuals, and calculate the preference weight of each target in the upper optimization and the lower optimization. In this specific embodiment, the preference weight is represented by the correlation between the electrical characteristics calculated in S61 and the structural characteristics and physical characteristics calculated in S2 and S4, and is summed after calculation using the Pearson correlation coefficient. Specifically, for 2 electrical characteristics and a total of 7 structural characteristics and physical characteristics, the preference weight is a vector with 7 components, namely is defined as follows:

[0091]

[0092] In the formula, The structural or physical characteristics representing these individuals are the goals of upper-layer optimization and lower-layer optimization mentioned above. There are seven of them, namely, critical dimension (CD), line width roughness (LWR), thickness uniformity (TU), activation rate (AR), defect density (DD), surface concentration (SC), and junction depth (JD). represents these individual threshold voltages (TV), represents the leakage current (LC) of these individuals, It represents the absolute value of the Pearson correlation coefficient between the two. Specifically, it can be calculated according to the following formula:

[0093]

[0094] in, represents the mathematical expectation of the target, It represents the tolerance of the target;

[0095] S7: Determine whether the termination condition of evolution is met. If not, return to S2. If met, end the evolution process.

[0096] S8: Output the parameters and objectives of the optimal solution.

[0097] The present invention can reduce the cost of semiconductor design and improve design efficiency: through simulation technology and meta-heuristic optimization algorithm, it can efficiently design semiconductor components that meet expectations, reduce manual design costs and unnecessary simulation calculations; the present invention can simultaneously optimize multiple targets, can optimize multiple conflicting performance indicators, and obtain semiconductor components with better simulation results; the present invention has strong generalization and covers the key processes of component design: it is suitable for various types of designs and can be optimized for different manufacturing processes, with broad application prospects and a large optimization range.

[0098] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A multi-objective dual-layer intelligent optimization method for semiconductor device technology, characterized in that: The following steps are involved: S1: Initialize wafer parameters, perform wafer geometry modeling and material property settings: first define the structural characteristics of the wafer including geometry and size; meanwhile define the physical characteristics of the wafer material; the structural characteristics include the critical dimensions, line width roughness, and thickness uniformity of the wafer after the photolithography process and the etching process; the physical characteristics specifically include doping activation, lattice damage, surface concentration, and doping junction depth of the wafer after annealing; S2: Execute the upper-level optimization algorithm to optimize the target structural characteristics: by changing the lithography process parameters and etching process parameters, evaluate the structural characteristics of the wafer after the lithography and etching processes and perform iterative optimization, and use the intelligent evolutionary algorithm to perform multi-objective optimization; The photolithography process parameters and etching process parameters specifically include: the type and thickness of the photoresist, the exposure dose and exposure wavelength, the exposure time and intensity during the exposure process, and the time and intensity of the development after the exposure in the photolithography process; the type of etching gas used and the gas flow rate, the power and time during the etching process, and the pressure and temperature in the etching environment in the etching process; S3: Check whether the structural characteristics of the wafer optimized in step S2 meet the upper target threshold: if the target threshold is reached, proceed to step S4; if the target threshold is not reached, return to step S2 and perform another round of optimization; S4: Execute the lower-level optimization algorithm to optimize the target physical properties: evaluate the physical properties of the annealed wafer and perform iterative optimization by changing the process parameters of deposition, ion implantation, diffusion and annealing, and perform multi-objective optimization using an intelligent evolutionary algorithm; the deposition, ion implantation, diffusion and annealing process parameters include the pressure and temperature of the deposition environment, the type and flow of gas during the deposition process; the type and dose of ions implanted during the ion implantation process, the energy added to the ions during the implantation and the angle of implantation, and the density of the ion beam; the pressure and temperature of the diffusion environment during the diffusion process, the type of impurities used for diffusion and the concentration of impurities; the annealing time and temperature during the annealing process, and the atmosphere during the annealing process; S5: Check whether the physical properties of the wafer after optimization in step S4 meet the lower target threshold: if the target threshold is reached, proceed to step S6; if the target threshold is not reached, determine the degree of deviation from the target threshold. If the number of targets that deviate from the target threshold is less than or equal to half, return to step S4 for a new round of optimization. If more than half of the targets deviate from the target threshold, return to step S2 for re-optimization of the structural properties. S6: Evaluate the electrical characteristics of the individuals that reach the lower target threshold in step S5, obtain the electrical characteristics of the wafer, and calculate the preference weight of each target; S7: Determine whether the termination condition of evolution is met. If not, return to step S2. If met, end the evolution process. S8: Output the parameters and objectives of the optimal solution.

2. The multi-objective dual-layer intelligent optimization method for semiconductor device process according to claim 1, characterized in that: Step S2 includes the following steps: S21: Selecting parameters in the photolithography process and the etching process as decision variables, and optimizing the structural characteristic simulation indicators after the photolithography process and the etching process as targets; Taking the minimization of multi-objective optimization problem as an example, a multi-objective optimization problem with m objectives and n decision variables is defined as follows: minf(x)=[f1(x),f2(x),...,f m (x)]; Where x=(x1,x2,...,x n ) represents the value of the current individual in the n decision variable dimensions; f m (x) represents the mth target value calculated by the individual through different objective function calculation formulas; for the upper optimization process, x represents a set of lithography and etching parameters, and f(x) represents the simulation index of lithography and etching results; In the current multi-objective optimization problem, the optimal solution of the problem is composed of a set of Pareto optimal solutions. For feasible solutions x1 and x2, if they satisfy: That is, in the case of m objective functions, for any i-th objective function f i , both feasible solutions x1 and x2 can ensure f i (x1)≤f i (x2), there is also the jth objective function f j , feasible solutions x1 and x2 can ensure f j (x1)<f j (x2), then x1 Pareto dominates x2, denoted as x1>x2; the final optimization obtains a Pareto non-dominated solution set P; S22: Initialize the upper optimization algorithm, including randomly generating the initial solution, initializing the population size, the dimension of the decision space, the number of iterations, and the number of elite solutions to be saved; S23: Start the simulator, initialize it according to the simulator configuration file and the initial population, and check whether the upper optimization algorithm and the simulator communicate well; S24: The upper optimization algorithm sends the current population to the simulator, and the simulator calculates the simulation index f(x) of each individual in the population on different targets through simulation; S25: Taking the current population as the parent, generating a child population through the crossover operator and mutation operator optimized for the upper layer, the size of the child population is the same as that of the parent population; S26: Calculate the result simulation index f(x) of the offspring population, the calculation method is the same as step S24; S27: Use non-dominated sorting to select the environment, pick out non-dominated solutions, and then use preference weights to screen the non-dominated solutions. Under the same non-dominated level, give priority to targets with high weights, and get the top N solutions as the next generation of population.

3. The multi-objective dual-layer intelligent optimization method for semiconductor device process according to claim 2, characterized in that: Step S4 includes the following steps: S41: Selecting parameters in the deposition process, ion implantation process, diffusion process and annealing process as decision variables for lower-level optimization; selecting physical property simulation indicators of the wafer after annealing as optimization targets for optimization; S42: Initialize the lower-level optimization algorithm, and then randomly generate individuals in the lower-level optimization, where the individual decision variables regarding lithography and etching are defined by the individuals that meet the target threshold in S3, and define the initial population size, the dimension of the decision space, the number of iterations, and the number of elite solutions that need to be saved; S43: Start the simulator, initialize it according to the simulator configuration file and the initial population, and check whether the lower-level optimization algorithm and the simulator communicate well; S44: the lower optimization algorithm sends the current population to the simulator, and the simulator calculates the simulation index of each individual in the population on different targets through simulation; S45: Using the current population as the parent, a offspring population is generated through the crossover operator and mutation operator optimized for the upper layer, and the population size of the offspring population is the same as that of the parent population; S46: Calculate the result simulation index of the offspring population, the calculation method is the same as step S44; S47: Use non-dominated sorting to select the environment, pick out non-dominated solutions, and then use preference weights to screen the non-dominated solutions to obtain the top N solutions as the next generation population.

4. The multi-objective dual-layer intelligent optimization method for semiconductor device technology according to claim 3, characterized in that: Step S6 includes the following steps: S61: Evaluate the electrical characteristics of the individuals that meet the target threshold in S5 to obtain their electrical characteristics; S62: Integrate the structural characteristics, physical characteristics and electrical characteristics of these individuals, and calculate the preference weight of each target in the upper optimization and the lower optimization, the preference weight W = (w1, w2, ..., w m ) is defined as follows: W=[per(y1,Y),per(y2,Y),...,per(y i ,And),...,per(and m ,AND)]; In the formula, y i represents the i-th structural or physical property of these individuals; Y represents the electrical properties of these individuals, per(y i , Y) represents the absolute value of the Pearson correlation coefficient between the two, which is calculated according to the following formula: Among them, E represents mathematical expectation and D represents tolerance.

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