Physical layer chip design generation method, device and medium based on module reuse

Abstract

The present invention relates to the field of chip technology, and in particular to a method, device and medium for generating physical layer chip design based on module reuse. The method comprises S1, obtaining a name list and interconnection information of the minimum component unit of the logic layer chip design at the logic layer; S2, obtaining reorganization configuration information; S3, generating minimum component unit reuse mapping information and standard modules; S4, if it is a reusable physical layer chip component module, executing S5, otherwise, executing S6; S5, generating a virtual module, comparing the virtual module with the standard module, if they are consistent, generating a corresponding physical layer component module instance based on the standard module, otherwise, generating error information and executing S7; S6, directly generating a physical layer chip component module; S7, if there is no error information, generating a physical layer chip design, otherwise, outputting all error information. The present invention improves the generation efficiency and accuracy of the physical layer chip design.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a physical layer chip design generation method, device and medium based on module reuse. Background Art

[0002] In the chip design process, it is usually necessary to first establish the logical interconnection between multiple logic chip components to generate a logic layer chip design. Then, based on the interconnection relationship between the smallest components in the logic layer chip design and the physical layout and routing, the physical interconnection between multiple physical layer chip components is established to generate a physical layer chip design. The logic chip component module and the physical layer chip component module are the smallest components or the modules composed of the interconnection of the smallest components. The interconnection relationship between the smallest components of the physical layer chip design and the logic layer chip design remains unchanged. The chip scale is very large. In the process of generating the physical layer chip design, if the physical layer chip component modules are generated one by one and the interconnection relationship between the physical layer chip component modules is constructed, it takes a lot of time and is extremely inefficient. In chip design, there are many scenarios where different instances can be generated by the same module. In the process of generating the physical chip design, if the chip component modules can be accurately reused, the generation efficiency and accuracy of the physical layer chip design will be greatly improved. It can be seen from this that how to improve the generation efficiency and accuracy of the physical layer chip design has become an urgent problem to be solved. Summary of the invention

[0003] The purpose of the present invention is to provide a method, device and medium for generating a physical layer chip design based on module reuse, thereby improving the generation efficiency and accuracy of the physical layer chip design.

[0004] According to a first aspect of the present invention, a method for generating a physical layer chip design based on module reuse is provided, comprising:

[0005] Step S1, obtaining a name list of the smallest component unit of the logic layer chip design at the logic layer and the interconnection information between the smallest component units, wherein the name of the smallest component unit at the logic layer is generated by concatenating the logic level information and the smallest component unit identifier;

[0006] Step S2, obtaining reorganization configuration information from logic layer chip design to physical layer chip design based on the interconnection relationship between the minimum component units and the physical layout and wiring;

[0007] Step S3, generating minimum component unit reuse mapping information and a standard module corresponding to each reusable physical layer chip component module based on the interconnection relationship and physical layout and routing between the minimum component units, the reusable chip component module is an instantiation module generated based on the standard module, and the standard module includes the component modules included in the standard module, the arrangement order of the component modules and the port list of the standard module;

[0008] Step S4, if the physical layer chip component module is a reusable physical layer chip component module, execute step S5, otherwise, execute step S6;

[0009] Step S5, generating a virtual module corresponding to the physical layer chip component module based on the reorganized configuration information, the standard module and the interconnection relationship between the minimum component units, comparing the virtual module with the corresponding standard module, if they are consistent, generating a corresponding physical layer component module instance based on the corresponding standard module, otherwise, generating a corresponding error message, and executing step S7;

[0010] Step S6, generating a physical layer chip component module based on the reorganized configuration information, the standard module and the interconnection relationship between the minimum component units, and executing step S7;

[0011] Step S7: If no error information exists in all physical layer chip component modules, a physical layer chip design is generated; otherwise, all error information is output.

[0012] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0013] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0014] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the physical layer chip design generation method, device and medium based on module reuse provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0015] The present invention realizes the reuse of chip component modules in the process of generating physical layer chip design by constructing a standard module corresponding to each reusable physical layer chip component module. In addition, the physical layer chip component modules to be generated can be verified during the reuse process, thereby improving the generation efficiency and accuracy of the physical layer chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A flow chart of a method for designing and generating a physical layer chip based on module reuse provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0019] The embodiment of the present invention provides a physical layer chip design generation method based on module reuse, such as Figure 1 As shown, including:

[0020] Step S1, obtaining a name list of the smallest component unit of the logic layer chip design at the logic layer and the interconnection information between the smallest component units, wherein the name of the smallest component unit at the logic layer is generated by concatenating the logic level information and the smallest component unit identifier.

[0021] It should be noted that both the logic layer chip design and the physical layer chip design are composed of multiple chip component modules interconnected. The chip component module is the smallest component unit or a module composed of the smallest component units interconnected. The chip component module is hierarchical. The smallest component unit has no child component module, and the top module has no parent module. Other chip component modules that are not the smallest component unit have a parent module and at least one child component module. As an example, the name of the smallest component unit in the logic layer is SOC.IP1.IP2.AU1, then SOC.IP1.IP2 is the hierarchical information of the smallest component unit, and AU1 is the smallest component unit identifier.

[0022] Step S2: obtaining reorganized configuration information from logic layer chip design to physical layer chip design based on the interconnection relationship between the smallest component units and the physical layout and wiring.

[0023] It should be noted that the minimum components required for chip design and the interconnection relationship between the minimum components are determined through the logic layer chip design. In the physical layer chip design stage, the intermediate layer chip component modules need to be re-determined based on physical layout and routing, but the required minimum components and the interconnection relationship between the minimum components are consistent with the logic layer chip design. The target position of each group of minimum components in the physical layer chip design is determined in the reorganized configuration information.

[0024] Step S3, based on the interconnection relationship between the minimum component units and the physical layout and routing, the minimum component unit reuse mapping information and the standard module corresponding to each reusable physical layer chip component module are generated. The reusable chip component module is an instantiated module generated based on the standard module. The standard module includes the component modules included in the standard module, the arrangement order of the component modules and the port list of the standard module.

[0025] It should be noted that the chip scale is very large. In the logic layer chip design, there are multiple minimum components that are instantiated based on the same module. If the physical layer chip component module is generated directly based on the reorganized configuration information, it is necessary to repeatedly generate a large number of minimum components and chip component modules that are not minimum components. Therefore, in step S3, a standard module corresponding to each reusable physical layer chip component module is first generated. In the subsequent process of generating the physical layer chip design, the standard module can be reused to reduce the number of chip component modules generated and improve the generation efficiency of the physical layer chip design of the chip component module.

[0026] Step S4: If the physical layer chip component module is a reusable physical layer chip component module, execute step S5; otherwise, execute step S6.

[0027] Step S5, based on the reorganization configuration information, the interconnection relationship between the standard modules and the minimum component units, generate a virtual module corresponding to the physical layer chip component module, and compare the virtual module with the corresponding standard module. If they are consistent, generate a corresponding physical layer component module instance based on the corresponding standard module. Otherwise, generate a corresponding error message and execute step S7.

[0028] It should be noted that there may be problems in the configuration information, so for the physical layer chip component module with standard modules, it can be verified based on the standard module first, and then quickly generated based on the standard module after the verification passes, otherwise, the corresponding error information is generated. The error information specifically includes the location information corresponding to the error point, including sequence information, layer information, port information, etc.

[0029] Step S6: Generate a physical layer chip component module based on the reorganized configuration information, the standard module, and the interconnection relationship between the minimum component units, and execute step S7.

[0030] It should be noted that no verification is performed in step S6, but the reusable sub-component modules involved in step S6 will be generated based on step S5 during the generation process and will also be verified.

[0031] Step S7: If no error information exists in all physical layer chip component modules, a physical layer chip design is generated; otherwise, all error information is output.

[0032] It should be noted that if there is no error information in all physical layer chip component modules, it means that all reusable physical layer chip component modules have passed the verification and the physical layer chip design can be generated. Otherwise, all error information is output, and the reorganization configuration information can be adjusted based on all error information. After the adjustment, steps S1-S7 can be iteratively executed until the physical layer chip design is generated. It can be understood that for all error information, it can be processed first based on the error information of the lower level (assuming that the top level is the highest level). After the low-level error information is processed, some high-level error information will also be processed accordingly.

[0033] As an embodiment, step S2 includes:

[0034] Step S21, determining the name of each minimum component unit at the physical layer before reuse based on the interconnection relationship between the minimum component units and the physical layout and routing, wherein the name of the minimum component unit at the physical layer is generated by concatenating the physical layer information and the minimum component unit identifier.

[0035] As an example, the name of the minimum component unit in the physical layer is SOC.TP1.TP2.AU2, then SOC.TP1.TP2 is the level information of the minimum component unit, and AU2 is the minimum component unit identifier.

[0036] Step S22: Generate reorganization configuration information {(A1, B1), (A2, B2), ..., (A n ,B n ),...,(A N ,B N )},(A n ,B n ) is the nth reorganization configuration information, A n is the name of the smallest component unit at the logical level, B n A n The name of the corresponding smallest component unit in the physical layer. The value range of n is 1 to N, where N is the total number of the smallest components of the logic layer chip design, {(A1, B1), (A2, B2),..., (An ,B n ),...,(A N ,B N )}, the reorganized configuration information with the same physical layer information is arranged in the order in which the smallest component units are generated at the physical layer.

[0037] It should be noted that the B corresponding to the reorganization configuration information with the same physical layer information n The hierarchy and the corresponding parent modules are the same, and the reorganized configuration information with the same physical hierarchy information is in {(A1, B1), (A2, B2),..., (A n ,B n ),...,(A N ,B N )} is the order of B with the same physical layer information n The order in which they are generated in the corresponding parent module.

[0038] As an embodiment, step S3 includes:

[0039] Step S31, obtain the name list {C1, C2, ..., C m ,...,C M}, C m It is the name of the mth reusable minimum component unit in the logic layer chip design at the logic layer, the value range of m is 1 to M, M is the total number of names of the reusable minimum component units in the logic layer chip design at the logic layer, M≤N.

[0040] The reusable minimum component unit is an instantiated minimum component unit generated based on the same standard module. Since the minimum component unit remains unchanged from the logic layer chip design to the physical layer chip design, it is only necessary to obtain the name list of the reusable minimum component unit in the logic layer chip design at the logic layer, and there is no need to obtain the chip component modules of other non-minimum components that are reusable in the logic layer chip design.

[0041] Step S33: Get C m Corresponding standard module D m , C m Based on D m Generated instantiation module,D m Includes a list of ports.

[0042] It should be noted that different C m Corresponding standard module D m Probably the same.

[0043] Step S34: C mThe physical layer information of the corresponding minimum component unit in the physical layer name remains unchanged, and the minimum component unit identifier is updated to D m , generating C m The name of the smallest component unit after reuse at the physical layer is E m .

[0044] Step S35: Based on all C m The corresponding E m The mapping relationship between the minimum component units generates the reuse mapping information.

[0045] Step S36, based on the interconnection relationship between the minimum components, physical layout and wiring, and the reuse mapping information of the small components, the standard modules corresponding to the reusable chip components of all levels of non-minimum components are generated. The standard modules corresponding to the reusable chip components of the non-minimum components include the components included in the standard modules, the arrangement order of the components, and the port list of the standard modules.

[0046] Standard modules corresponding to all levels in the physical layer are constructed through steps S31 to S36. Reusable chip component modules in the physical layer can be generated based on the same standard modules, which reduces the number of chip component modules generated in the physical layer and improves the generation efficiency of physical layer chip design.

[0047] As an embodiment, the port list is a list of port names generated in sequence by the standard unit based on the interconnection relationship between the smallest component units, and the port name includes the hierarchical information corresponding to the port and the port number. It should be noted that the order of the ports in the port name list is arranged in the order of the port interconnection.

[0048] As an embodiment, step S5 includes:

[0049] Step S51: Generate physical layer chip component modules F in order based on the reorganized configuration information i The corresponding virtual module H i ,H i ={G1 i ,G2 i ,...,G j i ,...,G f(i) i}, G j i H i The jth virtual submodule of H is composed of j values ​​ranging from 1 to f(i), where f(i) is i The corresponding total number of virtual modules, i ranges from 1 to I, and I is the total number of modules composed of the reusable physical layer chip.

[0050] It should be noted that before generating an instantiated module based on a standard module, a virtualized module is generated for verification. The process of generating a virtualized module is relatively fast and consumes less resources.

[0051] Step S52: G in the standard module j i Replaced with standard modules.

[0052] It should be noted that when checking each physical layer chip module, it is temporarily assumed that there is no problem inside each sub-module, so the G j i Replace with standard modules to facilitate the reuse of standard modules at each level.

[0053] Step S53, determine the replaced {G1 i ,G2 i ,...,G j i ,...,G f(i) i The order of arrangement of} and F i Whether the arrangement order of the sub-modules in the corresponding standard modules is consistent, if it is consistent, execute step S54, otherwise, execute step S56.

[0054] It should be noted that the arrangement order of the sub-modules in the standard module is the standard order. i ,G2 i ,...,G j i ,...,G f(i) i}If the arrangement order of the sub-modules in the standard module is inconsistent, it means that there is a problem and the corresponding error message needs to be generated.

[0055] Step S54: Generate F based on the interconnection relationship between the minimum component units i The port list of the corresponding virtual module, F i The corresponding virtual module port list is the same as F i The port lists of the standard modules of the corresponding standard modules are compared, and if they are consistent, step S55 is executed, otherwise step S56 is executed.

[0056] It should be noted that, when there is no problem with the arrangement order of the sub-modules, it is necessary to further determine whether the port list is correct. If the port list is incorrect, it also indicates that there is a problem and a corresponding error message needs to be generated.

[0057] Step S55: Based on F i The corresponding standard module instantiation generates Fi , wait for all F i After the execution is completed, execute step S7.

[0058] It should be noted that through F i The corresponding virtual module H i Perform verification. If the verification passes, then based on F i The corresponding standard module instantiation generates F i , that is, the actual generated F i The process is based on the instantiation of pre-generated standard modules, which greatly improves the F i The generation efficiency of physical layer chip design is improved.

[0059] Step S56: Based on F i Generate the corresponding error message and wait for all F i After the execution is completed, execute step S7.

[0060] As an embodiment, step S6 includes:

[0061] Step S61, based on the reorganization configuration information, the sub-component modules corresponding to the physical layer chip component module are generated in sequence. If the sub-component module has a corresponding standard module, the instantiation corresponding to the sub-component module is directly generated based on the standard module corresponding to the sub-component module; otherwise, the sub-component module is directly generated.

[0062] It should be noted that, in order to achieve the reuse of standard modules at all levels, for any sub-component module that has a corresponding standard module, the corresponding instantiation of the sub-component module is directly generated based on the standard module corresponding to the sub-component module.

[0063] Step S62: Generate a port list of component modules corresponding to the physical layer chip component module based on the interconnection relationship between the minimum component units.

[0064] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0065] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0066] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0067] The embodiment of the present invention realizes the reuse of chip component modules in the process of generating physical layer chip design by constructing a standard module corresponding to each reusable physical layer chip component module. In addition, the physical layer chip component modules to be generated can be verified during the reuse process, thereby improving the generation efficiency and accuracy of the physical layer chip design.

[0068] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A physical layer chip design generation method based on module reuse, characterized in that: include: Step S1, obtaining a name list of the smallest component unit of the logic layer chip design at the logic layer and the interconnection information between the smallest component units, wherein the name of the smallest component unit at the logic layer is generated by concatenating the logic level information and the smallest component unit identifier; Step S2, obtaining reorganization configuration information from logic layer chip design to physical layer chip design based on the interconnection relationship between the minimum component units and the physical layout and wiring; Step S3, generating minimum component unit reuse mapping information and a standard module corresponding to each reusable physical layer chip component module based on the interconnection relationship and physical layout and routing between the minimum component units, the reusable chip component module is an instantiation module generated based on the standard module, and the standard module includes the component modules included in the standard module, the arrangement order of the component modules and the port list of the standard module; Step S4, if the physical layer chip component module is a reusable physical layer chip component module, execute step S5, otherwise, execute step S6; Step S5, generating a virtual module corresponding to the physical layer chip component module based on the reorganized configuration information, the standard module and the interconnection relationship between the minimum component units, comparing the virtual module with the corresponding standard module, if they are consistent, generating a corresponding physical layer component module instance based on the corresponding standard module, otherwise, generating a corresponding error message, and executing step S7; Step S6, generating a physical layer chip component module based on the reorganized configuration information, the standard module and the interconnection relationship between the minimum component units, and executing step S7; Step S7: If no error information exists in all physical layer chip component modules, a physical layer chip design is generated; otherwise, all error information is output.

2. The method according to claim 1, characterized in that: The step S2 comprises: Step S21, determining the name of each minimum component unit at the physical layer before reuse based on the interconnection relationship between the minimum component units and the physical layout and routing, where the name of the minimum component unit at the physical layer is generated by concatenating the physical layer information and the minimum component unit identifier; Step S22: Generate reorganization configuration information {(A1, B1), (A2, B2), ..., (A n ,B n ),...,(A N ,B N )},(A n ,B n ) is the nth reorganization configuration information, A n is the name of the smallest component unit at the logical level, B n A n The name of the corresponding smallest component unit in the physical layer. The value range of n is 1 to N, where N is the total number of the smallest components of the logic layer chip design, {(A1, B1), (A2, B2),..., (A n ,B n ),...,(A N ,B N )}, the reorganized configuration information with the same physical layer information is arranged in the order in which the smallest component units are generated at the physical layer.

3. The method according to claim 1, characterized in that The step S3 comprises: Step S31, obtain the name list {C1, C2, ..., C m ,...,C M }, C m is the name of the mth reusable minimum component unit in the logic layer chip design at the logic layer, the value range of m is 1 to M, M is the total number of names of the reusable minimum component units in the logic layer chip design at the logic layer, M≤N, N is the total number of minimum component units of the logic layer chip design; Step S33: Get C m Corresponding standard module D m , C m Based on D m Generated instantiation module,D m Includes a list of ports; Step S34: C m The physical layer information of the corresponding minimum component unit in the physical layer name remains unchanged, and the minimum component unit identifier is updated to D m , generating C m The name of the smallest component unit after reuse at the physical layer is E m ; Step S35: Based on all C m The corresponding E m The mapping relationship between them generates the minimum component unit reuse mapping information; Step S36, based on the interconnection relationship between the minimum components, physical layout and wiring, and the reuse mapping information of the small components, the standard modules corresponding to the reusable chip components of all levels of non-minimum components are generated. The standard modules corresponding to the reusable chip components of the non-minimum components include the components included in the standard modules, the arrangement order of the components, and the port list of the standard modules.

4. The method according to claim 3, characterized in that The port list is a list of port names generated in sequence by the standard unit based on the interconnection relationship between the smallest component units, and the port name includes the hierarchical information corresponding to the port and the port number.

5. The method according to claim 1, characterized in that The step S5 comprises: Step S51: Generate physical layer chip component modules F in order based on the reorganized configuration information i The corresponding virtual module H i ,H i ={G1 i ,G2 i ,...,G j i ,...,G f(i) i }, G j i H i The jth virtual submodule of H is composed of j values ​​ranging from 1 to f(i), where f(i) is i The corresponding total number of virtual modules, i ranges from 1 to I, where I is the total number of modules that can be composed of reusable physical layer chips; Step S52: G in the standard module j i Replaced with standard modules; Step S53, determine the replaced {G1 i ,G2 i ,...,G j i ,...,G f(i) i The order of arrangement of} and F i Whether the arrangement order of the sub-modules in the corresponding standard module is consistent, if it is consistent, execute step S54, otherwise, execute step S56; Step S54: Generate F based on the interconnection relationship between the minimum component units i The port list of the corresponding virtual module, F i The corresponding virtual module port list is the same as F i Compare the port list of the standard module with the corresponding standard module, if they are consistent, execute step S55, otherwise execute step S56; Step S55: Based on F i The corresponding standard module instantiation generates F i , wait for all F i After the execution is completed, execute step S7; Step S56: Based on F i Generate the corresponding error message and wait for all F i After the execution is completed, execute step S7.

6. The method according to claim 1, characterized in that The step S6 comprises: Step S61: Generate the sub-component modules corresponding to the physical layer chip component module in order based on the reorganized configuration information. If the sub-component module has a corresponding standard module, directly generate the instantiation corresponding to the sub-component module based on the standard module corresponding to the sub-component module; otherwise, directly generate the sub-component module; Step S62: Generate a port list of component modules corresponding to the physical layer chip component module based on the interconnection relationship between the minimum component units.

7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method according to any one of the preceding claims 1-6.

Images