Barcode decoding chip, method, electronic device and storage medium for parallel decoding

Abstract

The present invention discloses a barcode decoding chip, method, electronic device and storage medium for parallel decoding, wherein the chip comprises: an MCU control unit, an XIP FLASH, a program RAM, a DVP / MIPI interface controller, a core decoding unit and a UART / USB communication interface; the MCU control unit performs unified scheduling; the XIP FLASH is used to store the program run by the MCU control unit; the program RAM is used to store program variables during operation; the DVP / MIPI interface controller is used to receive image data transmitted by a CMOS image sensor and transfer it to a core decoding unit; the core decoding unit is used for parallel barcode decoding; the UART / USB communication interface is used for the barcode decoding chip to communicate with a host computer. The present invention solves the problem of reduced decoding speed and inability to cope with high mobile adaptability scenarios caused by serial decoding.

Description

Technical Field

[0001] The present invention belongs to the technical field of barcode recognition, and in particular relates to a barcode decoding chip, method, electronic equipment and storage medium for parallel decoding. Background Art

[0002] Barcode technology is the abbreviation of barcode auto-identification technology. Barcode technology is a symbol automatic recognition technology that was generated and developed on the basis of contemporary information technology. It integrates the functions of symbol encoding, data collection, automatic identification, input, and information storage, and can effectively solve the problem of collecting and automatically inputting a large amount of data in real work and life. Barcode technology has been widely used in the fields of retail, intelligent traceability, logistics, engineering warehousing management, hospital medicine, etc. At present, the most widely used barcodes are one-dimensional barcodes and two-dimensional barcodes.

[0003] One-dimensional barcode is a graphic symbol composed of a group of regularly arranged black and white stripes. The barcode information is transmitted by the different widths and positions of black and white. This group of graphic symbols is used to represent information such as numbers, characters and symbols. This barcode technology can only store information in one direction through the combination of black and white, so it is called "one-dimensional barcode".

[0004] Two-dimensional barcodes record data symbol information through black and white graphics distributed on a plane (horizontally and vertically) according to a certain pattern; in the compilation of the code, the concept of 0 and 1 bit streams that constitute the internal logic basis of the computer is cleverly used, and several geometric figures corresponding to binary are used to represent textual numerical information. Two-dimensional barcodes use error correction coding in the generation process, making them highly resistant to contamination. Two-dimensional barcodes can express information in both horizontal and vertical directions at the same time, so they can express a large amount of information in a very small area.

[0005] Barcode reading is a technology that converts barcode images into data information. It mainly consists of two parts: barcode image acquisition and decoding processing. Barcode image acquisition scans the barcode image through an optical image sensor and converts the optical signal into an electrical signal. Decoding processing is the process of translating the collected electrical signal into corresponding data information according to certain rules. Barcode reading equipment can be divided into laser reading equipment, linear CCD reading equipment, and area array CMOS / CCD reading equipment according to different reading principles.

[0006] At present, the decoding core chip mainly uses CPU for decoding. The CPU adopts the von Neumann architecture, which is characterized by sequential execution of programs. This structure makes it impossible for the CPU to decode multiple types of barcodes in parallel. In order to increase the decoding speed, the processing process can usually only be accelerated by increasing the CPU's main frequency, but this approach will increase the overall power consumption during the decoding process.

[0007] The Chinese patent with publication number CN101908134A discloses a serial bus type barcode decoding chip and a barcode decoding device, the serial bus type barcode decoding chip includes a data storage device, a register group, a barcode decoding pipeline, a main control logic module, a serial bus interface, and a serial command interpreter. The serial bus interface receives serial bus commands and serial bus data from the serial bus, and temporarily stores the serial bus data in the data register; the serial command interpreter obtains the serial bus command from the serial bus interface, interprets the serial bus command as a readable command of the main control logic module, stores the command in the command register, and the main control logic module stores the serial bus data in the data storage device under the control of the command. This invention cannot realize efficient parallel decoding processing, which limits the decoding speed and processing capacity. Summary of the invention

[0008] The purpose of the present invention is to provide a barcode decoding chip, method, electronic device and storage medium for parallel decoding to solve the problems of reduced decoding speed and inability to cope with high mobility adaptability scenarios caused by serial decoding.

[0009] The technical solution of the present invention is as follows:

[0010] On the one hand, the present invention provides a barcode decoding chip for parallel decoding, including: an MCU control unit, a XIPFLASH, a program RAM, a DVP / MIPI interface controller, a core decoding unit, and a UART / USB communication interface.

[0011] The MCU control unit performs unified scheduling of the barcode decoding chip through the AMBA bus; the XIPFLASH is used to store the program run by the MCU control unit, and the MCU control unit is connected to the XIP FLASH through CACHE; the program RAM is used to store program variables during the operation of the MCU control unit, and the MCU control unit reads and writes the variables in the program RAM through the AHB bus; the DVP / MIPI interface controller is used to receive image data transmitted by the CMOS image sensor, and transfer it to the core decoding unit through a dedicated DMA channel; the core decoding unit specifically includes: an image BMP storage unit and a barcode hardware decoding logic unit, the image BMP storage unit is used to store image data in parallel, and the barcode hardware decoding logic unit is used to carry the barcode decoding core algorithm and perform barcode decoding according to the image data transmitted in parallel by the image BMP storage unit; the UART / USB communication interface is used for the barcode decoding chip to communicate with the host computer.

[0012] Preferably, the image BMP storage unit includes: a parallel copy unit and a plurality of BMP RAM units; the barcode hardware decoding logic unit includes a plurality of decoding logic units and a control / status register; each BMP RAM unit corresponds to a decoding logic unit.

[0013] The parallel copy unit is connected in parallel with all the BMP RAM units; each BMP RAM unit is connected with the corresponding decoding logic unit; and the control / status register is connected in parallel with all the decoding logic units.

[0014] Preferably, the parallel copying unit is used to connect to the DVP / MIPI interface controller to copy the image data transmitted by the DVP / MIPI interface controller in parallel to all BMP RAM units; each BMP RAM unit contains a consistent RAM size, and each RAM stores image data in the same transmission process.

[0015] Preferably, the image BMP storage unit includes: a plurality of parallel arbitrators and corresponding block-based BLOCKRAM units; the barcode hardware decoding logic unit includes a plurality of address resolution units, a plurality of decoding logic units and a control / status register; each parallel arbitrator corresponds to a block-based BLOCK RAM unit; each address resolution unit corresponds to a decoding logic unit.

[0016] Each parallel arbiter is connected to a corresponding block RAM unit; each address resolution unit is connected to all parallel arbiters; each address resolution unit is connected to a corresponding decoding logic unit.

[0017] Preferably, the parallel arbitrator performs arbitration control on the image data stored in the block RAM units according to the first-in-first-out principle, the sum of the sizes of all the block RAM units is the image data size of the same transmission process, and the number of block RAM units is determined by the preset number of image division areas or the number of image rows.

[0018] Accordingly, the present invention provides a barcode decoding method for parallel decoding, comprising the following steps:

[0019] After the barcode decoding chip is powered on, the MCU control unit obtains program instructions from the XIP FLASH and initializes each module inside the barcode decoding chip and the external CMOS image sensor.

[0020] The MCU control unit controls the DVP / MIPI interface controller to read image data from the external CMOS image sensor and store it in the image BMP storage unit. The parallel copy unit copies the image data sent by the DVP / MIPI interface controller in parallel and inputs it into the BMP RAM units corresponding to each barcode decoding unit.

[0021] The MCU control unit starts the barcode hardware decoding logic unit to perform parallel decoding operations on the image data: the MCU control unit starts one or more barcode types of decoding logic units according to the user configuration, and writes a start signal to the corresponding control / status register. Each decoding logic unit accesses the image BMP storage unit according to its own decoding algorithm. After each decoding logic unit completes decoding, it sends the completion flag and the flag of whether the decoding is successful to the control / status register to generate an interrupt signal.

[0022] The decoding logic unit notifies the MCU control unit of the barcode decoding result through an interrupt signal. The MCU control unit sends the barcode decoding result to the host computer through the UART / USB communication interface to complete a decoding operation.

[0023] In another aspect, the present invention provides a barcode decoding method for parallel decoding, comprising the following steps:

[0024] After the barcode decoding chip is powered on, the MCU control unit obtains program instructions from the XIP FLASH and initializes each module inside the barcode decoding chip and the external CMOS image sensor.

[0025] The MCU control unit controls the DVP / MIPI interface controller to read image data from an external CMOS image sensor and store the image data in a block RAM unit of an image BMP storage unit.

[0026] The MCU control unit starts the barcode hardware decoding logic unit to perform parallel decoding operations on the image data: it starts one or more barcode types of decoding logic units according to the user configuration, and writes the start signal to the corresponding control / status register. Each decoding logic unit accesses the corresponding block RAM unit according to its own decoding algorithm.

[0027] If the addresses of the block RAM units accessed by each decoding logic unit are different, the image data is directly output to the address resolution unit corresponding to each decoding logic unit for barcode decoding after the next machine cycle of the access; if multiple decoding logic units access the same block RAM unit, the parallel arbiter outputs the accessed image data to the address resolution unit corresponding to each decoding logic unit according to the first-in-first-out principle. After each decoding logic unit completes decoding, it sends the completion flag and the flag of whether the decoding is successful to the control / status register to generate an interrupt signal.

[0028] The decoding logic unit notifies the MCU control unit of the barcode decoding result through an interrupt signal. The MCU control unit sends the barcode decoding result to the host computer through the UART / USB communication interface to complete a decoding operation.

[0029] On the other hand, the present invention also provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the barcode decoding method of parallel decoding as described in any embodiment of the present invention is implemented.

[0030] On the other hand, the present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the barcode decoding method of parallel decoding as described in any embodiment of the present invention is implemented.

[0031] Compared with the prior art, the present invention has the following technical effects:

[0032] The barcode decoding chip proposed in the present invention significantly improves the processing speed of barcode decoding and the overall system performance through efficient modular design and parallel decoding mechanism. The barcode decoding chip coordinates the collaborative work of various functional modules through the centralized scheduling of the MCU control unit, realizes the efficient collection, storage and decoding of image data, can support efficient parallel decoding of different types of barcodes, and ensures the real-time and accuracy of the decoding process. At the same time, it improves the response speed and accuracy of barcode scanning applications, and is particularly suitable for scenarios requiring fast decoding and high concurrent processing, with significant technical advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is the overall architecture diagram of the barcode decoding chip for parallel decoding of the present invention;

[0034] Figure 2 is the overall architecture diagram of the core decoding unit in the second embodiment;

[0035] Figure 3 It is the overall architecture diagram of the core decoding unit in the third embodiment. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in combination with specific embodiments of the present application and with reference to the accompanying drawings.

[0037] Embodiment 1

[0038] This embodiment provides a barcode decoding chip for parallel decoding. Figure 1 As shown, the barcode decoding chip includes: an MCU control unit, XIP FLASH, a program RAM, a DVP / MIPI interface controller, a core decoding unit, and a UART / USB communication interface.

[0039] The MCU control unit performs unified scheduling of the barcode decoding chip through the AMBA bus; the XIPFLASH is used to store the program run by the MCU control unit, and the MCU control unit is connected to the XIP FLASH through the CACHE. The CACHE structure can greatly improve the speed at which the MCU control unit reads instructions and data in the XIP FLASH. There is no restriction on the storage capacity of the CACHE. In practical applications, a 32K CACHE is preferred; the program RAM is used to store program variables during the operation of the MCU control unit, and the MCU control unit reads and writes variables in the program RAM through the AHB bus; the DVP / MIPI interface controller is used to receive image data transmitted by the CMOS image sensor and transfer it to the core decoding unit through a dedicated DMA channel; the core decoding unit specifically includes: an image BMP storage unit and a barcode hardware decoding logic unit, the image BMP storage unit is used to store image data in parallel, and the barcode hardware decoding logic unit is used to carry the barcode decoding core algorithm and perform barcode decoding according to the image data transmitted in parallel by the image BMP storage unit; the UART / USB communication interface is used for the barcode decoding chip to communicate with the host computer.

[0040] Embodiment 2

[0041] This embodiment provides a barcode decoding chip for parallel decoding. Based on the first embodiment, the image BMP storage unit includes: a parallel copy unit and a plurality of BMP RAM units; the barcode hardware decoding logic unit includes a plurality of decoding logic units and a control / status register; each BMP RAM unit corresponds to a decoding logic unit. The BMP RAM unit is a RAM of image size, and each RAM block stores the same image data. Furthermore, this embodiment does not impose specific restrictions on the decoding type or decoding algorithm of the decoding logic unit, and the most suitable decoding algorithm for each decoding logic unit can be freely configured according to actual application requirements. See Figure 2As shown, the decoding logic unit may select 1D decoding logic, QR decoding logic, DM decoding logic, PDF417 decoding logic, etc.

[0042] The parallel copy unit is connected in parallel with all the BMP RAM units; each BMP RAM unit is connected with the corresponding decoding logic unit; and the control / status register is connected in parallel with all the decoding logic units.

[0043] As a preferred implementation mode of this embodiment, the parallel copying unit is used to connect to the DVP / MIPI interface controller to copy the image data transmitted by the DVP / MIPI interface controller in parallel to all BMP RAM units; the RAM size contained in each BMP RAM unit is consistent, and each RAM stores image data in the same transmission process.

[0044] Embodiment 3

[0045] This embodiment provides a barcode decoding chip for parallel decoding. Based on the first embodiment, the image BMP storage unit includes: a number of parallel arbiters and corresponding block RAM units; the barcode hardware decoding logic unit includes a number of address resolution units, a number of decoding logic units and a control / status register; each parallel arbiter corresponds to a block RAM unit; each address resolution unit corresponds to a decoding logic unit. Furthermore, this embodiment does not impose specific restrictions on the decoding type or decoding algorithm of the decoding logic unit, and the most suitable decoding algorithm for each decoding logic unit can be freely configured according to actual application requirements. Figure 3 As shown, the decoding logic unit may select 1D decoding logic, QR decoding logic, DM decoding logic, PDF417 decoding logic, etc.

[0046] Each parallel arbiter is connected to a corresponding block RAM unit; each address resolution unit is connected to all parallel arbiters; each address resolution unit is connected to a corresponding decoding logic unit.

[0047] As a preferred implementation of this embodiment, since the addresses of the image data accessed by each decoding logic unit may be different, and the BLOCK RAM storage unit can only output data of one address corresponding to one clock, the parallel arbitrator performs arbitration control on the image data stored in the block BLOCK RAM unit according to the first-in-first-out principle to reduce the number of arbitrations and speed up decoding. The sum of the sizes of all the block BLOCK RAM units is the image data size of the same transmission process, and the number of block BLOCK RAM units is determined by the preset number of image division areas or the number of image rows. The above parallel decoding architecture can speed up the decoding without increasing the RAM overhead.

[0048] Embodiment 4

[0049] Accordingly, this embodiment provides a barcode decoding method for parallel decoding, which is implemented based on the barcode decoding chip described in the second embodiment and includes the following steps:

[0050] After the barcode decoding chip is powered on, the MCU control unit obtains program instructions from the XIP FLASH and initializes each module inside the barcode decoding chip and the external CMOS image sensor.

[0051] The MCU control unit controls the DVP / MIPI interface controller to read image data from the external CMOS image sensor and store it in the image BMP storage unit. The parallel copy unit copies the image data sent by the DVP / MIPI interface controller in parallel and inputs it into the BMP RAM units corresponding to each barcode decoding unit. The parallel copy unit is a pure parallel processing, which does not require additional time overhead, and the image data in each BMP RAM unit is consistent.

[0052] The MCU control unit starts the barcode hardware decoding logic unit to perform parallel decoding operations on the image data: the MCU control unit starts one or more barcode types of decoding logic units according to the user configuration, and writes the start signal to the control register of the corresponding control / status register. Each decoding logic unit accesses the image BMP storage unit according to its own decoding algorithm. Each BMP RAM unit has independent storage content and independent interface, and the access does not interfere with each other. Therefore, all decoding is completely parallel and independent, and the decoding process of each decoding logic unit does not conflict. In this way, all decoding core units can be started for decoding at the same time, which greatly speeds up the decoding speed. After each decoding logic unit completes decoding, it sends the completion flag and the flag of whether the decoding is successful to the status register of the control / status register to generate an interrupt signal.

[0053] The decoding logic unit notifies the MCU control unit of the barcode decoding result through an interrupt signal. The MCU control unit sends the barcode decoding result to the host computer through the UART / USB communication interface to complete a decoding operation.

[0054] Embodiment 5

[0055] Accordingly, this embodiment provides a barcode decoding method for parallel decoding, which is implemented based on the barcode decoding chip described in the third embodiment and includes the following steps:

[0056] After the barcode decoding chip is powered on, the MCU control unit obtains program instructions from the XIP FLASH and initializes each module inside the barcode decoding chip and the external CMOS image sensor.

[0057] The MCU control unit controls the DVP / MIPI interface controller to read image data from an external CMOS image sensor and store the image data in a block RAM unit of an image BMP storage unit.

[0058] The MCU control unit starts the barcode hardware decoding logic unit to perform parallel decoding operations on the image data: it starts one or more barcode types of decoding logic units according to the user configuration, and writes the start signal to the control register of the corresponding control / status register. Each decoding logic unit accesses the corresponding block RAM unit according to its own decoding algorithm.

[0059] If the addresses of the block RAM units accessed by each decoding logic unit are different, the image data is directly output to the address resolution unit corresponding to each decoding logic unit for barcode decoding after the next machine cycle of the access; if multiple decoding logic units access the same block RAM unit, the parallel arbiter outputs the accessed image data to the address resolution unit corresponding to each decoding logic unit according to the first-in-first-out principle, and gives each accessed address resolution unit a data valid indication signal. After decoding is completed, each decoding logic unit sends the completion flag and the flag of whether the decoding is successful to the status register of the control / status register to generate an interrupt signal.

[0060] The decoding logic unit notifies the MCU control unit of the barcode decoding result through an interrupt signal. The MCU control unit sends the barcode decoding result to the host computer through the UART / USB communication interface to complete a decoding operation.

[0061] Embodiment 6

[0062] This embodiment provides an electronic device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, it implements the barcode decoding method of parallel decoding as described in any embodiment of the present invention.

[0063] Embodiment 7

[0064] This embodiment provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the barcode decoding method for parallel decoding as described in any embodiment of the present invention is implemented.

[0065] In the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

[0066] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0067] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0068] In several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory; hereinafter referred to as: ROM), random access memory (Random Access Memory; hereinafter referred to as: RAM), disk or optical disk, and other media that can store program codes.

[0069] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A barcode decoding chip for parallel decoding, characterized in that: include: MCU control unit, XIP FLASH, program RAM, DVP / MIPI interface controller, core decoding unit, UART / USB communication interface; The MCU control unit performs unified scheduling of the barcode decoding chip through the AMBA bus; the XIP FLASH is used to store the program run by the MCU control unit, and the MCU control unit is connected to the XIP FLASH through CACHE; the program RAM is used to store program variables during the operation of the MCU control unit, and the MCU control unit reads and writes variables in the program RAM through the AHB bus; the DVP / MIPI interface controller is used to receive image data transmitted by the CMOS image sensor and transfer it to the core decoding unit through a dedicated DMA channel; The core decoding unit specifically includes: an image BMP storage unit and a barcode hardware decoding logic unit, the image BMP storage unit is used to store image data in parallel, the barcode hardware decoding logic unit is used to carry the barcode decoding core algorithm and perform barcode decoding according to the image data transmitted in parallel by the image BMP storage unit; the UART / USB communication interface is used for the barcode decoding chip to communicate with the host computer; The image BMP storage unit includes one of the following two structures: a. A parallel replication unit and a plurality of BMP RAM units; the parallel replication unit and all the BMP RAM units are connected in parallel; b. A plurality of parallel arbiters and corresponding block RAM units; each parallel arbiter corresponds to a block RAM unit; each parallel arbiter is connected to the corresponding block RAM unit; The barcode hardware decoding logic unit includes one of the following two structures: a. Several decoding logic units and control / status registers; each BMP RAM unit corresponds to a decoding logic unit; each BMP RAM unit is connected to the corresponding decoding logic unit; the control / status register is connected in parallel to all decoding logic units; b. Several address resolution units, several decoding logic units and control / status registers; each address resolution unit corresponds to a decoding logic unit; each address resolution unit is connected to all parallel arbiters; each address resolution unit is connected to the corresponding decoding logic unit.

2. The barcode decoding chip for parallel decoding according to claim 1, characterized in that: The parallel copy unit is used to connect with the DVP / MIPI interface controller to copy the image data transmitted by the DVP / MIPI interface controller to all BMP RAM units in parallel; each BMP RAM unit contains a RAM of the same size, and each RAM stores image data in the same transmission process.

3. The barcode decoding chip for parallel decoding according to claim 1, characterized in that: The parallel arbitrator performs arbitration control on the image data stored in the block RAM unit according to the first-in-first-out principle. The sum of the sizes of all the block RAM units is the image data size of the same transmission process. The number of block RAM units is determined by the preset number of image division areas or the number of image rows.

4. A barcode decoding method for parallel decoding, characterized in that: The method is implemented based on the barcode decoding chip for parallel decoding according to any one of claims 1 to 2, and comprises the following steps: After the barcode decoding chip is powered on, the MCU control unit obtains program instructions from the XIP FLASH and initializes each module inside the barcode decoding chip and the external CMOS image sensor; The MCU control unit controls the DVP / MIPI interface controller to read image data from the external CMOS image sensor and store it in the image BMP storage unit. The parallel copy unit copies the image data sent by the DVP / MIPI interface controller in parallel and inputs it into the BMP RAM unit corresponding to each barcode decoding unit. The MCU control unit starts the barcode hardware decoding logic unit to perform parallel decoding operations on the image data: the MCU control unit starts one or more barcode decoding logic units according to the user configuration, and writes the start signal to the corresponding control / status register. Each decoding logic unit accesses the image BMP storage unit according to its own decoding algorithm. After each decoding logic unit completes decoding, it sends the completion flag and the decoding success flag to the control / status register to generate an interrupt signal; The decoding logic unit notifies the MCU control unit of the barcode decoding result through an interrupt signal. The MCU control unit sends the barcode decoding result to the host computer through the UART / USB communication interface to complete a decoding operation.

5. A barcode decoding method for parallel decoding, characterized in that: The method is implemented based on the barcode decoding chip for parallel decoding according to any one of claims 1 and 3, and comprises the following steps: After the barcode decoding chip is powered on, the MCU control unit obtains program instructions from the XIP FLASH and initializes each module inside the barcode decoding chip and the external CMOS image sensor; The MCU control unit controls the DVP / MIPI interface controller to read image data from the external CMOS image sensor and store it in the block RAM unit of the image BMP storage unit; The MCU control unit starts the barcode hardware decoding logic unit to perform parallel decoding operations on the image data: one or more barcode type decoding logic units are started according to the user configuration, and the start signal is written to the corresponding control / status register. Each decoding logic unit accesses the corresponding block RAM unit according to its own decoding algorithm; If the addresses of the block RAM units accessed by the decoding logic units are different, the image data is directly output to the address resolution unit corresponding to each decoding logic unit for barcode decoding after the next machine cycle of the access; if multiple decoding logic units access the same block RAM unit, the parallel arbiter outputs the accessed image data to the address resolution unit corresponding to each decoding logic unit according to the first-in-first-out principle, and after each decoding logic unit completes decoding, it sends the completion flag and the flag of whether the decoding is successful to the control / status register to generate an interrupt signal; The decoding logic unit notifies the MCU control unit of the barcode decoding result through an interrupt signal. The MCU control unit sends the barcode decoding result to the host computer through the UART / USB communication interface to complete a decoding operation.

6. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the barcode decoding method of parallel decoding as claimed in claim 4 or 5 when executing the computer program.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the barcode decoding method of parallel decoding as claimed in claim 4 or 5 is implemented.

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