Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a reset driving circuit, the reset driving circuit comprises a plurality of cascaded shift registers, the shift register comprises a pull-up control module and a pull-up module, and a square wave signal is connected to the pull-up module to replace a high potential signal, so that a low potential square wave signal is output as a reset control signal in a black insertion period. The low potential reset control signal is obtained in the black insertion period, so that the problem of driving timing error caused by output of the high potential reset control signal in the black insertion period is avoided.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] In a display panel, in order to achieve the desired display effect of the pixel circuit, it is necessary to provide the corresponding driving timing for the pixel circuit. This driving timing can be provided by the corresponding gate driving circuit.

[0003] However, as the driving timing required by the pixel circuit changes, the gate driving circuit also needs to be improved accordingly to achieve the desired display effect. Summary of the Invention

[0004] This application provides a display panel and display device to alleviate the technical problem of driving timing errors caused by the high-potential reset control signal output by the reset drive circuit in the gate drive circuit when black bars are inserted.

[0005] In a first aspect, this application provides a display panel, which includes a reset drive circuit. The reset drive circuit includes multiple cascaded shift registers. Each shift register includes a pull-up control module and a pull-up module. The pull-up control module is configured to control a high-potential signal to be transmitted to the pull-up node according to an initialization control signal. The pull-up module is configured to output a low-potential square wave signal as a reset control signal during the blackout period according to the signal from the pull-up node.

[0006] Secondly, this application provides a display device that includes the aforementioned display panel.

[0007] The display panel and display device provided in this application use a pull-up module to connect a square wave signal instead of a high-potential signal. This allows a low-potential square wave signal to be output as a reset control signal during the blackout period. This ensures a low-potential reset control signal during the blackout period, thus avoiding the problem of driving timing errors caused by outputting a high-potential reset control signal during blackout. Attached Figure Description

[0008] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0009] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application.

[0010] Figure 2 This is a schematic diagram of the shift register structure in the reset drive circuit provided in an embodiment of this application.

[0011] Figure 3This is a schematic diagram of the structure of the light-emitting driving unit in the light-emitting driving circuit provided in the embodiment of this application.

[0012] Figure 4 This is a schematic diagram of the pixel circuit provided in an embodiment of this application.

[0013] Figure 5 This is a timing diagram of a display panel provided in an embodiment of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0015] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0016] Please see Figures 1 to 5 , Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. The display panel includes a pixel circuit 50, a reset drive circuit 10 that provides a reset control signal REF to the pixel circuit 50, a light emission drive circuit 20 that provides a light emission control signal EM to the pixel circuit 50, a scan drive circuit 30 that provides a scan signal Gn to the pixel circuit 50, and an initialization drive circuit 40 that provides an initialization control signal INI to the pixel circuit 50.

[0017] In this embodiment, the reset driving circuit 10, the light-emitting driving circuit 20, the scan driving circuit 30, and the initialization driving circuit 40 are all one type of gate driving circuit (GOA circuit). In other embodiments, the scan signal Gn and the initialization control signal INI can also be provided by the same gate driving circuit.

[0018] The reset drive circuit 10 includes multiple cascaded shift registers, wherein the nth shift register can output the nth reset control signal REF[n].

[0019] The light-emitting driving circuit 20 may include multiple cascaded light-emitting driving units, wherein the nth stage light-emitting driving unit can output the nth stage light-emitting control signal EM[n].

[0020] The scan driving circuit 30 may include multiple cascaded scan driving units, wherein the (n-1)th level scan driving unit can output the (n-1)th level scan signal Gn[n-1], and the nth level scan driving unit can output the nth level scan signal Gn[n].

[0021] The initialization drive circuit 40 may include multiple cascaded initialization drive units, wherein the nth initialization drive unit can output the nth initialization control signal INI[n], and the (n+1)th initialization drive unit can output the (n+1)th initialization control signal INI[n+1].

[0022] The pixel circuits 50 can be arrayed in the display area of ​​the display panel.

[0023] In some of these embodiments, such as Figure 2 As shown, the shift register includes a pull-up control module 11 and a pull-up module 12. The pull-up control module 11 is configured to control the transmission of the high-level signal VGH to the pull-up node Q according to the initialization control signal INI. The pull-up module 12 is configured to output a low-level square wave signal LC as the nth level reset control signal REF[n] during the blackout period according to the signal of the pull-up node Q.

[0024] It is understood that the display panel provided in this embodiment uses the pull-up module 12 to connect a square wave signal LC to replace the high-potential signal VGH. During the blackout period, the low-potential square wave signal LC can be output as the nth level reset control signal REF[n]. This can obtain a low-potential reset control signal REF during the blackout period, thereby avoiding the problem of driving timing errors caused by outputting a high-potential reset control signal REF during blackout.

[0025] In some of these embodiments, such as Figure 2 As shown, the pull-up module 12 includes a pull-up transistor T21. The gate of the pull-up transistor T21 is connected to the pull-up node Q. The first terminal of the pull-up transistor T21 is configured to receive a square wave signal LC, and the second terminal of the pull-up transistor T21 is configured to output the nth stage reset control signal REF[n].

[0026] It should be noted that the pull-up transistor T21 can be an example of an N-channel transistor. During the blackout period, if the signal of the pull-up node Q is at a high potential, the pull-up transistor T21 is turned on, and the low-potential square wave signal LC can be output as a low-potential nth-level reset control signal REF[n].

[0027] In this configuration, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, if the first electrode is the source, the second electrode is the drain; or if the first electrode is the drain, the second electrode is the source.

[0028] Optionally, such as Figure 2 As shown, the pull-up module 12 also includes a first capacitor C1. The first terminal of the first capacitor C1 is connected to the gate of the pull-up transistor T21, and the second terminal of the first capacitor C1 is connected to the second terminal of the pull-up transistor T21. The first capacitor C1 can perform a bootstrap function, thereby increasing the gate potential of the pull-up transistor T21.

[0029] In some of these embodiments, such as Figure 2 As shown, the pull-up control module 11 may include a pull-up control transistor T11. The first terminal of the pull-up control transistor T11 is connected to a high-potential signal VGH, the gate of the pull-up control transistor T11 is connected to the (n+1)th stage initialization control signal INI[n+1], and the second terminal of the pull-up control transistor T11 is connected to the pull-up node Q.

[0030] The pull-up control transistor T11 can be exemplarily an N-channel transistor, which charges the pull-up node Q when it is turned on or off. In other embodiments, the pull-up control transistor T11 may also include two transistors connected in series with their gates connected to reduce leakage current.

[0031] In some of these embodiments, such as Figure 2 As shown, the shift register may further include a first transistor T43. The first terminal of the first transistor T43 is connected to the pull-up node Q, the second terminal of the first transistor T43 is connected to the first low-potential line, and the gate of the first transistor T43 is connected to the pull-down node QB. The first transistor T43 is used to transmit the first low-potential signal VGL1 in the first low-potential line to the pull-up node Q under the signal control of the pull-down node QB. The first transistor T43 may be, exemplarily, an N-channel transistor.

[0032] In some of these embodiments, such as Figure 2 As shown, the shift register may further include a second transistor T55. The first terminal of the second transistor T55 is connected to the pull-down node QB, the second terminal of the second transistor T55 is connected to the first low-potential line, and the gate of the second transistor T55 is connected to the pull-up node Q. The second transistor T55 is used to transmit the first low-potential signal VGL1 in the first low-potential line to the pull-down node QB under the signal control of the pull-up node Q. The second transistor T55 may be, exemplarily, an N-channel transistor.

[0033] In some of these embodiments, such as Figure 2As shown, the shift register may further include a third transistor T56. The first terminal of the third transistor T56 is connected to the pull-down node QB, the second terminal of the third transistor T56 is connected to the first low-potential line, and the gate of the third transistor T56 is connected to the (n+1)th stage initialization control signal INI[n+1]. The third transistor T56 is used to transmit the first low-potential signal VGL1 in the first low-potential line to the pull-down node QB under the control of the (n+1)th stage initialization control signal INI[n+1]. The third transistor T56 can be exemplarily an N-channel transistor.

[0034] In some of these embodiments, such as Figure 2 As shown, the shift register may further include a fourth transistor T42. The first terminal of the fourth transistor T42 is connected to the pull-up node Q, the second terminal of the fourth transistor T42 is connected to the first low-potential line, and the gate of the fourth transistor T42 is connected to the (n-1)th stage scan signal Gn[n-1]. The fourth transistor T42 is used to transmit the first low-potential signal VGL1 in the first low-potential line to the pull-up node Q under the control of the (n-1)th stage scan signal Gn[n-1]. The fourth transistor T42 can be exemplarily an N-channel transistor.

[0035] In some of these embodiments, such as Figure 2 As shown, the shift register may further include a fifth transistor T54 and a second capacitor C2. The first terminal of the fifth transistor T54 is connected to the first terminal of the second capacitor C2 and receives a high-level signal VGH. The second terminal of the fifth transistor T54 is connected to the pull-down node QB. The gate of the fifth transistor T54 is connected to the second terminal of the second capacitor C2 and the first node T. The fifth transistor T54 is used to transmit the high-level signal VGH to the pull-down node QB according to the signal at the first node T. The fifth transistor T54 can be exemplarily an N-channel transistor.

[0036] In some of these embodiments, such as Figure 2 As shown, the shift register may further include a sixth transistor T52_A. The first terminal of the sixth transistor T52_A is connected to its gate and receives the (n-1)th stage scan signal Gn[n-1]. The second terminal of the sixth transistor T52_A is connected to the first node T. The sixth transistor T52_A is used to transmit the (n-1)th stage scan signal Gn[n-1] to the first node T under the control of the (n-1)th stage scan signal Gn. The sixth transistor T52_A can be exemplarily an N-channel transistor.

[0037] In some of these embodiments, such as Figure 2As shown, the shift register may further include a seventh transistor T52_B. The first terminal of the seventh transistor T52_B is connected to a low-level signal VGL, the gate of the seventh transistor T52_B is connected to and connected to the nth-stage initialization control signal INI[n], and the second terminal of the seventh transistor T52_B is connected to the first node T. The seventh transistor T52_B is used to transmit the low-level signal VGL to the first node T under the control of the nth-stage initialization control signal INI[n]. The seventh transistor T52_B can be exemplarily an N-channel transistor.

[0038] In some of these embodiments, such as Figure 2 As shown, the shift register may further include an eighth transistor T31. The first terminal of the eighth transistor T31 is connected to a second low-level signal VGL2, the gate of the eighth transistor T31 is connected to a pull-down node QB, and the second terminal of the eighth transistor T31 is connected to the second terminal of a pull-up transistor T21. The eighth transistor T31 is used to output the second low-level signal VGL2 as a low-level nth-stage reset control signal REF[n] under the signal control of the pull-down node QB. The eighth transistor T31 can be exemplarily an N-channel transistor.

[0039] like Figure 3 As shown, the light-emitting driving unit includes a ninth transistor T13. The first terminal of the ninth transistor T13 is connected to a high-potential signal VGH, the second terminal of the ninth transistor T13 is connected to a second node Q[n], and the gate of the ninth transistor T13 is connected to a first clock signal. The first clock signal can be one of CKA1-CKA4. The ninth transistor T13 is used to control the transmission of the high-potential signal VGH to the second node Q[n] according to the first clock signal. The ninth transistor T13 can be, exemplarily, an N-channel transistor.

[0040] like Figure 3 As shown, the light-emitting driving unit also includes a tenth transistor T22. The first terminal of the tenth transistor T22 is connected to a high-potential signal VGH, and the second terminal of the tenth transistor T22 is used to output the nth-level light-emitting control signal EM[n]. The gate of the tenth transistor T22 is connected to the second node Q[n]. The tenth transistor T22 is used to output the nth-level light-emitting control signal EM[n] with a high-potential VGH according to the signal from the second node Q[n]. The tenth transistor T22 can be, for example, an N-channel transistor.

[0041] like Figure 3 As shown, the light-emitting driving unit also includes a third capacitor C3. The first terminal of the third capacitor C3 is connected to the second terminal of the tenth transistor T22, and the second terminal of the third capacitor C3 is connected to the gate of the tenth transistor T22.

[0042] like Figure 3As shown, the light-emitting driving unit also includes an eleventh transistor T32. The first terminal of the eleventh transistor T32 is connected to a first low-level signal VGL1, and the second terminal of the eleventh transistor T32 is used to output a low-level nth-stage light-emitting control signal EM[n]. The gate of the eleventh transistor T32 is connected to the third node QB[n]. The eleventh transistor T32 is used to output the first low-level signal VGL1 as a low-level nth-stage light-emitting control signal EM[n] according to the signal from the third node QB[n]. The eleventh transistor T32 can be exemplarily an N-channel transistor.

[0043] like Figure 3 As shown, the light-emitting driving unit also includes a twelfth transistor T12. The first terminal of the twelfth transistor T12 is connected to a first low-potential signal VGL1, the second terminal of the twelfth transistor T12 is connected to a third node QB[n], and the gate of the twelfth transistor T12 is connected to a first clock signal. The twelfth transistor T12 is used to control the transmission of the first low-potential signal VGL1 to the third node QB[n] according to the first clock signal. The twelfth transistor T12 can be exemplarily an N-channel transistor.

[0044] like Figure 3 As shown, the light-emitting driving unit also includes a thirteenth transistor T53. The first terminal of the thirteenth transistor T53 is connected to its gate and receives the nth-level initialization control signal INI[n]. The second terminal of the thirteenth transistor T53 is connected to the third node QB[n]. The thirteenth transistor T53 is used to control the transmission of the nth-level initialization control signal INI[n] to the third node QB[n] according to the nth-level initialization control signal INI[n]. The thirteenth transistor T53 can be exemplarily an N-channel transistor.

[0045] like Figure 3 As shown, the light-emitting driving unit also includes a fourteenth transistor T57. The first terminal of the fourteenth transistor T57 is connected to its gate and receives the nth-level scan signal Gn[n]. The second terminal of the fourteenth transistor T57 is connected to the third node QB[n]. The fourteenth transistor T57 is used to control the transmission of the nth-level scan signal Gn[n] to the third node QB[n] according to the nth-level scan signal Gn[n]. The fourteenth transistor T57 can be exemplarily an N-channel transistor.

[0046] like Figure 3As shown, the light-emitting driving unit also includes a fifteenth transistor T52. The first terminal of the fifteenth transistor T52 is connected to a first low-potential signal VGL1, the gate of the fifteenth transistor T52 is connected to the second node Q[n], and the second terminal of the fifteenth transistor T52 is connected to the third node QB[n]. The fifteenth transistor T52 is used to control the transmission of the first low-potential signal VGL1 to the third node QB[n] according to the signal from the second node Q[n]. The fifteenth transistor T52 can be exemplarily an N-channel transistor.

[0047] like Figure 3 As shown, the light-emitting driving unit also includes a sixteenth transistor T44 and a seventeenth transistor T45. The first terminal of the sixteenth transistor T44 is connected to the second node Q[n]. The gate of the sixteenth transistor T44 is connected to the gate of the seventeenth transistor T45 and the third node QB[n]. The second terminal of the sixteenth transistor T44 is connected to the first terminal of the seventeenth transistor T45. The second terminal of the seventeenth transistor T45 is connected to a first low-potential signal VGL1. The sixteenth transistor T44 and the seventeenth transistor T45 are used to control the transmission of the first low-potential signal VGL1 to the second node Q[n] according to the signal of the third node QB[n] in the case of leakage prevention. The sixteenth transistor T44 and the seventeenth transistor T45 can be exemplary N-channel transistors.

[0048] like Figure 3 As shown, the light-emitting driving unit also includes an eighteenth transistor T61 and a nineteenth transistor T62. The first terminal of the eighteenth transistor T61 is connected to a high-potential signal VGH. The gate of the eighteenth transistor T61 is connected to the gate of the nineteenth transistor T62 and the second node Q[n]. The second terminal of the eighteenth transistor T61 is connected to the first terminal of the nineteenth transistor T62, and the second terminal of the nineteenth transistor T62 is connected to the second terminal of the sixteenth transistor T44. The eighteenth transistor T61 and the nineteenth transistor T62 are used to control the transmission of the high-potential signal VGH to the second terminal of the sixteenth transistor T44 according to the signal of the second node Q[n], so as to prevent the second node Q[n] from leaking current through the sixteenth transistor T44 and the seventeenth transistor T45. The eighteenth transistor T61 and the nineteenth transistor T62 can be exemplary N-channel transistors.

[0049] like Figure 4 As shown, the pixel circuit 50 includes a driving transistor Tdr, a light-emitting control transistor Te, a light-emitting device Di, and a reset transistor Tr. The light-emitting control transistor Te is connected between the first power supply line and the first terminal of the driving transistor Tdr; the light-emitting device Di is connected between the second power supply line and the second terminal of the driving transistor Tdr; and the reset transistor Tr is connected between the gate of the driving transistor Tdr and the reference voltage line, with the gate of the reset transistor Tr connected to the reset control signal REF.

[0050] The pixel circuit 50 includes a black insertion period in its light-emitting phase. During this period, both the light-emitting control transistor Te and the reset transistor Tr are turned off. By turning off the light-emitting control transistor Te and the reset transistor Tr during the black insertion period, black insertion can be achieved without lowering the gate potential of the driving transistor Tdr.

[0051] The potential of the first power signal VDD transmitted in the first power line is higher than the potential of the second power signal VSS transmitted in the second power line.

[0052] The gate of the light-emitting control transistor Te is connected to the light-emitting control signal EM. The reference voltage line is used to transmit the reference voltage signal Vref.

[0053] The light-emitting device Di can be an organic light-emitting diode, a mini light-emitting diode, a micro light-emitting diode, or a quantum dot light-emitting diode.

[0054] In some of these embodiments, such as Figure 4 As shown, the pixel circuit 50 also includes a write transistor Tw, which is configured to control the transmission of the data signal Vdata to the gate of the drive transistor Tdr according to the scan signal Gn.

[0055] It should be noted that in the write frame, the write transistor Tw of the pixel circuit 50 is turned on to write the data signal Vdata to the gate of the drive transistor Tdr. In the hold frame, the write transistor Tw of the pixel circuit 50 is turned off to prevent the data signal Vdata from being written to the gate of the drive transistor Tdr.

[0056] In some of these embodiments, such as Figure 4 As shown, the pixel circuit 50 also includes a storage capacitor Cst, the first end of which is connected to the gate of the driving transistor Tdr, and the second end of which is connected to the source of the driving transistor Tdr.

[0057] In some of these embodiments, such as Figure 4 As shown, the pixel circuit 50 also includes an initialization transistor Ti. The first terminal of the initialization transistor Ti is connected to an initialization signal Vini, the second terminal of the initialization transistor Ti is connected to the source of the driving transistor Tdr, and the gate of the initialization transistor Ti is connected to an initialization control signal INI. The initialization transistor Ti is configured to control the transmission of the initialization signal Vini to the source of the driving transistor Tdr according to the initialization control signal INI.

[0058] Each transistor in the pixel circuit 50 can be an N-channel transistor, for example. Figure 5This is a timing diagram of a display panel provided in an embodiment of this application. Each frame of the display panel includes a write frame or a hold frame.

[0059] During the write frame, the square wave signal LC is at a high potential, the initialization control signal INI is at a high potential, and the initialization transistor Ti is turned on to initialize the source potential of the driving transistor Tdr; the reset control signal REF is at a high potential, and the reset transistor Tr is turned on to reset the gate potential of the driving transistor Tdr; the light emission control signal EM is at a low potential, and the light emission control transistor Te is turned off to isolate the influence of the first power supply signal VDD on the potentials of the driving transistor Tdr; when the scan signal Gn is at a high potential and the light emission control signal EM is at a low potential, the data signal Vdata can be written to the gate of the driving transistor Tdr through the write transistor Tw while the light emission control transistor Te is turned off. When the initialization control signal INI, the reset control signal REF, and the scan signal Gn are all at a low potential, and the light emission control signal EM is at a high potential, the pixel circuit 50 is in the light emission stage.

[0060] During the hold frame, the square wave signal LC is at a low potential. Since the second terminal of the pull-up transistor T21 is configured to output a low-potential square wave signal LC, the reset control signal REF is also at a low potential. Even if the initialization control signal INI is at a high potential, the reset control signal REF will not be at a high potential in the reset drive circuit 10, thus affecting the pixel circuit 50's black insertion function via the light-emitting control transistor Te. When the initialization control signal INI, the reset control signal REF, and the scan signal Gn are all at low potentials, and the light-emitting control signal EM is at a high potential, the pixel circuit 50 is in the light-emitting stage.

[0061] Both in a write frame and a hold frame, there is a light-emitting phase. Each light-emitting phase may include at least one of a light-emitting period and a black-insertion period. During the light-emitting period, the light-emitting device Di emits light, while during the black-insertion period, the light-emitting device Di does not emit light or is in a dark state.

[0062] In some embodiments, this embodiment provides a display device that includes the display panel described above.

[0063] It is understood that since the display device provided in this embodiment includes the aforementioned display panel, it can also use the pull-up module 12 to connect a square wave signal LC to replace the high-potential signal VGH. During the blackout period, a low-potential square wave signal LC can be output as a reset control signal REF. This can obtain a low-potential reset control signal REF during the blackout period, thereby avoiding the problem of driving timing errors caused by outputting a high-potential reset control signal REF during blackout.

[0064] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0065] The display panel and display device provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, The display panel includes a reset drive circuit, which includes multiple cascaded shift registers, each shift register including: A pull-up control module, configured to control the transmission of a high-potential signal to the pull-up node according to an initialization control signal; The pull-up module is configured to output a low-level reset control signal based on a low-level square wave signal during the black insertion period of the light-emitting phase in the holding frame, according to the signal of the pull-up node. The display panel further includes a pixel circuit, which includes a driving transistor and a reset transistor. The reset transistor is connected between the gate of the driving transistor and a reference voltage line, and the gate of the reset transistor is connected to the reset control signal. The light-emitting phase of the pixel circuit includes the black insertion period, during which the reset transistor is turned off.

2. The display panel according to claim 1, characterized in that, The pull-up module includes a pull-up transistor, the gate of which is connected to the pull-up node. The first terminal of the pull-up transistor is configured to receive the square wave signal, and the second terminal of the pull-up transistor is configured to output the reset control signal.

3. The display panel according to claim 2, characterized in that, Each frame of the display panel includes a write frame or a hold frame. In the hold frame, the square wave signal is at a low potential, and the second terminal of the pull-up transistor is configured to output the reset control signal at a low potential.

4. The display panel according to claim 3, characterized in that, During the write frame, the square wave signal is at a high potential.

5. The display panel according to any one of claims 1-4, characterized in that, The pixel circuit includes: A light-emitting control transistor, wherein the light-emitting control transistor is connected between a first power supply line and a first electrode of the driving transistor; A light-emitting device, wherein the light-emitting device is connected between the second power line and the second electrode of the driving transistor; During the blackout period, the light-emitting control transistor is turned off.

6. The display panel according to claim 5, characterized in that, The reset transistor is an N-channel transistor, and the reset control signal is at a low potential during the blackout period.

7. The display panel according to claim 5, characterized in that, The pixel circuit also includes a write transistor configured to control the transmission of a data signal to the gate of the drive transistor according to a scan signal.

8. The display panel according to claim 7, characterized in that, In the write frame, the write transistor of the pixel circuit is turned on to write the data signal to the gate of the drive transistor.

9. The display panel according to claim 8, characterized in that, During the holding frame, the write transistor is turned off to prevent the data signal from being written to the gate of the drive transistor.

10. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-9.

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